S i 5 1 0 0 / Si 5 11 0 - EVB E v a l u a t i o n B o a r d S e t f o r S i 5 1 0 0 a n d S i 5 11 0 OC-48/STM-16 SONET/SDH TRANSCEIVERS Description Features The Si5100-EVB and Si5110-EVB motherboard/ daughter card sets provide a platform for testing and characterizing Silicon Laboratories’ Si5100/Si5110 SiPHYTM OC-48/STM-16 SONET/SDH Transceiver. The Si5100 and Si5110 transceiver devices provide fullduplex operation at serial data rates up to 2.7 Gbps. The transceiver device is mounted on the EVB daughter card. The high-speed serial signals are accessed via SMA connectors on the daughter card itself. The lowspeed parallel data channels are routed from the daughter card to the motherboard through the industrystandard 300-pin meg-array connector. The included transceiver loopback motherboard provides a hardware connection between the transceiver low-speed parallel data outputs, RXDOUT, and the transceiver low-speed parallel data inputs, TXDIN. Test points are provided on the motherboard to allow monitoring of the parallel data channels. The clock signals associated with the low-speed data channels are routed to SMA connectors on the loopback motherboard. Static control and status signals are routed to standard 100-mil center posts. Separate supply connections for VDD (1.8 V) and VDDIO (1.8 V or 3.3 V) allow LVTTL I/Os to be powered at either 1.8 V or 3.3 V. Control inputs are jumper configurable. Status outputs brought out to headers for easy access. Potentiometers provided for controlling analog inputs. Loopback Motherboard (included) provides hardware path between low-speed parallel data outputs RXDOUT and low-speed parallel data inputs TXDIN. Optional full-duplex motherboard provides access to all low-speed parallel data outputs and inputs via SMA connectors. An optional full-duplex motherboard is also available for the transceiver daughter card. The full-duplex motherboard also utilizes the industry-standard 300-pin meg-array connector to allow attachment of the daughter card. The full-duplex motherboard routes all of the transceiver low-speed parallel data outputs and inputs to standard SMA connectors. The optional fullduplex motherboard is useful when connecting the transceiver device to a parallel bit error rate tester (ParBERT), or in other applications that require full access to the low-speed parallel data channels. Preliminary Rev. 0.5 6/03 Copyright © 2003 by Silicon Laboratories Si5100/Si5110-EVB-05 Si5100/Si5110-EVB Motherboard/Daughter Card Set 300-Pin Meg-Array Connector Testpoints Control Input Headers Pow er Connectors Status Header & LEDs er eiv nsc ac k Tra op b ard Lo erbo th Mo 0/ 10 Si5 11 0 5 i S 2.5 GHz transmit clock output SMA Connectors for Parallel Interface Clock signals 2.5 Gbps Interface SMA Connectors Daughter Card 2 Rev. 0.5 Si5100/Si5110-EVB Testpoints RXDOUT Bus TXDIN Bus TXCLK16OUT RXCLK2 300-Pin MSA Connector TXCLK16IN RXCLK1 TXREFCLK RXREFCLK 3.3 V 1.8 V GND Control Inputs Status Ouputs RXCLK2 RXCLK1 TXCLK16IN TXCLK16OUT Figure 1. Loopback Motherboard Functional Block Diagram TXDIN15 RXDOUT15 TXDIN1 RXDOUT1 300-Pin MSA Connector TXDIN0 TXREFCLK RXDOUT0 RXREFCLK 3.3V 1.8V GND Control Inputs Status Ouputs Figure 2. Optional Full-Duplex Motherboard Functional Block Diagram Rev. 0.5 3 Si5100/Si5110-EVB Control Inputs Status Ouputs 300-Pin MSA Connector TXCLK16IN/TXCLK4IN RXREFCLK 2 2 2 2 VREF SLICELVL TXDIN 16 pairs VREF LOSLVL VDD VDD33 RESET_N RXCLK2DSBL_N RXCLK2DIV_N LPTM_N FIFOERR_N FIFORST_N TXCLK16OUT/TXCLK4OUT 2 TXREFCLK RXDOUT 16 pairs RXCLK2 RXCLK1 3.3 V 1.8 V VREF PHASEADJ Si5100/Si5110 Other Input Signals Test Inputs Test Ouputs Other Ouput Signals Control Inputs Status Ouputs RXDIN TXCLKOUT TXDOUT Figure 3. Daughter Card Functional Block Diagram 4 Rev. 0.5 Si5100/Si5110-EVB Functional Description Data I/O Signals The Si5100-EVB and Si5110-EVB motherboard and daughter card sets simplify characterization of the OC48/STM-16 and FEC transceiver devices by providing convenient access to the device I/Os. Device performance can be evaluated in various modes by following the “Basic Test Setup” section. The serial 2.5 Gbps data and 2.5 GHz clock paths are routed as coplanar differentially-coupled microstrip transmission lines on the daughter card. These three signals (RXDIN, TXCLKOUT, and TXDOUT) are ac coupled to standard SMA jacks for ease in connection to industry standard test equipment. Take care when connecting cables to these jacks. Use a standard SMA torque wrench to minimize reflections at the cable-tojack interface. Finally, match all differential connections in length to minimize phase differences between the positive and negative terminals. Power Supply The transceiver device can be powered from a single 1.8 V supply or seperate 1.8 V and 3.3 V supplies. When the additional 3.3 V supply is applied, the status outputs are LVTTL compatible. The daughter card can be configured for either mode of operation by setting the VDD_IO SEL jumper as shown in Figure 4. The differential parallel data lines are routed through the 300-pin meg-array connector to the motherboard. The standard loopback motherboard directly couples the RXDOUT bus to the TXDIN bus. The optional fullduplex motherboard directly couples the RXDOUT and TXDIN buses to standard SMA jacks for connection to industry standard test equipment. For 3.3 V/1.8 V operation 1.8 V VDD_IO SEL 3.3 V For 1.8 V operation only VDD_IO SEL Differential Parallel Data and Clock I/O Signals Slice Level, Loss-of-Signal Level, and Phase Adjust 1.8 V 3.3 V Figure 4. VDD_IO Selection Jumpers Control Inputs The device control inputs are located on the motherboard and daughter card. Signals with equivalent module functions are routed to the motherboard header, JP1. Signals specific to the transceiver are routed on the daughter card to jumpers JP1 and JP2. In both cases, the signal is routed to the center pin of a three pin group where the adjacent pins are power and ground. The device inputs are pulled high or low so that leaving a signal unconnected will not harm the device. Status Outputs The device status outputs are located on the motherboard and daughter card. Signals with equivalent module functions are routed to the motherboard header, JP2. Signals specific to the transceiver are routed on the daughter card to headers JP3 and JP4. In both cases, the signal is routed to a header pin adjacent to a ground pin. Voltages present at the Slice Level (SLICELVL), Lossof-Signal Level (LOSLVL) and Phase Adjust (PHASEADJ) pins can be used to adjust the data slicing level, the loss-of-signal alarm level, and the sampling phase position, respectively. Because these inputs are high impedance, simple turn-based potentiometers are used to apply the control voltage. The Si5100-EVB provides 50 k potentiometers for each of these inputs: potentiometer R16 sets the voltage applied to the SLICELVL pin; R14 sets the voltage applied to the LOSLVL pin, and R15 sets the voltage applied to the PHASEADJ pin. The Si5110-EVB also provides 50 k potentiometers for each of these inputs. Potentiometer R5 sets the voltage applied to the SLICELVL pin; R3 sets the voltage applied to the LOSLVL pin, and R4 sets the voltage applied to the PHASEADJ pin. The potentiometers are connected so the voltage applied varies from GND to VREF. Refer to the device data sheet for details on the operation of these inputs. Basic Test Setup The configurations listed in Tables 1 and 3 allow easy setup of the transceiver evaluation system for operation in the line loopback, full duplex, or diagnostic loopback modes. Other configurations are supported; however, operation should first be verified in one of these modes in order to minimize the number of unknown variables. Rev. 0.5 5 Si5100/Si5110-EVB Line Loopback When configured in line-loopback mode, the device passes the received/recovered data and timing to the transmitter. The transmitter buffers the data through the FIFO and filters the jitter using the loop-bandwidth selected by BWSEL[1:0]. Operation in line loopback mode is depicted in Figure 5. Jumper settings for line loopback mode are given in Tables 1, 3 (Si5100), and 4 (Si5110). This mode of operation is attainable with both versions of the motherboard. Si5100/Si5110 Receiver RXCLK1 TXDOUT Receiver RXCLK1 TXDOUT TXREFCLK TXCLK RXDOUT RXDIN RXCLK1 TXREFCLK TXCLK TXCLK16IN/ TXCLK4IN TXDIN Figure 5. Line Loopback 6 RXDOUT RXDIN Si5100/Si5110 Transmitter TXDIN Si5100/Si5110 This mode passes the data present on the transmit parallel inputs (TXDIN[15:0] for Si5100; TXDIN[3:0] for Si5110) to the receive parallel data outputs (RXDOUT[15:0] for Si5100; RXDOUT[3:0] for Si5110). TXCLK16IN/TXCLK4IN is chosen as the transmitter CMU reference clock via the REFSEL pin. Operation in diagnostic loopback mode is depicted in Figure 7. Jumper settings for diagnostic loopback mode are given in Tables 2, 3 (Si5100), and 4 (Si5110). The full-duplex motherboard is required for this mode. TXDOUT TXCLK16IN/ TXCLK4IN Figure 6. Full Duplex Diagnostic Loopback (Parallel Side Loopback) Receiver Transmitter TXREFCLK TXCLK Full-Duplex This mode is identical to normal operation of the device in a system. TX and RX can be asynchronous (up to ±300 ppm) so all timing is independent. TXCLK16IN is chosen as the transmitter CMU reference clock via the REFSEL pin. Operation in full-duplex mode is depicted in Figure 6. Jumper settings for full-duplex mode are given in Tables 1, 3 (Si5100), and 4 (Si5110). If the loopback motherboard is used, the full-duplex mode effectively becomes an external loopback mode, and RXCLK1 should be connected to TXCLK16IN/ TXCLK4IN to clock in the data. RXDOUT RXDIN Rev. 0.5 Transmitter TXCLK16IN/ TXCLK4IN TXDIN Figure 7. Diagnostic Loopback Si5100/Si5110-EVB Both the motherboard and daughter card are placed in line loopback mode before shipment to customers. Table 1. Loopback Motherboard Setup Header—Pin JP10—2 JP1—14 JP1—11 JP1—8 JP1—5 JP1—2 JP2—5 JP2—2 JP3—8 JP3—5 JP3—2 JP7—5 JP7—2 JP6—4 Signal Name Voltage Select RXCLK1DSBL_N LTR_N RXSQLCH_N RXCLK2DIV_N RXCLK2DSBL_N TXREFRATE TXRESET_N DLBK_N LLBK_N LPTM_N RXREFRATE RXRESET_N FIFORST_N Line Loopback 3.3 V high high low don’t care don’t care high high high low (enables line loopback) high open high tie to FIFOERR Asynchronous TX/RX 3.3 V high high high don’t care don’t care high high high high high open high tie to FIFOERR Table 2. Full-Duplex Motherboard Setup Header—Pin JP8—2 JP1—14 JP1—11 JP1—8 JP1—5 JP1—2 JP2—5 JP2—2 JP3—8 JP3—5 JP3—2 JP7—5 JP7—2 JP6—4 Signal Name Voltage Select RXCLK1DSBL_N LTR_N RXSQLCH_N RXCLK2DIV_N RXCLK2DSBL_N REFRATE RESET_N DLBK_N LLBK_N LPTM_N Si5530 REFRATE Si5530 RESET_N FIFORST_N Line Loopback 3.3 V high high low don’t care don’t care high high high low (enables line loopback) high open high tie to FIFOERR Asynchronous TX/RX 3.3 V high high high don’t care don’t care high high high high high open high tie to FIFOERR Diagnostic Loopback 3.3 V high high high don’t care don’t care high high low high high open high tie to FIFOERR Table 3. Si5100 Daughter Card Setup Header—Pin JP1—20 JP1—23 Signal Name BWSEL0 BWSEL1 Line Loopback 11 (for widest CMU loop bandwidth) JP1—17 REFSEL high JP1—14 MODE16 high JP1—11 TXCLKDSBL low JP1—8 TXMSBSEL low JP1—5 TXSQLCH_N high JP1—2 RXMSBSEL low Note: Jump the VDD_IO selection jumper toward the 3.3 V side. Rev. 0.5 Asynchronous TX/RX 11 (for widest CMU loop bandwidth) high high low low high low Diagnostic Loopback 11 (for widest CMU loop bandwidth) high high low low high low 7 Si5100/Si5110-EVB Table 4. Si5110 Daughter Card Setup Header—Pin JP1—20 JP1—23 Line Loopback 11 (for widest CMU loop bandwidth) JP1—17 REFSEL high JP1—14 TXCLKDSBL low JP1—11 TXMSBSEL low JP1—8 TXSQLCH_N high JP1—5 SLICEMODE low JP1—2 RXMSBSEL low Note: Jump the VDD_IO selection jumper toward the 3.3 V side. 8 Signal Name BWSEL0 BWSEL1 Rev. 0.5 Asynchronous TX/RX 11 (for widest CMU loop bandwidth) high low low high low low Diagnostic Loopback 11 (for widest CMU loop bandwidth) high low low high low low VDD_IO VDD_IO 23 20 17 14 11 8 5 2 14 11 8 5 2 JP2 GND40 RSVD_GND6 RSVD_GND7 RSVD_GND4 RSVD_GND5 BWSEL1 BWSEL0 REFSEL MODE16 TXCLKDSBL TXMSBSEL TXSQLCH_N RXMSBSEL 0402 0.033uF C2 0402 0.033uF Reserved for Factory Testing HEADER 5X3 1 3 4 6 7 9 10 12 13 15 HEADER 8X3 1 3 4 6 7 9 10 12 13 15 16 18 19 21 22 24 JP1 J2 J1 C1 RSVD_GND4 RSVD_GND5 RSVD_GND6 RSVD_GND7 GND40 TXSQLCH_N TXCLKDSBL TXMSBSEL MODE16 BWSEL0 BWSEL1 RXMSBSEL REFSEL Do NOT install R17 0 ohm SW1 SW PUSHBUTTON LOSLVL PHASEADJ SLICELVL FIFORST_N RESET_N DLBK_N LLBK_N LPTM_N RXCLK2DIV_N RXCLK1DSBL_N RXCLK2DSBL_N LTR_N RXSQLCH_N REFRATE Si5530_REFCLK+ Si5530_REFCLK- TXCLK16IN+ TXCLK16IN- TXDIN0+ TXDIN0TXDIN1+ TXDIN1TXDIN2+ TXDIN2TXDIN3+ TXDIN3TXDIN4+ TXDIN4TXDIN5+ TXDIN5TXDIN6+ TXDIN6TXDIN7+ TXDIN7TXDIN8+ TXDIN8TXDIN9+ TXDIN9TXDIN10+ TXDIN10TXDIN11+ TXDIN11TXDIN12+ TXDIN12TXDIN13+ TXDIN13TXDIN14+ TXDIN14TXDIN15+ TXDIN15- L3 C11 M8 K4 C7 C6 E4 C3 D4 C4 M6 G4 F12 H12 J12 H4 L12 C9 D12 C12 F4 C8 E3 M12 K12 M9 G12 M7 M10 G14 H14 D1 E1 N2 N1 P4 P3 N4 N3 P6 P5 N6 N5 P8 P7 N8 N7 P10 P9 N10 N9 P12 P11 N12 N11 P14 P13 N14 N13 L14 M14 L13 M13 J14 K14 J13 K13 TXREXT RXREXT RSVD_GND4 RSVD_GND5 RSVD_GND6 RSVD_GND7 GND40 LOSLVL PHASEADJ SLICELVL FIFORST_N RESET_N DLBK_N LLBK_N LPTM_N REFRATE REFSEL RXSQLCH_N RXMSBSEL RXCLK2DIV_N RXCLK1DSBL_N RXCLK2DSBL_N LTR_N TXSQLCH_N TXCLKDSBL TXMSBSEL MODE16 BWSEL[0] BWSEL[1] REFCLK+ REFCLK- RXDIN+ RXDIN- TXCLK16IN+ TXCLK16IN- TXDIN0+ TXDIN0TXDIN1+ TXDIN1TXDIN2+ TXDIN2TXDIN3+ TXDIN3TXDIN4+ TXDIN4TXDIN5+ TXDIN5TXDIN6+ TXDIN6TXDIN7+ TXDIN7TXDIN8+ TXDIN8TXDIN9+ TXDIN9TXDIN10+ TXDIN10TXDIN11+ TXDIN11TXDIN12+ TXDIN12TXDIN13+ TXDIN13TXDIN14+ TXDIN14TXDIN15+ TXDIN15Si5100 U1 VREF NC1 NC2 RSVD_GND1 RSVD_GND2 RSVD_GND3 RXLOL_N TXLOL_N LOS_N FIFOERR_N TXCLK16OUT+ TXCLK16OUT- TXDOUT+ TXDOUT- TXCLKOUT+ TXCLKOUT- RXCLK2+ RXCLK2- RXCLK1+ RXCLK1- RXDOUT0+ RXDOUT0RXDOUT1+ RXDOUT1RXDOUT2+ RXDOUT2RXDOUT3+ RXDOUT3RXDOUT4+ RXDOUT4RXDOUT5+ RXDOUT5RXDOUT6+ RXDOUT6RXDOUT7+ RXDOUT7RXDOUT8+ RXDOUT8RXDOUT9+ RXDOUT9RXDOUT10+ RXDOUT10RXDOUT11+ RXDOUT11RXDOUT12+ RXDOUT12RXDOUT13+ RXDOUT13RXDOUT14+ RXDOUT14RXDOUT15+ RXDOUT15- VDD C5 C10 L4 M11 E12 D3 F3 M5 G3 K3 P2 P1 K1 L1 G1 H1 B2 B3 A2 A3 A4 A5 B4 B5 A6 A7 B6 B7 A8 A9 B8 B9 A10 A11 B10 B11 A12 A13 B12 B13 A14 B14 C13 D13 C14 D14 E13 F13 E14 F14 G13 H13 Figure 8. Si5100-EVB Daughter Card Schematic (page 1 of 3) R1 0603 3.09k H3 VDD_33 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 B1 C1 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 F1 J1 M1 J3 M3 J4 M4 D5 L5 D6 L6 D7 L7 D8 L8 D9 L9 D10 L10 D11 E11 F11 G11 H11 J11 K11 L11 Rev. 0.5 R2 0603 3.09k E5 F5 G5 H5 J5 K5 E6 F6 G6 H6 J6 K6 E7 F7 G7 H7 J7 K7 E8 F8 G8 H8 J8 K8 E9 F9 G9 H9 J9 K9 E10 F10 G10 H10 J10 K10 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD_IO RXCLK2+ RXCLK2- RXCLK1+ RXCLK1- NC2 NC1 J6 J5 J4 J3 2 4 6 2 JP8 1 2 JP7 HEADER 2X1 1 HEADER 2X1 JP4 1 3 5 HEADER 3X2 RXLOL_N TXLOL_N LOS_N FIFOERR_N TXCLK16OUT+ TXCLK16OUT- 0402 0.033uF C6 C5 0402 0.033uF C4 0402 0.033uF C3 RSVD_GND1 RSVD_GND2 RSVD_GND3 VREF RXDOUT0+ RXDOUT0RXDOUT1+ RXDOUT1RXDOUT2+ RXDOUT2RXDOUT3+ RXDOUT3RXDOUT4+ RXDOUT4RXDOUT5+ RXDOUT5RXDOUT6+ RXDOUT6RXDOUT7+ RXDOUT7RXDOUT8+ RXDOUT8RXDOUT9+ RXDOUT9RXDOUT10+ RXDOUT10RXDOUT11+ RXDOUT11RXDOUT12+ RXDOUT12RXDOUT13+ RXDOUT13RXDOUT14+ RXDOUT14RXDOUT15+ RXDOUT15- Reserved for Factory Testing Si5100/Si5110-EVB 9 10 VDD Rev. 0.5 0805 4.7uF 0805 4.7uF JP6 C28 C30 1.8V 3.3V 0402 0.1uF C31 LPTM_N LLBK_N DLBK_N 0402 100pF C13 3216 10 uF + REFRATE LOS_N C14 3216 10 uF L1 Murata BLM31P601SG 3.3V 1.8V TXLOL_N RXLOL_N RXCLK2DIV_N LTR_N RXSQLCH_N J7F F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 J7B B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 VDD J7I J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 C26 0805 4.7uF 0805 4.7uF 0402 100pF C25 C12 0402 100pF 0402 0.1uF C9 0402 100pF C23 0402 0.1uF C21 0402 100pF C24 0402 0.1uF C22 Place Close to 5100 part on bottom of board C11 0402 0.1uF C7 J7D D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 Figure 9. Si5100-EVB Daughter Card Schematic (page 2 of 3) + FIFOERR_N FIFORST_N RESET_N RXCLK2DSBL_N C10 0402 0.1uF C27 VDD_IO 0402 0.1uF C8 0402 0.1uF C15 0402 0.1uF C29 RXCLK1DSBL_N J7J K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 3.3V J7H Si5100/Si5110-EVB Si5530_REFCLK- Si5530_REFCLK+ 0402 0.1uF 0402 0.1uF C17 C16 TXDIN3+ TXDIN3- TXDIN2+ TXDIN2- TXDIN1+ TXDIN1- TXDIN0+ TXDIN0- RXREFCLK+ RXREFCLK- RXDOUT3+ RXDOUT3- RXDOUT2+ RXDOUT2- RXDOUT1+ RXDOUT1- J7A R7 49.9 ohm 1%, 0603 R6 49.9 ohm 1%, 0603 RXREFCLK+ RXREFCLK0603 0.1uf C19 0603 0.1uf C18 TXDIN7+ TXDIN7- TXDIN6+ TXDIN6- TXDIN5+ TXDIN5- TXDIN4+ TXDIN4- RXCLK2+ RXCLK2- RXDOUT7+ RXDOUT7- RXDOUT6+ RXDOUT6- RXDOUT5+ RXDOUT5- RXDOUT4+ RXDOUT4- J7C C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 TXCLK16OUT+ TXCLK16OUT- TXDIN11+ TXDIN11- TXDIN10+ TXDIN10- TXDIN9+ TXDIN9- TXDIN8+ TXDIN8- RXCLK1+ RXCLK1- RXDOUT11+ RXDOUT11- RXDOUT10+ RXDOUT10- RXDOUT9+ RXDOUT9- RXDOUT8+ RXDOUT8- JP9 J7E E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 R16 POT 2 R15 POT 2 R14 POT 2 VREF Figure 10. Si5100-EVB Daughter Card Schematic (page 3 of 3) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 1 3 1 3 1 Rev. 0.5 3 RXDOUT0+ RXDOUT0- 2 2 2 JP12 1 HEADER 2X1 JP11 1 HEADER 2X1 JP10 1 HEADER 2X1 TXCLK16IN+ TXCLK16IN- TXDIN15+ TXDIN15- TXDIN14+ TXDIN14- TXDIN13+ TXDIN13- TXDIN12+ TXDIN12- RXDOUT15+ RXDOUT15- RXDOUT14+ RXDOUT14- RXDOUT13+ RXDOUT13- RXDOUT12+ RXDOUT12- J7G SLICELVL PHASEADJ LOSLVL G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 Si5100/Si5110-EVB 11 Si5100/Si5110-EVB Bill of Materials: Si5100-EVB Daughter Card Assembly Revision D-01 Si5100EVB Assy Rev D-01 BOM Reference C1,C2,C3,C4,C5,C6 C7,C8,C9,C15,C16,C17, C21,C22,C27,C29,C31 C10,C11,C12,C23,C24 C14,C13 C18,C19 C25,C26,C28,C30 JP1 JP2 JP4 JP6 JP7,JP8,JP9,JP10,JP11, JP12 J1,J2,J3,J4,J5,J6 J7 L1 R1,R2 R6,R7 R14,R15,R16 U1 PCB No Load SW1 R17 12 Description CAP, SM, 0.033 uF, 0402 CAP, SM, 0.1 uF, 0402 Manu Number C0402X7R160333KNE C0402X7R160104KNE Manufacturer VENKEL VENKEL CAP, SM, 100 pF, 0402 CAP, SM, 10 uF, TANTALUM, 3216 CAP, SM, 0.1 uF, 0603 CAP,SM,4.7UF,6.3V,X7R,0805 CONNECTOR, HEADER, 8X3 CONNECTOR, HEADER, 5X3 CONNECTOR, HEADER, 3X2 CONNECTOR, HEADER, 3X1 CONNECTOR, HEADER, 2X1 C0402C0G500-101JNE TA010TCM106KAR C0603X7R160-104KNE CEJMK212BJ475KG-T 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN VENKEL VENKEL VENKEL TAIYO YUDEN 3M 3M 3M 3M 3M CONNECTOR, SMA, NOTCH MOUNT CONN,SM,RECPT,MEGARRAY,300 POS BGA FERRITE,SM,600 OHM,1500mA RESISTOR, SM, 3.09K, 1%, 0603 RES,SM,49.9,1%,0603 POT,50K,10%,MULTITURN TRIMMER Si5100 Rev D Device Printed Circuit Board 82 SMA-S50-1-45/111 NE 84502-101 BLM31P601SGPT CR0603-16W-3091FT CR0603-16W-49R9FT T93YA-50K-10%-D06 Si5100 Rev D Si5100-EVB Daughter Card PCB Rev D HUBER SUHNER FCI/BERG MURATA VENKEL VENKEL VISHAY/DALE SILICON LABORATORIES SILICON LABORATORIES SWITCH, PUSH BUTTON, MINIATURE RES,SM,0,0603 101-0161 CR0603-16W-000T MOUSER VENKEL Rev. 0.5 Rev. 0.5 VDD_IO VDD_IO 2 8 5 23 20 17 14 11 JP1 2 11 8 5 HEADER 4X3 1 3 4 6 7 9 10 12 JP2 HEADER 8X3 1 3 4 6 7 9 10 12 13 15 16 18 19 21 22 24 RSVD_GND1 RSVD_GND0 RSVD_GND3 RSVD_GND2 BWSEL1 BWSEL0 REFSEL TXCLKDSBL TXMSBSEL TXSQLCH_N RXMSBSEL SLICEMODE J6 J4 R1 0603 3.09k 1% LOSLVL PHASEADJ SLICELVL DLBK_N LLBK_N LPTM_N LTR_N REFRATE RXCLK2DIV_N RXCLK1DSBL_N RXCLK2DSBL_N RXSQLCH_N RESET_N TXREFCLK+ TXREFCLK- TXCLK4IN+ TXCLK4IN- R2 0603 3.09k 1% RSVD_GND3 RSVD_GND2 RSVD_GND1 RSVD_GND0 RXMSBSEL TXCLKDSBL TXSQLCH_N TXMSBSEL BWSEL0 BWSEL1 SLICEMODE REFSEL K3 A4 B3 A2 A3 J4 J3 B6 A6 E3 J7 F3 C8 D3 C7 A5 D8 J8 J6 H4 H6 H3 C6 H7 H8 G8 C4 E10 F10 B1 C1 K8 K7 H5 TXREXT RXREXT LOSLVL PHASEADJ SLICELVL RSVD_GND3 RSVD_GND2 RSVD_GND1 RSVD_GND0 RESET_N REFSEL REFRATE RXCLK2DIV_N RXCLK1DSBL_N RXCLK2DSBL_N RXSQLCH_N RXMSBSEL TXCLKDSBL TXSQLCH_N TXMSBSEL BWSEL0 BWSEL1 SLICEMODE DLBK_N LLBK_N LPTM_N LTR_N REFCLK+ REFCLK- RXDIN+ RXDIN- TXCLK4IN+ TXCLK4IN- FIFORST_N TXDIN0+ TXDIN0TXDIN1+ TXDIN1TXDIN2+ TXDIN2TXDIN3+ TXDIN3- Si5110 U1 VDD VREF NC RXAMPMON RSVD_GND5 RSVD_GND4 RXLOL_N TXLOL_N LOS_N TXCLK4OUT+ TXCLK4OUT- TXDOUT+ TXDOUT- TXCLKOUTTXCLKOUT+ RXCLK2+ RXCLK2- RXCLK1+ RXCLK1- FIFOERR_N RXDOUT0+ RXDOUT0RXDOUT1+ RXDOUT1RXDOUT2+ RXDOUT2RXDOUT3+ RXDOUT3- B4 K2 B5 G3 C5 C3 K4 D2 K6 K5 H1 J1 F1 E1 A8 A7 B8 B7 J5 A10 B10 A9 B9 C10 D10 C9 D9 Figure 11. Si5110-EVB Daughter Card Schematic (page 1 of 3) 0402 0.1uF C6 0402 0.1uF C5 FIFORST_N J10 K10 J9 K9 G10 H10 G9 H9 G2 VDD_33 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 B2 C2 D1 E2 E7 E8 E9 F2 F7 F8 F9 G1 H2 J2 K1 TXDIN0+ TXDIN0TXDIN1+ TXDIN1TXDIN2+ TXDIN2TXDIN3+ TXDIN3- D4 D5 D6 D7 E4 E5 E6 F4 F5 F6 G4 G5 G6 G7 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD_IO VREF RXLOL_N TXLOL_N LOS_N 1 JP10 1 JP4 2 JP11 1 JP3 TXCLK4OUT+ TXCLK4OUT- RXCLK2+ RXCLK2- RXCLK1+ RXCLK1- FIFOERR_N RXDOUT0+ RXDOUT0RXDOUT1+ RXDOUT1RXDOUT2+ RXDOUT2RXDOUT3+ RXDOUT3- 2 HEADER 2X1 2 HEADER 2X1 2 HEADER 2X1 1 3 HEADER 1X3 VDD_IO J5 J3 J2 J1 0402 0.1uF C4 0402 0.1uF C3 0402 0.1uF C2 0402 0.1uF C1 Si5100/Si5110-EVB 13 14 Rev. 0.5 TXLOL_N RXLOL_N RXCLK2DIV_N LTR_N RXSQLCH_N LPTM_N LLBK_N DLBK_N RXCLK1DSBL_N B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 J7B D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 J7D FIFOERR_N FIFORST_N RESET_N RXCLK2DSBL_N J7I J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 VDD 0805 4.7uF C9 0805 4.7uF C10 JP5 1.8V 0402 0.1uF C11 3.3V 0402 0.1uF C12 0402 0.1uF C7 0402 0.1uF C13 0402 0.1uF C8 VDD_IO 0402 100pF C14 Figure 12. Si5110-EVB Daughter Card Schematic (page 2 of 3) J7J K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 J7H H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 + C15 3216 10 uF + REFRATE LOS_N C16 3216 10 uF L1 Murata BLM31P601SG 3.3V 1.8V J7F F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 Si5100/Si5110-EVB TXREFCLK- TXREFCLK+ 0603 0.1uF 0603 0.1uF C18 C17 TXDIN3+ TXDIN3- TXDIN2+ TXDIN2- TXDIN1+ TXDIN1- TXDIN0+ TXDIN0- RXREFCLK+ RXREFCLK- RXDOUT3+ RXDOUT3- RXDOUT2+ RXDOUT2- RXDOUT1+ RXDOUT1- RXDOUT0+ RXDOUT0- VDD A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 TXCLK4OUT+ TXCLK4OUT- RXCLK1+ RXCLK1- Rev. 0.5 0402 0.1uF 0402 0.1uF 0402 0.1uF C23 0402 0.1uF C24 0402 100pF C25 0402 100pF C26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 J7E 0402 100pF C27 0402 100pF C28 TXCLK4IN+ TXCLK4IN- 0805 4.7uF C29 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 J7G 0805 4.7uF C30 Figure 13. Si5110-EVB Daughter Card Schematic (page 3 of 3) C22 C21 Place Close to 5110 part on bottom of board RXCLK2+ RXCLK2- C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 J7C JP6 1 3 1 3 1 3 J7A 2 2 R7 49.9 ohm 1%, 0603 2 SLICELVL RXREFCLK0603 0.1uf C20 LOSLVL PHASEADJ RXREFCLK+ 0603 0.1uf C19 JP9 1 HEADER 2X1 JP8 1 HEADER 2X1 JP7 1 HEADER 2X1 R6 49.9 ohm 1%, 0603 R5 POT 50K 2 R4 POT 50K 2 R3 POT 50K 2 VREF Si5100/Si5110-EVB 15 Si5100/Si5110-EVB Bill of Materials: Si5110-EVB Daughter Card Assembly Revision D-01 Si5110 EVB Daughter Card Assy Rev. E-01 BOM Reference Part Desc Part Number Manufacturer C1,C2,C3,C4,C5,C6,C7,C8 C11,C12,C13,C21,C22,C23 C24 C9,C10,C29,C30 C14,C25,C26,C27,C28 C15,C16 C17,C18,C19,C20 JP1 JP5 JP4,JP6,JP7,JP8,JP9 J1,J2,J3,J4,J5,J6 J7 L1 R2,R1 R3,R4,R5 R6,R7 U1 PCB CAP,SM,0.1UF,16V,10%,X7R,0402 C0402X7R160-104KNE VENKEL CAP,SM,4.7UF,6.3V,X7R,0805 CAP,SM,100PF,50V,5%,C0G,0402 CAP,SM,10UF,10V,10%,TANTALUM,3216 CAP,SM,0.1UF,16V,20%,X7R,0603 CONN,HEADER,8X3 CONN,HEADER,3X1 CONN,HEADER,2X1 CONNECTOR, SMA, NOTCH MOUNT CONN,SM,RECPT,MEGARRAY,300 POS BGA FERRITE,SM,600 OHM,1500mA RES,SM,3.09K,1%,0603 POT,50K,10%,MULTITURN TRIMMER RES,SM,49.9,1%,0603 Si5110 Rev E Device Printed Circuit Board CEJMK212BJ475KG-T C0402C0G500-101JNE TA010TCM106KAR C0603X7R160-104KNE 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 82 SMA-S50-1-45/111 NE 84502-101 BLM31P601SGPT CR0603-16W-3091FT T93YA-50K-10%-D06 CR0603-16W-49R9FT Si5110-BC Si5110-EVB Daughter Card PCB Rev C TAIYO YUDEN VENKEL VENKEL VENKEL 3M 3M 3M HUBER SUHNER FCI/BERG MURATA VENKEL VISHAY/DALE VENKEL SILICON LABS SILICON LABS JP2 JP3, JP10 JP11 CONN,HEADER,4X3 CONN,HEADER,2X1 CONN,HEADER,1X3 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 3M 3M 3M 16 Rev. 0.5 TXCLK16OUT+ TXCLK16OUT- TP31 TP29 TP27 TP25 TP23 TP21 TP19 TP17 RXCLK1+ RXCLK1- In In In In In In In In Rev. 0.5 1.8V 3.3V DATA11DATA11+ DATA10DATA10+ DATA9DATA9+ DATA8DATA8+ JP10 MOTHERBOARD OUTPUT SIGNAL VOLTAGE SELECT 1 1 1 1 1 1 1 1 VMBO POS3 POS2 POS1 3 2 1 MKDSN 2,5/3-5,08 3.3V/1.8V J14 TXCLK16IN+ TXCLK16IN- TP32 TP30 TP28 TP26 TP24 TP22 TP20 TP18 In In In In In In In In 3.3V 1 1 1 1 1 1 1 1 1.8V DATA15DATA15+ DATA14DATA14+ DATA13DATA13+ DATA12DATA12+ POS3 POS2 POS1 3 2 1 MKDSN 2,5/3-5,08 -5.2V/5V J15 Meg-Array 300 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 J1G -5.2V 5V J12 J10 J8 J6 J4 J2 SMA SMA SMA SMA SMA SMA 0603, 0 ohm R15 0603, 0 ohm R13 0603, 0 ohm R11 0603, 0 ohm R9 0603, 0 ohm R7 0603, 0 ohm R5 Figure 14. Loopback Motherboard Schematic (page 1 of 2) Meg-Array 300 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 J1E Layout Note: All loopback data pairs have testpoints to facilitate probing access. RXCLK1- RXCLK1+ RXREFCLK- RXREFCLK+ TXCLK16IN- TXCLK16IN+ J13 J11 J9 J7 J5 J3 SMA SMA SMA SMA SMA SMA 0603, 0 ohm R16 0603, 0 ohm R14 0603, 0 ohm R12 0603, 0 ohm R10 0603, 0 ohm R8 0603, 0 ohm R6 TXCLK16OUT- TXCLK16OUT+ RXCLK2- RXCLK2+ TXREFCLK- TXREFCLK+ Si5100/Si5110-EVB 17 VMBO 18 5 2 JP4 LLBK_N DLBK_N 8 JP5 1 2 1 3 2 JP7 RXREFRATE Rev. 0.5 2 4 6 HEADER 3X2 1 3 5 JP8 RXLOL_N TXLOL_N LOS_N RXRESET_N 2 FIFORST_N 5 HEADER 2X3 1 3 4 6 HEADER 1X3 JP6 HEADER 1X2 FIFOERR_N LPTM_N 2 TXREFRATE 5 HEADER 3X3 1 3 4 6 7 9 HEADER 2X3 1 3 4 6 JP2 TXRESET_N TP15 TP13 TP11 TP9 TP7 TP5 TP3 TP1 1 1 1 1 1 1 1 1 TXLOL_N RXLOL_N RXCLK2DIV_N LTR_N RXSQLCH_N DATA3DATA3+ DATA2DATA2+ DATA1DATA1+ DATA0DATA0+ Meg-Array 300 Meg-Array 300 LOS_N 1 1 1 1 1 1 1 1 TXREFRATE RXREFRATE In In In In In In In In D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 J1D Meg-Array 300 TP16 TP14 TP12 TP10 TP8 TP6 TP4 TP2 RXCLK2+ RXCLK2- B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 J1B J1A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 1.8V 3.3V LPTM_N LLBK_N DLBK_N Meg-Array 300 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 J1F DATA7DATA7+ DATA6DATA6+ DATA5DATA5+ DATA4DATA4+ J1C Meg-Array 300 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 J1H Meg-Array 300 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 Figure 15. Loopback Motherboard Schematic (page 2 of 2) Placed together to allow jumpering of FIFOERR_N to FIFORST In In In In In In In In RXREFCLK+ RXREFCLK- TXREFCLK+ TXREFCLK- RXCLK1DSBL_N RXSQLCH_N 8 LTR_N RXCLK2DIV_N 14 RXCLK2DSBL_N 2 5 11 JP1 HEADER 5X3 1 3 4 6 7 9 10 12 13 15 10 11 13 15 17 2 4 6 8 U1 3 1x3 HEADER 2 1 2 2OE 2Y1 2Y2 2Y3 2Y4 1Y1 1Y2 1Y3 1Y4 1OE FIFOERR_N FIFORST_N TXRESET_N RXCLK2DSBL_N RXCLK1DSBL_N RXRESET_N LED ENABLE/ DISABLE JP3 1 3 GND 2A1 2A2 2A3 2A4 1A1 1A2 1A3 1A4 VCC 74LCX244T, 20TSSOP 20 Meg-Array 300 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J1I LOS_N TXLOL_N RXLOL_N FIFOERR_N 3.3V 19 9 7 5 3 18 16 14 12 1 5V R3 R4 D3 D4 0402 0.1uF C1 R2 D2 0402 100pF C2 365r 0603 365r 0603 365r 0603 365r 0603 -5.2V Meg-Array 300 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 J1J 74244 Decoupling Caps 3.3V R1 D1 3.3V Si5100/Si5110-EVB Si5100/Si5110-EVB Bill of Materials: Loopback Motherboard Assembly Revision A-01 Si5100 Loopback Motherboard Assy Rev A-01 Reference Part Desc Part Number Manufacturer C1 C2 D1,D2,D3,D4 JP1 JP2,JP7 JP3,JP6 JP4 JP5 JP8 JP10 J1 J2,J3,J4,J5,J6,J7,J8,J9, J10,J11,J12,J13 J15,J14 R1,R2,R3,R4 R5,R6,R7,R8,R9,R10,R11, R12,R13,R14,R15,R16 TP1,TP2,TP3,TP4,TP5,TP6, TP7,TP8,TP9,TP10,TP11, TP12,TP13,TP14,TP15,TP16, TP17,TP18,TP19,TP20,TP21, TP22,TP23,TP24,TP25,TP26, TP27,TP28,TP29,TP30,TP31, TP32 U1 PCB CAP,SM,0.1UF,16V,10%,X7R,0402 CAP,SM,100PF,50V,5%,C0G,0402 LED,SM,RED CONN,HEADER,5X3 CONN,HEADER,2X3 CONN,HEADER,1X3 CONN,HEADER,3X3 CONN,HEADER,1X2 CONN,HEADER,3X2 CONN,HEADER,3X1 CONNECTOR,SM,300 POS,BGA CONNECTOR,SMA,SURFACE MOUNT C0402X7R160-104KNE C0402C0G500-101JNE LN1271RAL-TR 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 2380-6121TN or 2340-6111TN 84500-02 142-0711-201 VENKEL VENKEL PANASONIC 3M 3M 3M 3M 3M 3M 3M BERG JOHNSON COMPONENTS CONNECTOR,POWER,3 POSITION RESISTOR, SM, 365 OHM, 1%, 0603 RES,SM,0,0402 1729021 CR0603-16W-121JT CR0402-16W-000T PHOENIX CONTACT VENKEL VENKEL TEST POINTS ON PCB N/A N/A IC,SM,74LCX244,20TSSOP Printed Circuit Board 74LCX244MTC Si5100-EVB Loopback Motherboard PCB Rev A FAIRCHILD SILICON LABORATORIES Rev. 0.5 19 20 Rev. 0.5 J12 J11 J10 J9 J8 J7 J6 J5 J4 J3 J2 J1 0603, 0 ohm R12 0603, 0 ohm R11 0603, 0 ohm R10 0603, 0 ohm R9 0603, 0 ohm R8 0603, 0 ohm R7 0603, 0 ohm R6 0603, 0 ohm R5 0603, 0 ohm R4 0603, 0 ohm R3 0603, 0 ohm R2 0603, 0 ohm R1 RXDOUT5- RXDOUT5+ RXDOUT4- RXDOUT4+ RXDOUT3- RXDOUT3+ RXDOUT2- RXDOUT2+ RXDOUT1- RXDOUT1+ RXDOUT0- RXDOUT0+ J24 J23 J22 J21 J20 J19 J18 J17 J16 J15 J14 J13 0603, 0 ohm R24 0603, 0 ohm R23 0603, 0 ohm R22 0603, 0 ohm R21 0603, 0 ohm R20 0603, 0 ohm R19 0603, 0 ohm R18 0603, 0 ohm R17 0603, 0 ohm R16 0603, 0 ohm R15 0603, 0 ohm R14 0603, 0 ohm R13 J36 J35 J34 J33 J32 J31 J30 J29 J28 J27 J26 J25 0603, 0 ohm R36 0603, 0 ohm R35 0603, 0 ohm R34 0603, 0 ohm R33 0603, 0 ohm R32 0603, 0 ohm R31 0603, 0 ohm R30 0603, 0 ohm R29 0603, 0 ohm R28 0603, 0 ohm R27 0603, 0 ohm R26 0603, 0 ohm R25 TXDIN1- TXDIN1+ TXDIN0- TXDIN0+ RXDOUT15- RXDOUT15+ RXDOUT14- RXDOUT14+ RXDOUT13- RXDOUT13+ RXDOUT12- RXDOUT12+ J48 J47 J46 J45 J44 J43 J42 J41 J40 J39 J38 J37 0603, 0 ohm R48 0603, 0 ohm R47 0603, 0 ohm R46 0603, 0 ohm R45 0603, 0 ohm R44 0603, 0 ohm R43 0603, 0 ohm R42 0603, 0 ohm R41 0603, 0 ohm R40 0603, 0 ohm R39 0603, 0 ohm R38 0603, 0 ohm R37 TXDIN7- TXDIN7+ TXDIN6- TXDIN6+ TXDIN5- TXDIN5+ TXDIN4- TXDIN4+ TXDIN3- TXDIN3+ TXDIN2- TXDIN2+ J60 J59 J58 J57 J56 J55 J54 J53 J52 J51 J50 J49 0603, 0 ohm R60 0603, 0 ohm R59 0603, 0 ohm R58 0603, 0 ohm R57 0603, 0 ohm R56 0603, 0 ohm R55 0603, 0 ohm R54 0603, 0 ohm R53 0603, 0 ohm R52 0603, 0 ohm R51 0603, 0 ohm R50 0603, 0 ohm R49 TXDIN13- TXDIN13+ TXDIN12- TXDIN12+ TXDIN11- TXDIN11+ TXDIN10- TXDIN10+ TXDIN9- TXDIN9+ TXDIN8- TXDIN8+ J72 J71 SMA J70 J69 J68 J67 J66 J65 J64 J63 J62 J61 SMA SMA SMA SMA SMA SMA SMA R61 0603, 0 ohm R72 0603, 0 ohm R71 0603, 0 ohm R70 0603, 0 ohm R69 0603, 0 ohm R68 0603, 0 ohm R67 0603, 0 ohm R66 0603, 0 ohm R65 0603, 0 ohm R64 0603, 0 ohm R63 0603, 0 ohm R62 0603, 0 ohm Figure 16. Full-Duplex Motherboard Schematic (page 1 of 2) RXDOUT11- RXDOUT11+ RXDOUT10- RXDOUT10+ RXDOUT9- RXDOUT9+ RXDOUT8- RXDOUT8+ RXDOUT7- RXDOUT7+ RXDOUT6- RXDOUT6+ J76 J75 J74 J73 RXCLK1- RXCLK1+ RXCLK2- RXCLK2+ Si5530_REFCLK- Si5530_REFCLK+ RXREFCLK- RXREFCLK+ TXDIN15- TXDIN15+ TXDIN14- TXDIN14+ SMA SMA SMA SMA 0603, 0 ohm R76 0603, 0 ohm R75 0603, 0 ohm R74 0603, 0 ohm R73 TXCLK16IN- TXCLK16IN+ TXCLK16OUT- TXCLK16OUT+ Si5100/Si5110-EVB 3.3V Rev. 0.5 JP3 LLBK_N DLBK_N 5 8 JP5 1 2 2 Si5530_REFRATE 5 JP4 2 4 6 POS3 POS2 POS1 3 2 1 HEADER 3X2 1 3 5 1.8V RXLOL_N TXLOL_N LOS_N Si5530_RESET_N FIFORST_N 2 HEADER 2X3 1 3 4 6 JP7 HEADER 2X3 1 3 JP6 HEADER 3X2 FIFOERR_N LPTM 2 HEADER 3X3 1 3 4 6 7 9 3.3V REFRATE MKDSN 2,5/3-5,08 J78 RESET_N 2 5 HEADER 2X3 1 3 4 6 JP2 Placed together to allow jumpering of FIFOERR to FIFORST RXCLK1DSBL_N RXSQLCH_N 8 LTR_N RXCLK2DIV_N 14 RXCLK2DSBL_N 2 5 11 JP1 HEADER 5X3 1 3 4 6 7 9 10 12 13 15 Meg-Array 300 Meg-Array 300 J77D D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 Meg-Array 300 LOS_N REFRATE TXDIN7+ TXDIN7- TXDIN6+ TXDIN6- TXDIN5+ TXDIN5- TXDIN4+ TXDIN4- RXCLK2+ RXCLK2- RXDOUT7+ RXDOUT7- RXDOUT6+ RXDOUT6- RXDOUT5+ RXDOUT5- RXDOUT4+ RXDOUT4- J77C 1.8V 3.3V Meg-Array 300 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 J77F Meg-Array 300 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 LPTM_N LLBK_N DLBK_N TXCLK16OUT+ TXCLK16OUT- TXDIN11+ TXDIN11- TXDIN10+ TXDIN10- TXDIN9+ TXDIN9- TXDIN8+ TXDIN8- RXCLK1+ RXCLK1- RXDOUT11+ RXDOUT11- RXDOUT10+ RXDOUT10- RXDOUT9+ RXDOUT9- RXDOUT8+ RXDOUT8- J77E Meg-Array 300 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 J77H Meg-Array 300 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 Figure 17. Full-Duplex Motherboard Schematic (page 2 of 2) TXLOL_N RXLOL_N RXCLK2DIV_N LTR_N RXSQLCH_N J77A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 J77B Si5530_REFCLK+ Si5530_REFCLK- TXDIN3+ TXDIN3- TXDIN2+ TXDIN2- TXDIN1+ TXDIN1- TXDIN0+ TXDIN0- RXREFCLK+ RXREFCLK- RXDOUT3+ RXDOUT3- RXDOUT2+ RXDOUT2- RXDOUT1+ RXDOUT1- RXDOUT0+ RXDOUT0- Meg-Array 300 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J77I TXCLK16IN+ TXCLK16IN- TXDIN15+ TXDIN15- TXDIN14+ TXDIN14- TXDIN13+ TXDIN13- TXDIN12+ TXDIN12- RXDOUT15+ RXDOUT15- RXDOUT14+ RXDOUT14- RXDOUT13+ RXDOUT13- RXDOUT12+ RXDOUT12- J77G FIFOERR_N FIFORST_N RESET_N Si5530_REFRATE RXCLK2DSBL_N Si5530_RESET_N RXCLK1DSBL_N Meg-Array 300 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 3.3V J77J Meg-Array 300 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 Si5100/Si5110-EVB 21 Si5100/Si5110-EVB Bill of Materials: Full-Duplex Motherboard Assembly Revision C-01 Si5100 Motherboard Assy Rev C-01 BOM Reference R1,R2,R3,R4,R5,R6,R7,R8, R9,R10,R11,R12,R13,R14, R15,R16,R17,R18,R19,R20, R21,R22,R23,R24,R25,R26, R27,R28,R29,R30,R31,R32, R33,R34,R35,R36,R37,R38, R39,R40,R41,R42,R43,R44, R45,R46,R47,R48,R49,R50, R51,R52,R53,R54,R55,R56, R57,R58,R59,R60,R61,R62, R63,R64,R65,R66,R67,R68, R69,R70,R71,R72,R73,R74, R75,R76 JP1 JP2,JP4,JP7 JP3 JP5 JP6 J1,J2,J3,J4,J5,J6,J7,J8, J9,J10,J11,J12,J13,J14, J15,J16,J17,J18,J19,J20, J21,J22,J23,J24,J25,J26, J27,J28,J29,J30,J31,J32, J33,J34,J35,J36,J37,J38, J39,J40,J41,J42,J43,J44, J45,J46,J47,J48,J49,J50, J51,J52,J53,J54,J55,J56, J57,J58,J59,J60,J61,J62, J63,J64,J65,J66,J67,J68, J69,J70,J71,J72,J73,J74, J75,J76 J77 J78 PCB 22 Part Desc RES,SM,0,0402 Part Number CR0402-16W-000T Manufacturer VENKEL CONNECTOR,HEADER,5X3 CONNECTOR,HEADER,3X2 CONNECTOR,HEADER,3X3 CONNECTOR,HEADER,2X1 CONNECTOR,HEADER,3X1 CONNECTOR,SMA,SURFACE MOUNT 2340-6111TN or 2380-6121TN 2340-6111TN or 2380-6121TN 2340-6111TN or 2380-6121TN 2340-6111TN or 2380-6121TN 2340-6111TN or 2380-6121TN 142-0711-201 3M 3M 3M 3M 3M JOHNSON COMPONENTS CONNECTOR,SM,300 POS,BGA CONNECTOR,POWER,3 POSITION Printed Circuit Board 84500-02 1729021 Si5100-EVB Motherboard PCB Rev C BERG PHOENIX CONTACT SILICON LABORATORIES Rev. 0.5 Si5100/Si5110-EVB Figure 18. Si5100-EVB Component Side Assembly (Daughter Card) Figure 19. Si5100-EVB Solder Side Assembly (Daughter Card) Rev. 0.5 23 Si5100/Si5110-EVB Figure 20. Si5100-EVB Layer 1—Component Side (Daughter Card) Figure 21. Si5100-EVB Layer 2—GND1 Plane (Daughter Card) 24 Rev. 0.5 Si5100/Si5110-EVB Figure 22. Si5100-EVB Layer 3—Signal Plane (Daughter Card) Figure 23. Si5100-EVB Layer 4—GND2 Plane (Daughter Card) Rev. 0.5 25 Si5100/Si5110-EVB Figure 24. Si5100-EVB Layer 5—VDD Plane (Daughter Card) Figure 25. Si5100-EVB Layer 6—Signal Plane (Daughter Card) 26 Rev. 0.5 Si5100/Si5110-EVB Figure 26. Si5100-EVB Layer 7—GND3 Plane (Daughter Card) Figure 27. Si5100-EVB Layer 8—Solder Side (Daughter Card) Rev. 0.5 27 Si5100/Si5110-EVB Figure 28. Si5110-EVB Component Side Assembly (Daughter Card) Figure 29. Si5110-EVB Solder Side Assembly (Daughter Card) 28 Rev. 0.5 Si5100/Si5110-EVB Figure 30. Si5110-EVB Layer 1—Component Side (Daughter Card) Figure 31. Si5110-EVB Layer 2—GND1 Plane (Daughter Card) Rev. 0.5 29 Si5100/Si5110-EVB Figure 32. Si5110-EVB Layer 3—Signal Plane (Daughter Card) Figure 33. Si5110-EVB Layer 4—GND2 Plane (Daughter Card) 30 Rev. 0.5 Si5100/Si5110-EVB Figure 34. Si5110-EVB Layer 5—VDD Plane (Daughter Card) Figure 35. Si5110-EVB Layer 6—Signal Plane (Daughter Card) Rev. 0.5 31 Si5100/Si5110-EVB Figure 36. Si5110-EVB Layer 7—GND3 Plane (Daughter Card) Figure 37. Si5110-EVB Layer 8—Solder Side (Daughter Card) 32 Rev. 0.5 Si5100/Si5110-EVB Figure 38. Component Side Assembly (Loopback Motherboard) Rev. 0.5 33 Si5100/Si5110-EVB Figure 39. Layer 1—Component Side (Loopback Motherboard) 34 Rev. 0.5 Si5100/Si5110-EVB Figure 40. Layer 2—GND1 Plane (Loopback Motherboard) Rev. 0.5 35 Si5100/Si5110-EVB Figure 41. Layer 3—Signal 1 Plane (Loopback Motherboard) 36 Rev. 0.5 Si5100/Si5110-EVB Figure 42. Layer 4—Signal 2 Plane (Loopback Motherboard) Rev. 0.5 37 Si5100/Si5110-EVB Figure 43. Layer 5—GND2 Plane (Loopback Motherboard) 38 Rev. 0.5 Si5100/Si5110-EVB Figure 44. Layer 6—Solder Side (Loopback Motherboard) Rev. 0.5 39 Si5100/Si5110-EVB Figure 45. Component Side Assembly (Optional Full-Duplex Motherboard) 40 Rev. 0.5 Si5100/Si5110-EVB Figure 46. Layer 1—Component Side (Optional Full-Duplex Motherboard) Rev. 0.5 41 Si5100/Si5110-EVB Figure 47. Layer 2—GND1 Plane (Optional Full-Duplex Motherboard) 42 Rev. 0.5 Si5100/Si5110-EVB Figure 48. Layer 3—Signal 1 Plane (Optional Full-Duplex Motherboard) Rev. 0.5 43 Si5100/Si5110-EVB Figure 49. Layer 4—Signal 2 Plane (Optional Full-Duplex Motherboard) 44 Rev. 0.5 Si5100/Si5110-EVB Figure 50. Layer 5—GND2 Plane (Optional Full-Duplex Motherboard) Rev. 0.5 45 Si5100/Si5110-EVB Figure 51. Layer 6—Solder Side (Optional Full-Duplex Motherboard) 46 Rev. 0.5 Si5100/Si5110-EVB Document Change List Revision 0.4 to Revision 0.5 Split Table 3 into Tables 3 and 4 to reflect differences in the actual PCBs for the Si5100 and Si5110 devices. Updated table references to reflect the changes in Table 3 and the creation of Table 4. Evaluation Board Assembly Revision History Si5100-EVB Daughter Card Revision History Assembly Level PCB Si5600 Device Assembly Notes C-01 Rev. B Rev. C Assemble per BOM rev C-01 D-01 Rev. B Rev. D Assemble per BOM rev D-01 Full-Duplex Motherboard Revision History Assembly Level PCB Assembly Notes A-01 Rev. A Assemble per BOM rev A-01 B-01 Rev. B Assemble per BOM rev B-01 C-01 Rev. C Assemble per BOM rev C-01 Loopback Motherboard Revision History Assembly Level PCB A-01 Rev. A Assembly Notes Assemble per BOM rev A-01 Rev. 0.5 47 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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