The Flexible C8051F700 High Speed ADC In this training, we are going to cover the ADC of the Silicon Labs C8051F700 MCU family with high pin count and capacitive sensing. 1 Agenda C8051F700 Introduction C8051F700 device features and benefits Analog to digital converter module overview Where to learn more 2 We are going to look at the new C8051F700 devices in this module. We will first take a look at the high level block diagram and then dive into the ADC peripheral. 2 Introducing The C8051F700 New patented capacitive touch sense True capacitance-to-digital converter Robust and responsive Easy to use Port I/O Configuration CIP-51 8051 Controller Core Digital Peripherals UART 16 k Byte Flash Memory Power On Reset High performance MCU 25 MHz 8051 CPU Best in class ADC 16 kB Flash 32 B data-EEPROM 256 Byte RAM Debug / Programming Hardware Peripheral Power 256 Byte XRAM PCA 32 Bytes EEPROM WDT SYSCLK VDD Timer 3 / RTC Regulator Core Power Precision Internal Oscillator GND XTAL1 XTAL2 SFR Bus SMBus Crossbar Control External Memory Interface User configured as digital or analog Digital Crossbar assigns pins Up to 32 capacitive touch sense inputs Available in TQFP64, TQFP48, and QFN48 (7x7 mm) packages P2 Control P4 / P5 Address External Clock Circuit Port 1 Drivers P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Port 2 Drivers ... Port 3 Drivers ... Port 4 Drivers ... Port 5 Drivers ... Port 6 Drivers ... P2.0 P2.7 P3.0 P3.7 P4.0 P4.7 P5.0 P5.7 P3 Data System Clock Configuration 54 multi-function GPIO Priority Crossbar Decoder SPI C2D P0.0 / VREF P0.1 / VGND P0.2 / XTAL1 P0.3 / XTAL2 P0.4 P0.5 P0.6 P0.7 Timers 0, 1, 2, 4 Reset C2CK/ RST Port 0 Drivers P6.0 P6.5 Analog Peripherals VREF VDD 10-bit 500ksps ADC Cap Touch Sense CDC A M U X VDD + - Comparator Temp Sensor 3 The new C8051F700 microcontroller family is a high pin count device enabling maximum flexibility while allowing customers to cost effectively add capacitive sensing. Here are a few highlights. The Silicon labs patented Capacitance to Digital converter enables very accurate, responsive and very reliable capacitive touch sense capability. The MCU has a high performance core. A fast 25 MIPS CPU, best in class analog functions, such as the accurate 10 bit analog to digital converter with internal voltage reference. 2% calibrated internal precision oscillator. Up to 16Kbytes of in system programmable flash and 32 bytes of EEPROM with 100,000 cycle endurance guaranteed which helps to reduce overall system cost. As usual with Silicon Labs MCUs, you don’t have to choose between I2C, SPI or UART. All are included as independent functions. There is also the timers and PCA as well as the external memory interface. Finally, there are 54 general purpose I/O pins. You can configure most inputs to be analog inputs to the ADC, comparator or capacitance to digital converter via software and digital functions can be enabled through a priority encoded crossbar that provides complete flexibility in the choice of peripheral usage. 3 The High Speed 10-bit ADC 4 Full Featured Integrated ADC 10 bit SAR ADC with integrated trackand-hold Can run in 8 bit mode for faster conversions Up to 500 ksps Up to 16 external single-ended inputs Programmable gain stage (0.5x or 1x) Flexible voltage reference options Integrated high speed VREF Internal regulator VDD External pin Internal or external start of conversion source Built-in temperature sensor Programmable window detector 5 Here is the block diagram of the ADC. We will cover the different aspects of this peripheral in the upcoming slides such as the analog front end and the window comparator. 5 Simple ADC Configuration Steps Step 1: Set port pins to analog inputs using the port I/O registers Step 2: Set the AMX0P value for the channel to be converted Step 3: Set the tracking mode, and start of conversion trigger source (Timer 2 in this example) using ADC0CN Step 4: Select the reference source (VDD used in this example) using REF0CN Step 5: Set the SAR clock speed (8.3 MHz used in this example) and set the desired gain using ADC0CF Step 6: Enable the interrupts and the ADC0 peripheral using ADC0CN Step 7: In the ISR clear the convert complete interrupt flag Step 8: Read the data 6 6 ADC Analog Front End Block Diagram *16 channel single-ended input MUX Integrated track and hold Programmable attenuation Gains of 1x or .5x Enables analog voltage inputs greater than the ADC reference voltage Example: Sensor input = 3.3 V Analog ADC Vref = 1.65 V 3.3 V/1.65 V = 0.5 Can program the gain setting to 0.5 to provide a full scale input to the ADC front end maximizes ADC dynamic range! Integrated temperature sensor 7 *Depends on the device/package The analog front end of the ADC module provides several distinct advantages for many applications. First is the input MUX that can handle up to 16 single ended channels. That feeds the amplifier that provides a unity gain or a 0.5 gain attenuation of the input signals. The is very useful for sensor interfacing and allows some high output voltage sensors to be connected directly to the MCU. By providing an attenuation gain setting and flexible VREF configurations the input signal can be set to the full scale voltage as defined by the internal VREF. The example shows a sensor with a 3.3V output. The programmable attenuation allows the maximum dynamic range of the ADC by scaling the input to the VREF voltage. 7 Flexible ADC Input Multiplexor Up to 16 external single-ended inputs Uses ports 0 and 1 as single ended analog inputs Temperature sensor input Voltage regulator VDD and ground as input sources Controlled via AMX0P[4:0] in the ADC0MX register to select the channel to be converted Example: AMX0P = 00001b selects P0.1 as the input 8 The input multiplexor allows the flexibility to choose the input pin used to source the input to the ADC. Ports 0 and 1 are used as the analog inputs thus providing our 16 channels. In addition to pin inputs some integrated functions are used as inputs to the ADC such as the temperature sensor, voltage regulator and the VDD supply voltage. 8 Analog Input Pin Configuration Most port pins can be used for analog inputs Port pin configured as analog using PxMDIN register bits set to a ‘0’ The output mode is selected to be open drain using the PxMDOUT bit set to a ‘0’ The port latch bit should be set to a ‘1’ PxMDIN PxMDOUT Px Description 0 0 1 Analog Input 9 Digital and analog resources are available through 64 I/O pins. Each of the Port pins P0.0P2.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog function as shown. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. The state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings. To configure the inputs as analog inputs the PxMDIN and PxMDOUT bits should be set to a ‘0’ and the port latch bits (Px) should be set to a ‘1’. These settings disable the output drivers as well as the weak pull-up and the digital input buffer. 9 Crossbar Pin Assignment Using Config Wizard Pins configured as analog should have their pins skipped by the crossbar Generated Code for PxSKIP 10 This diagram is taken from the F700 family for reference. The crossbar works on a predefined priority order to allocate the digital peripheral I/O. When one of the analog functions are used and tied to a pin we should set the PxSKIP bit for the pin so the crossbar does not allocate a peripheral input or output signal to the same pin. 10 Common Issue: Analog I/O Set-up Common Issue: The I/O pins of the MCU are configured improperly MCU pins can be configured for digital or analog inputs For digital inputs the pins provide a weak pull-up enabled by default What it looks like: The pin is disturbing the analog input we are trying to measure Solution: Configure the I/O to be an analog input to disable the weak pull-up 11 Each of the I/O pins to be used for analog inputs need to be configured to turn off the weak pull-up. By configuring the pins as analog inputs the logic for the I/O will disable the weak pull-up and isolate the pin for the ADC measurements. 11 Simple ADC Configuration Steps Step 1: Set port pins to analog inputs using the port I/O registers Step 2: Set the AMX0P value for the channel to be converted Step 3: Set the tracking mode, and start of conversion trigger source (Timer 2 in this example) using ADC0CN Step 4: Select the reference source (VDD used in this example) using REF0CN Step 5: Set the SAR clock speed (8.3 MHz used in this example) and set the desired gain using ADC0CF Step 6: Enable the interrupts and the ADC0 peripheral using ADC0CN Step 7: In the ISR clear the convert complete interrupt flag Step 8: Read the data 12 12 SAR ADC: Tracking and Conversion Conversion Start CONV. TRACKING Data Ready CONVERTING TRACKING Tsettling Source Resistance (RSRC) Mux Resistance (RMUX) Converting Phase To Comparator AIN+ Tracking Phase Sampling Capacitor (CSAMPLE) VC VIN The sampling circuit of the ADC VERR looks like an RC low-pass filter. 13 0 t Note here that during the tracking phase, the sampling cap is being charged and the frontend of the ADC looks like an RC low-pass filter. Ideally, the switch will be in the tracking position long enough to charge the sampling cap to the same voltage as the source. 13 Tracking Using an External Trigger The AD0TM bit in register ADC0CN enables "delayed conversions“ The actual conversion start is delayed by three SAR clock cycles ADC continues to track the input When the CNVSTR pin is used to initiate conversions ADC0 will track when AD0TM bit in ADC0CN is logic 1 ADC0 will track when AD0TM bit in ADC0CN is logic 0 and CNVSTR is held low 14 The delayed trigger provides a means to provide extra tracking time to allow the input to settle to the desired accuracy. In many cases the 3 SAR clocks are all that is needed to provide adequate settling time. For an external trigger to the ADC the CNVSTR input is used. For the case where the AD0TM bit is ‘0’, the tracking of the input starts with the CNVSTR input being driven low and the conversion starts when the input returns high as shown in the diagram. With the AD0TM bit set to ‘1’ then the ADC continually tracks the input while CNVSTR is low and adds 3 extra SAR clocks of tracking time after CNVSTR goes high prior to initiating the conversion. 14 Tracking Using an Internal Trigger The AD0TM bit in register ADC0CN enables "delayed conversions“ AD0TM = 1: The actual conversion start is delayed by three SAR clock cycles AD0TM = 0: The conversion starts immediately For internal start-of-conversion sources ADC will track anytime it is not performing a conversion 15 The ADC can be triggered by multiple sources including Timers 0, 1 and 2 overflows. The internal track mode operates in the same manner as the external trigger source using the AD0TM bit. When set, the input tracking adds three extra SAR clocks to enable the input to settle to the desired accuracy. When cleared, the input continually tracks while a conversion is not in progress. 15 ADC Input Settling Time A minimum tracking time is required before each conversion to ensure that an accurate conversion is performed Tracking time is determined by any series impedance AMUX0 resistance The ADC0 sampling capacitance External series resistance Settling time to desired accuracy is approximated by the equation: 2n t ln xRTOTAL CSAMPLE SA Where n is the number of bits (10) SA is the settling accuracy (i.e..25 for ¼ LSB) RTOTAL is the total series resistance CSAMPLE is the capacitance of the ADC array Example: 210 RMUX = 5 KΩ x7 Kx30 pF t ln CSAMPLE = 30 pF .25 RINPUT = 2 KΩ 1.75s 16 The input settling time is highly dependent on the input source impedance as well as the input impedance of the ADC itself. The settling time to the desired accuracy can be represented by the equation listed above. In the equation SA is the settling accuracy or how close to the actual value, in fractions of an LSB, the input settles to its final value. In the example we use .25 as the SA value meaning we want our input to settle to within .25 LSBs of the input. If all of the tracking time requirements are met then the AC and DC performance of the ADC can be realized. 16 Common Issue: SAR Settling Time Common Issue: inadequate settling time The ADC connects the sampling cap to the input circuitry during the tracking phase of the conversion. Settling time for the input circuitry must be included during the tracking phase. What it looks like: Inadequate settling time will lead to measurement errors, especially when multiplexing channels Inadequate settling time can look like “crosstalk” between mux channels Solution: The ideal time to switch a mux is during the conversion, when the ADC is not tracking the input. This allows the maximum settling time for the ADC input. Conversion Start CONV. TRACKING Data Ready CONVERTING TRACKING Tsettling 17 Settling time should be observed regardless of whether the conversions are all being taken on a single channel or muxed through multiple channels. “Crosstalk” is actually any signal on a different mux channel which affects readings on the current channel. It would be the same regardless of whether the mux were switching channels. 17 ADC Starting a Conversion Conversions initiated in one of six ways Determined by programmed state of the ADC0 Start of Conversion Mode bits (AD0CM2–0) in register ADC0CN Writing a 1 to AD0BUSY provides software control for on-demand conversions During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete The falling edge of AD0BUSY triggers an interrupt One of four timer inputs can be used to trigger ADC conversions An external input can be used to trigger ADC conversions using the CNVSTR pin 18 The ADC provides a multiplexer in order to select different convert start sources. Writing the AD0BUSY bit can be used via software to generate an ADC conversion on demand. The timers can be used to generate periodic conversions. Timer 3 has the capability to run from the external oscillator if needed. 18 Simple ADC Configuration Steps Step 1: Set port pins to analog inputs using the port I/O registers Step 2: Set the AMX0P value for the channel to be converted Step 3: Set the tracking mode, and start of conversion trigger source (Timer 2 in this example) using ADC0CN Step 4: Select the reference source (VDD used in this example) using REF0CN Step 5: Set the SAR clock speed (8.3 MHz used in this example) and set the desired gain using ADC0CF Step 6: Enable the interrupts and the ADC0 peripheral using ADC0CN Step 7: In the ISR clear the convert complete interrupt flag Step 8: Read the data 19 19 Internal Voltage Reference (VREF) The Voltage reference multiplexer is configurable through REF0CN: Externally connected voltage reference On-chip high-speed reference voltage generator Internal 1.8 V regulator The VDD power supply voltage Temperature stable bandgap voltage reference generator 20 The internal high-speed voltage reference is used by the ADC and its output is 1.65V. The references sources available to the converter are derived from the internal multiplexor. The possible sources are the internal reference, an external reference, the internal 1.8V regulator or the VDD supply voltage. These sources combined with the programmable gain provides a very flexible sampling system. 20 ADC VREF and Gain Example Design goals Monitor parameters from multiple sensors each with a different output voltage Maximize the dynamic range of the ADC Sensor 1 3.3 V Max. Sensor 2 1/.5 ADC 1.8 V Max SMBus UART SPI Sensor 3 VREF 3.3 V Max. Vreg Sensor 4 1.65 V Max. MCU ADC Advantages Gain of 1x or 0.5x and ADC reference voltage options maximize the dynamic range of the ADC 21 Here is a real example highlighting how the gain settings along with the Vref options are used to maximize the ADC dynamic range. If the VDD = 3.3V, the above example can be realized by changing the Vref source to VDD and a gain of 1. It can also be realized by setting the gain to 0.5 and changing the Vref to the internal high speed voltage reference. 21 Common Issue: VREF Voltage Common Issue: forgetting to set the VREF voltage Vref sets the maximum input voltage that converter can sample An improperly configured Vref voltage may lead to measurement errors since the input voltage may always exceed the VREF voltage What it looks like: The ADC measured values always equals the maximum value Solution: Configure VREF such that the maximum analog input is equal to or below the VREF voltage. LSB VREF 2N V MaxVin 2 N 1 REF N 2 For a 10 bit converter: V MaxVin 1023 REF 1024 22 In many cases the Vref voltage gets set improperly. When the Vref voltage is lower than the full scale analog input voltage then either all or a portion of the ADC counts will appear to be stuck high. For example, let’s assume the maximum analog input voltage is 3.0V and the Vref voltage is set to 1.65V or not set at all and our gain is set to 1. The ADC counts for a 10 bit converter will be 0x3FF when the input exceeds the 1.65V reference. 22 Simple ADC Configuration Steps Step 1: Set port pins to analog inputs using the port I/O registers Step 2: Set the AMX0P value for the channel to be converted Step 3: Set the tracking mode, and start of conversion trigger source (Timer 2 in this example) using ADC0CN Step 4: Select the reference source (VDD used in this example) using REF0CN Step 5: Set the SAR clock speed (8.3 MHz used in this example) and set the desired gain using ADC0CF Step 6: Enable the interrupts and the ADC0 peripheral using ADC0CN Step 7: In the ISR clear the convert complete interrupt flag Step 8: Read the data 23 23 SAR ADC: Conversion Time The conversion time required by the ADC is determined by the speed of the SAR clock and the 8/10 bit mode selection bit The SAR clock speed does not determine output word rate (this is determined by the start-of-conversion source) 24 24 Common Issue: Conversion Time Common Issue: SAR clock too fast Running a SAR with a clock that is too fast will lead to settling time problems with the internal SAR DAC What it looks like: This will generally look like a linearity or missing code problem Solution: The SAR Clock should be as close to the maximum specification as possible, but not faster. This minimizes conversion time and allows for maximum input tracking time. Example: SYSCLK = 24.5 MHz Desired SAR clock = 8.33 MHz ADCOSC = SYSCLK/CLKSAR – 1 = 24.5 MHz/8.33 MHz – 1 = 0x02 25 One of the most common sources of error for the ADC is that the SAR clock is set too fast. The example shows the proper setting using the max SAR clock speed specified for the converter. 25 Simple ADC Configuration Steps Step 1: Set port pins to analog inputs using the port I/O registers Step 2: Set the AMX0P value for the channel to be converted Step 3: Set the tracking mode, and start of conversion trigger source (Timer 2 in this example) using ADC0CN Step 4: Select the reference source (VDD used in this example) using REF0CN Step 5: Set the SAR clock speed (8.3MHz used in this example) and set the desired gain using ADC0CF Step 6: Enable the interrupts and the ADC0 peripheral using ADC0CN Step 7: In the ISR clear the convert complete interrupt flag Step 8: Read the data 26 26 ADC Interrupts ADC conversion complete interrupt (AD0INT) ADC window comparator interrupt (AD0WINT) Continuously compares the ADC0 output registers to user-programmed limits in hardware and generates a unique interrupt based on test conditions (AD0WINT) Saves code space Saves CPU bandwidth Faster response time AD0INT Composed of “greater-than” and “lessthan” registers Indicates when measured data is inside or outside of the user-programmed limits 27 The AD0INT output of the ADC is used to determine the end of conversion. When enabled it will generate an interrupt to the CPU. The window comparator is used to compare single samples or the accumulated samples to preset values. The window comparator is driven by two sets of registers. One for less than measurements and one for greater than measurements. The comparisons are performed on 16 bit values. For single samples only the lower 12 bits would be used (for right justified data). However, if we are using the hardware accumulator to add samples together our data will increase in the number of bits we use for the comparison. The interrupt from the window comparator is only generated after all of the hardware accumulations have completed (1, 4, 8 or 16). We will take a look at how these are used in the next slide. 27 ADC Programmable Window Detector The programmable window detector interrupts the CPU when the ADC0 output is greater than or less than the user-programmed value Different window functions can be realized Comparisons can be made using the hardware accumulated values ADC0, ADC0LT and ADC0GT are all 16 bit registers ADC Counts 0x3FF 28 ADC0 > ADC0GT Interrupt generated in this range ADC0 > ADC0LT Interrupt not generated in this range ADC0GT ADC0LT ADC0LT < ADC0 < ADC0GT No interrupt generated in this range ADC0GT < ADC0 < ADC0LT Interrupt generated in this range ADC0LT ADC0GT ADC0 < ADC0LT Interrupt generated in this range ADC0 < ADC0GT Interrupt not generated in this range 0x000 The ADC window comparator is useful when the system only needs to act upon a certain alarm condition. For example, if we are monitoring motor current and we want the system to notify the CPU when the current passes a certain threshold set to protect the motor from stall conditions we could set up the window comparator as shown above on the left. Another example would be a monitor for the temperature sensor to provide an output when the temperature is too high or too low. For this scenario we could set the registers as shown in the figure on the right. Notice that the values set in the ADC0LT and ADC0GT registers determines how the window function operates. 28 ADC0 Configuration: ADC0CF Register Bits 7:3 Name Function AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in the ADC specification table. ADCOSC 2 AD0LJST SYSCLK 1 CLK SAR ADC0 Left Justify Select 0: Data in ADC0H:ADC0L registers are right-justified 1: Data in ADC0H:ADC0L registers are left-justified Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0) 1 AD08BE 8-Bit Mode Enable. 0: ADC operates in 10-bit mode (normal) 1: ADC operates in 8-bit mode Note: When AD08BE is set to 1, the AD0LJST bit is ignored 0 AMP0GN0 ADC Gain Control Bit 0: Gain = 0.5 1: Gain = 1 29 We won’t go through all of these bits, however, we may just highlight a few. The SAR conversion clock is used an important setting since it determines the settling time allowed by the internal DACs for the SAR conversion. If the SAR clock is too fast, nonlinearities, including missing codes, may appear in the ADC output. 29 AD0 Control: AD0CN Register Bits 7 Name Function AD0EN ADC0 Enable Bit 0: ADC0 Disabled. ADC0 is in low-power shutdown 1: ADC0 Enabled. ADC0 is active and ready for data conversions 6 AD0TM ADC0 Track Mode Bit 0: Normal Track Mode 1: Delayed Track Mode 5 AD0INT ADC0 Conversion Complete Interrupt Flag 0: ADC0 has not completed a data conversion since AD0INT was last cleared 1: ADC0 has completed a data conversion 4 AD0BUSY ADC0 Busy Bit Read: 0: ADC0 conversion is not in progress 1: ADC0 conversion is in progress 3 AD0WINT Write: 0: No effect 1: Initiates ADC0 conversion if ADC0CM[2:0] = 000b. ADC0 Window Compare Interrupt Flag 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared 1: ADC0 Window Comparison Data match has occurred 2:0 AD0CM[2:0] ADC0 Start of Conversion Mode Select 000: ADC0 start-of-conversion source is write of 1 to AD0BUSY 001: ADC0 start-of-conversion source is overflow of Timer 0 010: ADC0 start-of-conversion source is overflow of Timer 2 011: ADC0 start-of-conversion source is overflow of Timer 1 100: ADC0 start-of-conversion source is rising edge of external CNVSTR 101: ADC0 start-of-conversion source is overflow of Timer 3 11x: Reserved 30 In the control register we have the setting for the track mode bit we discussed previously as well as the conversion trigger source. AD0BUSY is also a part of this register for initiating a conversion on demand from software. The AD0INT bit should be used by software to determine when a new conversion has completed (instead of AD0BUSY). The AD0WINT bit indicates when an ADC result has passed the Window Comparator decision logic. Both AD0INT and AD0WINT are set by hardware and must be cleared by software. 30 ADC0 Code: I/O and ADC0 Configuration Step 1: Set port pins to analog inputs using the port I/O registers Step 2: Set the AMX0P value for the channel to be converted Step 3: Set the tracking mode, and start of conversion trigger source (Timer 2 in this example) using ADC0CN Step 4: Select the reference source (VDD used in this example) using REF0CN Step 5: Set the SAR clock speed (8.3 MHz used in this example) and set the desired gain using ADC0CF Step 6: Enable the interrupts and the ADC0 peripheral using ADC0CN Step 7: In the ISR clear the convert complete interrupt flag Step 8: Read the data Code examples can be found in the tools directory: Silabs/MCU/examples\C8051F70x_71x 31 Now we can take a look at some sample code and the steps required to configure and use the ADC in the device. Take a moment to look at the steps to familiarize yourself with how to use the peripheral. 31 C8051F700 Product Family Selection 25 FLASH Memory (bytes) 15kB Data EEPROM (bytes) 32 Serial Buses Timers (16-bit) PCA Chnls Internal Osc 512 Digital Port I/O Pins 54 UART, I2C, SPI 4 3 2% Cap Touch Sense Y C8051F701-GQ 25 15kB 32 512 54 UART, I2C, SPI 4 3 2% Y - C8051F702-GQ 25 16kB - 512 54 UART, I2C, SPI 4 3 2% Y 10-Bit C8051F703-GQ 25 C8051F704-GQ 25 16kB - 512 54 UART, I2C, SPI 4 3 2% Y - 15kB 32 512 39 UART, I2C, SPI 4 3 2% Y C8051F704-GM 25 15kB 32 512 39 UART, I2C, SPI 4 3 2% C8051F705-GQ 25 15kB 32 512 39 UART, I2C, SPI 4 3 C8051F705-GM 25 15kB 32 512 39 UART, I2C, SPI 4 3 Part Number MIPS (peak) C8051F700-GQ RAM (bytes) ADC0 Temp Sensor VREF Comp. Package 10-Bit Y Y 1 QFP64 1 QFP64 1 QFP64 1 QFP64 Y Y 10-Bit Y Y 1 QFP48 Y 10-Bit Y Y 1 QFN48 2% Y - 1 QFP48 2% Y - 1 QFN48 C8051F706-GQ 25 16kB - 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP48 C8051F706-GM 25 16kB - 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFN48 C8051F707-GQ 25 16kB - 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFP48 C8051F707-GM 25 16kB - 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFN48 C8051F708-GQ 25 8kB 32 512 54 UART, I2C, SPI 4 3 2% Y 10-Bit C8051F709-GQ 25 8kB 32 512 54 UART, I2C, SPI 4 3 2% Y - C8051F710-GQ 25 8kB - 512 54 UART, I2C, SPI 4 3 2% Y 10-Bit C8051F711-GQ 25 8kB - 512 54 UART, I2C, SPI 4 3 2% Y - Y Y Y Y 1 QFP64 1 QFP64 1 QFP64 1 QFP64 C8051F712-GQ 25 8kB 32 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP48 C8051F712-GM 25 8kB 32 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFN48 C8051F713-GQ 25 8kB 32 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFP48 C8051F713-GM 25 8kB 32 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFN48 C8051F714-GQ 25 8kB - 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFP48 C8051F714-GM 25 8kB - 512 39 UART, I2C, SPI 4 3 2% Y 10-Bit Y Y 1 QFN48 C8051F715-GQ 25 8kB - 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFP48 C8051F715-GM 25 8kB - 512 39 UART, I2C, SPI 4 3 2% Y - 1 QFN48 24 Unique part numbers! Choice of flash size Can select EEPROM (in larger flash size, EEPROM is traded for 1 kB flash) ADC or no-ADC Capacitive touch sense option 32 32 Learn More at the Education Resource Center Visit the Silicon Labs website to get more information on Silicon Labs products, technologies and tools. The Education Resource Center training modules are designed to get designers up and running quickly on the peripherals and tools needed to get the design done. http://www.silabs.com/ERC http://www.silabs.com/mcu AN118 - Improving ADC Resolution by Oversampling and Averaging AN119 - Calculating Settling Time For Switched Capacitor ADC's To provide feedback on this or any other training go to: http://www.silabs.com/ERC/feedback 33 Visit the Silicon Labs Education Resource Center to learn more about the MCU products. 33 www.silabs.com/MCU 34