Si5345C Datasheet Addendum Device Configuration Summary for Si5345C-B-GM Page 1 of 6 10-Output Low Phase Noise Jitter Attenuating Clock Generator Overview ======== Part: Design ID: Created By: Timestamp: Si5345 5345BP2 ClockBuilder Pro v1.7 [2015-03-26] 2015-03-26 09:24:52 GMT-05:00 Device Grade ============ Device Grade --------Si5345A Si5345B Si5345C* Si5345D Output Clock Frequency Range ----------------100 Hz to 712.5 MHz 100 Hz to 350 MHz 100 Hz to 712.5 MHz 100 Hz to 350 MHz Supported Frequency Synthesis Modes (Typical Jitter) ------------------------------------------Integer (<100 fs) and fractional (< 150 fs) " Integer only (< 100 fs) " * Device Grade Design ====== Host Interface: I/O Power Supply: VDD (Core) SPI Mode: 4-Wire I2C Address Range: 104d to 107d / 0x68 to 0x6B (selected via A0/A1 pins) XA/XB: 48 MHz (XTAL - Crystal) Inputs: IN0: IN1: IN2: IN3: Unused Unused Unused Unused Outputs: OUT0: OUT1: OUT2: OUT3: OUT4: OUT5: OUT6: OUT7: OUT8: OUT9: Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Frequency Plan ============== No plan Settings ======== Location -----------0x000B[0:6] 0x0016[1] 0x0017[0] Setting Name -------------------I2C_ADDR LOL_ON_HOLD SYSINCAL_INTR_MSK Decimal Value ------------104 1 0 Hex Value ---------------0x68 0x1 0x0 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5345C Datasheet Addendum Device Configuration Summary for Si5345C-B-GM Page 2 of 6 0x0017[1] 0x0017[5] 0x0018[0:3] 0x0018[4:7] 0x0019[1] 0x0019[5] 0x001A[5] 0x002B[3] 0x002B[5] 0x002C[0:3] 0x002C[4] 0x002D[0:1] 0x002D[2:3] 0x002D[4:5] 0x002D[6:7] 0x002E[0:15] 0x0030[0:15] 0x0032[0:15] 0x0034[0:15] 0x0036[0:15] 0x0038[0:15] 0x003A[0:15] 0x003C[0:15] 0x003F[0:3] 0x003F[4:7] 0x0040[0:2] 0x0041[0:4] 0x0042[0:4] 0x0043[0:4] 0x0044[0:4] 0x0045[0:4] 0x0046[0:7] 0x0047[0:7] 0x0048[0:7] 0x0049[0:7] 0x004A[0:7] 0x004B[0:7] 0x004C[0:7] 0x004D[0:7] 0x004E[0:2] 0x004E[4:6] 0x004F[0:2] 0x004F[4:6] 0x0051[0:3] 0x0052[0:3] 0x0053[0:3] 0x0054[0:3] 0x0055[0:3] 0x0056[0:3] 0x0057[0:3] 0x0058[0:3] 0x0059[0:1] 0x0059[2:3] 0x0059[4:5] 0x0059[6:7] 0x005A[0:25] 0x005E[0:25] 0x0062[0:25] 0x0066[0:25] 0x0092[1] 0x0093[4:7] 0x0095[2:3] 0x0096[4:7] 0x0098[4:7] LOSXAXB_INTR_MSK SMB_TMOUT_INTR_MSK LOS_INTR_MSK OOF_INTR_MSK LOL_INTR_MSK HOLD_INTR_MSK CAL_INTR_MSK SPI_3WIRE AUTO_NDIV_UPDATE LOS_EN LOSXAXB_DIS LOS0_VAL_TIME LOS1_VAL_TIME LOS2_VAL_TIME LOS3_VAL_TIME LOS0_TRG_THR LOS1_TRG_THR LOS2_TRG_THR LOS3_TRG_THR LOS0_CLR_THR LOS1_CLR_THR LOS2_CLR_THR LOS3_CLR_THR OOF_EN FAST_OOF_EN OOF_REF_SEL OOF0_DIV_SEL OOF1_DIV_SEL OOF2_DIV_SEL OOF3_DIV_SEL OOFXO_DIV_SEL OOF0_SET_THR OOF1_SET_THR OOF2_SET_THR OOF3_SET_THR OOF0_CLR_THR OOF1_CLR_THR OOF2_CLR_THR OOF3_CLR_THR OOF0_DETWIN_SEL OOF1_DETWIN_SEL OOF2_DETWIN_SEL OOF3_DETWIN_SEL FAST_OOF0_SET_THR FAST_OOF1_SET_THR FAST_OOF2_SET_THR FAST_OOF3_SET_THR FAST_OOF0_CLR_THR FAST_OOF1_CLR_THR FAST_OOF2_CLR_THR FAST_OOF3_CLR_THR FAST_OOF0_DETWIN_SEL FAST_OOF1_DETWIN_SEL FAST_OOF2_DETWIN_SEL FAST_OOF3_DETWIN_SEL OOF0_RATIO_REF OOF1_RATIO_REF OOF2_RATIO_REF OOF3_RATIO_REF LOL_FST_EN LOL_FST_DETWIN_SEL LOL_FST_VALWIN_SEL LOL_FST_SET_THR_SEL LOL_FST_CLR_THR_SEL 0 0 15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0xF 0xF 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0 0x0 0x4 0x00 0x00 0x00 0x00 0x0C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0000000 0x0000000 0x0000000 0x0000000 0x0 0x0 0x0 0x0 0x0 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5345C Datasheet Addendum Device Configuration Summary for Si5345C-B-GM Page 3 of 6 0x009A[1] 0x009B[4:7] 0x009D[2:3] 0x009E[4:7] 0x00A0[4:7] 0x00A2[1] 0x00A8[0:34] 0x0102[0] 0x0108[0] 0x0108[1] 0x0108[2] 0x0109[0:2] 0x0109[3] 0x0109[4:5] 0x0109[6:7] 0x010A[0:3] 0x010A[4:6] 0x010B[0:2] 0x010B[6:7] 0x010D[0] 0x010D[1] 0x010D[2] 0x010E[0:2] 0x010E[3] 0x010E[4:5] 0x010E[6:7] 0x010F[0:3] 0x010F[4:6] 0x0110[0:2] 0x0110[6:7] 0x0112[0] 0x0112[1] 0x0112[2] 0x0113[0:2] 0x0113[3] 0x0113[4:5] 0x0113[6:7] 0x0114[0:3] 0x0114[4:6] 0x0115[0:2] 0x0115[6:7] 0x0117[0] 0x0117[1] 0x0117[2] 0x0118[0:2] 0x0118[3] 0x0118[4:5] 0x0118[6:7] 0x0119[0:3] 0x0119[4:6] 0x011A[0:2] 0x011A[6:7] 0x011C[0] 0x011C[1] 0x011C[2] 0x011D[0:2] 0x011D[3] 0x011D[4:5] 0x011D[6:7] 0x011E[0:3] 0x011E[4:6] 0x011F[0:2] 0x011F[6:7] 0x0121[0] LOL_SLOW_EN_PLL LOL_SLW_DETWIN_SEL LOL_SLW_VALWIN_SEL LOL_SLW_SET_THR LOL_SLW_CLR_THR LOL_TIMER_EN LOL_CLR_DELAY OUTALL_DISABLE_LOW OUT0_PDN OUT0_OE OUT0_RDIV_FORCE2 OUT0_FORMAT OUT0_SYNC_EN OUT0_DIS_STATE OUT0_CMOS_DRV OUT0_CM OUT0_AMPL OUT0_MUX_SEL OUT0_INV OUT1_PDN OUT1_OE OUT1_RDIV_FORCE2 OUT1_FORMAT OUT1_SYNC_EN OUT1_DIS_STATE OUT1_CMOS_DRV OUT1_CM OUT1_AMPL OUT1_MUX_SEL OUT1_INV OUT2_PDN OUT2_OE OUT2_RDIV_FORCE2 OUT2_FORMAT OUT2_SYNC_EN OUT2_DIS_STATE OUT2_CMOS_DRV OUT2_CM OUT2_AMPL OUT2_MUX_SEL OUT2_INV OUT3_PDN OUT3_OE OUT3_RDIV_FORCE2 OUT3_FORMAT OUT3_SYNC_EN OUT3_DIS_STATE OUT3_CMOS_DRV OUT3_CM OUT3_AMPL OUT3_MUX_SEL OUT3_INV OUT4_PDN OUT4_OE OUT4_RDIV_FORCE2 OUT4_FORMAT OUT4_SYNC_EN OUT4_DIS_STATE OUT4_CMOS_DRV OUT4_CM OUT4_AMPL OUT4_MUX_SEL OUT4_INV OUT5_PDN 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 1 0x0 0x0 0x0 0x0 0x0 0x0 0x000000000 0x1 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5345C Datasheet Addendum Device Configuration Summary for Si5345C-B-GM Page 4 of 6 0x0121[1] 0x0121[2] 0x0122[0:2] 0x0122[3] 0x0122[4:5] 0x0122[6:7] 0x0123[0:3] 0x0123[4:6] 0x0124[0:2] 0x0124[6:7] 0x0126[0] 0x0126[1] 0x0126[2] 0x0127[0:2] 0x0127[3] 0x0127[4:5] 0x0127[6:7] 0x0128[0:3] 0x0128[4:6] 0x0129[0:2] 0x0129[6:7] 0x012B[0] 0x012B[1] 0x012B[2] 0x012C[0:2] 0x012C[3] 0x012C[4:5] 0x012C[6:7] 0x012D[0:3] 0x012D[4:6] 0x012E[0:2] 0x012E[6:7] 0x0130[0] 0x0130[1] 0x0130[2] 0x0131[0:2] 0x0131[3] 0x0131[4:5] 0x0131[6:7] 0x0132[0:3] 0x0132[4:6] 0x0133[0:2] 0x0133[6:7] 0x013A[0] 0x013A[1] 0x013A[2] 0x013B[0:2] 0x013B[3] 0x013B[4:5] 0x013B[6:7] 0x013C[0:3] 0x013C[4:6] 0x013D[0:2] 0x013D[6:7] 0x013F[0:11] 0x0141[1] 0x0141[5] 0x0141[6] 0x0141[7] 0x0142[1] 0x0142[5] 0x0202[0:31] 0x0206[0:1] 0x0208[0:47] OUT5_OE OUT5_RDIV_FORCE2 OUT5_FORMAT OUT5_SYNC_EN OUT5_DIS_STATE OUT5_CMOS_DRV OUT5_CM OUT5_AMPL OUT5_MUX_SEL OUT5_INV OUT6_PDN OUT6_OE OUT6_RDIV_FORCE2 OUT6_FORMAT OUT6_SYNC_EN OUT6_DIS_STATE OUT6_CMOS_DRV OUT6_CM OUT6_AMPL OUT6_MUX_SEL OUT6_INV OUT7_PDN OUT7_OE OUT7_RDIV_FORCE2 OUT7_FORMAT OUT7_SYNC_EN OUT7_DIS_STATE OUT7_CMOS_DRV OUT7_CM OUT7_AMPL OUT7_MUX_SEL OUT7_INV OUT8_PDN OUT8_OE OUT8_RDIV_FORCE2 OUT8_FORMAT OUT8_SYNC_EN OUT8_DIS_STATE OUT8_CMOS_DRV OUT8_CM OUT8_AMPL OUT8_MUX_SEL OUT8_INV OUT9_PDN OUT9_OE OUT9_RDIV_FORCE2 OUT9_FORMAT OUT9_SYNC_EN OUT9_DIS_STATE OUT9_CMOS_DRV OUT9_CM OUT9_AMPL OUT9_MUX_SEL OUT9_INV OUTX_ALWAYS_ON OUT_DIS_MSK OUT_DIS_LOL_MSK OUT_DIS_LOSXAXB_MSK OUT_DIS_MSK_LOS_PFD OUT_DIS_MSK_LOL OUT_DIS_MSK_HOLD XAXB_FREQ_OFFSET PXAXB P0_NUM 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 1 0 0 1 1 0 0 11 3 0 0 0 0 0 1 0 1 1 0 0 0 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x1 0x0 0x0 0x1 0x1 0x0 0x0 0xB 0x3 0x0 0x0 0x000 0x0 0x0 0x1 0x0 0x1 0x1 0x00000000 0x0 0x000000000000 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5345C Datasheet Addendum Device Configuration Summary for Si5345C-B-GM Page 5 of 6 0x020E[0:31] 0x0212[0:47] 0x0218[0:31] 0x021C[0:47] 0x0222[0:31] 0x0226[0:47] 0x022C[0:31] 0x0231[0:3] 0x0231[4] 0x0232[0:3] 0x0232[4] 0x0233[0:3] 0x0233[4] 0x0234[0:3] 0x0234[4] 0x0235[0:43] 0x023B[0:31] 0x024A[0:23] 0x024D[0:23] 0x0250[0:23] 0x0253[0:23] 0x0256[0:23] 0x0259[0:23] 0x025C[0:23] 0x025F[0:23] 0x0262[0:23] 0x0268[0:23] 0x026B[0:7] 0x026C[0:7] 0x026D[0:7] 0x026E[0:7] 0x026F[0:7] 0x0270[0:7] 0x0271[0:7] 0x0272[0:7] 0x0302[0:43] 0x0308[0:31] 0x030D[0:43] 0x0313[0:31] 0x0318[0:43] 0x031E[0:31] 0x0323[0:43] 0x0329[0:31] 0x032E[0:43] 0x0334[0:31] 0x0339[0:4] 0x033B[0:43] 0x0341[0:43] 0x0347[0:43] 0x034D[0:43] 0x0353[0:43] 0x0359[0:15] 0x035B[0:15] 0x035D[0:15] 0x035F[0:15] 0x0361[0:15] 0x0487[0] 0x0487[1:2] 0x0502[4] 0x0508[0:5] 0x0509[0:5] 0x050A[0:5] 0x050B[0:5] 0x050C[0:5] P0_DEN P1_NUM P1_DEN P2_NUM P2_DEN P3_NUM P3_DEN P0_FRACN_MODE P0_FRACN_EN P1_FRACN_MODE P1_FRACN_EN P2_FRACN_MODE P2_FRACN_EN P3_FRACN_MODE P3_FRACN_EN MXAXB_NUM MXAXB_DEN R0_REG R1_REG R2_REG R3_REG R4_REG R5_REG R6_REG R7_REG R8_REG R9_REG DESIGN_ID0 DESIGN_ID1 DESIGN_ID2 DESIGN_ID3 DESIGN_ID4 DESIGN_ID5 DESIGN_ID6 DESIGN_ID7 N0_NUM N0_DEN N1_NUM N1_DEN N2_NUM N2_DEN N3_NUM N3_DEN N4_NUM N4_DEN N_FSTEP_MSK N0_FSTEPW N1_FSTEPW N2_FSTEPW N3_FSTEPW N4_FSTEPW N0_DELAY N1_DELAY N2_DELAY N3_DELAY N4_DELAY ZDM_EN ZDM_IN_SEL ADD_DIV256 BW0_PLL BW1_PLL BW2_PLL BW3_PLL BW4_PLL 0 0 0 0 0 0 0 3 0 3 0 3 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 53 51 52 53 66 80 50 0 0 0 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000000 0x000000000000 0x00000000 0x000000000000 0x00000000 0x000000000000 0x00000000 0x3 0x0 0x3 0x0 0x3 0x0 0x3 0x0 0x00000000000 0x00000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x000000 0x35 0x33 0x34 0x35 0x42 0x50 0x32 0x00 0x00000000000 0x00000000 0x00000000000 0x00000000 0x00000000000 0x00000000 0x00000000000 0x00000000 0x00000000000 0x00000000 0x1F 0x00000000000 0x00000000000 0x00000000000 0x00000000000 0x00000000000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0 0x0 0x0 0x00 0x00 0x00 0x00 0x00 Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Si5345C Datasheet Addendum Device Configuration Summary for Si5345C-B-GM Page 6 of 6 0x050D[0:5] 0x050E[0:5] 0x050F[0:5] 0x0510[0:5] 0x0511[0:5] 0x0512[0:5] 0x0513[0:5] 0x0515[0:55] 0x051C[0:31] 0x0521[0:3] 0x0521[4] 0x0521[5] 0x052A[0] 0x052A[1:3] 0x052B[0] 0x052B[1] 0x052C[0] 0x052C[3] 0x052C[5:7] 0x052D[1] 0x052E[0:4] 0x052F[0:4] 0x0531[0:4] 0x0532[0:23] 0x0536[0:1] 0x0536[2] 0x0536[3] 0x0537[0:3] 0x0537[4:7] 0x0538[0:2] 0x0538[4:6] 0x0539[0:2] 0x0539[4:6] 0x090E[0] 0x0943[0] 0x0949[0:3] 0x0949[4:7] 0x094A[0:3] 0x0A02[0:4] 0x0A03[0:4] 0x0A04[0:4] 0x0A05[0:4] 0x0B44[0:3] 0x0B44[5] 0x0B46[0:3] 0x0B47[0:4] 0x0B48[0:4] 0x0B4A[0:4] BW5_PLL FAST_BW0_PLL FAST_BW1_PLL FAST_BW2_PLL FAST_BW_PLL FAST_BW4_PLL FAST_BW5_PLL M_NUM M_DEN M_FRAC_MODE M_FRAC_EN PLL_OUT_RATE_SEL IN_SEL_REGCTRL IN_SEL FASTLOCK_AUTO_EN FASTLOCK_MAN HOLD_EN HOLD_RAMP_BYP HOLD_RAMP_RATE HOLD_RAMPBYP_NOHIST HOLD_HIST_LEN HOLD_HIST_DELAY HOLD_REF_COUNT_FRC HOLD_15M_CYC_COUNT CLK_SWITCH_MODE HSW_EN HSW_RAMP_BYP IN_LOS_MSK IN_OOF_MSK IN0_PRIORITY IN1_PRIORITY IN2_PRIORITY IN3_PRIORITY XAXB_EXTCLK_EN IO_VDD_SEL IN_EN IN_PULSED_CMOS_EN INX_TO_PFD_EN N_ADD_0P5 N_CLK_TO_OUTX_EN N_PIBYP N_PDNB PDIV_FRACN_CLK_DIS FRACN_CLK_DIS_PLL LOS_CLK_DIS OOF_CLK_DIS OOF_DIV_CLK_DIS N_CLK_DIS 0 0 0 0 0 0 0 0 0 3 0 1 0 0 1 0 1 1 0 1 0 0 0 1024 2 1 1 0 0 0 0 0 0 0 0 0 0 15 0 31 0 31 0 0 0 0 15 0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00000000000000 0x00000000 0x3 0x0 0x1 0x0 0x0 0x1 0x0 0x1 0x1 0x0 0x1 0x00 0x00 0x00 0x000400 0x2 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xF 0x00 0x1F 0x00 0x1F 0x0 0x0 0x0 0x00 0x0F 0x00 This datasheet addendum is provided as supplemental information to the Si5345C datasheet, located at www.silabs.com/timing. You can search for and download any datasheet addendum for Si534x/8x part numbers. Go to http://www.silabs.com/custom-timing for more information. Silicon Laboratories 400 West Cesar Chavez Austin, TX 78701 Phone (512) 416-8500 www.silabs.com Copyright 2015 Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.