MCP3910 Rev. A Silicon Errata and Data Sheet Clarification

MCP3910
MCP3910 Rev. A Silicon Errata and Data Sheet Clarification
The MCP3910 parts you have received conform
functionally to the Device Data Sheet (DS20005116B),
except for the anomalies described in this document.
All of the issues listed here will be addressed in future
revisions of the MCP3910 silicon.
Contact Microchip Technology Inc. for the latest Silicon
fix.
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS20005116B):
None to report at this time.
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current.
1. Module: ADC Conversion
The converter internal phases can be erroneously
generated if there is a simultaneous occurrence of
a master clock edge and a reset event (a RESET
pin rising edge, the last SCK rising edge of a write
communication that generates an ADC reset and
restart as defined in Section 6.6, “Situations that
Reset and Restart Active ADCs” or a Power-on
Reset). This perturbation in the internal clock
phase generation can cause modulator instability
and generate erroneous results, so it is highly
recommended to avoid these events becoming
synchronized.
Work around
A possible work around for this issue is to freeze
the master clock during all the above detailed
events (a RESET pin rising edge, the last SCK
rising edge of a write communication that
generates an ADC reset and restart as defined in
Section 6.6, “Situations that Reset and Restart
Active ADCs” or a Power-on Reset). In this case,
the part will not exhibit any issue.
 2015 Microchip Technology Inc.
DS80000660A-page 1
MCP3910
APPENDIX A:
DOCUMENT
REVISION HISTORY
Rev A Document (7/2015)
Initial release of this document.
DS80000660A-page 2
 2015 Microchip Technology Inc.
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ISBN: 978-1-63277-570-2
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DS80000660A-page 3
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DS80000660A-page 4
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