EFR32 Mighty Gecko Family EFR32MG1 Errata This document contains the errata history for EFR32MG1 devices. For errata on latest revision, please refer to the errata for the device. The device data sheet explains how to identify chip revision, either from package marking or electronically. Errata history effective date: April 25th, 2016. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.3 EFR32MG1 Errata Errata Summary 1. Errata Summary Table 1.1. Errata History Overview Designator Title/Problem Exists on: Rev B Rev C ADC_E202 Wait After POR or EM4S Wakeup X X ADC_E206 PROGERRIF (Program Error Interrupt Flag) Will Not Clear X X ADC_E207 ADC Scan Repeat Mode with APORT X X ADC_E208 ADC Interrupt Flags X X ADC_E209 ADC and PRS Triggers X X ADC_E210 ADC with PRS and Software Triggers X X ADC_E211 ADC Single Repeat Mode and Tailgating X X ADC_E212 ADC with PRS in ASYNC Mode X X ADC_E213 ADC KEEPINSLOWACC Mode X X ADC_E214 Using ADC CHCONMODE with PRS X X ADC_E215 ADC CHCONMODE Set to MAXRESP Causes Extra Latency X X ADC_E216 ADC Conversion Start Delay X X ADC_E217 Multiple CLK Mode Switches X X ADC_E218 SINGLEACT and SCANACT Status Flags Delayed X X ADC_E219 STOP Command Causing FIFO Corruption X X BL_E201 UART Bootloader Not Available X X CORE_E201 SYSTICK and an External Clock X X CUR_E201 EM2 and EM3 Current Consumption X X CUR_E202 EM2/3 Current Consumption at Cold Temperatures X — DBG_E201 AUXHFRCO Debug Limitations X X DBG_E202 Debug Access to ADC and LEUART not Functioning as Intended X X DCDC Stops Regulating During a Fast EM0/1 to EM2/3/4H Transition X — EFR_E201 Bit Access Not Supported for Low Energy Peripherals X X EFR_E202 Read-Clear Access for LETIMER0 and RTCC Interrupts X X EMU_E201 High Temperature Operation X X EMU_E204 Restrictions Writing TEMPHIGH and TEMPLOW X X EMU_E205 Restrictions Reading TEMP X X EMU_E207 GPIO State can be Lost During EM4 Recovery X X EMU_E208 Occasional Full Reset After Exiting EM4H X X FLASH_E201 Potential Program Failure after Power On X X GPIO_E201 GPIO Default Slew Rate X — IDAC_E201 IDAC CURSTABLE Bit Not Reliable X X DCDC_E201 silabs.com | Smart. Connected. Energy-friendly. Rev. 1.3 | 1 EFR32MG1 Errata Errata Summary Designator Title/Problem Exists on: Rev B Rev C I2C ABORT Command X X Restrictions Setting TXDMAWU/RXDMAWU of LEUARTn_CTRL X X RADIO_E201 Receive Sensitivity X X RADIO_E202 802.15.4 Channel 14 X X RADIO_E203 Bluetooth Smart Channel 26 X X RADIO_E204 Increased EVM on Selected Channels X X RADIO_E206 Bluetooth Smart Receive Sensitivity X X RMU_E201 CTRL Register Reset on All Resets X X RTCC_E201 RTCC Does Not Support Compare/Capture Wrap with Prescaler X X RTCC_E202 RTCC Triggers to LETIMER Not Safe X X TIMER_E201 Timer in Input Capture Mode Can Stop Counting X X I2C_E201 LEUART_E201 Table 1.2. Errata Status Summary Errata # Designator Title/Problem Workaround Affected Fixed Exists Revision Revision 1 CUR_E202 EM2/3 Current Consumption at Cold Temperatures No B B, date code 1547 (November 16, 2015) 2 GPIO_E201 GPIO Default Slew Rate Yes B B, date code 1603 (January 18, 2016) 3 DCDC_E201 DCDC Stops Regulating During a Fast EM0/1 to EM2/3/4H Transition Yes B C silabs.com | Smart. Connected. Energy-friendly. Rev. 1.3 | 2 EFR32MG1 Errata Detailed Errata Descriptions 2. Detailed Errata Descriptions 2.1 CUR_E202 – EM2/3 Current Consumption at Cold Temperatures Description of Errata A small probability exists that the current consumption in EM2 and EM3 on some revision B devices could be on the order of 20 µA. This issue can only be observed at cold temperatures with devices that are fabricated under certain semiconductor process variations. Affected Conditions / Impacts The increased current consumption impacts applications that spend the majority of their time in these sleep modes. For applications that are dominated by current consumption from the higher energy modes, EM0 and EM1, the impact will be negligible. Workaround The higher leakage current can be significantly reduced by setting RAMPOWERDOWN in EMU_RAM0CTRL to BLK1TO4 (power down RAM blocks 1 and above) in EM2 and EM3. Resolution Revision B devices after date code 1547 (November 16, 2015) will not exhibit high current on the order of 20 µA. More information on the date code can be found in the Package Marking diagrams in the device data sheet. 2.2 GPIO_E201 – GPIO Default Slew Rate Description of Errata The default SLEWRATE and SLEWRATEALT value in the GPIO_Pn_CTRL registers is set too high. Affected Conditions / Impacts The default SLEWRATE and SLEWRATEALT setting of 0x6 may result in I/O ringing and excessive undershoot, which can lead to a risk of excessive current injection. Workaround The SLEWRATE and SLEWRATEALT fields for all GPIO_Pn_CTRL registers should be changed to a maximum value of 0x5 for most MCU applications. The control of SLEWRATE and SLEWRATEALT is application specific. For GPIO pins that are actively toggling during RF activity, consider reducing their slew rate to a minimum possible value in order to avoid spurs and interference with radio communications. Firmware can call the CHIP_Init() function in versions v4.3.0 or later of emlib to write a default value of 0x5 to the SLEWRATE and SLEWRATEALT fields for all GPIO_Pn_CTRL registers. If using a software stack on top of emlib, check the documentation for the version of emlib used. Resolution Revision B devices after date code 1603 (January 18, 2016) will have the default slew rate set to 0x05. More information on the date code can be found in the Package Marking diagrams in the device data sheet. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.3 | 3 EFR32MG1 Errata Detailed Errata Descriptions 2.3 DCDC_E201 – DCDC Stops Regulating During a Fast EM0/1 to EM2/3/4H Transition Description of Errata The DC-DC module can stop regulating during a fast transition from EM0 or EM1 to EM2, EM3, or EM4H. Affected Conditions / Impacts The LP controller stops charging the capacitor on the DC-DC output, resulting in a brown-out. Workaround Before changing DCDCCTRL->DCDCMODE (to turn on the DCDC), clear DCDCSMCTRL->LPCMPWAITDIS (bit 0 of DCDCSMCTRL). Wait for the low noise controller to start running before changing energy modes by polling DCDCSTATUS->LNRUNNING (bit 16 of the register at address EMU_BASE+0x07C). Resolution This issue has been fixed in revision C devices. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.3 | 4 EFR32MG1 Errata Revision History 3. Revision History 3.1 Revision 1.3 April 25th, 2016 Initial revision. Moved CUR_E202 and GPIO_E201 from the errata. Added DCDC_E201. silabs.com | Smart. Connected. Energy-friendly. Rev. 1.3 | 5 Simplicity Studio One-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! IoT Portfolio www.silabs.com/IoT SW/HW Quality Support and Community www.silabs.com/simplicity www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. 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