TS9 EMBER® EM35 X NCP BREAKOUT BOARD TECHNICAL SPECIFICATION The Silicon Labs’ Ember EM35x Network Co-Processor (NCP) Breakout Board contains the hardware peripherals for the development and deployment of a low-data-rate, low-power ZigBee application on a host micro interfacing via EZSP protocol to the EM300 series NCPs. The NCP Breakout Board supports SPI and UART EZSP interfaces for development flexibility. Modules separately contain the EM35x NCP and the HOST microcontroller to allow for higher degrees of freedom during application development. The modules are connected to the NCP Breakout Board though robust connectors. The EM35x NCP Breakout Board hardware stimuli include a temperature sensor, two buttons, a piezo buzzer, two LEDs, and a 1.6" x 1.8" through-hole prototyping area. The EM35x NCP Breakout Board also contains a USB transceiver with USB connector, a RS-232 transceiver with DB-9 connector, Data Emulation Interface (DEI), Packet Trace Port programming interface, and regulated power planes. The EM35x NCP Breakout Board also includes an optional host interface to 2 Mbit external DataFlash in support of the ZigBee OTA upgrade cluster for over-the-air (OTA) application bootloader purposes. You can obtain the EM35x NCP Breakout Board voltage supply from one of four sources: Debug Adapter (ISA3) (through the Packet Trace Port), external VDC supply, USB port, or AAA battery pack. The various voltage supplies offer a degree of flexibility when testing different network topologies. This document provides the technical specification for the EM35x NCP Breakout Board. It describes the board-level interfaces as well as the key performance parameters. In addition, it provides the necessary information for developer to validate their application designs using the EM35x NCP Breakout Board. New in This Revision Document renumbering. Contents 1 EM35x NCP Breakout Board Features ............................................................................................................ 3 2 Components ................................................................................................................................................... 5 2.1 Power supply and distribution ................................................................................................................... 5 2.1.1 External DC Power Supply (J1 and J32 or J3.2 and J32) ................................................................... 7 2.1.2 Battery Connector (J8) ...................................................................................................................... 7 2.1.3 Packet Trace Port (J8) ...................................................................................................................... 7 2.1.4 USB Host (J5) ................................................................................................................................... 7 2.2 NCP Current Measurements .................................................................................................................... 7 2.3 Host Current Measurements..................................................................................................................... 7 2.4 Deep Sleep Testing of the EM35x Module ................................................................................................ 7 2.5 ZigBee Application Peripherals................................................................................................................. 8 2.5.1 Temperature Sensor (U4).................................................................................................................. 8 2.5.2 Buttons (EM1, EM2) .......................................................................................................................... 9 Rev 0.6 Copyright © 2013 by Silicon Laboratories TS9 TS9 2.5.3 Buzzer (SPK1) .................................................................................................................................. 9 2.5.4 LEDs (DS6 and DS7) ........................................................................................................................ 9 2.5.5 External DataFlash (U7) .................................................................................................................... 9 2.6 EZSP and Serial Mode Configuration Switch (SW1) ................................................................................10 2.7 Data Emulation Interface (J43) ................................................................................................................15 2.8 EM35x Module Interface Connector (J21-J24) .........................................................................................15 2.9 Host Module interface connector (J37-J38)..............................................................................................18 2.10 3 2 Prototyping Area ..................................................................................................................................20 EM35x NCP Breakout Board Schematic .........................................................................................................21 Rev. 0.6 TS9 1 EM35x NCP Breakout Board Features The EM35x NCP Breakout Board offers: • Configurable hardware support for application development Temperature sensor (connects to host GPIO) Two buttons (connect to host GPIO) Piezo buzzer (connect to host GPIO) Two LEDs (connect to host GPIO) • • • • RS-232 transceiver with DB-9 connector for serial communication (with hardware (HW) handshake support) USB transceiver with USB connector (Type B) 2 MB external DataFlash for ZigBee OTA Profile support Control Interface for the EM35x Radio Communications Module (RCM) RCM RESET and Bootload buttons Voltage Supply connection (V_NCP_EN) • Control Interface for the Host Module RCM RESET and Bootload buttons Voltage Supply connection (V_HOST_EN) • • • • • • • • • • • 1.6" x 1.8", 0.1" pitch prototyping area 26-pin, 0.1" pitch, dual-row logic-analyzer shrouded connector 10-pin, 0.05" pitch, dual-row Packet Trace Port connector 12-pin, 0.1” pitch, dual-row, data emulation interface (DEI) with configuration header 14-pin, 0.05” pitch, single-row along with a 19-pin 0.05” pitch, single-row, board-to-board connector for the module 16-pin, 0.1” pitch, single-row along with a 20-pin 0.1” pitch, single-row, board-to-board connector for the host module Selection pins for DC power source selection (either external DC power supply, USB, Debug Adapter (ISA3), or AAA battery pack). LEDs indicate which power supply has been selected. 2-pin module VDC pin for connection of an ammeter for EM5x module current measurements 2-pin module VDC pin for connection of an ammeter for host module current measurements 2-pin jumpers for each of the HW application peripherals, buzzer, buttons, piezo, temperature sensor, and LEDs 2-pin jumpers for connection to TTL UART for either the EM35x UART (SC1) or host UART2. The selection jumpers route signals (RXD, TXD, nRTS, and nCTS) allow access to the TTL levels. Rev. 0.6 3 TS9 Table 1 lists the DC electrical characteristics of the EM35x NCP Breakout Board. Table 1. DC Electrical Characteristics Parameter Min. Typ. Max. Unit 20 V VDD supply External DC Supply (J1 / J32) 4 USB Host 4.5 5 Debug Adapter 3.1 3.3V 3.5 3.3 3.5 Battery 2.1 External DC supply (J3.2) 3.1 V V 3.6 V Current draw (peripherals) Piezo buzzer 10 mA Buttons (enabled) 6 mA Temperature sensor (enabled) 5 mA Current draw (miscellaneous) RS-232 transceiver 4 mA USB transceiver 15 mA LDO distribution 10 mA + 55 C Operating temperature 4 0 Rev. 0.6 TS9 2 Components Figure 1 illustrates the components on layer 1 (top side). Host Module Power Isolation Jumper (J34) NCP Module Power Isolation Jumper (J34) Power Source Selection Jumpers ZigBee Application Peripherals EM35x Radio Module Connectors (X1: J21-J22) Power Source LEDs DataFlash & Interface Connectors USB Connector (J5) Packet Trace Port (J31) Data Emulation Interface Selection Header (J27) TTL Access Jumpers (J25-J28) Data Emulation Interface (J28) SPI/UART Mode Config Switch (SW1) DB-9 Connector – RS-232 (J30) Host Module Connectors (X2: J37-J38) Prototype Area Host Bootloader (EM6) and Reset (EM5) Buttons NCP Bootloader (EM3) and Reset (EM4) Buttons Reset and Bootload Enable Jumpers (J14, J16, J35, J40) Figure 1. Assembly Print for Layer 1 2.1 Power Supply and Distribution The EM35x NCP Breakout Board can be powered from one of five sources: • • • • • 4 V to 20 V External DC Power supply (Positive connected J1 and Ground connected to J32) Battery pack connector (J8) USB Host (J5, via Wall wart or PC connection) Debug Adapter (ISA3) (through Packet Trace Port, J31) 2.1 to 3.6 V External DC Power supply (Positive connected to J3.2 and Ground connected to J32) Rev. 0.6 5 TS9 The EM35x NCP Breakout Board contains power source selection jumpers (J2 and J3) which allows only one DC source to power the board. This eliminates the possibility of overcurrent resulting from power supply contention. Table 2 illustrates the connection scheme and LED indication for each power source. Table 2. Power Supply connections Power Source High Voltage External supply (4 V to 20 V) Selection Scheme (J2 and J3) 1 VBATT J2 3 VREG J3 VBATT J2 3 VREG J3 Debug Adapterr (ISA3) VBATT J2 3 VREG J3 VBATT J2 3 VREG VISA VBAT 1 VBATT VPS VUSB VISA J2 3 VREG J3 6 VPS VUSB VISA J3 Connect directly to J3.2 with Ground connected to J32. VISA VBAT 1 Battery pack Low Voltage External DC supply (3.1 to 3.5) VPS VUSB VISA Connect AAA battery pack (supplied by Silicon Labs) to J8. VISA VBAT 1 Connect Debug Adapter (ISA3) to J31. VPS VUSB VISA Connect USB cable to J5. VISA VBAT 1 USB Host VPS VUSB VISA Connect VDD to J1 and GND to J32. LED Indicator Rev. 0.6 VISA VBAT TS9 2.1.1 External DC Power Supply (J1 and J32 or J3.2 and J32) The EM35x NCP Breakout Board allows two easy to use connections to an external power supply. • • The first connection (Low Voltage) allows for a 3.1 to 3.5 V DC external supply to be connected to J3.2 (positive) and J32 (Ground). The power supply should be able to source up to 250 mA at the set voltage. When using a power supply in this mode, there should be no jumpers on J2 or J3 as shown in Table 2. The second connection (High Voltage) allows for a 4 V to 20 V DC external supply to be connected to J1 (positive) and J32 (Ground). The power supply should be able to source up to 300 mA at the set voltage. When using a power supply in this mode, there should be a jumper connecting J3.3 and J3.2 as shown in Table 2. 2.1.2 Battery Connector (J8) The 2-pin, keyed battery connector (Hirose, P/N: DF13-2P-1.25H(50)) allows for connection to a DC power supply or battery pack. The EM35x NCP Breakout Board is shipped with a 2-AAA battery pack with appropriate mating connector for easy attachment. Batteries are sold separately. When using a battery pack, a jumper must be connected between J3.1 and J3.2 as shown in Table 2. 2.1.3 Packet Trace Port (J8) The EM35x NCP Breakout Board can also be powered from a Debug Adapter (ISA3). To enable this power supply, simply connect the Debug Adapter (ISA3) to the Packet Trace Port (J8) and connect the power selection jumper between J2 and J3.2 as shown in Table 2. In addition, the Debug Adapter (ISA3) selection toggle switch must be put in the INT. The Debug Adapter (ISA3) provides a target voltage of 3.3V and sources as much as 250 mA. See document TS7, Debug Adapter (ISA3) Technical Specification, for more details on the Debug Adapter (ISA3). Note: If the Debug Adapter (ISA3) is connected directly to the Packet Trace Port on the Module, the jumpers at J4 and J34 must be connected as well as the jumper across J2 and J3.2. 2.1.4 USB Host (J5) The EM35x NCP Breakout Board can also be powered by a USB Host (PC or Silicon Labs-supplied USB power supply). To operate in this mode, a USB Host must be connected to J5 and the power selection jumper must be connected between J3.1 and J3.2 as shown in Table 2. 2.2 NCP Current Measurements To allow for NCP current measurements, the EM35x NCP Breakout Board isolates the NCP module VDD power supply from the regulated power domain on the Breakout Board. The only connection point between the NCP module power supply and the Breakout Board supply is through the V_NCP_EN header (J4). Remove J4 and place an ammeter across this jumper to measure the NCP current draw. 2.3 Host Current Measurements To allow for Host current measurements, the EM35x NCP Breakout Board isolates the Host module VDD power supply from the regulated power domain on the Breakout Board. The only connection point between the Host module power supply and the Breakout Board supply is through the V_HOST_EN header (J34). Remove J34 and place an ammeter across this jumper to measure the Host current draw. 2.4 Deep Sleep Testing of the EM35x Module To perform accurate deep sleep measurements of the EM35x NCP, configure the EM35x NCP Breakout Board as follows: • Remove J4 and place ammeter across this jumper. Rev. 0.6 7 TS9 • • • • • Remove J6 so the V_NCP LED DS4 is not driven. If supplying voltage through J8 battery connector, also remove J7 so the V_BATT LED DS5 is not driven. Remove J33 jumpers to isolate DataFlash IC from circuit. Issue "shutdown" in nodetest. Once command is issued and node is asleep, remove J25-J28 (TTL jumpers). Make sure the Packet Trace Port cable, DEI cable, and RS-232 cable are all detached from the Breakout Board. This connection scheme offers the highest degree of power supply flexibility. Wake the EM35x NCP from deep sleep by pressing the NCP reset button. Note: The use of virtual UART port 4900 is not recommended when interfacing to nodetest for deep sleep testing, since this does not allow for proper configuration of the EM35x for deep sleep measurements. Therefore, please use either pass-through UART port 4901, USB, or RS-232 to interface to the nodetest application. 2.5 ZigBee Application Peripherals As previously mentioned, the EM35x NCP Breakout Board offers six host peripherals to assist in ZigBee application development including: • • • • • Temperature sensor Two (2) “normally open” buttons 4 kHz piezo buzzer Two (2) LEDs External DataFlash Each peripheral connects to a host GPIO through a two-pin peripheral header. Because each peripheral header on the EM35x NCP Breakout Board ships with a jumper in place, the peripherals default to “HW Enabled.” If application development does not require the peripheral, simply remove the jumper. Note: Each peripheral consumes power. Be sure to factor this into the current consumption equations when testing the module in deep sleep mode or if using the battery pack to power the Breakout Board. 2.5.1 Temperature Sensor (U4) The temperature sensor is an off-the-shelf component from National Semiconductor (MFG P/N: LM20BIM7). The temperature sensor requires an enable signal to be asserted (active high) prior to generating an analog voltage proportional to the ambient temperature of the EM35x NCP Breakout Board. Therefore, two host GPIO signals, HGPIO7 and HGPIO8, are routed to pin 2 of peripheral headers J13 and J15, respectively. • • HGPIO7 enables the temperature sensor when asserted (active high), when a jumper is installed at J13. HGPIO8 contains the analog temperature information from the sensor, when it is enabled and a jumper is installed at J15. The temperature sensor output is scaled to between 0 and 1.2 V through a resistive voltage divider. If you want to connect a temperature sensor from a different manufacturer, scale the output in a similar manner. The EM35x NCP Breakout Board is shipped with a jumper installed at J13 and J15. If the jumpers are removed, a different compatible device can be attached to pin 2 of both J13 and J15. For more information on the temperature sensor, refer to its data sheet (http://www.ti.com/product/LM20). 8 Rev. 0.6 TS9 2.5.2 Buttons (EM1, EM2) Two programmable, normally-open buttons are provided for software debugging and application development. When either button is pressed, the connected net is driven low. A single-pole RC filter minimizes the effects of switching noise. These buttons map to the backchannel button commands as follows: • • EM2: controlled by the button 0 command EM1: controlled by the button 1 command For information about the button command, see document UG110, the EM35x Development Kit User Guide. Two host GPIO signals, HGPIO3 and HGPIO2, are routed from the EM35x Module to pin 2 of peripheral headers J9 and J10, respectively. In the default configuration of the EM35x NCP Breakout Board, jumpers are positioned across J9 and J10 to enable buttons EM1 and EM2, respectively. If the jumpers are removed, different compatible devices can be attached to pin 2 of breakout headers J9 and J10 instead of the buttons. 2.5.3 Buzzer (SPK1) A programmable buzzer is provided for software debugging and application development. A host GPIO signal, HGPIO4, is routed to pin 2 of peripheral header J17. In the default configuration of the EM35x NCP Breakout Board, a jumper is positioned across J17 to enable use of the buzzer. The buzzer installed on the EM35x NCP Breakout Board is from CUI (MFG P/N: CEP-1160). For more information on the buzzer, refer to its datasheet (http://www.cui.com/Product/Resource/PDFRedirect/110/CEP-1160.pdf). 2.5.4 LEDs (DS6 and DS7) The EM35x NCP Breakout Board contains two LEDs for software debugging and application development. Each LED is buffered (non-inverting) to allow for connection to any host GPIO. Two host GPIOs, HGPIO0 and HGPIO1, are routed to pin 2 of headers J12 and J11 respectively. To turn on DS7 (RED) from the host module, install a jumper at J12, configure HGPIO0 as an output and drive it low. To turn on DS6 (GREEN), install a jumper at J11, configure HGPIO1 as an output and drive it low. 2.5.5 External DataFlash (U7) The external DataFlash is an off-the-shelf component from Atmel (MFG P/N: AT45DB021D-SSH-B). The DataFlash is used in cases where ZigBee OTA Profile application bootloader is required for the host. The DataFlash is connected to the host module through jumper block J33. The EM35x NCP Breakout Board is shipped with jumpers installed in a disconnected state at J33. If all six jumpers are installed properly at J33, the external DataFlash connects to the host for application bootloading. Figure 2 illustrates the J33 jumper configuration for the DataFlash interface. J33 DF_nSD HGPIO11 DF_SI HGPIO14 DF_SO HGPIO15 DF_SCK HGPIO13 DF_nCS HGPIO12 DF_3V 3V 1 2 Figure 2. Jumper for DataFlash connections For more information on the DataFlash, refer to its datasheet (http://www.atmel.com/Images/doc3638.pdf). Rev. 0.6 9 TS9 2.6 EZSP and Serial Mode Configuration Switch (SW1) To enhance the software development experience, the EM35x NCP Breakout Board allows for EZSP interfaces between the EM35x NCP and a host via both SPI and UART (either to the host module or an external host). A configuration switch (SW1) is used to set up EZSP mode and serial communication paths. Access to either the EM35x SC1 UART or host UART1 is available directly from the EM35x NCP Breakout Board or by telnetting into port 4901 of a Debug Adapter (ISA3) connected to an Ethernet network. On the EM35x NCP Breakout Board, it is available as RS-232, USB and TTL-compliant signal levels. To minimize current consumption and allow for the different configuration options, the EM35x NCP Breakout Board individually routes the TTL UART signals RXD, TXD nCTS, and nRTS to pin 2 of headers J25, J26, J27, and J28 respectively. To route the UART signals to the USB transceiver, move SW1 Serial to TTL and TTL Path to USB. To route the UART signals to the RS-232 transceiver, move SW1 Serial to TTL and TTL Path to 232. To access TTL signals, move SW1 Serial to TTL, remove the jumpers on J25, J26, J27 and J28 and connect to pin 2 of these jumpers. To route the UART signals to DEI, move SW1 Serial to DEI and place jumpers on the DEI jumper connector (J42) as summarized below and shown in Figure 3. • • • • TXD: J27.1 to J27.2 RXD: J27.5 to J27.6 nRTS: J27.7 to J27.8 nCTS: J27.9 to J27.10 Each SW1 configuration is shown in Table 3. TTL Access Jumper configuration is shown in Table 4. Table 3. EZSP and Serial Configuration Switch UART Path Selection Scheme (J22, J25, J24, and J26) J25 TXD J26 nCTS J27 nRTS J28 Connect Debug Adapter (ISA3) DEI cable to J31. SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB 10 2 1 EZSP SPI Mode, Host UART2 to DEI RXD Rev. 0.6 UART EXT TTL 232 TS9 UART Path Selection Scheme (J22, J25, J24, and J26) 2 1 EZSP SPI Mode, Host UART2 to RS232 RXD J25 TXD J26 nCTS J27 nRTS J28 SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB UART EXT TTL 232 2 1 RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP SPI Mode, Host UART2 to USB SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB UART EXT TTL 232 2 1 RXD J25 TXD J26 nCTS J27 nRTS J28 EZSP SPI Mode, Host UART2 to TTL SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB Rev. 0.6 UART EXT TTL 232 11 TS9 UART Path Selection Scheme (J22, J25, J24, and J26) 2 1 EZSP UART Mode to Host Module, Host UART2 to DEI RXD J25 TXD J26 nCTS J27 nRTS J28 Connect Debug Adapter (ISA3) DEI cable to J31. SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB 2 1 EZSP UART Mode to Host Module, Host UART2 to RS-232 UART EXT TTL 232 RXD J25 TXD J26 nCTS J27 nRTS J28 SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB 2 1 EZSP UART Mode to Host Module, Host UART2 to USB UART EXT TTL 232 RXD J25 TXD J26 nCTS J27 nRTS J28 SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB 12 Rev. 0.6 UART EXT TTL 232 TS9 UART Path Selection Scheme (J22, J25, J24, and J26) 2 1 EZSP UART Mode to Host Module, Host UART2 to TTL RXD J25 TXD J26 nCTS J27 nRTS J28 SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB 2 1 EZSP UART Mode to External Host, NCP UART to DEI UART EXT TTL 232 RXD J25 TXD J26 nCTS J27 nRTS J28 Connect DEI cable to J31. SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB 2 1 EZSP UART Mode to External Host, NCP UART to RS-232 UART EXT TTL 232 RXD J25 TXD J26 nCTS J27 nRTS J28 SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB Rev. 0.6 UART EXT TTL 232 13 TS9 UART Path Selection Scheme (J22, J25, J24, and J26) 2 1 EZSP UART Mode to External Host, NCP UART to USB RXD J25 TXD J26 nCTS J27 nRTS J28 SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB 2 1 EZSP UART Mode to External Host, NCP UART to TTL UART EXT TTL 232 RXD J25 TXD J26 nCTS J27 nRTS J28 SW1 EZSP MODE: SPI UART HOST: MOD SERIAL: DEI TTL PATH: USB Note: 14 UART EXT TTL 232 To connect to the UART through a Debug Adapter (ISA3), the Debug Adapter (ISA3) must be connected to an Ethernet connection. It can be accessed by issuing “Serial 1” within the Console view of the Ember Desktop or by telnetting to Port 4901. Rev. 0.6 TS9 J42 HOST_BTL SW_UART_MOD_EN SW_SPI_EN HOST_nRESET HGPIO2 nCTS nRTS RXD HGPIO3 TXD 1 2 Figure 3. Jumper Settings Required for EM35x SC1 UART Access by Debug Adapter (ISA3) Table 4. TTL Access Jumpers Configuration Selection Scheme (J25, J26, J27, and J28) J25 TXD J26 nCTS J27 nRTS J28 2.7 2 1 UART via TTL Access 2 1 UART via USB or Serial RXD RXD J25 TXD J26 nCTS J27 nRTS J28 Data Emulation Interface (J43) The 12-pin, dual-row, data emulation interface contains 4 host GPIO signals, 4 host or EM35x NCP UART signals, and 2 DEI control pins, as well as voltage (VBRD) and ground (GND) connections. When connected to the Debug Adapter (ISA3), the connector provides additional debug features to software developers. One feature involves the port 4901 UART connection through Debug Adapter (ISA3). To enable the UART connection to either the host or the EM35x NCP UART signals, configure SW1 for DEI mode as shown in Table 3 and install four jumpers on J42 as shown in Figure 3 for nCTS, nRTS, RXD, and TXD. Another feature involves manipulation of BUTTON0 and BUTTON1 GPIO signals. To enable GPIO manipulation of BUTTON0 and BUTTON1, install jumpers on J42 at HGPIO2 and HGPIO3, respectively. 2.8 EM35x Module Interface Connector (J21-J24) Two single-row, 0.05” pitch, connectors make up the EM35x module interface to the EM35x NCP Breakout Board. In addition, two single-row, guide connectors assist with connecting the EM35x module to the EM35x NCP Breakout Board. The board-to-board connector scheme allows access to all EM35x GPIO as well as nRESET and the JCLK signals. The connector is illustrated in Figure 4, while the dimensions are shown in Figure 5. Rev. 0.6 15 TS9 J21 GND 1 EM35x_PC5 2 EM35x_PC6 3 EM35x_PC7 4 EM35x_PA7 5 EM35x_PB3 6 EM35x_nRESET 7 EM35x_PB4 NC NC J23 34 35 33 GND 32 VDD_3V_EM35X 8 31 GND HOST_MOSI 9 30 EM35x_PB5 HOST_MISO 10 29 nWAKE HOST_SCK 11 28 EM35x_PB7 HOST_nSS 12 27 EM35x_PC0 GND 13 26 EM35x_PC1 EM35x_PA4 14 25 nSIMRST EM35x_PA5 15 24 EM35x_PC4 EM35x_PA6 16 23 EM35x_PC3 EM35x_PB1 17 22 EM35x_PC2 EM35x_PB2 18 21 EM35x_JCLK GND 19 20 GND J22 J24 36 37 NC NC Figure 4. Board-to-Board Connector for the EM35x Module Figure 5. Board-to-Board Connector Dimensions for the EM35x Module Table 5 describes the pinout and signal names at J21-J24. The EM35x UART1 signals (PB1, PB2, PB3, PB4) are exposed on the EM35x NCP Breakout Board at the 26-pin, dual row, 0.1” pitch GPIO connector (J41) for application development. 16 Rev. 0.6 TS9 Note: Custom EM35x modules (not shipped with development kits) containing external DataFlash should NOT be connected to the EM35x NCP Breakout Board, as the EM35x SPI1 is used for the EZSP SPI interface. For more information on the alternate functions of the GPIO connector, refer to document 120-035X-000, the EM351/7 Data Sheet. Table 5. Pinout and Signal Names of the NCP Interface Connector Signal name Direction2 Connector Description 1 GND Power J21 Ground Connection 2 PC5 I/O J21 EM35x GPIO 3 PC6 I/O J21 EM35x GPIO 4 PC7 I/O J21 EM35x GPIO 5 PA7 I/O J21 EM35x GPIO 6 PB3 I/O J21 EM35x GPIO 7 nRESET I/O J21 Active low chip reset (internal pull-up on EM35x) 8 PB4 I/O J21 EM35x GPIO 9 PA0 I/O J21 EM35x GPIO 10 PA1 I/O J21 EM35x GPIO 11 PA2 I/O J21 EM35x GPIO Pin # 12 PA3 I/O J21 EM35x GPIO 13 GND Power J21 Ground connection 14 PA4 I/O J21 EM35x GPIO 15 PA5 I/O J21 EM35x GPIO 16 PA6 I/O J21 EM35x GPIO 17 PB1 I/O J21 EM35x GPIO 18 PB2 I/O J21 EM35x GPIO 19 GND Power J21 Ground connection 20 GND Power J22 Ground connection 21 JCLK Input J22 JTAG interface, serial clock 22 PC2 I/O J22 EM35x GPIO 23 PC3 I/O J22 EM35x GPIO 24 PC4 I/O J22 EM35x GPIO 25 PB0 I/O J22 EM35x GPIO 26 PC1 I/O J22 EM35x GPIO 27 PC0 I/O J22 EM35x GPIO 28 PB7 I/O J22 EM35x GPIO 29 PB6 I/O J22 EM35x GPIO 30 PB5 I/O J22 EM35x GPIO 31 GND Power J22 Ground connection 32 VDD Power J22 2.1 to 3.6V Module Power Domain 33 GND Power J22 Ground connection 34 NC N/A J23 Not connected; guide pin 35 NC N/A J23 Not connected; guide pin Rev. 0.6 17 TS9 Pin # 2 2 Signal name Direction Connector Description 36 NC N/A J24 Not connected; guide pin 37 NC N/A J24 Not connected; guide pin with respect to the RCM 2.9 Host Module interface connector (J37-J38) Two single-row, 0.1” pitch, connectors make up the host module interface to the EM35x NCP Breakout Board. The board-to-board connector scheme allows access to 16 host GPIO. The connector is illustrated in Figure 6, while the dimensions are shown in Figure 7. J38 J37 VDD_3V_HOST 17 EZSP_UART2_nRTS 18 1 HGPIO10 EZSP_UART2_nCTS 19 2 HGPIO11 EZSP_UART2_RXD 20 3 HGPIO0 EZSP_UART2_TXD 21 4 HGPIO1 HGPIO7 22 5 HOST_nRESET HGPIO6 23 6 HGPIO8 HGPIO5 24 7 HGPIO9 HGPIO4 25 8 SER_UART1_nCTS HGPIO15 26 9 SER_UART1_nRTS HGPIO14 27 10 SER_UART1_TXD HGPIO13 28 11 SER_UART1_RXD HGPIO12 29 12 HOST_nSS HGPIO3 30 13 HOST_SCK HGPIO2 31 14 HOST_MISO HOST_BTL 32 15 HOST_MOSI NCP_nRESET 33 16 nHOST_INT nWAKE 34 N/C 35 GND 36 Figure 6. Board-to-Board Connector for the Host Module 18 Rev. 0.6 TS9 Figure 7. Board-to-Board Connector Dimensions for the Host Module Table 6 describes the pinout and signal names at both J37 and J38. 16 host GPIOs are exposed on the EM35x NCP Breakout Board at the 26-pin, dual row, 0.1” pitch GPIO connector (J41) for application development. For more information on the alternate functions of the GPIO connector, refer to the data sheet for the host microprocessor included on the host module. Table 6. Pinout and Signal Names of the Host Interface Connector Signal name Direction2 Connector Description 1 HGPIO10 I/O J37 Spare Host GPIO 2 HGPIO11 I/O J37 DataFlash Shutdown (DF_nSD) 3 HGPIO0 I/O J37 Application LED (LED0) 4 HGPIO1 I/O J37 Application LED (LED1) 5 HOST_nRESET I/O J37 Active low host reset 6 HGPIO8 I/O J37 Temperature Sensor ADC (TEMP_SENSOR) 7 HGPIO9 I/O J37 Spare Host GPIO 8 SER_UART1_nCTS I/O J37 Host UART1 Clear to Send 9 SER_UART1_nRTS I/O J37 Host UART1 Ready to Send Pin # 10 SER_UART1_TXD I/O J37 Host UART1 Transmit Data 11 SER_UART1_RXD I/O J37 Host UART1 Receive Data 12 HOST_nSS I/O J37 EZSP SPI Slave Select 13 HOST_SCK I/O J37 EZSP SPI Clock 14 HOST_MISO I/O J37 EZSP Master In-Slave Out 15 HOST_MOSI I/O J37 EZSP Master Out-Slave In 16 nHOST_INT I/O J37 EZSP Host Interrupt 17 VDD_3V_HOST Power J38 3.3V Connection 18 EZSP_UART2_nRTS I/O J38 EZSP UART Ready to Send 19 EZSP_UART2_nCTS I/O J38 EZSP UART Clear to Send Rev. 0.6 19 TS9 Pin # 2 2 Signal name Direction Connector Description 20 EZSP_UART2_RXD I/O J38 EZSP UART Receive Data 21 EZSP_UART2_TXD I/O J38 EZSP UART Transmit Data 22 HGPIO7 I/O J38 Temperature Sensor Enable (TEMP_ENABLE) 23 HGPIO6 I/O J38 Spare Host GPIO 24 HGPIO5 I/O J38 Spare Host GPIO 25 HGPIO4 I/O J38 Application Speaker (PIEZO) 26 HGPIO15 I/O J38 DataFlash SPI Serial Out (DF_SO) 27 HGPIO14 I/O J38 DataFlash SPI Serial In (DF_SI) 28 HGPIO13 I/O J38 DataFlash SPI Clock (DF_SCK) 29 HGPIO12 I/O J38 DataFlash SPI Chip Select (DF_nSS) 30 HGPIO3 I/O J38 Application Button (BUTTON1) 31 HGPIO2 I/O J38 Application Button (BUTTON0) 32 HOST_BTL I/O J38 Host Bootloader 33 NCP_nRESET I/O J38 Active low NCP reset 34 nWAKE I/O J38 EZSP SPI Wake 35 NC N/A J38 Not connected 36 GND Power J38 Ground connection with respect to the host 2.10 Prototyping Area The 1.6" x 1.8" (0.1” pitch) prototyping area on the EM35x NCP Breakout Board offers software developers an extra degree of flexibility. As shown in Figure 4, it allows access to VBRD, GND, and 16 host GPIOs. Therefore, you can solder any sensor or input device to the prototyping area and connect it to the host GPIO for development and debugging. As shown in Figure 8, the leftmost column is connected to GND and the rightmost column to VBRD. The top row is connected to the host GPIOs. Included in the top row are additional GND and JCLK connections. The remainder of the array is available for application development. 20 Rev. 0.6 VBRD HGPIO15 HGPIO13 HGPIO14 HGPIO11 HGPIO12 HGPIO7 HGPIO8 HGPIO9 HGPIO10 HGPIO5 HGPIO6 HGPIO3 HGPIO4 GND HGPIO0 HGPIO1 HGPIO2 TS9 Figure 8. EM35x NCP Breakout Board prototyping area 3 EM35x NCP Breakout Board Schematic The EM35x NCP Breakout Board schematic is included at the end of this document. Rev. 0.6 21 4 3 2 1 B B EM35X NCP Breakout Board Sheet 1 2 3 4 5 6 7 8 Details COVER SHEET POWER MANAGEMENT, MANUFACTURING APPLICATIONS CIRCUITS, BREADBOARD EM35X RCM CONNECTORS, USER INTERFACES HOST MODULE CONNECTOR, INTERFACES SPI/UART MUX/DEMUX CIRCUIT SPI/UART BLOCK DIAGRAM REVISION NOTES A A Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com DWG TITLE PAGE SCH0681 EM35X NCP BREAKOUT BOARD COVER SHEET REV A0 The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation SIZE B 4 3 2 DATE: SHEET: 19-09-2010_22:13 1 1 of 8 4 2 3 POWER SUPPLY, DC, 4V to 20V 1 Breakout Board and Module Power Selector USB / VIN_PWR_JACK Down Conversion * Place J1 close to J31 Headers J2 and J3 allow the user to select the power source. There are five possible power sources for the Breakout board. 1. External 3V Supply (Connect directly to J3.2) 2. External Regulated supply from 4V to 20V (Connect shorting jumper between J3 pins 2.3) 3. Ember battery pack with 2 AAA (Connect shorting jumper between J3 pins 1.2) 2. USB Bus Powered (Connect shorting jumper between J3 pins 2.3) 4. Debug Adapter (Connect shorting jumper between J2 and J3.2) VIN_PWR_SUPPLY J1 TEST_POINT 1 D1 BAT54C VIN_PWR_SUPPLY VDD_3V U1 LT1763CS8-3.3#PBF Datasheet 1 VREGIN 8 IN OUT 2 7 GND-3 SENSE 6 3 GND-1 4 5 GND-2 NSHDN BYP J32 TEST_POINT 1 C1 330NF L4P 1 VIN_USB 3 2 R1 0_Ohm VOUT_SENSE VIN_BATT VDD_3V_BB VDD_3V VDD_3V_EM35X J2 HEADER-1 C3 10uF BYPASS 1 J3 HEADER-3 J4 HEADER-2 3 2 20V MAX IN, 3V/500mA OUT C30 1uF 1 VDD_3V_HOST The shorting jumper at J4 can be replaced with a current meter to measure EM35x module current draw Kit Provide Battery Pack for 2 AAAs, voltage range 1.5V to 3.1V J34 HEADER-2 EM35x IC will not operate properly at voltages below 1.8V 1 D2 BAT54C J8 DF13-2P-1.25H(50) 1 BATTERY_IN 2 B 2 VIN_BATT 1 The shorting jumper at J34 can be replaced with a current meter to measure Host module current draw L4P C7 220NF 2 1 BATTERY INTERFACE B VDD_ISA C2 10NF 3 2 NC Power Indicator LEDs * Remove J6, J36 when performing a Deep Sleep Test USB CONNECTION (TYPE B) 5V VIN_USB VDD_ISA VIN_PWR_SUPPLY VDD_3V_EM35X VDD_3V_HOST 2 VIN_BATT DS1 RED DS3 RED J36 HEADER-2 1 1 USB_DM J5 USB-B-RA C4 47PF 2 U2 NUP2301MW6T1G DS5 RED VIN_USB VBUS 1 C6 10NF R3 1.0K R4 510 DS4 GREEN R2 2.2K DS8 GREEN 3 Datasheet R39 510 R5 510 R6 510 5 S1 1 2 3 4 S2 DS2 RED 1 J7 HEADER-2 FB1 BLM18PG600SN1D SHIELD1 VBUS DD+ GND SHIELD2 J6 HEADER-2 2 VIN_USB 2 * Remove J67 when performing a Deep Sleep Test with Battery USB_DP C5 47PF ESD Suppression (Power Supply) Test Equipment GND Connection PCB Information Shorting Jumpers A A PCB1 710-0681-000 FID1 FID2 FID3 Place shorting jumpers across the following connector pins; VIN_PWR_SUPPLY VIN_USB D3 GSOT15C-GS08 Datasheet J29 is placed close to J41 1 2 3 J29 HEADER-2 2 1 VIN_BATT D4 GSOT12C-GS08 Datasheet 1 2 3 NC J2 and J3.2 J4 J6 J7 J9 J10 J11 J12 J13 J14 J15 J16 J17 J25 J26 J27 J28 J33.2 J33.4 J33.6 J33.8 J33.10 J33.12 J34 J35 J36 J39.1 J40 J42.1 and J42.2 J42.3 and J42.4 J42.5 and J42.6 J42.7 and J42.8 J42.9 and J42.10 J42.11 and J42.12 J42.13 and J42.14 SN1 130-0681-000 Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com SHORTING JUMPER X 35 DWG TITLE PAGE 3 REV A0 SCH0681 EM35X NCP BREAKOUT BOARD POWER MANAGEMENT, MANUFACTURING The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation SIZE B 4 Fiducials 2 DATE: SHEET: 19-09-2010_22:20 1 2 of 8 4 2 3 Host Application LEDs 1 Host Application Buttons VDD_3V_BB Buttons C8 100nF C9 100nF VDD_3V_BB J9 HEADER-2 2 1 R8 100K J11 HEADER-2 2 1 HGPIO1 2 HGPIO0 U3 SN74LVC2G07DBVR 1 LED1 1 3 LED0 OUT1 IN2 OUT2 LED_1 4 1 3 2 4 J10 HEADER-2 2 1 HGPIO2 EM2 B3S-1000 R12 1.0K BUTTON0 EM2 1 3 2 4 DS6 LED_0 C11 100nF DS7 R11 510 DS7 RED 2 GND J12 HEADER-2 6 EM1 VDD_3V_BB DS6 GREEN R10 510 IN1 BUTTON1 C10 100nF SN74LVC2G07DBVR Datasheet VCC R7 100K 5 HGPIO3 EM1 B3S-1000 R9 1.0K B B EM35x RESET Button (Active Low) Host Temperature Sensor D5 EM35x Reset Selection BAT54AWT-TP J15 HEADER-2 2 1 HGPIO8 R15 100K MUX_nRESET TEMP_SENSE TEMP_SENSOR EM4 B3S-1000 J13 HEADER-2 2 1 HGPIO7 U4 LM20BIM7/NOPB TEMP_ENABLE 4 V+ VO 3 GND1 2 GND2 NC 5 1 C12 100nF R16 100K R13 0_Ohm VO 1 3 2 4 1 3 R17 1.0K EM35X_nRESET_BUTTON J16 HEADER-2 2 1 R33 nSIMRST DNI EM35X_nRESET_SRC R32 0_Ohm EM35X_nRESET 2 EM4 C13 DNI NC Datasheet LM20BIM7/NOPB EM35x Bootloader Button (Active Low) Host Piezo Speaker SPK1 CEP-1160 EM3 B3S-1000 Datasheet HGPIO4 J17 HEADER-2 2 1 PIEZO 1 2 Host RESET Button (Active Low) V+ V- 1 3 2 4 R14 1.0K EM3 J14 HEADER-2 2 1 EM5 B3S-1000 EM35X_PA5 A VDD_3V_BB J19 DNI 15x16_PIN_BREADBOARD_AREA J18 DNI HGPIO0 HGPIO1 HGPIO2 HGPIO3 HGPIO4 HGPIO5 HGPIO6 HGPIO7 HGPIO8 HGPIO9 HGPIO10 HGPIO11 HGPIO12 HGPIO13 HGPIO14 HGPIO15 3 2 4 R31 1.0K J35 HEADER-2 2 1 EM5 HOST_nRESET Host Bootloader Button (Active Low) Peripheral Scratch Pad (0.1" pitch) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 J20 DNI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 26-Pin, Dual Row Test Connector J41 S-HEADER-26 2 1 HGPIO0 4 3 HGPIO2 6 5 HGPIO4 8 7 HGPIO6 10 9 HGPIO8 12 11 HGPIO10 14 13 HGPIO12 16 15 HGPIO14 18 HOST_MOSI 17 20 HOST_SCK 19 22 EM35X_PB1 21 24 EM35X_PB3 23 26 25 nWAKE HGPIO1 HGPIO3 HGPIO5 HGPIO7 HGPIO9 HGPIO11 HGPIO13 HGPIO15 HOST_MISO HOST_nSS EM35X_PB2 EM35X_PB4 A EM6 B3S-1000 3 2 4 J40 HEADER-2 2 1 EM6 HOST_BTL Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com DWG TITLE PAGE X3 1 R34 1.0K REV A0 SCH0681 EM35X NCP BREAKOUT BOARD APPLICATIONS CIRCUITS, BREADBOARD The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation SIZE B 4 3 2 DATE: SHEET: 19-09-2010_22:13 1 3 of 8 4 2 3 EM3XX RCM Interface Header VCC30 U5 FT232RQ_R NC NC 14 J22 HEADER-14 Datasheet 33 32 31 30 29 28 27 26 25 24 23 22 21 20 CTS# NC NC NC NC NC VCC30 EM35X_PB5 nWAKE EM35X_PB7 EM35X_PC0 EM35X_PC1 nSIMRST EM35X_PC4 EM35X_PC3 EM35X_PC2 EM35X_JCLK 5 12 13 25 29 18 NC NC NC 23 27 28 16 NC-6 NC-5 NC-1 NC-4 NC-3 DSR# DCD# RI# FTDI_RXD C15 4.7UF C16 100nF NC-2 OSC1 OSC2 CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 3V3OUT CBUS2 TP2 TP3 FTDI_NCTS NDCD TP4 31 NDTR NDSR TP5 6 NDSR NRI TP6 7 NDCD CBUS0 TP7 3 NRI CBUS1 TP8 NDTR TP9 FTDI_NRTS 8 U5 FT232RQ_R 5 via grid for U5 PCB Footprint 22 21 10 11 9 CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 B T491A475K020AT NC NC 24 37 36 C14 100nF TP1 CBUS4 32 RESET# C17 100nF DNI DTR# 2 CBUS3 TEST J24 RTS# USBDP FTDI_TXD GND-5 GND-6 GND-7 GND-8 GND-9 USB_DP VDD_3V_EM35X RXD USBDM 30 26 EM35X_PA4 EM35X_PA5 EM35X_PA6 EM35X_PB1 EM35X_PB2 15 AGND B USB_DM TXD 34 35 36 37 38 DNI Datasheet EM35X_PC5 EM35X_PC6 EM35X_PC7 EM35X_PA7 EM35X_PB3 EM35X_nRESET EM35X_PB4 HOST_MOSI HOST_MISO HOST_SCK HOST_nSS FTDi GPIO Test Points VCC30 VCCIO VCC GND-2 GND-1 GND-3 GND-4 J23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 USB IC Decoupling VIN_USB 1 19 33 4 17 20 J21 HEADER-19 USB / UART IC Datasheet 34 35 X1 RCM_INTERFACE VIN_USB 1 VALUE Access to unused EM35x GPIO 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 (JTCK/SWCLK) (JTMS/SWDIO) (nRESET) (Packet Trace Frame) (Packet Trace Data) VDD_3V_BB J31 FTSH-105-01-F-DV-K EM35X_PC2 EM35X_PC0 EM35X_PC3 EM35X_JCLK EM35X_PC4 EM35X_nRESET EM35X_PA4 EM35X_PA5 R18 100K R19 100K C20 100nF C21 100nF 1 3 4 5 11 10 RS232_TXD RS232_nRTS 12 9 RS232_RXD RS232_nCTS C1+ C1C2+ C2TR1_IN TR2_IN V+ V- 2 C19 100nF 6 C22 100nF 14 TR1_OUT 7 TR2_OUT RX1_OUT RX2_OUT 13 RX1_IN 8 RX2_IN 15 GND DB9_TXD DB9_nRTS DB9_RXD DB9_nCTS J30 RECEPTACLE_DB9 NC 1 NC 6 2 7 3 8 NC 4 NC 9 5 DS10 DNI SERIAL_RXD TTL_TXD J26 HEADER-2 2 1 SERIAL_TXD TTL_nCTS J27 HEADER-2 2 1 SERIAL_nCTS TTL_nRTS J28 HEADER-2 2 1 SERIAL_nRTS 1 6 2 7 3 8 4 9 5 Datasheet VDD_3V_BB TTL_RXD J25 HEADER-2 2 1 U6 LTC1386CS#PBF 1 2 3 4 5 6 7 8 9 10 DNI A ---> TO USB/232 MUX 10NF 16 (Target Power) (JTDO/SWO) (nJRST) (JTDI) FROM DEI/TTL MUX <--- C18 VCC J44 EM35X_PA6 EM35X_PA7 EM35X_PB5 EM35X_PB7 EM35X_PC1 EM35X_PC5 EM35X_PC6 EM35X_PC7 VDD_3V_BB Datasheet VDD_3V_BB TTL Signal Access TTL to RS-232 Transceiver EM35x Packet Trace Port EM35x GPIO Header Configuration Mode Enable Switches A DS11 DNI VDD_3V_BB R36 DNI SPI_EN UART_MOD_EN R37 DNI R22 10K SW_SPI_EN SW_UART_MOD_EN R29 R30 DNI DNI R26 R27 0_Ohm 0_Ohm HW_SPI_EN HW_UART_MOD_EN DEI_EN USB_EN R23 10K R24 10K R25 10K Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com SW1 ADE0404 Datasheet 1 2 3 4 DWG 8 7 6 5 TITLE PAGE The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation Software/Hardware Enable SIZE B 4 REV A0 SCH0681 EM35X NCP BREAKOUT BOARD EM35X RCM CONNECTORS, USER INTERFACES 3 2 DATE: SHEET: 19-09-2010_22:13 1 4 of 8 4 2 3 Host DEI Host Module Interface Headers 1 Host Module Application Peripheral GPIO Mapping VDD_3V_BB J43 S-HEADER-12 2 1 4 3 6 5 8 7 10 9 11 12 DEI_BUTTON1 DEI_nRTS DEI_BUTTON0 DEI_SW_SPI_EN DEI_HOST_BTL X2 HOST_INTERFACE DEI_TXD DEI_RXD DEI_nCTS DEI_HOST_nRESET DEI_SW_UART_MOD_EN J37 SOCKET-16 Datasheet HGPIO10 HGPIO11 HGPIO0 HGPIO1 HOST_nRESET HGPIO8 HGPIO9 SER_UART1_nCTS SER_UART1_nRTS SER_UART1_TXD SER_UART1_RXD HOST_nSS HOST_SCK HOST_MISO HOST_MOSI nHOST_INT B Host DEI Jumpers Should be placed near J43 J42 Header-20 DEI_TXD DEI_BUTTON1 DEI_RXD DEI_nRTS DEI_nCTS DEI_BUTTON0 DEI_HOST_nRESET DEI_SW_SPI_EN DEI_SW_UART_MOD_EN DEI_HOST_BTL 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 DEI_TXD_JMP HGPIO3 DEI_RXD_JMP DEI_nRTS_JMP DEI_nCTS_JMP HGPIO2 HOST_nRESET SW_SPI_EN SW_UART_MOD_EN HOST_BTL VDD_3V_HOST J38 SOCKET-20 Datasheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 EZSP_UART2_nRTS EZSP_UART2_nCTS EZSP_UART2_RXD EZSP_UART2_TXD HGPIO7 HGPIO6 HGPIO5 HGPIO4 HGPIO15 HGPIO14 HGPIO13 HGPIO12 HGPIO3 HGPIO2 HOST_BTL NCP_nRESET nWAKE NC J37p35 - NC, available for later use HOST NET NAME GPIO FUNCTION HGPIO0 Application LED (LED0) HGPIO1 Application LED (LED1) HGPIO2 Application Button (BUTTON0) HGPIO3 Application Button (BUTTON1) HGPIO4 Application Speaker (PIEZO) HGPIO5 Spare GPIO HGPIO6 Spare GPIO HGPIO7 Temperature Sensor Enable (TEMP_ENABLE) HGPIO8 Temperature Sensor ADC (TEMP_SENSOR) HGPIO9 Spare GPIO HGPIO10 Spare GPIO HGPIO11 DataFlash Shutdown (DF_nSD) HGPIO12 DataFlash SPI Chip Select (DF_nCS) HGPIO13 DataFlash SPI Clock (DF_SCK) HGPIO14 DataFlash SPI Serial In (DF_SI) HGPIO15 DataFlash SPI Serial Out (DF_SO) B DataFlash (SPI Interface with Host) Voltage range of the AT45DB021D is 2.7V to 3.6V Radio Modules which are expected to operate at voltages below 2.7V will require a DC to DC up-converter supply source for the AT45DB021D Input data on SI is always latched on the rising edge of SCK Output data on SO is always clocked out on the falling edge of SCK VDD_3V_DF 0_Ohm DF_SI DF_SCK DF_nRESET DF_nCS 8 7 6 5 VDD_3V_HOST DF_SO HGPIO12 HGPIO13 HGPIO15 HGPIO14 HGPIO11 NDS355N R21 VDD_3V_DF 3 A R20 C23 10NF DF_nWP 0_Ohm DF_nSD R35 DNI 1 1 3 5 7 9 11 J33 Header-12 2 4 6 8 10 12 VDD_3V_DF DF_nCS DF_SCK DF_SO DF_SI DF_nSD A 2 VDD_3V_DF U7 AT45DB021D-SSH-B Datasheet 1 SI SO 2 SCK GND 3 nRESET VCC 4 nCS nWP R28 100K Q1 NDS355N Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com DWG TITLE PAGE REV A0 SCH0681 EM35X NCP BREAKOUT BOARD HOST MODULE CONNECTORS, INTERFACES The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation SIZE B 4 3 2 DATE: SHEET: 19-09-2010_22:13 1 5 of 8 4 2 3 1 SPI/UART Multiplexer/Demultiplexer Circuit VDD_3V_BB C24 100nF VDD_3V_BB VDD_3V_BB U8 SPI_EN AorB 14 TTL_RXD 4 8 TTL_TXD 15 X Y Z 16 SERIAL_RXD DEI_RXD_JMP TTL_nCTS 14 RS232_RXD FTDI_TXD TTL_nRTS 15 RS232_TXD FTDI_RXD MUX_nRESET DEI_EN USB_EN 4 X VDD_3V_BB Z 7 6 VEE nEN VDD_3V_BB Y Z SERIAL_TXD DEI_TXD_JMP 15 4 VCC Y Z AorB 7 6 VEE nEN DEI_EN 12 X0 13 X1 2 Y0 1 Y1 5 Z0 3 Z1 11 A 10 B 9 C 16 16 nCTS 8 GND 7 6 VEE nEN SER_UART1_TXD X NDTR EZSP_UART2_nRTS EM35X_PB4 SER_UART1_nCTS 14 nRTS SERIAL_nCTS DEI_nCTS_JMP 15 X Y 4 Z AorB 7 6 VEE nEN DEI_EN 12 X0 13 X1 2 Y0 1 Y1 5 Z0 3 Z1 11 A 10 B 9 C EZSP_UART2_nCTS SER_UART1_nRTS SERIAL_nRTS DEI_nRTS_JMP AorB DEI_EN 8 4 U13 CD74HC4053M Datasheet 14 HEADER-2 2 SPI_EN U12 EM35X_PB3 1 USB_EN CD74HC4053M Datasheet GND 15 NDTR_MUX NCP_nRESET U11 EZSP_UART2_RXD B J39 C29 100nF 8 TXD X RS232_nRTS FTDI_nCTS CD74HC4053M Datasheet 12 X0 13 X1 2 Y0 1 Y1 5 Z0 3 Z1 11 A 10 B 9 C VCC 14 RS232_nCTS FTDI_nRTS VDD_3V_BB C28 100nF 16 C27 100nF EM35X_PB1 12 X0 13 X1 2 Y0 1 Y1 5 Z0 3 Z1 11 A 10 B 9 C Y 8 GND 7 6 VEE nEN 12 X0 13 X1 2 Y0 1 Y1 5 Z0 3 Z1 11 A 10 B 9 C VCC RXD U10 CD74HC4053M Datasheet VCC GND 7 6 VEE nEN SER_UART1_RXD U9 CD74HC4053M Datasheet GND B Z EZSP_UART2_TXD C26 100nF GND 4 Y C25 100nF EM35X_PB2_UART nHOST_INT 12 X0 13 X1 2 Y0 1 Y1 5 Z0 3 Z1 11 A 10 B 9 C 8 15 X 16 14 VCC EM35X_PB2 VCC 16 CD74HC4053M Datasheet A A SPI_EN (A) or UART_MOD_EN (B) U14 74LX1G32STR Datasheet SPI_EN 1 UART_MOD_EN 2 3 1A Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com VDD_3V_BB VCC DWG 5 TITLE 1B GND 1Y 4 AorB PAGE REV A0 SCH0681 EM35X NCP BREAKOUT BOARD SPI/UART MUX/DEMUX CIRCUIT The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation SIZE B 4 3 2 DATE: SHEET: 19-09-2010_22:13 1 6 of 8 4 2 3 1 UART EM35X_PA0 (MOSI) EM35X_PA1 (MISO) EM35X_PA2 (SCLK) EM35X_PA3 (nSSEL) EM35X_PB0 (nSIMRST) EM35X_PB2 (nHOST_INT) EM35X_PB6 (nWAKE) EM35X EM35X_PB1 (TXD) EM35X_PB2 (RXD) EM35X_PB3 (nCTS) EM35X_PB4 (nRTS) SPI SPI_EN (A) || UART_MOD_EN (B) B 0 1 B DEI_EN SPI SPI_EN (A) || UART_MOD_EN (B) 0 MOSI MISO SCK nSS nHOST_INT nWAKE NCP_nRESET 1 TXD RXD nCTS nRTS 1 0 DEI_TXD DEI_RXD DEI_nCTS DEI_nRTS TTL_TXD TTL_RXD TTL_nCTS TTL_nRTS HOST USB_EN EZSP_UART2_RXD EZSP_UART2_TXD EZSP_UART2_nRTS EZSP_UART2_nCTS UART A TTL signal access by pulling 4 jumpers J25, J26,J27,J28 1 SERIAL_TXD SERIAL_RXD SERIAL_nCTS SERIAL_nRTS 0 FTDI_RXD FTDI_TXD FTDI_nRTS FTDI_nCTS RS232_TXD RS232_RXD RS232_nCTS RS232_nRTS A SER_UART1_TXD SER_UART1_RXD SER_UART1_nCTS SER_UART1_nRTS Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com DWG TITLE PAGE SCH0681 EM35X NCP BREAKOUT BOARD SPI/UART BLOCK DIAGRAM REV A0 The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation SIZE B 4 3 2 DATE: SHEET: 19-09-2010_22:13 1 7 of 8 2 B 1 SCHEMATIC NOTES: PCB LAYOUT NOTES: -- Version P0 -*Released: 2010-06-11 *Initial version released, Version P0 (initial draft) -- Version P0 -*Released: 2010-06-11 *Initial version released, Version P0 (initial draft) -- Version A0 --- Version A0 -*Released: 2010-09-20 *Released: 2010-09-20 *Production version release *Production version release *Changes from P0 to A0: *Changes from P0 to A0: 1) Schematic changes reflected in layout. 1) Swapped UART1 nets with UART2 nets based on changes for UART1 STM32 BTL. 2) Corrected J41p15 SST error (was HGPIO1 instead of HGPIO14). 2) Renamed UART1 nets to SER_UART1_TXD, etc. 3) Added pin1 marking for U7 SST. 3) Renamed UART2 nets to EZSP_UART1_TXD, etc. 4) Corrected board outline dimensioning error. 4) Updated sheet 7 chart for UART changes. 5) Added bump-on outlines in SSB and ASB. 5) Added SJ34-35 for J7 and J33.12. 6) Removed SW_DEI_EN and DEI_SW_DEI_EN (DS9, R28, R35, R38). 6) Corrected D5 decal error (was SOT23 instead of SOT323). 7) Updated LED0603 decal with Cathode C marking. 7) Updated J43p11 from DEI_SW_DEI_EN to DEI_HOST_BTL. 8) Updated J42p19/20 from DEI_EN to HOST_BTL. 8) Test point coverage for nets without probe access. 9) Symbol clean-up for using PART_NUMBER rather than Manufacturer P/N. 10) Replaced 570_0603_100 with _101, and _400 with _401. 11) Added Q1 shutdown transistor circuit for DataFlash. 12) Changed title block text from EZSP to NCP to reflect product name. 13) Corrected 500_4053_001 symbol due to error with Ember P/N (-000 instead of -001). 14) Added 1uF cap to input of regulator U1. 15) Changed C3 from 554-106A-016 (ESR 7 ohm) to 554-106A-020 (ESR 1 ohm). A B A Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999 www.ember.com DWG TITLE PAGE SCH0681 EM35X NCP BREAKOUT BOARD REVISION NOTES REV A0 The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in this document are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document is the proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwise used without the express permission of Ember Corporation SIZE A 2 DATE: SHEET: 19-09-2010_22:13 1 8 of 8 TS9 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page for ZigBee products: www.silabs.com/zigbee-support and register to submit a technical support request Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and Ember are registered trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 22 Rev. 0.6