PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Product Description The KXTF9 is a tri-axis +/-2g, +/-4g or +/-8g silicon micromachined accelerometer with integrated orientation, tap/double tap, and activity detecting algorithms. The sense element is fabricated using Kionix’s proprietary plasma micromachining process technology. Acceleration sensing is based on the principle of a differential capacitance arising from acceleration-induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from process variation, temperature, and environmental stress. The sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. A separate ASIC device packaged with the sense element provides signal conditioning, and intelligent user-programmable application algorithms. The accelerometer is delivered in a 3 x 3 x 0.9 mm LGA plastic package operating from a 1.8 – 3.6V DC supply. I2C interface is used to communicate to the chip to configure and check updates to the orientation, Directional TapTM detection and activity monitoring algorithms. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 1 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Functional Diagram X Sensor Y Sensor Charge Amp A/D Z Sensor Vdd 5 IO Vdd 1 I 2C Digital Engine Digital Filter GND 4 7 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] 9 10 © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 2 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Product Specifications Table 1. Mechanical (specifications are for operation at 1.8V and T = 25C unless stated otherwise) Parameters Units Min Typical Max Operating Temperature Range ºC -40 - 85 Zero-g Offset mg -125 - +125 Zero-g Offset Variation from RT over Temp. mg/ºC GSEL1=0, GSEL=0 (± 2g) Sensitivity (12-bit) 1 GSEL1=0, GSEL0=1 (± 4g) counts/g GSEL1=1, GSEL0=0 (± 8g) Sensitivity (8-bit) 1 GSEL1=0, GSEL=0 (± 2g) GSEL1=0, GSEL0=1 (± 4g) GSEL1=1, GSEL0=0 (± 8g) 0.7 (xy) 0.4 (z) counts/g 988 1024 1060 494 512 530 247 61 30 15 256 64 32 16 265 67 34 17 %/ºC 0.01 (xy) 0.03 (z) Offset Ratiometric Error (Vdd = 1.8V ± 5%) % 0.3 Sensitivity Ratiometric Error (Vdd = 1.8V ± 5%) % 0.4 (xy) 0.2 (z) Self Test Output change on Activation g 0.9 (x) 0.8 (y) 0.7 (z) Hz 3500 (xy) 1800 (z) % of FS 1 % 2 Sensitivity Variation from RT over Temp. Mechanical Resonance (-3dB) Non-Linearity Cross Axis Sensitivity Notes: 2 2 1. Resolution and acceleration ranges are user selectable via I C. 2. Resonance as defined by the dampened mechanical sensor. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 3 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Table 2. Electrical (specifications are for operation at 1.8V and T = 25C unless stated otherwise) Parameters Supply Voltage (Vdd) Operating I/O Pads Supply Voltage (VIO) Units Min Typical Max V 1.8 1.8 3.6 V 1.7 All On (Res = 1) Current Consumption All On (RES = 0) 470 A Bandwidth (-3dB) 0.9 * Vio 0.8 * Vio A ms ms kHz 4 Hz RES = 0 RES = 1 kHz Hz Output Data Rate (ODR) 5 V V V V 570 670 230 Standby 1 Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Pull-down Current RES = 0 RES = 1, ODR = 25 Hz RES = 1, ODR = 50Hz 2 Start Up Time RES = 1, ODR = 100Hz RES = 1, ODR = 200Hz RES = 1, ODR = 400Hz RES = 1, ODR = 800Hz 3 Power Up Time 2 I C Communication Rate Vdd 0.1 0 0.050 80 40 20 10 5 2.5 20 0.2 * Vio 0.2 * Vio - 400 25 50 1.59 ODR/2 800 Notes: 2 1. Assuming I C communication and minimum 1.5k pull-up resistor on SCL and SDA pins. Assuming Vio < 2V, if Vio > 2 V then the maximum Output Low Voltage is 0.4V. 2. Start up time is from PC1 set to valid outputs. 3. Power up time is from Vdd valid to device boot completion. 2 4. User selectable through I C. 5. User selectable and dependant on ODR and RES. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 4 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Table 3. Environmental Units Min Typical Max Supply Voltage (Vdd) Absolute Limits Operating Temperature Range Parameters V ºC -0.3 -40 - 6.0 85 Storage Temperature Range ºC -55 - Mech. Shock (powered and unpowered) g - - ESD V - - 150 5000 for 0.5ms 10000 for 0.2ms 2000 HBM Caution: ESD Sensitive and Mechanical Shock Sensitive Component, improper handling can cause permanent damage to the device. This product conforms to Directive 2002/95/EC of the European Parliament and of the Council of the European Union (RoHS). Specifically, this product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), or polybrominated diphenyl ethers (PBDE) above the maximum concentration values (MCV) by weight in any of its homogenous materials. Homogenous materials are "of uniform composition throughout." HF This product is halogen-free per IEC 61249-2-21. Specifically, the materials used in this product contain a maximum total halogen content of 1500 ppm with less than 900-ppm bromine and less than 900-ppm chlorine. Soldering Soldering recommendations are available upon request or from www.kionix.com. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 5 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Application Schematic SDA 10 IO Vdd C2 1 9 2 8 SCL KXTF9 3 7 4 6 INT 5 C1 Vdd Table 4. KXTF9 Pin Descriptions Pin Name Description 1 2 3 4 5 6 7 8 9 10 IO Vdd DNC DNC GND Vdd DNC INT DNC SCL SDA The power supply input for the digital communication bus. Decouple this pin to ground with a 0.1uF ceramic capacitor. Reserved – Do Not Connect Reserved – Do Not Connect Ground The power supply input. Decouple this pin to ground with a 1uF ceramic capacitor. Reserved – Do Not Connect Physical Interrupt Reserved – Do Not Connect I2C Serial Clock I2C Serial Data 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 6 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Test Specifications ! Special Characteristics: These characteristics have been identified as being critical to the customer. Every part is tested to verify its conformance to specification prior to shipment. Table 5. Test Specifications Parameter Zero-g Offset @ RT Sensitivity @ RT Current Consumption -- Operating 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] Specification 0 +/- 128 counts 1024 +/- 35.8 counts/g 470 <= Idd <= 670 uA Test Conditions 25C, Vdd = 1.8 V 25C, Vdd = 1.8 V 25C, Vdd = 1.8 V © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 7 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Package Dimensions and Orientation 3 x 3 x 0.9 mm LGA All dimensions and tolerances conform to ASME Y14.5M-1994 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 8 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Orientation +Y Pin 1 +X +Z When device is accelerated in +X, +Y or +Z direction, the corresponding output will increase. Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g): GSEL1=0, GSEL0=0 (± 2g) Position 1 2 3 4 Diagram Resolution (bits) X (counts) Y (counts) Z (counts) X-Polarity Y-Polarity Z-Polarity 12 8 0 0 1024 64 0 0 0 0 + 0 12 1024 0 0 + 0 0 8 64 0 0 12 0 -1024 0 8 0 -64 0 0 0 12 -1024 0 0 0 0 8 -64 0 0 5 Top 6 Bottom Bottom Top 12 8 0 0 0 0 1024 64 0 0 + 12 0 0 -1024 8 0 0 -64 0 0 - (1g) Earth’s Surface 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 9 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g): GSEL1=0, GSEL0=1 (± 4g) Position 1 2 3 4 Diagram Resolution (bits) X (counts) Y (counts) Z (counts) X-Polarity Y-Polarity Z-Polarity 12 8 0 0 512 32 0 0 0 0 + 0 12 512 0 0 8 32 0 0 + 0 0 12 0 -512 0 8 0 -32 0 0 0 12 -512 0 0 8 -32 0 0 0 0 5 Top 6 Bottom Bottom Top 12 0 0 512 0 0 + 8 0 0 32 12 0 0 -512 8 0 0 -32 0 0 - (1g) Earth’s Surface 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 10 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g): GSEL1=1, GSEL0=0 (± 8g) Position 1 2 3 4 5 Top Diagram Resolution (bits) X (counts) Y (counts) Z (counts) X-Polarity Y-Polarity Z-Polarity 6 Bottom Top 12 8 0 0 256 16 0 0 0 0 + 0 12 256 0 0 8 16 0 0 + 0 0 12 0 -256 0 8 0 -16 0 0 0 12 -256 0 0 0 0 Bottom 8 12 8 -16 0 0 0 0 0 0 256 16 0 0 + 12 0 0 -256 8 0 0 -16 0 0 - (1g) Earth’s Surface 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 11 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 KXTF9 Digital Interface The Kionix KXTF9 digital accelerometer has the ability to communicate on the I 2C digital serial interface bus. This flexibility allows for easy system integration by eliminating analog-to-digital converter requirements and by providing direct communication with system micro-controllers. The serial interface terms and descriptions as indicated in Table 6 below will be observed throughout this document. Term Transmitter Receiver Master Slave Description The device that transmits data to the bus. The device that receives data from the bus. The device that initiates a transfer, generates clock signals, and terminates a transfer. The device addressed by the Master. Table 6. Serial Interface Terminologies I2C Serial Interface As previously mentioned, the KXTF9 has the ability to communicate on an I 2C bus. I2C is primarily used for synchronous serial communication between a Master device and one or more Slave devices. The Master, typically a micro controller, provides the serial clock signal and addresses Slave devices on the bus. The KXTF9 always operates as a Slave device during standard Master-Slave I2C operation. I2C is a two-wire serial interface that contains a Serial Clock (SCL) line and a Serial Data (SDA) line. SCL is a serial clock that is provided by the Master, but can be held low by any Slave device, putting the Master into a wait condition. SDA is a bi-directional line used to transmit and receive data to and from the interface. Data is transmitted MSB (Most Significant Bit) first in 8-bit per byte format, and the number of bytes transmitted per transfer is unlimited. The I2C bus is considered free when both lines are high. I2C Operation Transactions on the I2C bus begin after the Master transmits a start condition (S), which is defined as a highto-low transition on the data line while the SCL line is held high. The bus is considered busy after this condition. The next byte of data transmitted after the start condition contains the Slave Address (SAD) in the seven MSBs (Most Significant Bits), and the LSB (Least Significant Bit) tells whether the Master will be receiving data ‘1’ from the Slave or transmitting data ‘0’ to the Slave. When a Slave Address is sent, each device on the bus compares the seven MSBs with its internally stored address. If they match, the device considers itself addressed by the Master. The Slave Address associated with the KXTF9 is 0001111. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 12 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 It is mandatory that receiving devices acknowledge (ACK) each transaction. Therefore, the transmitter must release the SDA line during this ACK pulse. The receiver then pulls the data line low so that it remains stable low during the high period of the ACK clock pulse. A receiver that has been addressed, whether it is Master or Slave, is obliged to generate an ACK after each byte of data has been received. To conclude a transaction, the Master must transmit a stop condition (P) by transitioning the SDA line from low to high while SCL is high. The I2C bus is now free. Writing to a KXTF9 8-bit Register Upon power up, the Master must write to the KXTF9’s control registers to set its operational mode. Therefore, when writing to a control register on the I2C bus, as shown Sequence 1 on the following page, the following protocol must be observed: After a start condition, SAD+W transmission, and the KXTF9 ACK has been returned, an 8-bit Register Address (RA) command is transmitted by the Master. This command is telling the KXTF9 to which 8-bit register the Master will be writing the data. Since this is I2C mode, the MSB of the RA command should always be zero (0). The KXTF9 acknowledges the RA and the Master transmits the data to be stored in the 8-bit register. The KXTF9 acknowledges that it has received the data and the Master transmits a stop condition (P) to end the data transfer. The data sent to the KXTF9 is now stored in the appropriate register. The KXTF9 automatically increments the received RA commands and, therefore, multiple bytes of data can be written to sequential registers after each Slave ACK as shown in Sequence 2 on the following page. Reading from a KXTF9 8-bit Register When reading data from a KXTF9 8-bit register on the I2C bus, as shown in Sequence 3 on the next page, the following protocol must be observed: The Master first transmits a start condition (S) and the appropriate Slave Address (SAD) with the LSB set at ‘0’ to write. The KXTF9 acknowledges and the Master transmits the 8-bit RA of the register it wants to read. The KXTF9 again acknowledges, and the Master transmits a repeated start condition (Sr). After the repeated start condition, the Master addresses the KXTF9 with a ‘1’ in the LSB (SAD+R) to read from the previously selected register. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NACK) it received the transmitted data, but transmits a stop condition to end the data transfer. Note that the KXTF9 automatically increments through its sequential registers, allowing data to be read from multiple registers following a single SAD+R command as shown below in Sequence 4 on the following page. If a receiver cannot transmit or receive another complete byte of data until it has performed some other function, it can hold SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases SCL. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 13 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Data Transfer Sequences The following information clearly illustrates the variety of data transfers that can occur on the I2C bus and how the Master and Slave interact during these transfers. Table 7 defines the I 2C terms used during the data transfers. Term S Sr SAD W R ACK NACK RA Data P Definition Start Condition Repeated Start Condition Slave Address Write Bit Read Bit Acknowledge Not Acknowledge Register Address Transmitted/Received Data Stop Condition Table 7. I2C Terms Sequence 1. The Master is writing one byte to the Slave. Master Slave S SAD + W RA ACK DATA ACK P ACK Sequence 2. The Master is writing multiple bytes to the Slave. Master Slave S SAD + W RA ACK DATA ACK DATA ACK P ACK Sequence 3. The Master is receiving one byte of data from the Slave. Master Slave S SAD + W RA ACK Sr SAD + R ACK NACK ACK P DATA Sequence 4. The Master is receiving multiple bytes of data from the Slave. Master Slave S SAD + W 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] RA ACK Sr ACK SAD + R ACK ACK DATA NACK DATA © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 14 of 49 P PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 KXTF9 Embedded Registers The KXTF9 has 39 embedded 8-bit registers that are accessible by the user. This section contains the addresses for all embedded registers and also describes bit functions of each register. Table 8 below provides a listing of the accessible 8-bit registers and their addresses. Register Name XOUT_HPF_L XOUT_HPF_H YOUT_HPF_L YOUT_HPF_H ZOUT_HPF_L ZOUT_HPF_H XOUT_L XOUT_H YOUT_L YOUT_H ZOUT_L ZOUT_H DCST_RESP Not Used Not Used WHO_AM_I TILT_POS_CUR TILT_POS_PRE Kionix Reserved Kionix Reserved Kionix Reserved INT_SRC_REG1 INT_SRC_REG2 Not Used STATUS_REG Not Used INT_REL CTRL_REG1* 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] Type Read/Write R R R R R R R R R R R R R R R R R R R R R/W I2C Read/Write Address Hex Binary 0x00 0000 0000 0x01 0000 0001 0x02 0000 0010 0x03 0000 0011 0x04 0001 0100 0x05 0001 0101 0x06 0000 0110 0x07 0000 0111 0x08 0000 1000 0x09 0000 1001 0x0A 0001 1010 0x0B 0001 1011 0x0C 0000 1100 0x0D 0000 1101 0x0E 0000 1110 0x0F 0000 1111 0x10 0001 0000 0x11 0001 0001 0x12 0001 0010 0x13 0001 0011 0x14 0001 0100 0x15 0001 0101 0x16 0001 0110 0x17 0001 0111 0x18 0001 1000 0x19 0001 1001 0x1A 0001 1010 0x1B 0001 1011 © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 15 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications CTRL_REG2* CTRL_REG3* INT_CTRL_REG1* INT_CTRL_REG2* INT_CTRL_REG3* DATA_CTRL_REG* Not Used TILT_TIMER* WUF_TIMER* Not Used TDT_TIMER* TDT_H_THRESH* TDT_L_THRESH* TDT_TAP_TIMER* TDT_TOTAL_TIMER* TDT_LATENCY_TIMER* TDT_WINDOW_TIMER* Reserved SELF_TEST Reserved WUF_THRESH* Reserved TILT_ANGLE* Reserved HYST_SET* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 – 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 – 0x39 0x3A 0x3B – 0x59 0x5A 0x5B 0x5C 0x5D – 0x5E 0x5F KXTF9-4100 Rev. 6 Jun-2011 0001 1100 0001 1101 0001 1110 0001 1111 0010 0000 0010 0001 0010 1000 0010 1001 0010 1010 0010 1011 0010 1100 0010 1101 0010 1110 0010 1111 0011 0000 0011 0001 0011 1010 0101 1010 0101 1011 0101 1100 0101 1111 * Note: When changing the contents of these registers, the PC1 bit in CTRL_REG1 must first be set to “0”. Table 8. KXTF9 Register Map 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 16 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 KXTF9 Register Descriptions Accelerometer Outputs These registers contain up to 12-bits of valid acceleration data for each axis depending on the setting of the RES bit in CTRL_REG1, where the acceleration outputs are represented in 12-bit valid data when RES = ‘1’ and 8-bit valid data when RES = ‘0’. The data is updated every user-defined ODR period, is protected from overwrite during each read, and can be converted from digital counts to acceleration (g) per Figure 9. The register acceleration output binary data is represented in 2’s complement format. For example, if N = 12 bits, then the Counts range is from -2048 to 2047, and if N = 8 bits, then the Counts range is from -128 to 127. 12-bit Register Data (2’s complement) 0111 1111 1111 0111 1111 1110 … 0000 0000 0001 0000 0000 0000 1111 1111 1111 … 1000 0000 0001 1000 0000 0000 8-bit Register Data (2’s complement) 0111 1111 0111 1110 … 0000 0001 0000 0000 1111 1111 … 1000 0001 1000 0000 Equivalent Counts in decimal 2047 2046 … 1 0 -1 … -2047 -2048 Range = +/-2g +1.999g +1.998g … +0.001g 0.000g -0.001g … -1.999g -2.000g Range = +/-4g +3.998g +3.996g … +0.002g 0.000g -0.002g … -3.998g -4.000g Range = +/-8g +7.996g +7.992g … +0.004g 0.000g -0.004g … -7.996g -8.000g Equivalent Counts in decimal 127 126 … 1 0 -1 … -127 -128 Range = +/-2g +1.984g +1.968g … +0.016g 0.000g -0.016g … -1.984g -2.000g Range = +/-4g +3.968g +3.936g … +0.032g 0.000g -0.032g … -3.968g -4.000g Range = +/-8g +7.936g +7.872g … +0.064g 0.000g -0.064g … -7.936g -8.000g Figure 9. Acceleration (g) Calculation 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 17 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 XOUT_HPF_L X-axis high-pass filtered accelerometer output least significant byte R XOUTD3 Bit7 R XOUTD2 Bit6 R XOUTD1 Bit5 R XOUTD0 Bit4 R X Bit3 R X Bit2 R X Bit1 R X Bit0 2 I C Address: 0x00h XOUT_HPF_H X-axis high-pass filtered accelerometer output most significant byte R R R XOUTD11 XOUTD10 XOUTD9 Bit7 Bit6 Bit5 R XOUTD8 Bit4 R XOUTD7 Bit3 R XOUTD6 Bit2 R XOUTD5 Bit1 R XOUTD4 Bit0 2 I C Address: 0x01h YOUT_HPF_L Y-axis high-pass filtered accelerometer output least significant byte R YOUTD3 Bit7 R YOUTD2 Bit6 R YOUTD1 Bit5 R YOUTD0 Bit4 R X Bit3 R X Bit2 R X Bit1 R X Bit0 2 I C Address: 0x02h YOUT_HPF_H Y-axis high-pass filtered accelerometer output most significant byte R R R YOUTD11 YOUTD10 YOUTD9 Bit7 Bit6 Bit5 R YOUTD8 Bit4 R YOUTD7 Bit3 R YOUTD6 Bit2 R YOUTD5 Bit1 R YOUTD4 Bit0 2 I C Address: 0x03h 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 18 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 ZOUT_HPF_L Z-axis high-pass filtered accelerometer output least significant byte R ZOUTD3 Bit7 R ZOUTD2 Bit6 R ZOUTD1 Bit5 R ZOUTD0 Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 I2C Address: 0x04h ZOUT_HPF_H Z-axis high-pass filtered accelerometer output most significant byte R R R ZOUTD11 ZOUTD10 ZOUTD9 Bit7 Bit6 Bit5 R ZOUTD8 Bit4 R ZOUTD7 Bit3 R ZOUTD6 Bit2 R ZOUTD5 Bit1 R ZOUTD4 Bit0 2 I C Address: 0x05h XOUT_L X-axis accelerometer output least significant byte R XOUTD3 Bit7 R XOUTD2 Bit6 R XOUTD1 Bit5 R XOUTD0 Bit4 R X Bit3 R X Bit2 R X Bit1 R X Bit0 2 I C Address: 0x06h XOUT_H X-axis accelerometer output most significant byte R R R XOUTD11 XOUTD10 XOUTD9 Bit7 Bit6 Bit5 R XOUTD8 Bit4 R XOUTD7 Bit3 R XOUTD6 Bit2 R XOUTD5 Bit1 R XOUTD4 Bit0 2 I C Address: 0x07h 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 19 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 YOUT_L Y-axis accelerometer output least significant byte R YOUTD3 Bit7 R YOUTD2 Bit6 R YOUTD1 Bit5 R YOUTD0 Bit4 R X Bit3 R X Bit2 R X Bit1 R X Bit0 2 I C Address: 0x08h YOUT_H Y-axis accelerometer output most significant byte R R R YOUTD11 YOUTD10 YOUTD9 Bit7 Bit6 Bit5 R YOUTD8 Bit4 R YOUTD7 Bit3 R YOUTD6 Bit2 R YOUTD5 Bit1 R YOUTD4 Bit0 2 I C Address: 0x09h ZOUT_L Z-axis accelerometer output least significant byte R ZOUTD3 Bit7 R ZOUTD2 Bit6 R ZOUTD1 Bit5 R ZOUTD0 Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 I2C Address: 0x0Ah ZOUT_H Z-axis accelerometer output most significant byte R R R ZOUTD11 ZOUTD10 ZOUTD9 Bit7 Bit6 Bit5 R ZOUTD8 Bit4 R ZOUTD7 Bit3 R ZOUTD6 Bit2 R ZOUTD5 Bit1 R ZOUTD4 Bit0 2 I C Address: 0x0Bh 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 20 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 DCST_RESP This register can be used to verify proper integrated circuit functionality. It always has a byte value of 0x55h unless the DCST bit in CTRL_REG3 is set. At that point this value is set to 0xAAh. The byte value is returned to 0x55h after reading this register. R DCSTR7 Bit7 R DCSTR6 Bit6 R DCSTR5 Bit5 R DCSTR4 Bit4 R DCSTR3 Bit3 R DCSTR2 Bit2 R DCSTR1 Bit1 R DCSTR0 Bit0 Reset Value 01010101 2 I C Address: 0x0Ch WHO_I_AM This register can be used for supplier recognition, as it can be factory written to a known byte value. The default value is 0x01h. R WIA7 Bit7 R WIA6 Bit6 R WIA5 Bit5 R WIA4 Bit4 R WIA3 Bit3 R WIA2 Bit2 R WIA1 Bit1 R WIA0 Bit0 Reset Value 00000001 2 I C Address: 0x0Fh 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 21 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Tilt Position Registers These two registers report previous and current position data that is updated at the user-defined ODR frequency and is protected during register read. Table 9 describes the reported position for each bit value. TILT_POS_CUR Current tilt position register R 0 Bit7 R 0 Bit6 R LE Bit5 R RI Bit4 R DO Bit3 R UP Bit2 R FD Bit1 R FU Bit0 Reset Value 00100000 2 I C Address: 0x10h TILT_POS_PRE Previous tilt position register R 0 Bit7 R 0 Bit6 R LE Bit5 R RI Bit4 R DO Bit3 R UP Bit2 R FD Bit1 R FU Bit0 Reset Value 00100000 2 I C Address: 0x11h Bit LE RI DO UP FD FU Description Left State (X-) Right State (X+) Down State (Y-) Up State (Y+) Face-Down State (Z-) Face-Up State (Z+) Table 9. KXTF9 Tilt Position 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 22 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Interrupt Source Registers These two registers report function state changes. This data is updated when a new state change or event occurs and each applications result is latched until the interrupt release register is read. The motion interrupt bit WUFS can be configured to report data in an unlatched manner via the interrupt control registers. INT_SRC_REG1 This register reports which axis and direction detected a single or double tap event, per Table 10. R 0 Bit7 R 0 Bit6 R TLE Bit5 R TRI Bit4 R TDO Bit3 R TUP Bit2 R TFD Bit1 R TFU Bit0 2 I C Address: 0x15h Bit TLE TRI TDO TUP TFD TFU Description X Negative (X-) Reported X Positive (X+) Reported Y Negative (Y-) Reported Y Positive (Y+) Reported Z Negative (Z-) Reported Z Positive (Z+) Reported Table 10. KXTF9 Directional TapTM Reporting INT_SRC_REG2 This register reports which function caused an interrupt. Reading from the interrupt release register will clear the entire contents of this register. R 0 Bit7 R 0 Bit6 R 0 Bit5 R DRDY Bit4 R TDTS1 Bit3 R TDTS0 Bit2 R WUFS Bit1 R TPS Bit0 2 I C Address: 0x16h DRDY indicates that new acceleration data is available. This bit is cleared when acceleration data is read or the interrupt release register is read. DRDY = 0 – new acceleration data not available DRDY = 1 – new acceleration data available 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 23 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 TDTS1, TDTS0 indicates whether a single or double-tap event was detected per Table 11. TDTS1 0 0 1 1 TDTS0 Event 0 No Tap 1 Single Tap 0 Double Tap 1 DNE Table 11. Directional TapTM Event Description TPS reflects the status of the tilt position function. TPS = 0 – tilt position state has not changed TPS = 1 – tilt position state has changed STATUS_REG This register reports the status of the interrupt. R 0 Bit7 R 0 Bit6 R 0 Bit5 R INT Bit4 R 0 Bit3 R 0 Bit2 R 0 Bit1 R 0 Bit0 2 I C Address: 0x18h INT reports the combined interrupt information of all enabled functions. This bit is released to 0 when the interrupt source latch register (1Ah) is read. INT = 0 – no interrupt event INT = 1 – interrupt event has occurred 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 24 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 INT_REL Latched interrupt source information (INT_SRC_REG1 and INT_SRC_REG2), the status register, and the physical interrupt pin (7) are cleared when reading this register. R X Bit7 R X Bit6 R X Bit5 R X Bit4 R X Bit3 R X Bit2 R X Bit1 R X Bit0 2 I C Address: 0x1Ah CTRL_REG1 Read/write control register that controls the main feature set. R/W PC1 Bit7 R/W RES Bit6 R/W DRDYE Bit5 R/W GSEL1 Bit4 R/W GSEL0 Bit3 R/W TDTE Bit2 R/W WUFE Bit1 R/W TPE Bit0 Reset Value 00000000 2 I C Address: 0x1Bh PC1 controls the operating mode of the KXTF9. PC1 = 0 - stand-by mode PC1 = 1 – operating mode RES determines the performance mode of the KXTF9. Note that to change the value of this bit, the PC1 bit must first be set to “0”. RES = 0 – low current, 8-bit valid RES = 1- high current, 12-bit valid DRDYE enables the reporting of the availability of new acceleration data on the interrupt. Note that to change the value of this bit, the PC1 bit must first be set to “0”. DRDYE = 0 – availability of new acceleration data not reflected on interrupt pin (7) DRDYE = 1- availability of new acceleration data reflected on interrupt pin (7) 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 25 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 GSEL1, GSEL0 selects the acceleration range of the accelerometer outputs per Table 12. Note that to change the value of this bit, the PC1 bit must first be set to “0”. GSEL1 GSEL0 0 0 0 1 1 0 1 1 Range +/-2g +/-4g +/-8g NA Table 12. Selected Acceleration Range TDTE enables the Directional TapTM function that will detect single and double tap events. Note that to change the value of this bit, the PC1 bit must first be set to “0”. TDTE = 0 – disable TDTE = 1- enable WUFE enables the Wake Up (motion detect) function that will detect a general motion event. Note that to change the value of this bit, the PC1 bit must first be set to “0”. WUFE = 0 – disable WUFE = 1- enable TPE enables the Tilt Position function that will detect changes in device orientation. Note that to change the value of this bit, the PC1 bit must first be set to “0”. TPE = 0 – disable TPE = 1- enable 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 26 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 CTRL_REG2 Read/write control register that controls tilt position state enabling. Per Table 13, if a state’s bit is set to one (1), a transition into the corresponding orientation state will generate an interrupt. If it is set to zero (0), a transition into the corresponding orientation state will not generate an interrupt. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W 0 Bit7 R/W 0 Bit6 R/W LEM Bit5 R/W RIM Bit4 R/W DOM Bit3 R/W UPM Bit2 R/W FDM Bit1 R/W FUM Bit0 Reset Value 00111111 2 I C Address: 0x1Ch Bit LEM RIM DOM UPM FDM FUM Description Left State Right State Down State Up State Face-Down State Face-Up State Table 13. Tilt Position State Enabling 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 27 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 CTRL_REG3 Read/write control register that provides more feature set control. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W SRST Bit7 R/W OTPA Bit6 R/W OTPB Bit5 R/W DCST Bit4 R/W OTDTA Bit3 R/W OTDTB Bit2 R/W OWUFA Bit1 R/W OWUFB Bit0 Reset Value 01001101 2 I C Address: 0x1Dh SRST initiates software reset, which performs the RAM reboot routine. This bit will remain 1 until the RAM reboot routine is finished. SRST = 0 – no action SRST = 1 – start RAM reboot routine OTPA, OTPB sets the output data rate for the Tilt Position function per Table 14. The default Tilt Position ODR is 12.5Hz. OTPA 0 0 1 1 OTPB 0 1 0 1 Output Data Rate 1.6Hz 6.3Hz 12.5Hz 50Hz Table 14. Tilt Position Function Output Data Rate DCST initiates the digital communication self-test function. DCST = 0 – no action DCST = 1 – sets ST_RESP register to 0xAAh and when ST_RESP is read, sets this bit to 0 and sets ST_RESP to 0x55h 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 28 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 OTDTA, OTDTB sets the output data rate for the Directional TapTM function per Table 15. The default Directional TapTM ODR is 400Hz. OTDTA OTDTB Output Data Rate 0 0 50Hz 0 1 100Hz 1 0 200Hz 1 1 400Hz Table 15. Directional TapTM Function Output Data Rate OWUFA, OWUFB sets the output data rate for the general motion detection function and the high-pass filtered outputs per Table 16. The default Motion Wake Up ODR is 50Hz. OWUFA OWUFB Output Data Rate 0 0 25Hz 0 1 50Hz 1 0 100Hz 1 1 200Hz Table 16. Motion Wake Up Function Output Data Rate 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 29 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 INT_CTRL_REG1 This register controls the settings for the physical interrupt pin (7). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W 0 Bit7 R/W 0 Bit6 R/W IEN Bit5 R/W IEA Bit4 R/W IEL Bit3 R/W IEU Bit2 R/W 0 Bit1 R/W 0 Bit0 Reset Value 00010000 2 I C Address: 0x1Eh IEN enables/disables the physical interrupt pin (7) IEN = 0 – physical interrupt pin (7) is disabled IEN = 1 – physical interrupt pin (7) is enabled IEA sets the polarity of the physical interrupt pin (7) IEA = 0 – polarity of the physical interrupt pin (7) is active low IEA = 1 – polarity of the physical interrupt pin (7) is active high IEL sets the response of the physical interrupt pin (7) IEL = 0 – the physical interrupt pin (7) latches until it is cleared by reading INT_REL IEL = 1 – the physical interrupt pin (7) will transmit one pulse with a period of 0.05ms IEU sets an alternate unlatched response for the physical interrupt pin (7) when the motion interrupt feature (WUF) only is enabled. IEU = 0 – the physical interrupt pin (7) latches or pulses per the IEL bit until it is cleared by reading INT_REL IEU = 1 – the physical interrupt pin (7) will follow an unlatched response if the motion interrupt feature is enabled 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 30 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 INT_CTRL_REG2 This register controls motion detection axis enabling. Per Table 17, if an axis’ bit is set to one (1), a motion on that axis will generate an interrupt. If it is set to zero (0), a motion on that axis will not generate an interrupt. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W XBW Bit7 R/W YBW Bit6 R/W ZBW Bit5 R/W 0 Bit4 R/W 0 Bit3 Bit XBW YBW ZBW R/W 0 Bit2 R/W R/W 0 0 Bit1 Bit0 I2C Address: 0x1Fh Reset Value 11100000 Description X-Axis Motion Y-Axis Motion Z-Axis Motion Table 17. Motion Detection Axis Enabling 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 31 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 INT_CTRL_REG3 This register controls the tap detection direction axis enabling. Per Table 18, if a direction’s bit is set to one (1), a single or double tap in that direction will generate an interrupt. If it is set to zero (0), a single or double tap in that direction will not generate an interrupt. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W 0 Bit7 R/W 0 Bit6 R/W TLEM Bit5 R/W TRIM Bit4 R/W TDOM Bit3 R/W TUPM Bit2 R/W TFDM Bit1 R/W TFUM Bit0 Reset Value 00111111 2 I C Address: 0x20h Bit TLEM TRIM TDOM TUPM TFDM TFUM Description X Negative (X-) X Positive (X+) Y Negative (Y-) Y Positive (Y+) Z Negative (Z-) Z Positive (Z+) Table 18. Directional TapTM Axis Mask 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 32 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 DATA_CTRL_REG Read/write control register that configures the acceleration outputs. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W 0 Bit7 R/W 0 Bit6 R/W HPFROA Bit5 R/W HPROB Bit4 R/W 0 Bit3 R/W OSAA Bit2 R/W OSAB Bit1 R/W OSAC Bit0 Reset Value 00000010 2 I C Address: 0x21h HPFROA, HPFROB sets the roll-off frequency for the first-order high-pass filter in conjunction with the output data rate (OWUFA, OWUFB) that is chosen for the HPF acceleration outputs that are used in the Motion Wake Up (WUF) application per Table 19. Note that this roll-off frequency is also applied to the X, Y and Z high-pass filtered outputs. High-Pass Filter Configuration HPFROA HPFROB Beta HPF Roll-Off (Hz) 0 0 7/8 ODR / 50 0 1 15/16 ODR / 100 1 0 31/32 ODR / 200 1 1 63/64 ODR / 400 Table 19. High-Pass Filter Roll-Off Frequency OSAA, OSAB, OSAC sets the output data rate (ODR) for the low-pass filtered acceleration outputs per Table 20. OSAA 0 0 0 1 1 1 1 OSAB 0 1 1 0 0 1 1 OSAC 1 0 1 0 1 0 1 Output Data Rate 25Hz 50Hz 100Hz 200Hz 400Hz 800Hz Does Not Exist LPF Roll-Off 12.5Hz 25Hz 50Hz 100Hz 200Hz 400Hz Does Not Exist Table 20. LPF Acceleration Output Data Rate (ODR) 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 33 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 TILT_TIMER This register is the initial count register for the tilt position state timer (0 to 255 counts). Every count is calculated as 1/ODR delay period, where the ODR is user-defined per Table 14. A new state must be valid as many measurement periods before the change is accepted. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TSC7 Bit7 R/W TSC6 Bit6 R/W TSC5 Bit5 R/W TSC4 Bit4 R/W TSC3 Bit3 R/W TSC2 Bit2 R/W TSC1 Bit1 R/W TSC0 Bit0 Reset Value 00000000 2 I C Address: 0x28h WUF_TIMER This register is the initial count register for the motion detection timer (0 to 255 counts). Every count is calculated as 1/ODR delay period, where the ODR is user-defined per Table 16. A new state must be valid as many measurement periods before the change is accepted. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W WUFC7 Bit7 R/W WUFC6 Bit6 R/W WUFC5 Bit5 R/W WUFC4 Bit4 R/W WUFC3 Bit3 R/W R/W R/W WUFC2 WUFC1 WUFC0 Bit2 Bit1 Bit0 2 I C Address: 0x29h Reset Value 00000000 TDT_TIMER This register contains counter information for the detection of a double tap event. Every count is calculated as 1/ODR delay period, where the ODR is user-defined per Table 15. TDT_TIMER represents the minimum time separation between the first tap and the second tap in a double tap event. The Kionix recommended default value is 0.3 seconds (0x78h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TDTC7 Bit7 R/W TDTC6 Bit6 R/W TDTC5 Bit5 R/W TDTC4 Bit4 R/W TDTC3 Bit3 R/W TDTC2 Bit2 R/W TDTC1 Bit1 R/W TDTC0 Bit0 Reset Value 01111000 2 I C Address: 0x2Bh 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 34 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 TDT_H_THRESH This register represents the 9-bit jerk high threshold to determine if a tap is detected. The Performance Index (PI) is the jerk signal that is expected to be less than this threshold, but greater than the TDT_L_THRESH threshold during single and double tap events. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. The Kionix recommended default value is 182 (0xB6h) and the Performance Index is calculated as: X’ = X(current) – X(previous) Y’ = Y(current) – Y(previous) Z’ = Z(current) – Z(previous) PI = |X’| + |Y’| + |Z’| Equation 1. Performance Index R/W TTH8 Bit7 R/W TTH7 Bit6 R/W TTH6 Bit5 R/W TTH5 Bit4 R/W TTH4 Bit3 R/W TTH3 Bit2 R/W TTH2 Bit1 R/W TTH1 Bit0 Reset Value 10110110 2 I C Address: 0x2Ch TDT_L_THRESH This register represents the 7-bit jerk low threshold to determine if a tap is detected. The Performance Index (PI) is the jerk signal that is expected to be greater than this threshold and less than the TDT_H_THRESH threshold during single and double tap events. This register also contains the LSB of the TDT_H_THRESH threshold. The Kionix recommended default value is 26 (0x1Ah). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TTH0 Bit7 R/W TTL6 Bit6 R/W TTL5 Bit5 R/W TTL4 Bit4 R/W TTL3 Bit3 R/W TTL2 Bit2 R/W TTL1 Bit1 R/W TTL0 Bit0 Reset Value 00011010 2 I C Address: 0x2Dh 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 35 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 TDT_TAP_TIMER This register contains counter information for the detection of any tap event. Every count is calculated as 1/ODR delay period, where the ODR is user-defined per Table 17. In order to ensure that only tap events are detected, these time limits are used. A tap event must be above the performance index threshold (TDT_THRESH) for at least the low limit (FTDL0 – FTDL2) and no more than the high limit (FTDH0 – FTDH4). The Kionix recommended default value for the high limit is 0.05 seconds and for the low limit is 0.005 seconds (0xA2h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W FTDH4 Bit7 R/W FTDH3 Bit6 R/W FTDH2 Bit5 R/W FTDH1 Bit4 R/W FTDH0 Bit3 R/W FTDL2 Bit2 R/W FTDL1 Bit1 R/W FTDL0 Bit0 Reset Value 10100010 2 I C Address: 0x2Eh TDT_TOTAL_TIMER This register contains counter information for the detection of a double tap event. Every count is calculated as 1/ODR delay period, where the ODR is user-defined per Table 17. In order to ensure that only tap events are detected, this time limit is used. This register sets the total amount of time that the two taps in a double tap event can be above the PI threshold (TDT_L_THRESH). The Kionix recommended default value for TDT_TOTAL_TIMER is 0.09 seconds (0x24h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W STD7 Bit7 R/W STD6 Bit6 R/W STD5 Bit5 R/W STD4 Bit4 R/W STD3 Bit3 R/W STD2 Bit2 R/W STD1 Bit1 R/W STD0 Bit0 Reset Value 00100100 2 I C Address: 0x2Fh 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 36 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 TDT_LATENCY_TIMER This register contains counter information for the detection of a tap event. Every count is calculated as 1/ODR delay period, where the ODR is user-defined per Table 17. In order to ensure that only tap events are detected, this time limit is used. This register sets the total amount of time that the tap algorithm will count samples that are above the PI threshold (TDT_L_THRESH) during a potential tap event. It is used during both single and double tap events. However, reporting of single taps on the physical interrupt pin (7) will occur at the end of the TDT_WINDOW_TIMER. The Kionix recommended default value for TDT_LATENCY_TIMER is 0.1 seconds (0x28h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TLT7 Bit7 R/W TLT6 Bit6 R/W TLT5 Bit5 R/W TLT4 Bit4 R/W TLT3 Bit3 R/W TLT2 Bit2 R/W TLT1 Bit1 R/W TLT0 Bit0 Reset Value 00101000 2 I C Address: 0x30h TDT_WINDOW_TIMER This register contains counter information for the detection of single and double taps. Every count is calculated as 1/ODR delay period, where the ODR is user-defined per Table 17. It defines the time window for the entire tap event, single or double, to occur. Reporting of single taps on the physical interrupt pin (7) will occur at the end of this tap window. The Kionix recommended default value for TDT_WINDOW_TIMER is 0.4 seconds (0xA0h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TWS7 Bit7 R/W TWS6 Bit6 R/W TWS5 Bit5 R/W TWS4 Bit4 R/W TWS3 Bit3 R/W TWS2 Bit2 R/W TWS1 Bit1 R/W TWS0 Bit0 Reset Value 10100000 2 I C Address: 0x31h SELF_TEST When 0xCA is written to this register, the MEMS self-test function is enabled. Electrostatic-actuation of the accelerometer, results in a DC shift of the X, Y and Z axis outputs. Writing 0x00 to this register will return the accelerometer to normal operation. R/W 1 Bit7 R/W 1 Bit6 R/W 0 Bit5 R/W 0 Bit4 R/W 1 Bit3 R/W 0 Bit2 R/W 1 Bit1 R/W 0 Bit0 Reset Value 00000000 2 I C Address: 0x3Ah 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 37 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 WUF_THRESH This register sets the acceleration threshold, WUF Threshold that is used to detect a general motion input. The KXTF9 will ship from the factory with WUF_THRESH set to a change in acceleration of 0.5g. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W R/W R/W R/W R/W R/W R/W R/W WUFTH7 WUFTH6 WUFTH5 WUFTH4 WUFTH3 WUFTH2 WUFTH1 WUFTH0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 00001000 2 I C Address: 0x5Ah TILT_ANGLE This register sets the tilt angle that is used to detect the transition from Face-up/Face-down states to Screen Rotation states. The KXTF9 ships from the factory with tilt angle set to a low threshold of 26° from horizontal. A different default tilt angle can be requested from the factory. Note that the minimum suggested tilt angle is 10°. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TA7 Bit7 R/W TA6 Bit6 R/W TA5 Bit5 R/W TA4 Bit4 R/W TA3 Bit3 R/W TA2 Bit2 R/W R/W TA1 TA0 Bit1 Bit0 2 I C Address: 0x5Ch Reset Value 00001100 HYST_SET This register sets the Hysteresis that is placed in between the Screen Rotation states. The KXTF9 ships from the factory with HYST_SET set to +/-15° of hysteresis. A different default hysteresis can be requested from the factory. Note that when writing a new value to this register the current values of RES0, RES1, RES2 and RES3 must be preserved. These values are set at the factory and must not change. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W RES2 Bit7 R/W RES1 Bit6 R/W RES0 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] R/W HYST4 Bit4 R/W HYST3 Bit3 R/W R/W R/W HYST2 HYST1 HYST0 Bit2 Bit1 Bit0 2 I C Address: 0x5Fh Reset Value ---10100 © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 38 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 KXTF9 Embedded Applications Orientation Detection Feature The orientation detection feature of the KXTF9 will report changes in face up, face down, +/- vertical and +/horizontal orientation. This intelligent embedded algorithm considers very important factors that provide accurate orientation detection from low cost tri-axis accelerometers. Factors such as: hysteresis, device orientation angle and delay time are described below as these techniques are utilized inside the KXTF9. Hysteresis A 45° tilt angle threshold seems like a good choice because it is halfway between 0° and 90°. However, a problem arises when the user holds the device near 45°. Slight vibrations, noise and inherent sensor error will cause the acceleration to go above and below the threshold rapidly and randomly, so the screen will quickly flip back and forth between the 0° and the 90° orientations. This problem is avoided in the KXTF9 by choosing a 30° threshold angle. With a 30° threshold, the screen will not rotate from 0° to 90° until the device is tilted to 60° (30° from 90°). To rotate back to 0°, the user must tilt back to 30°, thus avoiding the screen flipping problem. This example essentially applies +/15° of hysteresis in between the four screen rotation states. Table 21 shows the acceleration limits implemented for 30°. Orientation 0°/360° 90° 180° 270° X Acceleration (g) -0.5 < ax < 0.5 ax > 0.866 -0.5 < ax < 0.5 ax < -0.866 Y Acceleration (g) ay > 0.866 -0.5 < ay < 0.5 ay < -0.866 -0.5 < ay < 0.5 Table 21. Acceleration at the four orientations with +/- 15° of hysteresis 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 39 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 The KXTF9 allows the user to change the amount of hysteresis in between the four screen rotation states. By simply writing to the HYST_SET register, the user can adjust the amount of hysteresis up to +/- 45°. The plot in Figure 1 shows the typical amount of hysteresis applied for a given digital count value of HYST_SET. HYST_SET vs Hysteresis 50 45 Hysteresis (+/- degrees) 40 35 30 25 Hysteresis 20 15 10 5 0 0 5 10 15 20 25 30 HYST_SET Value (Counts) Figure 1. HYST_SET vs Hysteresis 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 40 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Device Orientation Angle (aka Tilt Angle) To ensure that horizontal and vertical device orientation changes are detected, even when it isn’t in the ideal vertical orientation – where the angle θ in Figure 2 is 90°, the KXTF9 considers device orientation angle in its algorithm. Angle Figure 2. Device Orientation Angle As the angle in Figure 2 is decreased, the maximum gravitational acceleration on the X-axis or Y-axis will also decrease. Therefore, when the angle becomes small enough, the user will not be able to make the screen orientation change. When the device orientation angle approaches 0° (device is flat on a desk or table), ax = ay = 0g, az = +1g, and there is no way to determine which way the screen should be oriented, the internal algorithm determines that the device is in either the face-up or facedown orientation, depending on the sign of the z-axis. The KXTF9 will only change the screen orientation when the orientation angle is above the factory-defaulted/user-defined threshold set in the TILT_ANGLE register. Equation 2 can be used to determine what value to write to the TILT_ANGLE register to set the device orientation angle. TILT_ANGLE (counts) = sin θ * (32 (counts/g)) Equation 2. Tilt Angle Threshold Tilt Timer The 8-bit register, TILT_TIMER can be used to qualify changes in orientation. The KXTF9 does this by incrementing a counter with a size that is specified by the value in TILT_TIMER for each set of acceleration samples to verify that a change to a new orientation state is maintained. A user defined output data rate (ODR) determines the time period for each sample. Equation 3 shows how to calculate the TILT_TIMER register value for a desired delay time. TILT_TIMER (counts) = Delay Time (sec) x ODR (Hz) Equation 3. Tilt Position Delay Time 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 41 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Motion Interrupt Feature Description The Motion interrupt feature of the KXTF9 reports qualified high-pass filtered acceleration based on the Wake Up (WUF) threshold. If the high-pass filtered acceleration on any axis is greater than the user-defined wake up threshold (WUF_THRESH), the device has transitioned from an inactive state to an active state. When configured in the unlatched mode, the KXTF9 will report when the motion event finished and the device has returned to an inactive state. Equation 4 shows how to calculate the WUF_THRESH register value for a desired wake up threshold. WUF_THRESH (counts) = Wake Up Threshold (g) x 16 (counts/g) Equation 4. Wake Up Threshold A WUF (WUF_TIMER) 8-bit raw unsigned value represents a counter that permits the user to qualify each active/inactive state change. Note that each WUF Timer count qualifies 1 (one) user-defined ODR period (OWUF). Equation 5 shows how to calculate the WUF_TIMER register value for a desired wake up delay time. WUF_TIMER (counts) = Wake Up Delay Time (sec) x OWUF (Hz) Equation 5. Wake Up Delay Time 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 42 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Figure 3 below shows the latched response of the motion detection algorithm with WUF Timer = 10 counts. Typical Motion Interrupt Example HPF Acceleration WUF Threshold 0g Time Ex: Delay Counter = 10 10 WUF Timer Motion Inactive Figure 3. Latched Motion Interrupt Response 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 43 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Figure 4 below shows the unlatched response of the motion detection algorithm with WUF Timer = 10 counts. Typical Motion Interrupt Example HPF Acceleration WUF Threshold 0g Time Ex: Delay Counter = 10 10 WUF Timer Motion Inactive Figure 4. Unlatched Motion Interrupt Response 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 44 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Directional Tap Detection Feature Description The Directional Tap Detection feature of the KXTF9 recognizes single and double tap inputs and reports the acceleration axis and direction that each tap occurred. Eight performance parameters, as well as a userselectable ODR are used to configure the KXTF9 for a desired tap detection response. Performance Index The Directional TapTM detection algorithm uses low and high thresholds to help determine when a tap event has occurred. A tap event is detected when the previously described jerk summation exceeds the low threshold (TDT_L_THRESH) for more than the tap detection low limit, but less than the tap detection high limit as contained in TDT_TAP_TIMER. Samples that exceed the high limit (TDT_H_THRESH) will be ignored. Figure 5 shows an example of a single tap event meeting the performance index criteria. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 45 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Calculated Performance Index PI 180 : Sampled Data 160 140 jerk (counts) 120 100 80 60 40 TDT_L_THRESH 20 0 3.14 3.15 3.16 3.17 3.18 time(sec) 3.19 3.2 3.21 Figure 5. Jerk Summation vs Threshold 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 46 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Single Tap Detection The latency timer (TDT_LATENCY_TIMER) sets the time period that a tap event will only be characterized as a single tap. A second tap has to occur outside of the latency timer. If a second tap occurs inside the latency time, it will be ignored as it occurred too quickly. The single tap will be reported at the end of the TDT_WINDOW_TIMER. Figure 6 shows a single tap event meeting the PI, latency and window requirements. Calculated Performance Index 160 PI 140 TDT_WINDOW_TIMER 120 jerk (counts) 100 TDT_LATENCY_TIMER 80 60 40 TDT_L_THRESH 20 0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 time(sec) 2.8 2.9 3 3.1 Figure 6. Single Directional TapTM Timing 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 47 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Double Tap Detection An event can be characterized as a double tap only if the second tap crosses the performance index (TDT_L_THRESH) outside the TDT_TIMER. This means that the TDT_TIMER determines the minimum time separation that must exist between the two taps of a double tap event. Similar to the single tap, the second tap event must exceed the performance index for the time limit contained in TDT_TAP_TIMER. The double tap will be reported at the end of the second TDT_LATENCY_TIMER. Figure 7 shows a double tap event meeting the PI, latency and window requirements. Calculated Performance Index PI TDT_WINDOW_TIMER 200 150 jerk (counts) TDT_TIMER 100 TDT_LATENCY_TIMER TDT_LATENCY_TIMER 50 TDT_L_THRESH 0 3.1 3.2 3.3 3.4 3.5 time(sec) 3.6 3.7 3.8 3.9 Figure 7. Double Directional TapTM Timing 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 48 of 49 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTF9-4100 Rev. 6 Jun-2011 Revision History REVISION 1 DESCRIPTION Initial Release 2 Corrected default register values and Table 15 references. 3 Removed all references to 12.5 Hz ODR related to acceleration output registers and changed axes labels in Figures 3 and 4. Updated Drawing and Photo with Pin 1 Marking 4 5 6 Updated paragraph to include explanation of accelerometer output format in page 17 and updated Figure 9 for 2's complement representation. Updated Static X/Y/Z Output Response versus Orientation. Modified Output Low Voltage level from 0.3Vio to 0.2Vio. Also modified Note1: Assuming Vio < 2V, if Vio > 2 V then the maximum Output Low Voltage is 0.4V. DATE 18-Dec2009 16-Mar2010 01-Jul2010 11-Oct2010 29-Mar2011 24-Jun2011 "Kionix" is a registered trademark of Kionix, Inc. Products described herein are protected by patents issued or pending. No license is granted by implication or otherwise under any patent or other rights of Kionix. The information contained herein is believed to be accurate and reliable but is not guaranteed. Kionix does not assume responsibility for its use or distribution. Kionix also reserves the right to change product specifications or discontinue this product at any time without prior notice. This publication supersedes and replaces all information previously supplied. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - [email protected] © 2010 Kionix – All Rights Reserved 425-2397-1106241613 Page 49 of 49