ICE2QR4765G Data Sheet (2 MB, EN)

Edition 2014-04-01
Published by Infineon Technologies AG,
81726 Munich, Germany.
© 2014 Infineon Technologies AG
All Rights Reserved.
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CoolSET™Q1
ICE2QR4765G
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™,
TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by
AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS
Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of
Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems
Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc.
SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software
Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.
TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™
of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™
of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2011-11-11
Data Sheet
3
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Revision History
Major changes since previous revision
Date
Version
2014-04-01
2.1
Changed By
Change Description
Added VVCCPD and marking drawing.
Revised typo, IVCCcharge1, IVCCcharge2,
IZCMAX, outline dimension drawing and
standby power. Upgraded the operating
temperature from -25°C to -40°C.
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Please send your proposal (including a reference to this document title/number) to:
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Data Sheet
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V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Table of Contents
Revision History ...................................................................................................................................................4
Table of Contents .................................................................................................................................................5
1
1.1
1.2
Pin Configuration and Functionality ..............................................................................................7
Pin Configuration with PG-DSO-16/12...............................................................................................7
Pin Functionality.................................................................................................................................7
2
Representative Block Diagram .......................................................................................................8
3
3.1
3.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.2
3.3.2.1
3.3.3
3.4
3.4.1
3.5
3.5.1
3.5.2
3.5.3
3.6
Functional Description ....................................................................................................................9
VCC Pre-Charging and Typical VCC Voltage During Start-up...........................................................9
Soft-start ............................................................................................................................................9
Normal Operation.............................................................................................................................10
Digital Frequency Reduction.......................................................................................................10
Up/down counter....................................................................................................................10
Zero crossing (ZC counter) ....................................................................................................11
Ringing suppression time............................................................................................................12
Switch on determination ........................................................................................................12
Switch Off Determination ............................................................................................................12
Current Limitation.............................................................................................................................12
Foldback Point Correction...........................................................................................................13
Active Burst Mode Operation ...........................................................................................................14
Entering Active Burst Mode Operation........................................................................................14
During Active Burst Mode Operation ..........................................................................................14
Leaving Active Burst Mode Operation ........................................................................................14
Protection Functions ........................................................................................................................15
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
Electrical Characteristics ..............................................................................................................17
Absolute Maximum Ratings .............................................................................................................17
Operating Range..............................................................................................................................17
Characteristics .................................................................................................................................18
Supply Section ............................................................................................................................18
Internal Voltage Reference .........................................................................................................18
PWM Section ..............................................................................................................................19
Current Sense.............................................................................................................................19
Soft Start.....................................................................................................................................19
Foldback Point Correction...........................................................................................................19
Digital Zero Crossing ..................................................................................................................20
Active Burst Mode.......................................................................................................................20
Protection....................................................................................................................................21
TM
CoolMOS Section ....................................................................................................................21
6
Input power curve ..........................................................................................................................24
8
Marking ...........................................................................................................................................26
Data Sheet
5
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Off-Line SMPS Quasi-Resonant PWM Controller with integrated 650V
CoolMOSTM and startup cell in DSO-16/12
Product Highlights
 Active Burst Mode to reach the lowest standby power requirement
<50mW @ no load
 Quasi resonant operation
 Digital frequency reduction for better overall system efficiency
 Integrated 650V startup cell
 Pb-free lead plating, halogen free mold compound, RoHS compliant
Features
•
•
•
•
•
•
•
•
•
PG-DSO-16/12
TM
650V avalanche rugged CoolMOS with built-in startup cell
Quasi resonant operation till very low load
Active burst mode operation for low standby input power (< 0.05W)
Digital frequency reduction with decreasing load for reduced switching loss
Built-in digital soft-start
Foldback point correction and cycle-by-cycle peak current limitation
Maximum on time limitation
Auto restart mode for VCC over-voltage protection, under-voltage protection, over-load protection and overtemperature protection
Latch-off mode for adjustable output over-voltage protection and transformer short-winding protection
Description
®
TM
The CoolSET -Q1 series (ICE2QRxx65G) is the first generation of quasi-resonant controller and CoolMOS
integrated power IC. Operating the MOSFET switch in quasi-resonant mode, lower EMI, higher efficiency and
lower voltage stress on secondary diodes are expected for the SMPS. Based on the BiCMOS technology, the
®
CoolSET -Q1 series has a wide operation range (up to 25V) of IC power supply and lower power consumption.
It also offers many advantages such as quasi-resonant operation till very low load, increasing the higher
average system efficiency compared to other conventional solutions, achieving ultra-low power consumption
with small and controllable output voltage ripple at standby mode with Active Burst Mode operation, etc.
Applications
 Adapter/Charger
 LCD monitor, DVD R/W, DVD Combo, Blue-ray/DVD player, Set-top box
 Auxiliary power supply for PC, Printer, TV, Home theater/Audio System, etc.
Figure 1
Typical Application
Type
ICE2QR4765G
Package
PG-DSO-16/12
Marking
ICE2QR4765G
VDS
650V
1
VDS
4.70
2
2
230VAC ±15%
85-265 VAC
29W
17W
1 typ @ T=25°C
2 Calculated maximum input power rating at Ta=50°C, Ti=125°C and without copper area as heat sink.
Data Sheet
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V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Pin Configuration and Functionality
1
Pin Configuration and Functionality
1.1
Pin Configuration with PGDSO-16/12
Table 1
1.2
ZC (Zero Crossing)
At this pin, the voltage from the auxiliary winding
after a time delay circuit is applied. Internally, this
pin is connected to the zero-crossing detector for
switch-on determination. Additionally, the output
overvoltage detection is realized by comparing the
voltage Vzc with an internal preset threshold.
Pin configuration
Pin
Symbol
1
ZC
Zero Crossing
2
FB
Feedback
3
N.C.
4
CS
5
Drain
6
Drain
7
Drain
Function
FB (Feedback)
Normally an external capacitor is connected to this
pin for a smooth voltage VFB. Internally this pin is
connected to the PWM signal generator block for
switch-off determination (together with the current
sensing signal), to the digital signal processing
block for the frequency reduction with decreasing
load during normal operation, and to the Active
Burst Mode controller block for entering Active
Burst Mode operation determination and burst ratio
control during Active Burst Mode operation.
Additionally, the open-loop / over-load protection is
implemented by monitoring the voltage at this pin.
Not Connected
Current Sense/
1
TM
650V CoolMOS Source
1)
TM
Drain
1)
TM
Drain
1)
TM
Drain
1)
TM
Drain
650V CoolMOS
650V CoolMOS
650V CoolMOS
8
Drain
650V CoolMOS
9
N.C.
Not Connected
10
N.C.
Not Connected
11
VCC
Controller Supply Voltage
12
GND
Controller Ground
Pin Functionality
CS (Current Sense)
This pin is connected to the shunt resistor for the
primary current sensing externally and to the PWM
signal generator block for switch-off determination
(together with the feedback voltage) internally.
Moreover, short-winding protection is realized by
monitoring the voltage Vcs during on-time of the
main power switch.
TM
Drain (Drain of integrated CoolMOS )
Drain pin is the connection to the drain of the
TM.
internal CoolMOS
VCC (Power supply)
VCC pin is the positive supply of the IC. The
operating range is between VVCCoff and VVCCOVP.
GND (Ground)
This is the common ground of the controller.
Figure 2
1
Pin configuration PG-DSO-16/12
(top view)
at Tj=110°C
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CoolSET™Q1
ICE2QR4765G
Representative Block Diagram
2
Representative Block Diagram
Figure 3
Representative Block Diagram
Data Sheet
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CoolSET™Q1
ICE2QR4765G
Functional Description
3
Functional Description
3.1
VCC Pre-Charging and Typical VCC Voltage During Start-up
TM
In ICE2QR4765G, a startup cell is integrated into the CoolMOS . As shown in Figure 3, the start cell consists
of a high voltage device and a controller, whereby the high voltage device is controlled by the controller. The
startup cell provides a pre-charging of the VCC capacitor till VCC voltage reaches the VCC turned-on threshold
VVCCon and the IC begins to operate.
Once the mains input voltage is applied, a rectified voltage shows across the capacitor Cbus. The high voltage
device provides a current to charge the VCC capacitor Cvcc. Before the VCC voltage reaches a certain value,
the amplitude of the current through the high voltage device is only determined by its channel resistance and
can be as high as several mA. After the VCC voltage is high enough, the controller controls the high voltage
device so that a constant current around 1mA is provided to charge the VCC capacitor further, until the VCC
voltage exceeds the turned-on threshold VVCCon. As shown as the time phase I in Figure 4, the VCC voltage
increase near linearly and the charging speed is independent of the mains voltage level.
Figure 4
VCC voltage at start up

The time taking for the VCC pre-charging can then be approximately calculated as:
where IVCCcharge2 is the charging current from the startup cell which is 1.05mA, typically.
When the VCC voltage exceeds the VCC turned-on threshold VVCCon at time t1, the startup cell is switched off
and the IC begins to operate with soft-start. Due to power consumption of the IC and the fact that there is still no
energy from the auxiliary winding to charge the VCC capacitor before the output voltage is built up, the VCC
voltage drops (Phase II). Once the output voltage is high enough, the VCC capacitor receives the energy from
the auxiliary winding from the time point t2 onward. The VCC then will reach a constant value depending on
output load.
3.2
Soft-start
As shown in Figure 5, at the time ton, the IC begins to operate with a soft-start. By this soft-start the switching
TM
stresses for the switch, diode and transformer are minimized. The soft-start implemented in CoolSET Q1 is a
digital time-based function. The preset soft-start time is tSS (12ms) with 4 steps. If not limited by other functions,
the peak voltage on CS pin will increase step by step from 0.32V to 1V finally.
Data Sheet
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V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Functional Description
Figure 5
Maximum current sense voltage during soft start
3.3
Normal Operation
The PWM controller during normal operation consists of a digital signal processing circuit including an up/down
counter, a zero-crossing counter (ZC counter) and a comparator, and an analog circuit including a current
measurement unit and a comparator. The switch-on and -off time points are each determined by the digital
circuit and the analog circuit, respectively. As input information for the switch-on determination, the zerocrossing input signal and the value of the up/down counter are needed, while the feedback signal V FB and the
current sensing signal VCS are necessary for the switch-off determination. Details about the full operation of the
PWM controller in normal operation are illustrated in the following paragraphs.
3.3.1
Digital Frequency Reduction
As mentioned above, the digital signal processing circuit consists of an up/down counter, a ZC counter and a
comparator. These three parts are key to implement digital frequency reduction with decreasing load. In
addition, a ringing suppression time controller is implemented to avoid mis-triggering by the high frequency
oscillation, when the output voltage is very low under conditions such as soft start period or output short circuit.
Functionality of these parts is described as in the following.
3.3.1.1
Up/down counter
The up/down counter stores the number of the zero crossing where the main power switch is switched on after
demagnetization of the transformer. This value is fixed according to the feedback voltage, V FB, which contains
information about the output power. Indeed, in a typical peak current mode control, a high output power results
in a high feedback voltage, and a low output power leads to a low regulation voltage. Hence, according to V FB,
the value in the up/down counter is changed to vary the power MOSFET off-time according to the output power.
In the following, the variation of the up/down counter value according to the feedback voltage is explained.
The feedback voltage VFB is internally compared with three threshold voltages VFBZL, VFBZH and VFBR1, at each
clock period of 48ms. The up/down counter counts then upward, keep unchanged or count downward, as shown
in Table 2.
Table 2
Operation of the up/down counter
VFB
up/down counter action
Always lower than VFBZL
Count upwards till 7
Once higher than VFBZL, but always lower than VFBZH
Stop counting, no value changing
Once higher than VFBZH, but always lower than VFBR1
Count downwards till 1
Once higher than VFBR1
Set up/down counter to 1
Data Sheet
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V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Functional Description
In the ICE2QR4765G, the number of zero crossing is limited to 7. Therefore, the counter varies between 1 and
7, and any attempt beyond this range is ignored. When VFB exceeds VFBR1 voltage, the up/down counter is reset
to 1, in order to allow the system to react rapidly to a sudden load increase. The up/down counter value is also
reset to 1 at the start-up time, to ensure an efficient maximum load start up. Figure 6 shows some examples on
how up/down counter is changed according to the feedback voltage over time.
The use of two different thresholds VFBZL and VFBZH to count upward or downward is to prevent frequency
jittering when the feedback voltage is close to the threshold point. However, for a stable operation, these two
thresholds must not be affected by the foldback current limitation (see section 3.4.1), which limits the V CS
voltage. Hence, to prevent such situation, the threshold voltages, VFBZL and VFBZH, are changed internally
depending on the line voltage levels.
Figure 6
Up/down counter operation
3.3.1.2
Zero crossing (ZC counter)
In the system, the voltage from the auxiliary winding is applied to the zero-crossing pin through a RC network,
which provides a time delay to the voltage from the auxiliary winding. Internally this pin is connected to a
clamping network, a zero-crossing detector, an output overvoltage detector and a ringing suppression time
controller.
During on-state of the power switch a negative voltage applies to the ZC pin. Through the internal clamping
network, the voltage at the pin is clamped to certain level.
The ZC counter has a minimum value of 0 and maximum value of 7. After the internal MOSFET is turned off,
every time when the falling voltage ramp of on ZC pin crosses the VZCCT (100mV) threshold, a zero crossing is
detected and ZC counter will increase by 1. It is reset every time after the DRIVER output is changed to high.
The voltage VZC is also used for the output overvoltage protection. Once the voltage at this pin is higher than the
threshold VZCOVP during off-time of the main switch, the IC is latched off after a fixed blanking time.
To achieve the switch-on at voltage valley, the voltage from the auxiliary winding is fed to a time delay network
(the RC network consists of Dzc, Rzc1, Rzc2 and Czc as shown in Figure 1) before it is applied to the zero-crossing
detector through the ZC pin. The needed time delay to the main oscillation signal Δt should be approximately
one fourth of the oscillation period, Tosc (by transformer primary inductor and drain-source capacitor) minus the
propagation delay from the detected zero-crossing to the switch-on of the main switch tdelay.
Data Sheet
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V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Functional Description
This time delay should be matched by adjusting the time constant of the RC network which is calculated as:
3.3.2
Ringing suppression time
After MOSFET is turned off, there will be some oscillation on VDS, which will also appear on the voltage on ZC
pin. To avoid mis-triggering by such oscillations to turn on the MOSFET, a ringing suppression timer is
implemented. This suppression time is depended on the voltage VZC. If the voltage VZC is lower than the
threshold VZCRS, a longer preset time tZCRS2 is applied. However, if the voltage VZC is higher than the threshold, a
shorter time tZCRS1 is set.
3.3.2.1
Switch on determination
After the gate drive goes to low, it cannot be changed to high during ring suppression time.
After ring suppression time, the gate drive can be turned on when the ZC counter value is higher or equal to
up/down counter value.
However, it is also possible that the oscillation between primary inductor and drain-source capacitor damps very
fast and IC cannot detect enough zero crossings and ZC counter value will not be high enough to turn on the
gate drive. In this case, a maximum off time is implemented. After gate drive has been remained off for the
period of TOffMax, the gate drive will be turned on again regardless of the counter values and V ZC. This function
can effectively prevent the switching frequency from going lower than 20kHz. Otherwise it will cause audible
noise during start up.
3.3.3
Switch Off Determination
In the converter system, the primary current is sensed by an external shunt resistor, which is connected
between low-side terminal of the main power switch and the common ground. The sensed voltage across the
shunt resistor VCS is applied to an internal current measurement unit, and its output voltage V1 is compared with
the regulation voltage VFB. Once the voltage V1 exceeds the voltage VFB, the output flip-flop is reset. As a result,
the main power switch is switched off. The relationship between the V1 and the VCS is described by:
To avoid mis-triggering caused by the voltage spike across the shunt resistor at the turn on of the main power
switch, a leading edge blanking time, tLEB, is applied to the output of the comparator. In other words, once the
gate drive is turned on, the minimum on time of the gate drive is the leading edge blanking time.
In addition, there is a maximum on time, tOnMax, limitation implemented in the IC. Once the gate drive has been
in high state longer than the maximum on time, it will be turned off to prevent the switching frequency from going
too low because of long on time.
3.4
Current Limitation
There is a cycle by cycle current limitation realized by the current limit comparator to provide an over-current
detection. The source current of the MOSFET is sensed via a sense resistor R CS. By means of RCS the source
current is transformed to a sense voltage VCS which is fed into the pin CS. If the voltage VCS exceeds an internal
voltage limit, adjusted according to the Mains voltage, the comparator immediately turns off the gate drive.
To prevent the Current Limitation process from distortions caused by leading edge spikes, a Leading Edge
Blanking time (tLEB) is integrated in the current sensing path.
Data Sheet
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V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Functional Description
A further comparator is implemented to detect dangerous current levels (V CSSW) which could occur if one or
more transformer windings are shorted or if the secondary diode is shorted. To avoid an accidental latch off, a
spike blanking time of tCSSW is integrated in the output path of the comparator.
3.4.1
Foldback Point Correction
When the main bus voltage increases, the switch on time becomes shorter and therefore the operating
frequency is also increased. As a result, for a constant primary current limit, the maximum possible output
power is increased which is beyond the converter design limit.
To avoid such a situation, the internal foldback point correction circuit varies the V CS voltage limit according to
the bus voltage. This means the VCS will be decreased when the bus voltage increases. To keep a constant
maximum input power of the converter, the required maximum VCS versus various input bus voltage can be
calculated, which is shown in Figure 7.
Figure 7
Variation of the VCS limit voltage according to the IZC current
According to the typical application circuit, when MOSFET is turned on, a negative voltage proportional to bus
TM
voltage will be coupled to auxiliary winding. Inside CoolSET
Q1, an internal circuit will clamp the voltage on
ZC pin to nearly 0V. As a result, the current flowing out from ZC pin can be calculated as
When this current is higher than IZC_FS, the amount of current exceeding this threshold is used to
generate an offset to decrease the maximum limit on VCS. Since the ideal curve shown in Figure 7 is a
nonlinear one, a digital block in CoolSETTM Q1 is implemented to get a better control of maximum
output power. Additional advantage to use digital circuit is the production tolerance is smaller
compared to analog solutions. The typical maximum limit on VCS versus the ZC current is shown in
Figure 8.
Data Sheet
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V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Functional Description
Figure 8
VCS-max versus IZC
3.5
Active Burst Mode Operation
At light load condition, the IC enters Active Burst Mode operation to minimize the power consumption. Details
about Active Burst Mode operation are explained in the following paragraphs.
3.5.1
Entering Active Burst Mode Operation
For determination of entering Active Burst Mode operation, three conditions apply:
 the feedback voltage is lower than the threshold of VFBEB (1.25V). Accordingly, the peak current sense
voltage across the shunt resistor is 0.17V;
 the up/down counter is NZC_ABM (7) and
 a certain blanking time tBEB (24ms).
Once all of these conditions are fulfilled, the Active Burst Mode flip-flop is set and the controller enters Active
Burst Mode operation. This multi-condition determination for entering Active Burst Mode operation prevents mistriggering of entering Active Burst Mode operation, so that the controller enters Active Burst Mode operation
only when the output power is really low during the preset blanking time.
3.5.2
During Active Burst Mode Operation
After entering the Active Burst Mode the feedback voltage rises as VOUT starts to decrease due to the inactive
PWM section. One comparator observes the feedback signal if the voltage level V FBBOn (3.6V) is exceeded. In
that case the internal circuit is again activated by the internal bias to start with switching.
Turn-on of the power MOSFET is triggered by the timer. The PWM generator for Active Burst Mode operation
composes of a timer with a fixed frequency of fsB (52kHz, typical) and an analog comparator. Turn-off is resulted
if the voltage across the shunt resistor at CS pin hits the threshold VcsB (0.34V). A turn-off can also be triggered
if the duty ratio exceeds the maximal duty ratio DmaxB (50%). In operation, the output flip-flop will be reset by one
of these signals which come first.
If the output load is still low, the feedback signal decreases as the PWM section is operating. When feedback
signal reaches the low threshold VFBBOff (3.0V), the internal bias is reset again and the PWM section is disabled
until next time regulation signal increases beyond the VFBBOn (3.6V) threshold. If working in Active Burst Mode
the feedback signal is changing like a saw tooth between VFBBOff and VFBBOn shown in Figure 9.
3.5.3
Leaving Active Burst Mode Operation
The feedback voltage immediately increases if there is a high load jump. This is observed by a comparator. As
the current limit is 34% during Active Burst Mode a certain load is needed so that feedback voltage can exceed
VFBLB (4.5V). After leaving active burst mode, maximum current can now be provided to stabilize V O. In addition,
Data Sheet
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V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Functional Description
the up/down counter will be set to 1 immediately after leaving Active Burst Mode. This is helpful to decrease the
output voltage undershoot.
Figure 9
Signals in Active Burst Mode
3.6
Protection Functions
The IC provides full protection functions. The following table summarizes these protection functions.
Table 3
Protection features
VCC Over-voltage
VCC Under-voltage
Over-load/Open Loop
Over-temperature
Output Over-voltage
Short Winding
Auto Restart Mode
Auto Restart Mode
Auto Restart Mode
Auto Restart Mode
Latched Off Mode
Latched Off Mode
During operation, the VCC voltage is continuously monitored. In case of an under-voltage or an over-voltage,
the IC is reset and the main power switch is then kept off. After the VCC voltage falls below the threshold
Data Sheet
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V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Functional Description
VVCCoff, the startup cell is activated. The VCC capacitor is then charged up. Once the voltage exceeds the
threshold VVCCon, the IC begins to operate with a new soft-start.
In case of open control loop or output over load, the feedback voltage will be pulled up. After a blanking time of
tOLP_B (30ms), the IC enters auto-restart mode. The blanking time here enables the converter to provide a peak
power in case the increase in VFB is due to a sudden load increase. This output over load protection is disabled
during burst mode.
During off-time of the power switch, the voltage at the zero-crossing pin is monitored for output over-voltage
detection. If the voltage is higher than the preset threshold VZCOVP, the IC is latched off after the preset blanking
time tZCOVP. This latch off mode can only be reset if the Vcc < VVCCPD.
If the junction temperature of IC controller exceeds TjCon (130 °C), the IC enters into OTP auto restart mode.
This OTP is disabled during burst mode.
If the voltage at the current sensing pin is higher than the preset threshold VCSSW during on-time of the power
switch, the IC is latched off. This is short-winding protection. The short winding protection is disabled during
burst mode.
During latch-off protection mode, the VCC voltage drops to VVCCoff (10.5V) and then the startup cell is activated.
The VCC voltage is then charged to VVCCon (18V). The startup cell is shut down again. This action repeats again
and again.
TM
There is also a maximum on time limitation implemented inside the CoolSET Q1. Once the gate voltage is
high and longer than tOnMax, the switch is turned off immediately.
Data Sheet
16
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Electrical Characteristics
4
Electrical Characteristics
Note : All voltages are measured with respect to ground (Pin 12). The voltage levels are valid if other
ratings are not violated.
4.1
Absolute Maximum Ratings
Note : Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of
the integrated circuit. For the same reason it needs to make sure that any capacitor that will be connected
to pin 11 (VCC) is discharged before assembling the application circuit.
Parameter
Symbol
Limit Values
Unit
min.
max.
VDS
-
650
V
Switching drain current, pulse width tp
limited by Tjmax
IS
-
1.67
A
Pulse drain current, tp limited by Tjmax
ID_Puls
-
2.32
A
Avalanche energy, repetitive tAR
1
limited by max. Tj=150°C
EAR
-
0.01
mJ
Avalanche current, repetitive tAR
1
limited by max. Tj=150°C
IAR
-
0.5
A
VVCC
-0.3
27
V
FB Voltage
VFB
-0.3
5.5
V
ZC Voltage
VZC
-0.3
5.5
V
CS Voltage
VCS
-0.3
5.5
V
IZCMAX
-
3
mA
Junction Temperature
Tj
-40
150
°C
Storage Temperature
TS
-55
150
°C
Thermal Resistance
Junction -Ambient
RthJA
-
110
K/W
ESD Capability (incl. Drain Pin)
VESD
-
2
kV
Drain Source Voltage
VCC Supply Voltage
Current out from ZC pin
4.2
Remarks
Tj=110°C
Controller &
TM
CoolMOS
Human body
2
model
Operating Range
Note : Within the operating range the IC operates as described in the functional description.
Parameter
VCC Supply Voltage
Symbol
VVCC
Limit Values
min.
max.
VVCCoff
VVCCOVP
Unit
Remarks
V
1
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f
2
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kW series resistor)
Data Sheet
17
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Electrical Characteristics
Junction Temperature of
Controller
TjCon
-40
130
°C
Junction Temperature of
TM
CoolMOS
TjCoolMOS
-40
150
C
4.3
Characteristics
4.3.1
Supply Section
Limited by over temperature
protection
Note : The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range Tj from – 40 °C to 125 °C. Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
IVCCstart
-
300
550
μA
VVCC =VVCCon -0.2V
IVCCcharge1
-
1.22
5.0
mA
VVCC = 0V
IVCCcharge2
0.8
1.1
-
mA
VVCC = 1V
IVCCcharge3
-
1
-
mA
VVCC =VVCCon -0.2V
Maximum Input Current of
TM
Startup Cell and CoolMOS
IDrainIn
-
-
2
mA
VVCC =VVCCon -0.2V
Leakage Current of
TM
Startup Cell and CoolMOS
IDrainLeak
-
0.2
50
μA
VDrain = 600V
at Tj=100°C
Supply Current in normal
operation
IVCCNM
-
1.5
2.3
mA
IFB = 0A
Supply Current in
Auto Restart Mode with Inactive
Gate
IVCCAR
-
300
-
μA
IFB = 0A
Supply Current in Latch-off
Mode
IVCClatch
-
300
-
μA
IFB = 0A
Supply Current in Burst Mode
with inactive Gate
IVCCburst
-
500
950
μA
VFB = 2.5V, exclude
the current flowing out
from FB pin
VCC Turn-On Threshold
VVCCon
17.0
18.0
19.0
V
VCC Turn-Off Threshold
VVCCoff
9.8
10.5
11.2
V
VCC Turn-On/Off Hysteresis
VVCChys
-
7.5
-
V
Start Up Current
VCC Charge Current
4.3.2
Internal Voltage Reference
Parameter
Internal Reference Voltage
Data Sheet
Symbol
VREF
Limit Values
min.
typ.
max.
4.80
5.00
5.20
18
Unit
V
Test Condition
Measured at pin FB
IFB=0
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Electrical Characteristics
4.3.3
PWM Section
Parameter
Symbol
Limit Values
Unit
min.
typ.
max.
RFB
14
23
33
kΩ
PWM-OP Gain
GPWM
3.18
3.3
-
-
Offset for Voltage Ramp
VPWM
0.6
0.7
-
V
Maximum on time in normal
operation
tOnMax
22
30
41
μs
Feedback Pull-Up Resistor
4.3.4
Current Sense
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Peak current limitation in
normal operation
VCSth
0.97
1.03
1.09
V
Leading Edge Blanking time
tLEB
200
330
460
ns
Peak Current Limitation in
Active Burst Mode
VCSB
0.29
0.34
0.39
V
4.3.5
Test Condition
Soft Start
Parameter
Soft-Start time
Symbol
Limit Values
min.
typ.
max.
8.5
12
-
tSS
Unit
soft-start time step
-
3
-
ms
Internal regulation voltage
at first step
VSS1
1
-
1.76
-
V
Internal regulation voltage
step at soft start
VSS_S
-
0.56
-
V
4.3.6
1
Test Condition
ms
1
tSS_S
Foldback Point Correction
Parameter
Symbol
ZC current first step threshold
Limit Values
Unit
min.
typ.
max.
IZC_FS
0.35
0.5
0.621
mA
ZC current last step threshold
IZC_LS
1.3
1.7
2.2
mA
CS threshold minimum
VCSMF
-
0.66
-
V
1
Test Condition
Test Condition
Izc=2.2mA, VFB=3.8V
The parameter is not subjected to production test - verified by design/characterization
Data Sheet
19
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Electrical Characteristics
4.3.7
Digital Zero Crossing
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Zero crossing threshold
voltage
VZCCT
50
100
170
mV
Ringing suppression threshold
VZCRS
-
0.7
-
V
Minimum ringing suppression
time
tZCRS1
1.62
2.5
4.5
μs
VZC > VZCRS
Maximum ringing suppression
time
tZCRS2
-
25
-
μs
VZC < VZCRS
Threshold to set Up/Down
Counter to one
VFBR1
-
3.9
-
V
Threshold for downward
counting at low line
VFBZHL
-
3.2
-
V
Threshold for upward counting
at low line
VFBZLL
-
2.5
-
V
Threshold for downward
counting at high line
VFBZHH
-
2.9
-
V
Threshold for upward counting
at high line
VFBZLH
-
2.3
-
V
ZC current for IC switch
threshold to high line
IZCSH
-
1.3
-
mA
ZC current for IC switch
threshold to low line
IZCSL
-
0.8
-
mA
tCOUNT
-
48
-
ms
tOffMax
30
42
57.5
μs
Counter time
1
Maximum restart time in
normal operation
4.3.8
Active Burst Mode
Parameter
Symbol
Limit Values
Unit
min.
typ.
max.
VFBEB
-
1.25
-
NZC_ABM
-
7
-
tBEB
-
24
-
ms
Feedback voltage for leaving
Active Burst Mode
VFBLB
-
4.5
-
V
Feedback voltage for burst-on
VFBBOn
-
3.6
-
V
Feedback voltage for burst-off
VFBBOff
-
3.0
-
V
Feedback voltage for entering
Active Burst Mode
Minimum Up/down value for
entering Active Burst Mode
Blanking time for entering
Active Burst Mode
1
Test Condition
V
The parameter is not subjected to production test - verified by design/characterization
Data Sheet
20
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Electrical Characteristics
Fixed Switching Frequency in
Active Burst Mode
Max. Duty Cycle in Active
Burst Mode
4.3.9
fsB
39
52
65
DmaxB
-
0.5
-
kHz
Protection
Parameter
Symbol
VCC overvoltage threshold
Limit Values
Unit
min.
typ.
max.
VVCCOVP
24.0
25.0
26.0
V
Over Load or Open Loop
Detection threshold for OLP
protection at FB pin
VFBOLP
-
4.5
-
V
Over Load or Open Loop
Protection Blanking Time
tOLP_B
20
30
44
ms
Output Overvoltage detection
threshold at the ZC pin
VZCOVP
3.55
3.7
3.84
V
Blanking time for Output
Overvoltage protection
tZCOVP
-
100
-
μs
Threshold for short winding
protection
VCSSW
1.63
1.68
1.78
V
Blanking time for short-winding
protection
tCSSW
-
190
-
ns
TjCon
130
140
150
°C
VVCCPD
5.2
-
7.8
V
Over temperature protection
1
Power Down Reset threshold
for Latched Mode
Test Condition
After Latched Off
Mode is entered
Note : The trend of all the voltage levels in the Control Unit is the same regarding the deviation except
VVCCOVP & VVCCPD.
CoolMOSTM Section
4.3.10
Parameter
Drain Source Breakdown
Voltage
Symbol
Limit Values
Rise Time
Fall Time
1
2
Test Condition
typ.
max.
V(BR)DSS
650
-
-
V
Tj = 110°C
RDSon
-
4.70
10.0
5.44
12.5
Ω
Ω
Tj = 25°C
1
Tj=125°C
at ID = 0.5A
-
pF
VDS = 0V to 480V
Drain Source On-Resistance
Effective output capacitance,
energy related
Unit
min.
Co(er)
-
4.75
trise
-
30
2
30
2
tfall
-
1
-
ns
-
ns
The parameter is not subjected to production test - verified by design/characterization
Measured in a Typical Flyback Converter Application
Data Sheet
21
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Electrical Characteristics
5
Typical CoolMOSTM Performance Characteristic
Figure 10
Safe Operating Area (SOA) curve for ICE2QR4765G
Figure 11
Power dissipation; Ptot=f(Ta)
Data Sheet
22
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Electrical Characteristics
Figure 12
Data Sheet
Drain-source breakdown voltage; VBR(DSS)=f(Tj)
23
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Input power curve
6
Input power curve
Two input power curves gives typical input power versus ambient temperature are showed below;
Vin=85~265Vac (Figure 13) and Vin=230Vac (Figure 14). The curves are derived based on a typical
discontinuous mode flyback model which considers either 50% duty ratio or 115V maximum secondary to
primary reflected voltage (high priority). The calculation is based on no copper area as heatsink for the device.
The input power already includes power loss at input common mode choke and bridge rectifier and the
TM
CoolMOS . The device saturation current (ID_plus@Tj=125°C) is also considered.
To estimate the out power of the device, it is simply multiplying the input power at a particular ambient
temperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure
13), operating temperature is 50 °C, estimated efficiency is 85%,the output power is 14.45W (17W*0.85).
Figure 13
Input Power curve Vin=85~265Vac; Pin=f(Ta)
Figure 14
Input Power curve Vin=230Vac; Pin=f(Ta)
Data Sheet
24
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Input power curve
7
Outline Dimension
Figure 15
Data Sheet
PG-DSO-16/12 (Pb-free lead plating Plastic Dual Small Outline Package)
25
V2.1, 2014-04-01
CoolSET™Q1
ICE2QR4765G
Marking
8
Marking
Figure 16
Marking for ICE2QR4765G
Data Sheet
26
V2.1, 2014-04-01
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG