Data Sheet

LPC2292/2294
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with
CAN, 10-bit ADC and external memory interface
Rev. 8 — 8 June 2011
Product data sheet
1. General description
The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with
real-time emulation and embedded trace support, together with 256 kB of embedded
high-speed flash memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at the maximum clock rate. For critical code
size applications, the alternative 16-bit Thumb mode reduces code by more than 30 %
with minimal performance penalty.
With their 144-pin package, low power consumption, various 32-bit timers, 8-channel
10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine
external interrupt pins these microcontrollers are particularly suitable for automotive and
industrial control applications as well as medical systems and fault-tolerant maintenance
buses. The number of available GPIOs ranges from 76 (with external memory) through
112 (single-chip). With a wide range of additional serial communications interfaces, they
are also suited for communication gateways and protocol converters as well as many
other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with
and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from
other devices only when necessary.
2. Features and benefits
2.1 Key features brought by LPC2292/2294/01 devices
 Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.
They also allow for a port pin to be read at any time regardless of its function.
 Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are
5 V tolerant when configured for digital I/O function(s).
 UART0/1 include fractional baud rate generator, auto-bauding capabilities and
handshake flow-control fully implemented in hardware.
 Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
 SPI programmable data length and master mode enhancement.
 Diversified Code Read Protection (CRP) enables different security levels to be
implemented. This feature is available in LPC2292/2294/00 devices as well.
 General purpose timers can operate as external event counters.
2.2 Key features common for all devices
 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
 16 kB on-chip static RAM and 256 kB on-chip flash program memory. 128-bit wide
interface/accelerator enables high-speed 60 MHz operation.
 In-System Programming/In-Application Programming (ISP/IAP) via on-chip bootloader
software. Single flash sector or full chip erase in 400 ms and programming of 256 B in
1 ms.
 EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software as well as high-speed real-time tracing of instruction
execution.
 Two/four (LPC2292/2294) interconnected CAN interfaces with advanced acceptance
filters. Additional serial interfaces include two UARTs (16C550), Fast I2C-bus
(400 kbit/s) and two SPIs.
 Eight channel 10-bit ADC with conversion time as low as 2.44 s.
 Two 32-bit timers (with four capture and four compare channels), PWM unit (six
outputs), Real-Time Clock (RTC), and watchdog.
 Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
 Configurable external memory interface with up to four banks, each up to 16 MB and
8/16/32-bit data width.
 Up to 112 general purpose I/O pins (5 V tolerant). Up to nine edge/level sensitive
external interrupt pins available.
 60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 s.
 The on-chip crystal oscillator should have an operating range of 1 MHz to 25 MHz.
 Power saving modes include Idle and Power-down.
 Processor wake-up from Power-down mode via external interrupt.
 Individual enable/disable of peripheral functions for power optimization.
 Dual power supply:
 CPU operating voltage range of 1.65 V to 1.95 V (1.8 V  0.15 V).
 I/O power supply range of 3.0 V to 3.6 V (3.3 V  10 %) with 5 V tolerant I/O pads.
3. Ordering information
Table 1.
Ordering information
Type number
LPC2292_2294
Product data sheet
Package
Name
Description
Version
LPC2292FBD144/01
LQFP144
plastic low profile quad flat package;
144 leads; body 20  20  1.4 mm
SOT486-1
LPC2292FET144/00
TFBGA144
plastic thin fine-pitch ball grid array package;
144 balls; body 12  12  0.8 mm
SOT569-2
LPC2292FET144/01
TFBGA144
plastic thin fine-pitch ball grid array package;
144 balls; body 12  12  0.8 mm
SOT569-2
LPC2292FET144/G
TFBGA144
plastic thin fine-pitch ball grid array package;
144 balls; body 12  12  0.8 mm
SOT569-2
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
2 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 1.
Ordering information …continued
Type number
Package
Name
Description
Version
LPC2294HBD144
LQFP144
plastic low profile quad flat package;
144 leads; body 20  20  1.4 mm
SOT486-1
LPC2294HBD144/00
LQFP144
plastic low profile quad flat package;
144 leads; body 20  20  1.4 mm
SOT486-1
LPC2294HBD144/01
LQFP144
plastic low profile quad flat package;
144 leads; body 20  20  1.4 mm
SOT486-1
3.1 Ordering options
Table 2.
Ordering options
Type number
LPC2292_2294
Product data sheet
Flash
memory
RAM
CAN
Fast GPIO/
SSP/
Enhanced
UART, ADC,
Timer
Temperature range
LPC2292FBD144/01 256 kB
16 kB
2 channels
yes
40 C to +85 C
LPC2292FET144/00
16 kB
2 channels
no
40 C to +85 C
256 kB
LPC2292FET144/01
256 kB
16 kB
2 channels
yes
40 C to +85 C
LPC2292FET144/G
256 kB
16 kB
2 channels
no
40 C to +85 C
LPC2294HBD144
256 kB
16 kB
4 channels
no
40 C to +125 C
LPC2294HBD144/00 256 kB
16 kB
4 channels
no
40 C to +125 C
LPC2294HBD144/01 256 kB
16 kB
4 channels
yes
40 C to +125 C
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
3 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
4. Block diagram
TMS(1) TDI(1)
TRST(1) TCK(1) TDO(1)
P0, P1
TEST/DEBUG
INTERFACE
ARM7TDMI-S
HIGH-SPEED
GPIO(4)
48 PINS TOTAL
AHB BRIDGE
INTERNAL
SRAM
CONTROLLER
INTERNAL
FLASH
CONTROLLER
16 kB
SRAM
256 kB
FLASH
4 × CAP0
4 × CAP1
4 × MAT0
4 × MAT1
SYSTEM
FUNCTIONS
PLL
system
clock
VECTORED
INTERRUPT
CONTROLLER
AMBA AHB
(Advanced High-performance Bus)
ARM7 local bus
EINT3 to EINT0
EMULATION
TRACE MODULE
LPC2292
LPC2294
XTAL2
XTAL1 RESET
AHB
DECODER
AHB TO APB
BRIDGE
APB
DIVIDER
CS3 to CS0(2)
A23 to A0(2)
BLS3 to BLS0(2)
OE, WE(2)
D31 to D0(2)
EXTERNAL MEMORY
CONTROLLER
APB (advanced
peripheral bus)
EXTERNAL
INTERRUPTS
SCL
I2C-BUS SERIAL
INTERFACE
SDA
CAPTURE/
COMPARE
TIMER 0/TIMER 1
SCK1
SPI1/SSP(4)
MOSI1
SERIAL INTERFACE
MISO1
SSEL1
AIN3 to AIN0
A/D CONVERTER
SCK0
AIN7 to AIN4
P0[30:0]
P1[31:16], P1[1:0]
P2[31:0]
MOSI0
SPI0
SERIAL INTERFACE
MISO0
SSEL0
GENERAL
PURPOSE I/O
TXD0, TXD1
P3[31:0]
RXD0, RXD1
DSR1, CTS1,
DCD1, RI1
TD2, TD1
RD2, RD1
TD4, TD3(3)
RD4, RD3(3)
UART0/UART1
PWM6 to PWM1
PWM0
CAN
REAL-TIME CLOCK
WATCHDOG
TIMER
SYSTEM CONTROL
002aad184
(1) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(2) Pins shared with GPIO.
(3) Available in LPC2294 only.
(4) SSP interface and high-speed GPIO are available on LPC2292/2294/01 only.
Fig 1. Block diagram
LPC2292_2294
Product data sheet
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
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LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
5. Pinning information
109
144
5.1 Pinning
1
108
LPC2292FBD
LPC2294HBD(1)
72
73
37
36
002aad185
(1) Pin configuration is identical for devices with and without /00 and /01 suffixes.
Fig 2. LQFP144 pinning
ball A1
index area
LPC2292FET144(1)
1 2 3 4 5 6 7 8 9 10 11 12 13
A
B
C
D
E
F
G
H
J
K
L
M
N
002aad191
Transparent top view
(1) Pin configuration is identical for devices with and without /00 and /01 suffixes.
Fig 3. TFBGA144 pinning
LPC2292_2294
Product data sheet
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
5 of 54
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NXP Semiconductors
LPC2292_2294
Product data sheet
Table 3.
Ball allocation
Row Column
3
4
5
6
7
8
9
10
11
12
13
VDDA(1V8)
P1[28]/
TDI
P2[21]/
D21
P2[18]/
D18
P2[14]/
D14
P1[29]/
TCK
P2[11]/
D11
P2[10]/
D10
P2[7]/D7
VDD(3V3)
VDD(1V8)
P2[4]/D4
B
VDD(3V3)
P1[27]/
TDO
XTAL2
VSSA(PLL)
P2[19]/
D19
P2[15]/
D15
P2[12]/
D12
P0[20]/
MAT1[3]/
SSEL1/
EINT3
VDD(3V3)
P2[6]/D6
VSS
P2[3]/D3
VSS
C
P0[21]/
PWM5/
CAP1[3]
VSS
XTAL1
VSSA
RESET
P2[16]/
D16
P2[13]/
D13
P0[19]/
MAT1[2]/
MOSI1/
CAP1[2]
P2[9]/D9
P2[5]/D5
P2[2]/D2
P2[1]/D1
VDD(3V3)
D
P0[24]/
TD2
P1[19]/
TRACE
PKT3
P0[23]/
RD2
P0[22]/
CAP0[0]/
MAT0[0]
P2[20]/
D20
P2[17]/
D17
VSS
P0[18]/
CAP1[3]/
MISO1/
MAT1[3]
P2[8]/D8
P1[30]/
TMS
VSS
P1[20]/
TRACE
SYNC
P0[17]/
CAP1[2]/
SCK1/
MAT1[2]
E
P2[25]/
D25
P2[24]/
D24
P2[23]
VSS
P0[16]/
EINT0/
MAT0[2]/
CAP0[2]
P0[15]/
RI1/
EINT2
P2[0]/D0
P3[30]/
BLS1
F
P2[27]/
D27/
BOOT1
P1[18]/
TRACE
PKT2
VDDA(3V3)
P2[26]/
D26/
BOOT0
P3[31]/
BLS0
P1[21]/
PIPE
STAT0
VDD(3V3)
VSS
G
P2[29]/
D29
P2[28]/
D28
P2[30]/
P2[31]/
D30/AIN4 D31/AIN5
P0[14]/
DCD1/
EINT1
P1[0]/CS0 P3[0]/A0
P1[1]/OE
H
P0[25]/
RD1
TD1
P0[27]/
AIN0/
CAP0[1]/
MAT0[1]
P1[17]/
TRACE
PKT1
P0[13]/
DTR1/
MAT1[1]
P1[22]/
PIPE
STAT1
P3[2]/A2
P3[1]/A1
J
P0[28]/
AIN1/
CAP0[2]/
MAT0[2]
VSS
P3[29]/
BLS2/
AIN6
P3[28]/
BLS3/
AIN7
P3[3]/A3
P1[23]/
PIPE
STAT2
P0[11]/
CTS1/
CAP1[1]
P0[12]/
DSR1/
MAT1[0]
K
P3[27]/
WE
P3[26]/
CS1
VDD(3V3)
P3[22]/
A22
VDD(3V3)
P0[10]/
RTS1/
CAP1[0]
VSS
P3[4]/A4
P3[20]/
A20
P0[1]/
RXD0/
PWM3/
EINT0
P3[14]/
A14
P1[25]/
EXTIN0
P3[11]/
A11
LPC2292/2294
6 of 54
© NXP B.V. 2011. All rights reserved.
2
P2[22]/
D22
16/32-bit ARM microcontrollers with external memory interface
Rev. 8 — 8 June 2011
All information provided in this document is subject to legal disclaimers.
1
A
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Ball allocation …continued
NXP Semiconductors
LPC2292_2294
Product data sheet
Table 3.
Row Column
2
3
4
5
6
7
8
9
10
11
12
13
L
P0[29]/
AIN2/
CAP0[3]/
MAT0[3]
P0[30]/
AIN3/
EINT3/
CAP0[0]
P1[16]/
TRACE
PKT0
P0[0]/
TXD0/
PWM1
P3[19]/
A19
P0[2]/
SCL/
CAP0[0]
P3[15]/
A15
P0[4]/
SCK0/
CAP0[1]
P3[12]/
A12
VSS
P1[24]/
TRACE
CLK
P0[8]/
TXD1/
PWM4
P0[9]/
RXD1/
PWM6/
EINT3
M
P3[25]/
CS2
P3[24]/
CS3
VDD(3V3)
P1[31]/
TRST
P3[18]/
A18
VDD(3V3)
P3[16]/
A16
P0[3]/
SDA/
MAT0[0]/
EINT1
P3[13]/
A13
P3[9]/A9
P0[7]/
SSEL0/
PWM2/
EINT2
P3[7]/A7
P3[5]/A5
N
VDD(1V8)
VSS
P3[23]/
A23/
XCLK
P3[21]/
A21
P3[17]/
A17
P1[26]/
RTCK
VSS
VDD(3V3)
P0[5]/
MISO0/
MAT0[1]
P3[10]/
A10
P0[6]/
MOSI0/
CAP0[2]
P3[8]/A8
P3[6]/A6
LPC2292/2294
7 of 54
© NXP B.V. 2011. All rights reserved.
16/32-bit ARM microcontrollers with external memory interface
Rev. 8 — 8 June 2011
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1
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
5.2 Pin description
Table 4.
Pin description
Symbol
Pin (LQFP)
Pin
(TFBGA)[1]
P0[0] to P0[31]
Type
Description
I/O
Port 0: Port 0 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 0 pins
depends upon the pin function selected via the Pin Connect
Block.
Pins 26 and 31 of port 0 are not available.
P0[0]/TXD0/
PWM1
42[2]
L4[2]
O
O
PWM1 — Pulse Width Modulator output 1.
P0[1]/RXD0/
PWM3/EINT0
49[4]
K6[4]
I
RXD0 — Receiver input for UART0.
O
PWM3 — Pulse Width Modulator output 3.
I
EINT0 — External interrupt 0 input
P0[2]/SCL/
CAP0[0]
50[5]
L6[5]
I/O
SCL — I2C-bus clock input/output. Open-drain output (for
I2C-bus compliance).
I
CAP0[0] — Capture input for Timer 0, channel 0.
P0[3]/SDA/
MAT0[0]/EINT1
58[5]
M8[5]
I/O
SDA — I2C-bus data input/output. Open-drain output (for
I2C-bus compliance).
O
MAT0[0] — Match output for Timer 0, channel 0.
I
EINT1 — External interrupt 1 input.
I/O
SCK0 — Serial clock for SPI0. SPI clock output from master
or input to slave.
I
CAP0[1] — Capture input for Timer 0, channel 1.
I/O
MISO0 — Master In Slave OUT for SPI0. Data input to SPI
master or data output from SPI slave.
O
MAT0[1] — Match output for Timer 0, channel 1.
I/O
MOSI0 — Master Out Slave In for SPI0. Data output from SPI
master or data input to SPI slave.
I
CAP0[2] — Capture input for Timer 0, channel 2.
I
SSEL0 — Slave Select for SPI0. Selects the SPI interface as
a slave.
O
PWM2 — Pulse Width Modulator output 2.
I
EINT2 — External interrupt 2 input.
O
TXD1 — Transmitter output for UART1.
O
PWM4 — Pulse Width Modulator output 4.
I
RXD1 — Receiver input for UART1.
O
PWM6 — Pulse Width Modulator output 6.
P0[4]/SCK0/
CAP0[1]
59[2]
L8[2]
P0[5]/MISO0/
MAT0[1]
61[2]
N9[2]
P0[6]/MOSI0/
CAP0[2]
68[2]
N11[2]
P0[7]/SSEL0/
PWM2/EINT2
69[4]
M11[4]
P0[8]/TXD1/
PWM4
75[2]
P0[9]/RXD1/
PWM6/EINT3
76[4]
P0[10]/RTS1/
CAP1[0]
78[2]
K11[2]
P0[11]/CTS1/
CAP1[1]
83[2]
J12[2]
LPC2292_2294
Product data sheet
L12[2]
L13[4]
TXD0 — Transmitter output for UART0.
I
EINT3 — External interrupt 3 input.
O
RTS1 — Request to Send output for UART1.
I
CAP1[0] — Capture input for Timer 1, channel 0.
I
CTS1 — Clear to Send input for UART1.
I
CAP1[1] — Capture input for Timer 1, channel 1.
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© NXP B.V. 2011. All rights reserved.
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LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
P0[12]/DSR1/
MAT1[0]/RD4
84[2]
J13[2]
I
DSR1 — Data Set Ready input for UART1.
O
MAT1[0] — Match output for Timer 1, channel 0.
I
RD4 — CAN4 receiver input (LPC2294 only).
P0[13]/DTR1/
MAT1[1]/TD4
85[2]
O
DTR1 — Data Terminal Ready output for UART1.
O
MAT1[1] — Match output for Timer 1, channel 1.
O
TD4 — CAN4 transmitter output (LPC2294 only).
P0[14]/DCD1/
EINT1
92[4]
I
DCD1 — Data Carrier Detect input for UART1.
I
EINT1 — External interrupt 1 input.
H10[2]
G10[4]
Note: LOW on this pin while RESET is LOW forces on-chip
bootloader to take over control of the part after reset.
P0[15]/RI1/
EINT2
99[4]
E11[4]
P0[16]/EINT0/
MAT0[2]/
CAP0[2]
100[4]
E10[4]
P0[17]/CAP1[2]/
SCK1/MAT1[2]
101[2]
P0[18]/CAP1[3]/
MISO1/MAT1[3]
121[2]
P0[19]/MAT1[2]/
MOSI1/CAP1[2]
122[2]
P0[20]/MAT1[3]/
SSEL1/EINT3
123[4]
P0[21]/PWM5/
RD3/CAP1[3]
4[2]
P0[22]/TD3/
CAP0[0]/
MAT0[0]
5[2]
P0[23]/RD2
6[2]
D3[2]
P0[24]/TD2
8[2]
D1[2]
P0[25]/RD1
21[2]
H1[2]
LPC2292_2294
Product data sheet
D13[2]
D8[2]
C8[2]
B8[4]
C1[2]
D4[2]
I
RI1 — Ring Indicator input for UART1.
I
EINT2 — External interrupt 2 input.
I
EINT0 — External interrupt 0 input.
O
MAT0[2] — Match output for Timer 0, channel 2.
I
CAP0[2] — Capture input for Timer 0, channel 2.
I
CAP1[2] — Capture input for Timer 1, channel 2.
I/O
SCK1 — Serial Clock for SPI1/SSP[3]. SPI clock output from
master or input to slave.
O
MAT1[2] — Match output for Timer 1, channel 2.
I
CAP1[3] — Capture input for Timer 1, channel 3.
I/O
MISO1 — Master In Slave Out for SPI1/SSP[3]. Data input to
SPI master or data output from SPI slave.
O
MAT1[3] — Match output for Timer 1, channel 3.
O
MAT1[2] — Match output for Timer 1, channel 2.
I/O
MOSI1 — Master Out Slave In for SPI1/SSP[3]. Data output
from SPI master or data input to SPI slave.
I
CAP1[2] — Capture input for Timer 1, channel 2.
O
MAT1[3] — Match output for Timer 1, channel 3.
I
SSEL1 — Slave Select for SPI1/SSP[3]. Selects the SPI
interface as a slave.
I
EINT3 — External interrupt 3 input.
O
PWM5 — Pulse Width Modulator output 5.
I
RD3 — CAN3 receiver input (LPC2294 only).
I
CAP1[3] — Capture input for Timer 1, channel 3.
O
TD3 — CAN3 transmitter output (LPC2294 only).
I
CAP0[0] — Capture input for Timer 0, channel 0.
O
MAT0[0] — Match output for Timer 0, channel 0.
I
RD2 — CAN2 receiver input.
O
TD2 — CAN2 transmitter output.
I
RD1 — CAN1 receiver input.
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
9 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
P0[27]/AIN0/
CAP0[1]/
MAT0[1]
23[6]
H3[6]
I
AIN0 — ADC, input 0. This analog input is always connected
to its pin.
I
CAP0[1] — Capture input for Timer 0, channel 1.
O
MAT0[1] — Match output for Timer 0, channel 1.
I
AIN1 — ADC, input 1. This analog input is always connected
to its pin.
I
CAP0[2] — Capture input for Timer 0, channel 2.
O
MAT0[2] — Match output for Timer 0, channel 2.
I
AIN2 — ADC, input 2. This analog input is always connected
to its pin.
I
CAP0[3] — Capture input for Timer 0, Channel 3.
O
MAT0[3] — Match output for Timer 0, channel 3.
I
AIN3 — ADC, input 3. This analog input is always connected
to its pin.
I
EINT3 — External interrupt 3 input.
I
CAP0[0] — Capture input for Timer 0, channel 0.
I/O
Port 1: Port 1 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 1 pins
depends upon the pin function selected via the Pin Connect
Block.
P0[28]/AIN1/
CAP0[2]/
MAT0[2]
P0[29]/AIN2/
CAP0[3]/
MAT0[3]
P0[30]/AIN3/
EINT3/CAP0[0]
25[6]
32[6]
33[6]
J1[6]
L1[6]
L2[6]
P1[0] to P1[31]
Pins 2 through 15 of port 1 are not available.
P1[0]/CS0
91[7]
G11[7]
P1[1]/OE
90[7]
G13[7]
O
OE — LOW-active Output Enable signal.
P1[16]/
TRACEPKT0
34[7]
L3[7]
O
TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with
internal pull-up.
P1[17]/
TRACEPKT1
24[7]
H4[7]
O
TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with
internal pull-up.
P1[18]/
TRACEPKT2
15[7]
F2[7]
O
TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with
internal pull-up.
P1[19]/
TRACEPKT3
7[7]
D2[7]
O
TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with
internal pull-up.
P1[20]/
TRACESYNC
102[7]
D12[7]
O
TRACESYNC — Trace Synchronization. Standard I/O port
with internal pull-up.
O
CS0 — LOW-active Chip Select 0 signal.
(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)
Note: LOW on this pin while RESET is LOW, enables pins
P1[25:16] to operate as Trace port after reset.
P1[21]/
PIPESTAT0
95[7]
F11[7]
O
PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with
internal pull-up.
P1[22]/
PIPESTAT1
86[7]
H11[7]
O
PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with
internal pull-up.
P1[23]/
PIPESTAT2
82[7]
J11[7]
O
PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with
internal pull-up.
P1[24]/
TRACECLK
70[7]
L11[7]
O
TRACECLK — Trace Clock. Standard I/O port with internal
pull-up.
LPC2292_2294
Product data sheet
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
10 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
P1[25]/EXTIN0
60[7]
K8[7]
I
EXTIN0 — External Trigger Input. Standard I/O with internal
pull-up.
P1[26]/RTCK
52[7]
N6[7]
I/O
RTCK — Returned Test Clock output. Extra signal added to
the JTAG port. Assists debugger synchronization when
processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET is LOW, enables pins
P1[31:26] to operate as Debug port after reset.
P1[27]/TDO
144[7]
B2[7]
O
TDO — Test Data out for JTAG interface.
P1[28]/TDI
140[7]
A3[7]
I
TDI — Test Data in for JTAG interface.
P1[29]/TCK
126[7]
A7[7]
I
TCK — Test Clock for JTAG interface. This clock must be
slower than 1⁄6 of the CPU clock (CCLK) for the JTAG
interface to operate.
P1[30]/TMS
113[7]
D10[7]
I
TMS — Test Mode Select for JTAG interface.
P1[31]/TRST
43[7]
M4[7]
I
TRST — Test Reset for JTAG interface.
I/O
Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 2 pins
depends upon the pin function selected via the Pin Connect
Block.
P2[0] to P2[31]
P2[0]/D0
98[7]
E12[7]
I/O
D0 — External memory data line 0.
P2[1]/D1
105[7]
C12[7]
I/O
D1 — External memory data line 1.
P2[2]/D2
106[7]
C11[7]
I/O
D2 — External memory data line 2.
P2[3]/D3
108[7]
B12[7]
I/O
D3 — External memory data line 3.
P2[4]/D4
109[7]
A13[7]
I/O
D4 — External memory data line 4.
P2[5]/D5
114[7]
C10[7]
I/O
D5 — External memory data line 5.
P2[6]/D6
115[7]
B10[7]
I/O
D6 — External memory data line 6.
P2[7]/D7
116[7]
A10[7]
I/O
D7 — External memory data line 7.
P2[8]/D8
117[7]
D9[7]
I/O
D8 — External memory data line 8.
P2[9]/D9
118[7]
C9[7]
I/O
D9 — External memory data line 9.
P2[10]/D10
120[7]
A9[7]
I/O
D10 — External memory data line 10.
P2[11]/D11
124[7]
A8[7]
I/O
D11 — External memory data line 11.
P2[12]/D12
125[7]
B7[7]
I/O
D12 — External memory data line 12.
P2[13]/D13
127[7]
C7[7]
I/O
D13 — External memory data line 13.
P2[14]/D14
129[7]
A6[7]
I/O
D14 — External memory data line 14.
P2[15]/D15
130[7]
B6[7]
I/O
D15 — External memory data line 15.
P2[16]/D16
131[7]
C6[7]
I/O
D16 — External memory data line 16.
P2[17]/D17
132[7]
D6[7]
I/O
D17 — External memory data line 17.
P2[18]/D18
133[7]
A5[7]
I/O
D18 — External memory data line 18.
P2[19]/D19
134[7]
B5[7]
I/O
D19 — External memory data line 19.
P2[20]/D20
136[7]
D5[7]
I/O
D20 — External memory data line 20.
P2[21]/D21
137[7]
A4[7]
I/O
D21 — External memory data line 21.
P2[22]/D22
1[7]
A1[7]
I/O
D22 — External memory data line 22.
P2[23]/D23
10[7]
E3[7]
I/O
D23 — External memory data line 23.
LPC2292_2294
Product data sheet
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
11 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
P2[24]/D24
11[7]
E2[7]
I/O
D24 — External memory data line 24.
P2[25]/D25
12[7]
E1[7]
I/O
D25 — External memory data line 25.
P2[26]/D26/
BOOT0
13[7]
F4[7]
I/O
D26 — External memory data line 26.
I
BOOT0 — While RESET is low, together with BOOT1
controls booting and internal operation. Internal pull-up
ensures high state if pin is left unconnected.
P2[27]/D27/
BOOT1
16[7]
I/O
D27 — External memory data line 27.
I
BOOT1 — While RESET is low, together with BOOT0
controls booting and internal operation. Internal pull-up
ensures high state if pin is left unconnected.
F1[7]
BOOT1:0 = 00 selects 8-bit memory on CS0 for boot.
BOOT1:0 = 01 selects 16-bit memory on CS0 for boot.
BOOT1:0 = 10 selects 32-bit memory on CS0 for boot.
BOOT1:0 = 11 selects internal flash memory.
P2[28]/D28
17[7]
G2[7]
I/O
D28 — External memory data line 28.
P2[29]/D29
18[7]
G1[7]
I/O
D29 — External memory data line 29.
P2[30]/D30/
AIN4
19[6]
G3[6]
I/O
D30 — External memory data line 30.
I
AIN4 — ADC, input 4. This analog input is always connected
to its pin.
P2[31]/D31/
AIN5
20[6]
I/O
D31 — External memory data line 31.
I
AIN5 — ADC, input 5. This analog input is always connected
to its pin.
I/O
Port 3 — Port 3 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 3 pins
depends upon the pin function selected via the Pin Connect
Block.
G4[6]
P3[0] to P3[31]
P3[0]/A0
89[7]
G12[7]
O
A0 — External memory address line 0.
P3[1]/A1
88[7]
H13[7]
O
A1 — External memory address line 1.
P3[2]/A2
87[7]
H12[7]
O
A2 — External memory address line 2.
P3[3]/A3
81[7]
J10[7]
O
A3 — External memory address line 3.
P3[4]/A4
80[7]
K13[7]
O
A4 — External memory address line 4.
P3[5]/A5
74[7]
M13[7]
O
A5 — External memory address line 5.
P3[6]/A6
73[7]
N13[7]
O
A6 — External memory address line 6.
P3[7]/A7
72[7]
M12[7]
O
A7 — External memory address line 7.
P3[8]/A8
71[7]
N12[7]
O
A8 — External memory address line 8.
P3[9]/A9
66[7]
M10[7]
O
A9 — External memory address line 9.
P3[10]/A10
65[7]
N10[7]
O
A10 — External memory address line 10.
P3[11]/A11
64[7]
K9[7]
O
A11 — External memory address line 11.
P3[12]/A12
63[7]
L9[7]
O
A12 — External memory address line 12.
P3[13]/A13
62[7]
M9[7]
O
A13 — External memory address line 13.
P3[14]/A14
56[7]
K7[7]
O
A14 — External memory address line 14.
P3[15]/A15
55[7]
L7[7]
O
A15 — External memory address line 15.
P3[16]/A16
53[7]
M7[7]
O
A16 — External memory address line 16.
LPC2292_2294
Product data sheet
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
12 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
P3[17]/A17
48[7]
N5[7]
O
A17 — External memory address line 17.
P3[18]/A18
47[7]
M5[7]
O
A18 — External memory address line 18.
P3[19]/A19
46[7]
L5[7]
O
A19 — External memory address line 19.
P3[20]/A20
45[7]
K5[7]
O
A20 — External memory address line 20.
P3[21]/A21
44[7]
N4[7]
O
A21 — External memory address line 21.
P3[22]/A22
41[7]
K4[7]
O
A22 — External memory address line 22.
P3[23]/A23/
XCLK
40[7]
N3[7]
I/O
A23 — External memory address line 23.
O
XCLK — Clock output.
P3[24]/CS3
36[7]
M2[7]
O
CS3 — LOW-active Chip Select 3 signal.
P3[25]/CS2
35[7]
M1[7]
O
P3[26]/CS1
30[7]
K2[7]
(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)
CS2 — LOW-active Chip Select 2 signal.
(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)
O
CS1 — LOW-active Chip Select 1 signal.
(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)
P3[27]/WE
29[7]
K1[7]
P3[28]/BLS3/
AIN7
28[6]
J4[6]
P3[29]/BLS2/
AIN6
27[6]
P3[30]/BLS1
97[7]
O
WE — LOW-active Write enable signal.
O
BLS3 — LOW-active Byte Lane Select signal (Bank 3).
I
AIN7 — ADC, input 7. This analog input is always connected
to its pin.
O
BLS2 — LOW-active Byte Lane Select signal (Bank 2).
I
AIN6 — ADC, input 6. This analog input is always connected
to its pin.
E13[7]
O
BLS1 — LOW-active Byte Lane Select signal (Bank 1).
P3[31]/BLS0
96[7]
F10[7]
O
BLS0 — LOW-active Byte Lane Select signal (Bank 0).
TD1
22[7]
H2[7]
O
TD1: CAN1 transmitter output.
RESET
135[8]
C5[8]
I
External Reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
XTAL1
142[9]
C3[9]
I
Input to the oscillator circuit and internal clock generator
circuits.
XTAL2
141[9]
B3[9]
O
Output from the oscillator amplifier.
VSS
3, 9, 26, 38,
54, 67, 79,
93, 103, 107,
111, 128
C2, E4, J2,
N2, N7, L10,
K12, F13,
D11, B13,
B11, D7
I
Ground: 0 V reference.
VSSA
139
C4
I
Analog ground: 0 V reference. This should nominally be the
same voltage as VSS, but should be isolated to minimize noise
and error.
VSSA(PLL)
138
B4
I
PLL analog ground: 0 V reference. This should nominally be
the same voltage as VSS, but should be isolated to minimize
noise and error.
VDD(1V8)
37, 110
N1, A12
I
1.8 V core power supply: This is the power supply voltage
for internal circuitry.
LPC2292_2294
Product data sheet
J3[6]
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
13 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
VDDA(1V8)
143
A2
I
Analog 1.8 V core power supply: This is the power supply
voltage for internal circuitry. This should be nominally the
same voltage as VDD(1V8) but should be isolated to minimize
noise and error.
VDD(3V3)
2, 31, 39, 51, B1, K3, M3,
I
57, 77, 94,
M6, N8, K10,
104, 112, 119 F12, C13,
A11, B9
3.3 V pad power supply: This is the power supply voltage for
the I/O ports.
VDDA(3V3)
14
Analog 3.3 V pad power supply: This should be nominally
the same voltage as VDD(3V3) but should be isolated to
minimize noise and error.
F3
I
[1]
LPC2294 only.
[2]
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
[3]
SSP interface available on LPC2292/2294/01 only.
[4]
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input
function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[5]
Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output
functionality. Open-drain configuration applies to all output functions on this pin.
[6]
5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured
for a digital input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input,
digital section of the pad is disabled.
[7]
5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
The pull-up resistor’s value ranges from 60 k to 300 k.
[8]
5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
[9]
Pad provides special analog functionality.
LPC2292_2294
Product data sheet
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
14 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on RISC
principles, and the instruction set and related decode mechanism are much simpler than
those of microprogrammed CISC. This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set
• A 16-bit Thumb set
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2 On-chip flash program memory
The LPC2292/2294 incorporate a 256 kB flash memory system respectively. This memory
may be used for both code and data storage. Programming of the flash memory may be
accomplished in several ways. It may be programmed In System via the serial port. The
application program may also erase and/or program the flash while the application is
running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.
When the on-chip bootloader is used, 248 kB of flash memory is available for user code.
The LPC2292/2294 flash memory provides a minimum of 100000 erase/write cycles and
20 years of data retention.
On-chip bootloader (as of revision 1.64) provides Code Read Protection (CRP) for the
LPC2292/2294 on-chip flash memory. When the CRP is enabled, the JTAG debug port,
external memory boot and ISP commands accessing either the on-chip RAM or flash
memory are disabled. However, the ISP flash erase command can be executed at any
time (no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of
full on-chip user flash. With the CRP off, full access to the chip via the JTAG and/or ISP is
restored.
LPC2292_2294
Product data sheet
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
15 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
6.3 On-chip SRAM
On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed
as 8-bit, 16-bit, and 32-bit. The LPC2292/2294 provide 16 kB of SRAM.
6.4 Memory map
The LPC2292/2294 memory maps incorporate several distinct regions, as shown in
Figure 4.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.19
“System control”.
4.0 GB
0xFFFF FFFF
AHB PERIPHERALS
3.75 GB
APB PERIPHERALS
0xF000 0000
0xEFFF FFFF
3.5 GB
0xE000 0000
0xDFFF FFFF
3.0 GB
0xC000 0000
RESERVED ADDRESS SPACE
2.0 GB
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP FLASH MEMORY)
0x8000 0000
0x7FFF FFFF
0x7FFF E000
0x7FFF DFFF
RESERVED ADDRESS SPACE
0x4000 4000
0x4000 3FFF
16 kB ON-CHIP STATIC RAM
0x4000 0000
0x3FFF FFFF
1.0 GB
RESERVED ADDRESS SPACE
0x0004 0000
0x0003 FFFF
256 kB ON-CHIP FLASH MEMORY
0x0000 0000
0.0 GB
002aaa754
Fig 4. LPC2292/2294 memory map
LPC2292_2294
Product data sheet
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Rev. 8 — 8 June 2011
© NXP B.V. 2011. All rights reserved.
16 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
6.5 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as Fast Interrupt
Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by
programmable settings. The programmable assignment scheme means that priorities of
interrupts from the various peripherals can be dynamically assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ, because then
the FIQ service routine can simply start dealing with that device. But if more than one
request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC
that identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Table 5 lists the interrupt sources for each peripheral function. Each peripheral device has
one interrupt line connected to the VIC, but may have several internal interrupt flags.
Individual interrupt flags may also represent more than one interrupt source.
Table 5.
Interrupt sources
Block
Flag(s)
VIC channel #
WDT
Watchdog Interrupt (WDINT)
0
-
Reserved for software interrupts only
1
ARM Core
EmbeddedICE, DbgCommRx
2
ARM Core
EmbeddedICE, DbgCommTx
3
Timer 0
Match 0 to 3 (MR0, MR1, MR2, MR3)
4
Capture 0 to 3 (CR0, CR1, CR2, CR3)
Timer 1
Match 0 to 3 (MR0, MR1, MR2, MR3)
5
Capture 0 to 3 (CR0, CR1, CR2, CR3)
UART0
RX Line Status (RLS)
6
Transmit Holding Register Empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
Auto-baud time-out (ABTO)[1]End of auto-baud (ABEO)[1]
LPC2292_2294
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Rev. 8 — 8 June 2011
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17 of 54
LPC2292/2294
NXP Semiconductors
16/32-bit ARM microcontrollers with external memory interface
Table 5.
Interrupt sources …continued
Block
Flag(s)
VIC channel #
UART1
RX Line Status (RLS)
7
Transmit Holding Register empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
Auto-baud time-out (ABTO)[1]End of auto-baud (ABEO)[1]
PWM0
Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
8
I2C
SI (state change)
9
SPIF, MODF
10
SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS
11
PLL
PLL Lock (PLOCK)
12
RTC
RTCCIF (Counter Increment), RTCALF (Alarm)
13
System Control
External Interrupt 0 (EINT0)
14
External Interrupt 1 (EINT1)
15
External Interrupt 2 (EINT2)
16
External Interrupt 3 (EINT3)
17
ADC
ADC
18
CAN
1 ORed CAN Acceptance Filter
19
SPI0
SPI1 and
[1]
SSP[1]
CAN1/2 Tx
20, 21
CAN2/3 Tx (LPC2294 only)
22, 23
reserved
24, 25
CAN1/2 Rx
26, 27
CAN3/4 Rx (LPC2294 only)
28,29
SSP interface and UART0/1 auto-baud control are available on LPC2292/2294/01 only.
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.
6.7 External memory controller
The external Static Memory Controller is a module which provides an interface between
the system bus and external (off-chip) memory devices. It provides support for up to four
independently configurable memory banks (16 MB each with byte lane enable control)
simultaneously. Each memory bank is capable of supporting SRAM, ROM, flash EPROM,
burst ROM memory, or some external I/O devices.
Each memory bank may be 8-bit, 16-bit, or 32-bit wide.
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6.8 General purpose parallel I/O (GPIO) and Fast I/O
Device pins that are not connected to a specific peripheral function are controlled by the
parallel I/O registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.
6.8.1 Features
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.
6.8.2 Features added with the Fast GPIO set of registers available on
LPC2292/2294/01 only
• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O
timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
• All Fast GPIO registers are byte addressable.
• Entire port value can be written in one instruction.
• Ports are accessible via either the legacy group of registers (GPIOs) or the group of
registers providing accelerated port access (Fast GPIOs).
6.9 10-bit ADC
The LPC2292/2294 each contain a single 10-bit successive approximation ADC with four
multiplexed channels.
6.9.1 Features
•
•
•
•
Measurement range of 0 V to 3 V.
Capable of performing more than 400000 10-bit samples per second.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
6.9.2 ADC features available in LPC2292/2294/01 only
• Every analog input has a dedicated result register to reduce interrupt overhead.
• Every analog input can generate an interrupt once the conversion is completed.
• The ADC pads are 5 V tolerant when configured for digital I/O function(s).
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6.10 CAN controllers and acceptance filter
The LPC2292/2294 each contain two/four CAN controllers. The CAN is a serial
communications protocol which efficiently supports distributed real-time control with a
very high level of security. Its domain of application ranges from high-speed networks to
low cost multiplex wiring.
6.10.1 Features
•
•
•
•
•
Data rates up to 1 Mbit/s on each bus.
32-bit register and RAM access.
Compatible with CAN specification 2.0B, ISO 11898-1.
Global Acceptance Filter recognizes 11-bit and 29-bit RX identifiers for all CAN buses.
Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard identifiers.
6.11 UARTs
The LPC2292/2294 each contain two UARTs. In addition to standard transmit and receive
data lines, the UART1 also provides a full modem control handshake interface.
6.11.1 Features
•
•
•
•
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
• UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
6.11.2 UART features available in LPC2292/2294/01 only
Compared to previous LPC2000 microcontrollers, UARTs in LPC2292/2294/01 introduce
a fractional baud rate generator for both UARTs, enabling these microcontrollers to
achieve standard baud rates such as 115200 Bd with any crystal frequency above 2 MHz.
In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware.
• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be
achieved with any crystal frequency above 2 MHz.
• Auto-bauding.
• Auto-CTS/RTS flow-control fully implemented in hardware.
6.12 I2C-bus serial I/O controller
The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
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receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2292/2294 supports bit rate up to 400 kbit/s (Fast
I2C-bus).
6.12.1 Features
•
•
•
•
•
•
Compliant with standard I2C-bus interface.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus may be used for test and diagnostic purposes.
6.13 SPI serial I/O controller
The LPC2292/2294 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
6.13.1 Features
•
•
•
•
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex communication.
Combined SPI master and slave.
Maximum data bit rate of 1⁄8 of the input clock rate.
6.13.2 Features available in LPC2292/2294/01 only
• Eight to 16 bits per frame.
• When the SPI interface is used in Master mode, the SSELn pin is not needed (can be
used for a different function).
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6.14 SSP controller (LPC2292/94/01 only)
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data flowing from the master to the
slave and from the slave to the master.
While the SSP and SPI1 peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. Application can switch on the
fly from SPI1 to SSP and back.
6.14.1 Features
• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
•
•
•
•
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four to 16 bits per frame.
6.15 General purpose timers
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
6.15.1 Features
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
• Timer or external event counter operation
• Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Four external outputs per timer corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
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6.15.2 Features available in LPC2292/2294/01 only
The LPC2292/2294/01 can count external events on one of the capture inputs if the
external pulse lasts at least one half of the period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs, or used as external
interrupts.
• Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied
clock.
• When counting cycles of an externally supplied clock, only one of the timer’s capture
inputs can be selected as the timer’s clock. The rate of such a clock is limited to
PCLK / 4. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter
than 1 / (2PCLK).
6.16 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
6.16.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•
•
•
•
Incorrect/incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (Tcy(PCLK)  256  4) to (Tcy(PCLK)  232  4) in multiples of
Tcy(PCLK)  4.
6.17 Real-time clock
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use little
power, making it suitable for battery powered systems where the CPU is not running
continuously (Idle mode).
6.17.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra-low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
• Programmable Reference Clock Divider allows adjustment of the RTC to match
various crystal frequencies.
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6.18 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2292/2294. The Timer is designed to
count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform
other actions when specified timer values occur, based on seven match registers. The
PWM function is also based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an MR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
6.18.1 Features
• Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
• The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
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• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit Timer/Counter with a programmable 32-bit prescaler.
6.19 System control
6.19.1 Crystal oscillator
The oscillator supports crystals in the range of 1 MHz to 25 MHz. The oscillator output
frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for
purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is
running and connected. Refer to Section 6.19.2 “PLL” for additional information.
6.19.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100 s.
6.19.3 Reset and wake-up timer
Reset has two sources on the LPC2292/2294: the RESET pin and watchdog reset. The
RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip
reset by any source starts the Wake-up Timer (see Wake-up Timer description below),
causing the internal chip reset to remain asserted until the external reset is de-asserted,
the oscillator is running, a fixed number of clocks have passed, and the on-chip flash
controller has completed its initialization.
When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The Wake-up Timer ensures that the oscillator and other analog functions required for
chip operation are fully functional before the processor is allowed to execute instructions.
This is important at power-on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the Wake-up Timer.
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The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power-on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.19.4 Code security (Code Read Protection - CRP)
This feature of the LPC2292/2294/01 allows the user to enable different levels of security
in the system so that access to the on-chip flash and use of the JTAG and ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
Remark: Devices without a /00 or /01 in the name have only a security level equivalent to
CRP2 available.
6.19.5 External interrupt inputs
The LPC2292/2294 include up to nine edge or level sensitive External Interrupt Inputs as
selectable pin functions. When the pins are combined, external events can be processed
as four independent interrupt signals. The External Interrupt Inputs can optionally be used
to wake up the processor from Power-down mode.
6.19.6 Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
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6.19.7 Power control
The LPC2292/2294 support two reduced power modes: Idle mode and Power-down
mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates power used
by the processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down, and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode, and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
6.19.8 APB bus
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB bus so that they can operate at
the speed chosen for the ARM processor. In order to achieve this, the APB bus may be
slowed down to 1⁄2 to 1⁄4 of the processor clock rate. Because the APB bus must work
properly at power-up (and its timing cannot be altered if it does not work since the APB
divider control registers reside on the APB bus), the default condition at reset is for the
APB bus to run at 1⁄4 of the processor clock rate. The second purpose of the APB divider
is to allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the APB divider is connected to the PLL output, the PLL
remains active (if it was running) during Idle mode.
6.20 Emulation and debugging
The LPC2292/2294 support emulation and debugging via a JTAG serial port. A trace port
allows tracing program execution. Debugging and trace functions are multiplexed only
with GPIOs on Port 1. This means that all communication, timer and interface peripherals
residing on Port 0 are available during the development and debugging phase as they are
when the application is run in the embedded system itself.
6.20.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol converter. EmbeddedICE protocol converter converts the remote
debug protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
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communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG
interface to operate.
6.20.2 Embedded trace
Since the LPC2292/2294 have significant amounts of on-chip memory, it is not possible to
determine how the processor core is operating simply by observing the external pins. The
Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply
embedded processor cores. It outputs information about processor execution to the trace
port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of execution of the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the
pipeline status on a cycle by cycle basis. Trace information generation can be controlled
by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace information is compressed the software debugger
requires a static image of the code being executed. Self-modifying code cannot be traced
because of this restriction.
6.20.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables
real-time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the Debug
Communications Channel (DCC), which is present in the EmbeddedICE logic. The
LPC2292/2294 contain a specific configuration of RealMonitor software programmed into
the on-chip flash memory.
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7. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Min
Max
Unit
supply voltage (1.8 V)
[2]
0.5
+2.5
V
VDD(3V3)
supply voltage (3.3 V)
[3]
0.5
+3.6
V
VDDA(3V3)
analog supply voltage (3.3 V)
0.5
+4.6
V
VIA
analog input voltage
VDD(1V8)
Parameter
Conditions
0.5
+5.1
V
5 V tolerant I/O pins
[4][5]
0.5
+6.0
V
other I/O pins
[4][6]
0.5
VDD(3V3) + 0.5
V
supply current
[7][8]
-
100
mA
ISS
ground current
[8][9]
-
100
mA
Tj
junction temperature
-
150
C
input voltage
VI
IDD
[10]
Tstg
storage temperature
Ptot(pack)
total power dissipation (per
package)
based on package heat
transfer, not device
power consumption
Vesd
electrostatic discharge voltage
human body model
all pins
[1]
65
+150
C
-
1.5
W
2000
+2000
V
[11]
The following applies to Table 6:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2]
Internal rail.
[3]
External rail.
[4]
Including voltage on outputs in 3-state mode.
[5]
Only valid when the VDD(3V3) supply voltage is present.
[6]
Not to exceed 4.6 V.
[7]
Per supply pin.
[8]
The peak current is limited to 25 times the corresponding maximum current.
[9]
Per ground pin.
[10] Dependent on package type.
[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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8. Static characteristics
Table 7.
Static characteristics
Tamb = 40 C to +125 C, unless otherwise specified.
Symbol
VDD(1V8)
VDD(3V3)
Min
Typ[1]
Max
Unit
supply voltage (1.8 V)
[2]
1.65
1.8
1.95
V
supply voltage (3.3 V)
[3]
3.0
3.3
3.6
V
2.5
3.3
3.6
V
Parameter
Conditions
VDDA(3V3) analog supply voltage
(3.3 V)
Standard port pins, RESET, RTCK
IIL
LOW-level input current
VI = 0 V; no pull-up
-
-
3
A
IIH
HIGH-level input current
VI = VDD(3V3); no pull-down
-
-
3
A
IOZ
OFF-state output current
VO = 0 V, VO = VDD(3V3);
no pull-up/down
-
-
3
A
Ilatch
I/O latch-up current
(0.5VDD(3V3)) < VI <
(1.5VDD(3V3)); Tj < 125 C
100
-
-
mA
VI
input voltage
0
-
5.5
V
[4][5]
[6]
VO
output voltage
0
-
VDD(3V3)
V
VIH
HIGH-level input voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
Vhys
hysteresis voltage
0.4
-
-
V
output active
VOH
HIGH-level output voltage
IOH = 4 mA
[7]
VDD(3V3)  0.4 -
-
V
VOL
LOW-level output voltage
IOL = 4 mA
[7]
-
-
0.4
V
IOH
HIGH-level output current
VOH = VDD(3V3)  0.4 V
[7]
4
-
-
mA
VOL = 0.4 V
[7]
4
-
-
mA
-
-
45
mA
IOL
LOW-level output current
IOHS
HIGH-level short-circuit
output current
VOH = 0 V
[8]
IOLS
LOW-level short-circuit
output current
VOL = VDD(3V3)
[8]
-
-
50
mA
Ipd
pull-down current
VI = 5 V
[9]
10
50
150
A
Ipu
pull-up current
VI = 0 V
[10]
15
50
85
A
0
0
0
A
VDD(3V3) < VI < 5 V
LPC2292_2294
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Table 7.
Static characteristics …continued
Tamb = 40 C to +125 C, unless otherwise specified.
Symbol
Parameter
Min
Typ[1]
Max
Unit
-
50
-
mA
VDD(1V8) = 1.8 V;
Tamb = 25 C
-
10
-
A
VDD(1V8) = 1.8 V;
Tamb = 85 C
-
110
500
A
VDD(1V8) = 1.8 V;
Tamb = 125 C
-
300
1000
A
-
45
-
mA
-
11.5
-
mA
VDD(1V8) = 1.8 V;
Tamb = 25 C
-
10
-
A
VDD(1V8) = 1.8 V;
Tamb = 85 C
-
110
500
A
VDD(1V8) = 1.8 V;
Tamb = 125 C
-
300
1000
A
V
Conditions
Power consumption LPC2292, LPC2292/00, LPC2294, LPC2294/00
IDD(act)
active mode supply current
VDD(1V8) = 1.8 V;
CCLK = 60 MHz;
Tamb = 25 C; code
while(1){}
executed from flash; all
peripherals enabled via
PCONP[11] register but not
configured to run
IDD(pd)
Power-down mode supply
current
Power consumption LPC2292/01 and LPC2294/01
IDD(act)
active mode supply current
VDD(1V8) = 1.8 V;
CCLK = 60 MHz;
Tamb = 25 C; code
while(1){}
executed from flash; all
peripherals enabled via
PCONP[11] register but not
configured to run
IDD(idle)
Idle mode supply current
VDD(1V8) = 1.8 V;
CCLK = 60 MHz;
Tamb = 25 C;
executed from flash; all
peripherals enabled via
PCONP[11] register but not
configured to run
IDD(pd)
Power-down mode supply
current
I2C-bus pins
VIH
HIGH-level input voltage
0.7VDD(3V3)
-
-
VIL
LOW-level input voltage
-
-
0.3VDD(3V3) V
Vhys
hysteresis voltage
-
0.05VDD(3V3) -
V
IOLS = 3 mA
[7]
-
-
0.4
V
VI = VDD(3V3)
[12]
-
2
4
A
-
10
22
A
VOL
ILI
LOW-level output voltage
input leakage current
VI = 5 V
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Table 7.
Static characteristics …continued
Tamb = 40 C to +125 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Oscillator pins
Vi(XTAL1)
input voltage on pin XTAL1
0
-
1.8
V
Vo(XTAL2)
output voltage on pin
XTAL2
0
-
1.8
V
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), nominal supply voltages.
[2]
Internal rail.
[3]
External rail.
[4]
Including voltage on outputs in 3-state mode.
[5]
VDD(3V3) supply voltages must be present.
[6]
3-state outputs go into 3-state mode when VDD(3V3) is grounded.
[7]
Accounts for 100 mV voltage drop in all supply lines.
[8]
Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[9]
Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
[10] Applies to P1[25:16].
[11] See the LPC2119/2129/2194/2292/2294 User Manual.
[12] To VSS.
Table 8.
ADC static characteristics
VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +125 C unless otherwise specified. ADC frequency 4.5 MHz.
Symbol
Parameter
Min
Typ
Max
Unit
VIA
analog input voltage
Conditions
0
-
VDDA
V
Cia
analog input
capacitance
-
-
1
pF
ED
differential linearity
error
-
-
1
LSB
[1][2][3]
integral non-linearity
[1][4]
-
-
2
LSB
offset error
[1][5]
-
-
3
LSB
EG
gain error
[1][6]
-
-
0.5
%
ET
absolute error
[1][7]
-
-
4
LSB
EL(adj)
EO
[1]
Conditions: VSSA = 0 V, VDDA = 3.3 V.
[2]
The ADC is monotonic, there are no missing codes.
[3]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5.
[4]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 5.
[5]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 5.
[6]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 5.
[7]
The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the
non-calibrated ADC and the ideal transfer curve. See Figure 5.
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gain
error
EG
offset
error
EO
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
(5)
4
(4)
3
(3)
2
1 LSB
(ideal)
1
0
1
2
3
4
5
6
7
1018
1019
1020
1021
1022
1023
1024
VIA (LSBideal)
1 LSB =
offset
error
EO
VDDA − VSSA
1024
002aaa668
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 5. ADC characteristics
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8.1 Power consumption measurements for LPC2292/01 and LPC2294/01
The power consumption measurements represent typical values for the given conditions.
The peripherals were enabled through the PCONP register, but for these measurements,
the peripherals were not configured to run. Peripherals were disabled through the PCONP
register. For a description of the PCONP register bits, refer to the
LPC2119/2129/2194/2292/2294 User Manual.
002aad102
50
IDD(act)
(mA)
40
all peripherals enabled
all peripherals disabled
30
20
10
0
12
20
28
36
44
52
60
frequency (MHz)
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; core voltage 1.8 V.
Fig 6.
Typical LPC2292/01 IDD(act) measured at different frequencies
50
IDD(act)
(mA)
002aad103
60 MHz
48 MHz
40
30
20
12 MHz
10
0
1.65
1.80
voltage (V)
1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; all peripherals enabled but not active.
Fig 7.
Typical LPC2292/01 IDD(act) measured at different core voltages
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002aad104
45
60 MHz
IDD(act)
(mA)
48 MHz
35
25
15
12 MHz
5
-40
-15
10
35
60
temperature (°C) 85
Test conditions: Active mode entered executing code on-chip flash; PCLK = CCLK⁄4;
core voltage 1.8 V; all peripherals disabled.
Fig 8.
Typical LPC2292/01 IDD(act) measured at different temperatures
002aad105
10.0
IDD(idle)
(mA)
8.0
all peripherals enabled
6.0
all peripherals disabled
4.0
2.0
0.0
12
20
28
36
44
52
60
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; core voltage 1.8 V.
Fig 9.
Typical LPC2292/01 IDD(idle) measured at different frequencies
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002aad106
10.0
IDD(idle)
(mA)
60 MHz
8.0
48 MHz
6.0
4.0
12 MHz
2.0
1.65
1.80
voltage (V)
1.95
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; all peripherals enabled but not active.
Fig 10. Typical LPC2292/01 IDD(idle) measured at different core voltages
002aad107
6.0
IDD(idle)
(mA)
5.0
60 MHz
4.0
48 MHz
3.0
2.0
12 MHz
1.0
-40
-15
10
35
60
temperature (°C)
85
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Core voltage 1.8 V; all peripherals disabled.
Fig 11. Typical LPC2292/01 IDD(idle) measured at different temperatures
LPC2292_2294
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002aad108
200
IDD(pd)
(μA)
1.95 V
1.8 V
1.65 V
160
120
80
40
0
-40
-15
10
35
60
temperature (°C)
85
Test conditions: Power-down mode entered executing code from on-chip flash.
Fig 12. Typical LPC2292/01 core power-down current IDD(pd) measured at different temperatures
002aad109
50.0
IDD(act)
(mA)
all peripherals enabled
all peripherals disabled
40.0
30.0
20.0
10.0
0.0
12
20
28
36
44
52
60
frequency (MHz)
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; core voltage 1.8 V.
Fig 13. Typical LPC2294/01 IDD(act) measured at different frequencies
LPC2292_2294
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002aad110
55.0
IDD(act)
(mA)
60 MHz
45.0
48 MHz
35.0
25.0
12 MHz
15.0
5.0
1.65
1.80
voltage (V)
1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; all peripherals enabled but not active.
Fig 14. Typical LPC2294/01 IDD(act) measured at different core voltages
002aad111
45.0
60 MHz
IDD(act)
(mA)
48 MHz
35.0
25.0
15.0
12 MHz
5.0
-40
-25
-10
5
20
35
50
65
80
95
110
125
temperature (°C)
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
core voltage 1.8 V; all peripherals disabled.
Fig 15. Typical LPC2294/01 IDD(act) measured at different temperatures
LPC2292_2294
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002aad112
15.0
IDD(idle)
(mA)
10.0
all peripherals enabled
5.0
all peripherals disabled
0.0
12
20
28
36
44
52
60
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; core voltage 1.8 V.
Fig 16. Typical LPC2294/01 IDD(idle) measured at different frequencies
002aad113
15.0
IDD(idle)
(mA)
60 MHz
10.0
48 MHz
5.0
12 MHz
0.0
1.65
1.80
voltage (V)
1.95
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; all peripherals enabled but not active.
Fig 17. Typical LPC2294/01 IDD(idle) measured at different core voltages
LPC2292_2294
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002aad114
6.50
IDD(idle)
(mA)
5.50
60 MHz
48 MHz
4.50
3.50
2.50
12 MHz
1.50
0.50
-40
-25
-10
5
20
35
50
65
80
95
110
125
temperature (°C)
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
core voltage 1.8 V; all peripherals disabled.
Fig 18. Typical LPC2294/01 IDD(idle) measured at different temperatures
002aad115
500
IDD(pd)
(μA)
1.95 V
1.8 V
400
1.65 V
300
200
100
0
-40
-25
-10
5
20
35
50
65
80
95
110
125
temperature (°C)
Test conditions: Power-down mode entered executing code from on-chip flash.
Fig 19. Typical LPC2294/01 core power-down current IDD(pd) measured at different temperatures
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002aad116
45.0
IDD(act)
(mA)
60 MHz
35.0
48 MHz
25.0
15.0
12 MHz
5.0
1.65
1.80
1.95
voltage (V)
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; all peripherals disabled.
Fig 20. Typical LPC2292/01 and LPC2294/01 IDD(act) measured at different core voltages
002aad117
10.0
IDD(idle)
(mA)
60 MHz
48 MHz
5.0
12 MHz
0.0
1.65
1.80
voltage (V)
1.95
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;
Tamb = 25 C; all peripherals disabled.
Fig 21. Typical LPC2292/01 and LPC2294/01 IDD(idle) measured at different core voltages
Table 9.
Typical LPC2292/01 peripheral power consumption in active mode
Core voltage 1.8 V; Tamb = 25 C; all measurements in A; PCLK = CCLK⁄4; all peripherals enabled.
LPC2292_2294
Product data sheet
Peripheral
CCLK = 12 MHz
CCLK = 48 MHz
CCLK = 60 MHz
Timer0
43
141
184
Timer1
46
150
180
UART0
98
320
398
UART1
103
351
421
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Table 9.
Typical LPC2292/01 peripheral power consumption in active mode …continued
Core voltage 1.8 V; Tamb = 25 C; all measurements in A; PCLK = CCLK⁄4; all peripherals enabled.
Peripheral
CCLK = 12 MHz
CCLK = 48 MHz
CCLK = 60 MHz
PWM0
103
341
407
I2C-bus
9
37
53
SPI0/1
6
27
29
RTC
16
55
78
PCEMC
306
994
1205
ADC
33
128
167
CAN1/2
229
771
914
Table 10. Typical LPC2294/01 peripheral power consumption in active mode
Core voltage 1.8 V; Tamb = 25 C; all measurements in A; PCLK = CCLK⁄4; all peripherals enabled.
Peripheral
CCLK = 12 MHz
CCLK = 48 MHz
CCLK = 60 MHz
Timer0
43
141
184
Timer1
46
150
180
UART0
98
320
398
UART1
103
351
421
PWM0
103
341
407
I2C-bus
9
37
53
SPI0/1
6
27
29
RTC
16
55
78
PCEMC
306
994
1205
ADC
33
128
167
CAN1/2/3/4
230
769
912
9. Dynamic characteristics
Table 11. Dynamic characteristics
Tamb = 40 C to +125 C; VDD(1V8), VDD(3V3) over specified ranges.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
oscillator frequency
supplied by an external
oscillator (signal generator)
1
-
25
MHz
external clock frequency
supplied by an external
crystal oscillator
1
-
25
MHz
external clock frequency if
on-chip PLL is used
10
-
25
MHz
external clock frequency if
on-chip bootloader is used
for initial code download
10
-
25
MHz
External clock
fosc
Tcy(clk)
clock cycle time
20
-
1000
ns
tCHCX
clock HIGH time
Tcy(clk)  0.4
-
-
ns
tCLCX
clock LOW time
Tcy(clk)  0.4
-
-
ns
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Table 11. Dynamic characteristics …continued
Tamb = 40 C to +125 C; VDD(1V8), VDD(3V3) over specified ranges.[1]
Symbol
Parameter
tCLCH
tCHCL
Conditions
Min
Typ
Max
Unit
clock rise time
-
-
5
ns
clock fall time
-
-
5
ns
Port pins (except P0[2] and P0[3])
tr
rise time
-
10
-
ns
tf
fall time
-
10
-
ns
-
ns
I2C-bus
pins (P0[2] and P0[3])
fall time
tf
VIH to VIL
[2]
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Bus capacitance Cb in pF, from 10 pF to 400 pF.
LPC2292_2294
Product data sheet
20 + 0.1  Cb -
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Table 12. External memory interface dynamic characteristics
CL = 25 pF, Tamb = 40 C
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Common to read and write cycles
tCHAV
XCLK HIGH to address valid
time
-
-
10
ns
tCHCSL
XCLK HIGH to CS LOW time
-
-
10
ns
tCHCSH
XCLK HIGH to CS HIGH
time
-
-
10
ns
tCHANV
XCLK HIGH to address
invalid time
-
-
10
ns
Read cycle parameters
tCSLAV
CS LOW to address valid
time
[1]
5
-
+10
ns
tOELAV
OE LOW to address valid
time
[1]
5
-
+10
ns
tCSLOEL
CS LOW to OE LOW time
5
-
+5
ns
(Tcy(CCLK)  (2 + WST1)) +
(20)
-
-
ns
tam
memory access time
[2][3]
tam(ibr)
memory access time (initial
burst-ROM)
[2][3]
(Tcy(CCLK)  (2 + WST1)) +
(20)
-
-
ns
tam(sbr)
memory access time
(subsequent burst-ROM)
[2][4]
Tcy(CCLK) + (20)
-
-
ns
th(D)
data input hold time
0
-
-
ns
tCSHOEH
CS HIGH to OE HIGH time
5
-
+5
ns
tOEHANV
OE HIGH to address invalid
time
5
-
+5
ns
tCHOEL
XCLK HIGH to OE LOW time
5
-
+5
ns
tCHOEH
XCLK HIGH to OE HIGH
time
5
-
+5
ns
Tcy(CCLK)  10
-
-
ns
[5]
Write cycle parameters
[1]
tAVCSL
address valid to CS LOW
time
tCSLDV
CS LOW to data valid time
5
-
+5
ns
tCSLWEL
CS LOW to WE LOW time
5
-
+5
ns
tCSLBLSL
CS LOW to BLS LOW time
5
-
+5
ns
tWELDV
WE LOW to data valid time
5
-
+5
ns
tCSLDV
CS LOW to data valid time
5
-
+5
ns
Tcy(CCLK)  (1 + WST2)  5
-
Tcy(CCLK)  (1 +
WST2) + 5
ns
tWELWEH
WE LOW to WE HIGH time
[2]
tBLSLBLSH
BLS LOW to BLS HIGH time
[2]
Tcy(CCLK)  (1 + WST2)  5
-
Tcy(CCLK) 
(1 + WST2) + 5
ns
tWEHANV
WE HIGH to address invalid
time
[2]
Tcy(CCLK)  5
-
Tcy(CCLK) + 5
ns
tWEHDNV
WE HIGH to data invalid time
[2]
(2  Tcy(CCLK))  5
-
(2  Tcy(CCLK)) + 5 ns
BLS HIGH to address invalid
time
[2]
Tcy(CCLK)  5
-
Tcy(CCLK) + 5
tBLSHANV
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Table 12. External memory interface dynamic characteristics …continued
CL = 25 pF, Tamb = 40 C
Symbol
Parameter
Conditions
[2]
Min
Typ Max
Unit
(2  Tcy(CCLK))  5
-
(2  Tcy(CCLK)) + 5 ns
tBLSHDNV
BLS HIGH to data invalid
time
tCHDV
XCLK HIGH to data valid
time
-
-
10
ns
tCHWEL
XCLK HIGH to WE LOW
time
-
-
10
ns
tCHBLSL
XCLK HIGH to BLS LOW
time
-
-
10
ns
tCHWEH
XCLK HIGH to WE HIGH
time
-
-
10
ns
tCHBLSH
XCLK HIGH to BLS HIGH
time
-
-
10
ns
tCHDNV
XCLK HIGH to data invalid
time
-
-
10
ns
[1]
Except on initial access, in which case the address is set up Tcy(CCLK) earlier.
[2]
Tcy(CCLK) = 1⁄CCLK.
[3]
Latest of address valid, CS LOW, OE LOW to data valid.
[4]
Address valid to data valid.
[5]
Earliest of CS HIGH, OE HIGH, address change to data invalid.
Table 13.
Standard read access specifications
Access cycle
Max frequency
WST[1] setting
Memory access time requirement
WST  0; round up to
integer
standard read
2 + WST1
f MAX  -------------------------------t RAM + 20 ns
t RAM + 20 ns
WST1  -------------------------------- – 2
t cy  CCLK 
t RAM  t cy  CCLK    2 + WST1  – 20 ns
standard write
1 + WST2
f MAX  ---------------------------------t WRITE + 5 ns
t WRITE – t CYC + 5
WST2  ------------------------------------------t cy  CCLK 
t WRITE  t cy  CCLK    1 + WST2  – 5 ns
burst read - initial
2 + WST1
f MAX  -------------------------------t INIT + 20 ns
t INIT + 20 ns
WST1  -------------------------------- – 2
t cy  CCLK 
t INIT  t cy  CCLK    2 + WST1  – 20 ns
burst read - subsequent 3
1
f MAX  --------------------------------t ROM + 20 ns
N/A
t ROM  t cy  CCLK  – 20 ns
[1]
See the LPC2119/2129/2194/2292/2294 User Manual for a description of the WSTn bits.
LPC2292_2294
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9.1 Timing
XCLK
tCSLAV
tCSHOEH
CS
addr
tam
th(D)
data
tCSLOEL
tOELAV
tOEHANV
OE
tCHOEL
tCHOEH
002aaa749
Fig 22. External memory read access
XCLK
tCSLDV
CS
tAVCSL
tCSLWEL
tWELWEH
tBLSLBLSH
BLS/WE
tWEHANV
tCSLBLSL
tWELDV
tBLSHANV
addr
tCSLDV
tWEHDNV
tBLSHDNV
data
OE
002aaa750
Fig 23. External memory write access
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tCHCL
tCHCX
tCLCH
tCLCX
Tcy(clk)
002aaa907
Fig 24. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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10. Package outline
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm
SOT486-1
c
y
X
A
73
72
108
109
ZE
e
E HE
A A2
(A 3)
A1
θ
wM
Lp
bp
L
pin 1 index
detail X
37
144
1
36
v M A
ZD
wM
bp
e
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
20.1
19.9
20.1
19.9
0.5
HD
HE
22.15 22.15
21.85 21.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.08
0.08
Z D(1) Z E(1)
1.4
1.1
1.4
1.1
θ
o
7
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT486-1
136E23
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-03-14
03-02-20
Fig 25. Package outline SOT486-1 (LQFP144)
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TFBGA144: plastic thin fine-pitch ball grid array package; 144 balls
A
B
D
SOT569-2
ball A1
index area
A
E
A2
A1
detail X
e1
e
∅v
∅w
b
N
M
L
K
J
H
G
F
E
D
C
B
A
ball A1
index area
M
M
C
C A B
C
y
y1 C
e
e2
1
2
3
5
4
6
7
8
9
10
11
12
13
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
max
nom
min
A
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
1.20
1.05
0.95
0.40
0.35
0.30
0.80
0.70
0.65
0.50
0.45
0.40
12.1
12.0
11.9
12.1
12.0
11.9
0.8
9.6
9.6
0.15
0.05
0.1
0.08
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
08-01-29
08-03-14
SOT569-2
Fig 26. Package outline SOT569-2 (TFBGA144)
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11. Abbreviations
Table 14.
LPC2292_2294
Product data sheet
Acronym list
Acronym
Description
ADC
Analog-to-Digital Converter
AHB
Advanced High-performance Bus
AMBA
Advanced Microcontroller Bus Architecture
APB
Advanced Peripheral Bus
CAN
Controller Area Network
CISC
Complex Instruction Set Computer
FIFO
First In, First Out
GPIO
General Purpose Input/Output
I/O
Input/Output
JTAG
Joint Test Action Group
LSB
Least Significant Bit
PLL
Phase-Locked Loop
PWM
Pulse Width Modulator
RISC
Reduced Instruction Set Computer
SPI
Serial Peripheral Interface
SRAM
Static Random Access Memory
SSI
Synchronous Serial Interface
SSP
Synchronous Serial Port
TTL
Transistor-Transistor Logic
UART
Universal Asynchronous Receiver/Transmitter
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12. Revision history
Table 15.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
LPC2292_2294 v.8
20110608
Product data sheet
201004021F
LPC2292_2294 v.7
Modifications:
LPC2292_2294 v.7
Modifications:
LPC2292_2294 v.6
Modifications:
•
Table 7 “Static characteristics”; Changed /01 Power-down mode supply current (IDD(pd))
from 180 A to 500 A for industrial temperature range, and 430 A to 1000 A for
extended temperature range.
•
Table 7 “Static characteristics”; Changed I2C pad hysteresis from 0.5VDD(3V3) to
0.05VDD(3V3).
20081204
Product data sheet
-
LPC2292_2294_6
•
•
Figure 1 “Block diagram”: corrected high-speed GPIO ports 48 pins; P0/P1 only.
•
Table 4 “Pin description”: pad descriptions corrected for pins P2[30], P2[31], P3[28], P3[30],
P3[31].
•
•
•
•
•
Table 5 “Interrupt sources”: CAN and UART0/1 interrupt sources corrected.
Figure 24 “External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)”:
removed figure note row “VDD = 1.8 V”, updated graphic.
Table 7 “Static characteristics”: Vhys, moved 0.4 from Typ to Min column.
Maximum frequency fosc for external oscillator and external crystal updated.
Changed SOT569-1 to SOT569-2.
Added overbar to indicate LOW-active for BLSn, CSn, OE, and WE
20071210
Product data sheet
-
LPC2292_2294_5
•
•
•
•
Type number LPC2292FBD144/01 has been added.
•
•
Power consumption measurements for LPC2292/2294/01 added.
Type number LPC2292FET144/01 has been added.
Type number LPC2294HBD144/01 has been added.
Details introduced with /01 devices on new peripherals/features (Fast I/O ports, SSP, CRP)
and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) added.
Description of JTAG pin TCK has been updated.
LPC2292_2294 v.5
20070215
Product data sheet
-
LPC2292_2294 v.4
LPC2292_2294 v.4
20060711
Product data sheet
-
LPC2292_2294 v.3
LPC2292_2294 v.3
20051101
Product data sheet
-
LPC2292_2294 v.2
LPC2292_2294 v.2
20041223
Product data
-
LPC2292_2294 v.1
LPC2292_2294 v.1
20040205
Preliminary data
-
-
LPC2292_2294
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13. Legal information
13.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
13.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
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representations or warranties, expressed or implied, as to the accuracy or
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In no event shall NXP Semiconductors be liable for any indirect, incidental,
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
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with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
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Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
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NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
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Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
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Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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15. Contents
1
2
2.1
2.2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.5
6.5.1
6.6
6.7
6.8
6.8.1
6.8.2
6.9
6.9.1
6.9.2
6.10
6.10.1
6.11
6.11.1
6.11.2
6.12
6.12.1
6.13
6.13.1
6.13.2
6.14
6.14.1
6.15
6.15.1
6.15.2
6.16
6.16.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Key features brought by LPC2292/2294/01
devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key features common for all devices . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional description . . . . . . . . . . . . . . . . . . 15
Architectural overview . . . . . . . . . . . . . . . . . . 15
On-chip flash program memory . . . . . . . . . . . 15
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 17
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 17
Pin connect block . . . . . . . . . . . . . . . . . . . . . . 18
External memory controller. . . . . . . . . . . . . . . 18
General purpose parallel I/O (GPIO)
and Fast I/O . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Features added with the Fast GPIO set of
registers available on LPC2292/2294/01 only 19
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ADC features available in LPC2292/2294/01
only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CAN controllers and acceptance filter . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
UART features available in LPC2292/2294/01
only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I2C-bus serial I/O controller . . . . . . . . . . . . . . 20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPI serial I/O controller. . . . . . . . . . . . . . . . . . 21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Features available in LPC2292/2294/01 only . 21
SSP controller (LPC2292/94/01 only). . . . . . . 22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
General purpose timers . . . . . . . . . . . . . . . . . 22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Features available in LPC2292/2294/01 only . 23
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 23
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.17
Real-time clock . . . . . . . . . . . . . . . . . . . . . . .
6.17.1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18
Pulse width modulator . . . . . . . . . . . . . . . . . .
6.18.1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19
System control . . . . . . . . . . . . . . . . . . . . . . . .
6.19.1
Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . .
6.19.2
PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19.3
Reset and wake-up timer . . . . . . . . . . . . . . . .
6.19.4
Code security (Code Read Protection - CRP)
6.19.5
External interrupt inputs . . . . . . . . . . . . . . . . .
6.19.6
Memory mapping control . . . . . . . . . . . . . . . .
6.19.7
Power control . . . . . . . . . . . . . . . . . . . . . . . . .
6.19.8
APB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20
Emulation and debugging . . . . . . . . . . . . . . .
6.20.1
EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . .
6.20.2
Embedded trace. . . . . . . . . . . . . . . . . . . . . . .
6.20.3
RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
8
Static characteristics . . . . . . . . . . . . . . . . . . .
8.1
Power consumption measurements for
LPC2292/01 and LPC2294/01 . . . . . . . . . . . .
9
Dynamic characteristics. . . . . . . . . . . . . . . . .
9.1
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
12
Revision history . . . . . . . . . . . . . . . . . . . . . . .
13
Legal information . . . . . . . . . . . . . . . . . . . . . .
13.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
13.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Contact information . . . . . . . . . . . . . . . . . . . .
15
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
24
24
25
25
25
25
26
26
26
27
27
27
27
28
28
29
30
34
42
46
48
50
51
52
52
52
52
53
53
54
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 8 June 2011
Document identifier: LPC2292_2294