The Essential Guide to Data conversion “Real-World” Sampled Data Systems Consist of ADCs and DACs ANALOG DIGITAL ADC SENSOR CHANNEL DSP g Converters (ADC) ( ) and Digital-to-Analog g Analog-to-Digital g g Converters ((DAC)) allow DSPs to interact with real-world signals. Real-world signals are continuous (analog) signals. MEMORY Pressure sensor Temperature sensor, sensor etc. etc Real-world signal processing allows for efficient and cost effective extraction of information from a signal. DIGIT TAL VALU UE ANALO OG AMPLITU UDE DAC TIME Signal amplitude Phase, etc. TIME ADC SAMPLED AND QUANTIZED WAVEFORM DAC RECONSTRUCTED WAVEFORM Digital information differs from real-world information in two important respects…it is sampled, and it is quantized. Both of these restrict how digital much h iinformation f ti a di it l signal i l can contain. t i Converter Resolution, INL, and DNL Converter resolution represents the analog signal at a number of discrete levels or steps. The smallest resolvable signal is 1 Least Significant Bit (LSB), which is equal to FS/8 in this example. IDEAL FS 7/8 Nonlinearity the maximum deviation LSBs, ffrom IIntegral t lN li it (INL) iis a measure off th i d i ti iin LSB a straight line passing through negative full-scale and positive full-scale. Good INL is required for open-loop systems and many closed-loop systems. 5/8 4/8 1 LSB 3/8 DNL ANALOG G ANALOG IDEAL INL 6/8 ACTUAL QUANTIZATION UNCERTAINTY 2/8 NON-MONOTONIC 1/8 000 001 010 011 100 101 110 000 001 010 011 100 101 110 111 111 A DAC is monotonic if its output increases or remains the same for an increment in the digital code, i.e., DNL > –1 LSB (a key requirement in a control system). Conversely, a DAC is nonmonotonic if the output decreases for an increment in the digital code. code An ADC has no missing codes if the input voltage is swept over the entire input range and all output code combinations appear at the converter output. A DNL error of > –0.99 LSB guarantees that the converter will have no missing codes. DIGITAL INPUT DIGITAL y ((DNL)) is the difference between the actual step p size and Differential Nonlinearity the ideal 1 LSB change between two adjacent codes. DNL error results in: Smaller or larger step sizes than the ideal Additive noise/spurs beyond the effects of quantization Converter Errors (Unipolar) POSITIVE GAIN ERROR NEGATIVE GAIN ERROR OUTPUT VOLTAGE ACTUAL IDEAL DAC Definitions GAIN AND OFFSET ERROR U FULL-SCALE SC ERROR Zero-Code Error is typically expressed in LSBs. DAC Offset Error is a measure of the difference between the actual VOUT and the ideal VOUT in the linear region of the transfer function. Offset error can be negative or positive in the DAC and output amplifier. OUTPUT VOLTAGE ACTUAL IDEAL ZERO-CODE ERROR POSITIVE OFFSET DAC CODE Zero-Code Error is the measured output voltage from VOUT of the DAC when zero code (all zeros) is loaded to the DAC register. Offset Error is typically expressed in mV or mA. mA DAC Gain Error is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal. Gain Error Ga o is s usua usually ye expressed p essed as a pe percentage ce tage o of tthe e full-scale u sca e range. a ge Full-Scale Error is a measure of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be VREF − 1 LSB. (Full-Scale Error = Offset Error + Gain Error) DAC CODE Full-Scale Error is typically expressed as a percentage of the full-scale range. GAIN AND OFFSET ERROR FULL-SCALE ERROR OUTPUT VOLTAGE ACTUAL IDEAL NEGATIVE OFFSET DEADBAND CODES AMPLIFIER FOOTROOM NEGATIVE OFFSET ZERO-CODE ERROR Deadband Errors, DACs with integrated output amplifiers will have performance degradation, deadbands, at codes outside of the linear region of the output amplifier. amplifier The number of deadband codes depends on the DAC output voltage span, the headroom and footroom of the amplifier, and the power supply rails used. ADC C Definitions e to s ADC Offset Error is the deviation of the first code transition, for example (000…000) to (000…001) from the ideal (AGND + 1 LSB). Offset error is typically expressed in LSBs. DAC CODE ADC Gain Error is the deviation of the last code transition, for example (111…110) to (111…111) from the ideal (VREF – 1 LSB) after the offset error is adjusted out. Gain error for an ADC does not include the reference error and is typically expressed in LSBs. www.analog.com/DataConverters The Essential Guide to Data conversion Time Domain DAC Output OVERSHOOT Clock to output delay Group delay due to DAC propagation delay GLITCH IMPULSE ENERGY CLOCK / DATA FEEDTHROUGH Settling time Measured relative to output signal alone Time between when signal leaves ±0.5 LSB error band to when it remains within ±0.5 LSB error band of final value NON-IDEAL RESPONSE DNL ERROR DAC ANALOG OUT TPUT SETTLING ERROR BAND IDEAL RESPONSE 1 LSB NONLINEAR SLEWING Slew rate Defined as maximum rate of change of voltage or current at output Specified as V/sec or A/sec depending on DAC output stage Typically measured for full-scale step size with 10% to 90% error band CLOCK / DATA FEEDTHROUGH CLOCK TO OUTPUT DELAY CODE = ZEROSCALE CODE = ZEROSCALE T1 CODE = MIDSCALE CODE = MIDSCALE T3 T2 CODE = MIDSCALE + 1 T4 TIME T5 Glitch impulse energy C Caused db by unequall propagation ti d delays l within ithi DAC Often measured for midscale LSB transition (011..111 to 100..000) Measured as “area” of glitch impulse with units p/nV-s or p/nA-s Frequency Domain DAC Output FULL-SCALE –x dB FROM FULL-SCALE (dBFS) –3.9dBc @ FDAC/2 FUNDAMENTAL SIGNAL SINC ATTENUATION DESIRED SIGNAL IMAGES Sinc(x) DAC’s time domain step response (zero-order hold) modifies DAC frequency response DAC output signals are attenuated by sin(π f/fdac)/(π f/fdac) envelope Harmonics Created by DAC’s static and dynamic nonlinearities AMPL ITUDE (dB) Amp plitude (dB) SFDR (dBc) 2nd AND 3rd HARMONICS DAC CLOCK FEEDTHROUGH DESIRED SIGNAL 2nd AND 3rd IMAGE HARMONICS NSD (dBm/Hz) FDAC/2 FDAC Frequency FREQUENCY g Images Duplicate of the desired signal (and its DAC induced harmonics) at higher Nyquist zones Images are predicted by sampling theory SFDR Measured with single-tone output in first Nyquist band (unit is dBc) Difference between single-tone g amplitude p to the next highest g spurious p tone Noise Spectral Density (NSD) Integration g of the noise floor in a small frequency q y band (unit ( is dBm/Hz or nV/rtHz) Nyquist’s Criteria AMP ITUDE AMPLITUDE NYQUIST ZONE 1 (BASEBAND) 0 Fs fa IMAGE FREQUENCY 0.5Fs NYQUIST ZONE 2 A signal with a maximum frequency fa must be sampled at a rate Fs > 2fa or information about the signal will be lost because of aliasing. aliasing Aliasing occurs whenever Fs < 2fa. NYQUIST ZONE 3 The concept p of aliasing g is widely y used in communications applications such as direct IF-to-digital conversion. fa NYQUIST ZONE 4 Undersampled analog signal fa sampled @ Fs has images 0.5, ((aliases) li ) att | ± KFs ± fa|, | K=0 5 1 1, 1 5… 1.5 1.5Fs A signal that has frequency components between fa and fb must be sampled at a rate Fs > 2 (fb – fa) in order to prevent alias components from overlapping the signal frequencies. 2Fs www.analog.com/DataConverters The Essential Guide to Data conversion Analog-to-Digital Converter AC Performance Specifications SNR (Signal-to-Noise Ratio, dB or dBFS) The ratio of the RMS value of the measured output signal (peak or full scale) to the RMS sum of all other spectral components excluding the first 6 harmonics and DC. FULL-SCALE (FS) ( ) INPUT SIGNAL LEVEL (CARRIER) RMS Signal = (FSR / 2) / √(2), RMS Noise = Qn = q / √(12) SNR (dB) = RMS Signal / RMS Noise = 20 × log(2(n – 1) × √6)) = 6.02 × n + 1.76 SFDR (dBFS) SFDR (dBc) dB SINAD (Signal-to-Noise Ratio and Distortion, dB) The ratio of the RMS signal amplitude to the RMS value of the sum of all other spectral components including harmonics, but excluding DC. SINAD (dB) = –20 × log (√(10(–SNR W/O DIST/10) + 10(THD/10))) ENOB (BITS) = (SINAD – 1.76 + 20 × log (FSR/Actual FSR)) / 6.02 WORST SPUR LEVEL THD (Total Harmonic Distortion, dBc) The ratio of the RMS sum of the first 6 harmonics to the RMS value of the measured fundamental. 6TH HAR/20))2 ) 2ND HAR/20))2 + (10((–3RD 3RD HAR/20))2 +… THD (–dB) ( dB) = 20 × log (√((10((–2ND + (10((–6TH SFDR (Spurious-Free Dynamic Range, dB or dBFS) 0, DC The ratio of the RMS value of the peak signal amplitude (or full-scale) to the RMS value of the amplitude of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. fs 2 FREQUENCY Oversampling Relaxes Requirements on Baseband Antialiasing Filter Oversampling Relaxes Requirements on Baseband Antialiasing Filter fa A B fa fs – fa Kfs – fa Generally an antialiasing filter is required on the analog front end of an ADC. If the sampling frequency is not much greater than the max input frequency fa, then the requirements on an antialiasing filter can be severe, as in (A). g indicate where the dynamic y range g can be limited by y signals g The dotted regions outside the bandwidth of interest. DR Oversampling relaxes the requirements of the analog antialiasing filter as shown in (B). Sigma delta converters are a good example. Sigma-delta example fs 2 fs STOPBAND ATTENUATION = DR TRANSITION BAND: fa to fs – fa CORNER FREQUENCY: fa Kfs 2 STOPBAND ATTENUATION = DR TRANSITION BAND: fa to Kfs – fa Kfs Outputs of DACs need filtering also, and these are called “anti-imaging” filters. They serve essentially the same purpose as the antialiasing filter ahead of an ADC. CORNER FREQUENCY: fa Theoretical SNR and ENOB Due to Jitter vs. Full-scale Sinewave Analog Input Frequency Theoretical SNR and ENOB Due to Jitter vs. Full-Scale Sine Wave A l Analog IInputt F Frequency 130 RMS JITTER 110 0.125 ps 100 0.5 ps 0.25 ps TOTAL JITTER = t j (RMS) SNR = 20log 10 1 2 π ft j The total amount of jitter is dependent on the effective aperture jitter within the converter, as well as the external jitter generated by the sampling clock circuit. 16 BITS 1 ps 90 2 ps 14 BITS 80 12 BITS 70 ENOB SNR IN dB S B 120 dV TOTAL JITTER = (ADC APERTURE JITTER) 2 + (SAMPLING CLOCK JITTER) 2 10 BITS 60 ERROR VOLTAGE 50 40 30 These terms are root sum squared to determine the total amount of jitter applied to the signal chain. 1 10 100 1000 FULL-SCALE ANALOG INPUT FREQUENCY IN MHz ENCODE dt www.analog.com/DataConverters In this example, if a 12-bit ENOB, 74 dB SNR is desired for the design with an analog MHz, then the total input frequency of 100 MHz jitter required must be 0.5 ps or less. The Essential Guide to Data conversion Analog Input/Output Configurations VIN UNIPOLAR SINGLE-ENDED FS 0V UNIPOLAR DIFFERENTIAL FS VIN+ VIN+ 0V + – −FS/2 VIN− Differential signals measure the difference in voltage between the positive and negative input terminals. The inputs are 180 degrees out of phase with each other. Many benefits in using differential inputs. inputs Vcm 1V Vcm = 1 VDC 0V BIPOLAR DIFFERENTIAL 1.5V VIN+ VIN– 1V p-p +FS/2 VIN BIPOLAR SINGLE-ENDED Single-ended signaling is most common. p Example: p Unipolar Differential VIN− Input transient reduction Input noise reduction Signal swing is doubled 1V p-p VIN– VIN +FS/2 0 5V 0.5V Pseudo differential is a single-ended/differential hybrid. 0V VIN+ Separation of signal ground from ADC ground for the ADC conversion −FS/2 VIN(adc) = VIN+ – VIN– = 2 V p-p Consider differential common-mode requirements VIN+ PSEUDO DIFFERENTIAL Consider ADC common-mode requirements Vcm = ((Vp q p + Vn)) / 2. The ADC converts VIN+ – VIN–. FS LOW DC INPUT VIN− 0V What Resolution Do I Need? Dynamic Range vs. Signal-to-Noise Ratio Requirements Dynamic Range (DR) is the difference in level between the highest signal y the system y peak that can be reproduced by and the amplitude of the highest spectral component of the noise floor. DR provides amplitude range so the converter can “see” the signal of interest. Converter DR is limited by SFDR and, theoretically, by its resolution. C Consider id using i analog l gain i tto iincrease DR capability bilit off th the system. t Si Signal-to-Noise lt N i R Ratio ti (SNR) iis th t th between the RMS the diff difference iin llevell b signal level and the RMS level of the noise floor, except the first six harmonics and DC. ADC FULL-SCALE (dBFS) 0 SNR limits li it the th capability bilit off the th converter to see “small” signals. ADC AAF DYNAMIC RANGE SIGNAL CHAIN FREQUENCY Effective Number of Bits (ENOB) is calculated from SNR: ENOB = (SNR – 1.76) / 6.02 (bits). FREQUENCY 74dB = 6.02N + 1.76dB = SNR 40 AM MPLITUDE (dB) VGA DYNAMIC RANGE AMPLITUDE AMPLITUDE Converter SNR is, theoretically, limited by its resolution. Quantization noise of an ideal ADC will have an SNR = 6.02N + 1.76 (dB), N = Number of bits. N = 12 BITS M = 4096 # OF FFT PTS FS = 245.76MSPS FS BIN SPACING = 4096 20 60 RMS QUANTIZATION NOISE LEVEL 80 74dB M 33dB = 10log 10 ( 2 ) = FFT NOISE FLOOR (PER BIN) 100 107dB 120 140 Example: 10-bit ADC with an FSR = 4 V p-p has an LSB = 3.9 mV p-p or 4/2BITS. Therefore, 4 V / 3.9 mV = 1024 codes. This can also be expressed in dB or 20 × log (1024) = 60 dB. FS 2 78 = 10log10(FS/2) = NOISE FLOOR (PER Hz) 152dB 160 Quantization: The Size of a Least Significant Bit (LSB) FREQUENCY (Hz) Converter Circuits DAC Amplifier Coupled Circuit 500Ω VDD AVDD RESOLUTION N 2N VOLTAGE (2 V/10 V FS) ppm FS % FS dBFS 2-bit 4 0.5/2.5 V 250,000 25 –12 4-bit 16 125/625 mV 62,500 6.25 –24 6-bit 64 31.3/156 mV 15,625 1.56 –36 8-bit 8 bit 256 7.8/39.1 mV 3906 0.39 –48 48 10-bit 1024 2/9.77 mV 977 0.098 –60 0.49/2.44 mV 244 0.024 –72 12-bit 4096 14-bit 16,384 122/610 µV 61 0.0061 16-bit 65,536 30.5/153 µV 15 0.0015 –96 18-bit 262,144 7.6/38 µV 4 0.0004 –108 20-bit 1,048,576 1.9/9.54 µV 1 0.0001 –120 22-bit 4,194,304 0.47/2.38 µV 0.24 0.000024 –132 24-bit 16,777,216 119/596 nV* 0.06 0.000006 –144 *600 nV is the Johnson Noise in a 10 kHz BW of a 2.2 kΩ resistor @ 25°C. –84 225Ω Ω IOUTB DAC AMP 225Ω IOUTA GND 25Ω COPT AVSS 25Ω 500Ω ROPT AVDD 1kΩ ADC Amplifier Coupled Circuit AMP-AVDD AVDD 205Ω 24Ω ANALOG INPUT 200Ω 62Ω 10kΩ 0.1µF +VS VOCM 10kΩ 200Ω G = UNITY –VS 27Ω Remember: 10 bits and 10 V FS yields an LSB of 10 mV, 1000 ppm, or 0.1%. (All other values may be calculated by powers of 2.) 10kΩ REQUIRED FOR UNBUFFERED ADC 10kΩ 24Ω 205Ω 0.1µF 1 F 0.1µF 0 33Ω VIN+ 2p DRVDD BUFFERED OR UNBUFFERED ADC R C ADC INTERNAL INPUT Z 33Ω VIN– VCM 0.1µF www.analog.com/DataConverters