MLX71121 300 to 930MHz FSK/FM/ASK Receiver Features ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Dual RF input for antenna space and frequency diversity, LNA cascading or differential feeding Fully integrated PLL-based synthesizer 2nd mixer with image rejection Reception of ASK or FSK modulated signals Wide operating voltage and temperature ranges Very low standby current consumption Low operating current consumption Internal IF filter Internal FSK demodulator Average or peak detection data slicer mode RSSI output with high dynamic range for RF level indication Output noise cancellation filter MCU clock output High over-all frequency accuracy 32-pin Quad Flat No-Lead Package (QFN) Ordering Information Part Number Temperature Code Package Code Delivery Form MLX71121 K (-40 °C to 125 °C) LQ (32 L QFN 5x5 Quad) 73 pc/tube 5000 pc/T&R LNAI1 VEE LNAO1 MIXP MIXN LNAO2 VEE LNAI2 bottom ROI DTAO CLKO IFSEL top MLX71121 RSSI CINT VCC PDN PDP SLC DFO DF1 VCC MIXO VEE IFAP IFAN MODSEL SLCSEL DF2 ! General digital and analog RF receivers at 300 to 930MHz ! Tire pressure monitoring systems (TPMS) ! Remote keyless entry (RKE) ! Low power telemetry systems ! Alarm and security systems ! Active RFID tags ! Remote controls ! Garage door openers ! Home and building automation Pin Description LNASEL RFSEL Application Examples General Description The MLX71121 is a multi-band, single-channel/dual-channel RF receiver based on a double-conversion super-heterodyne architecture. It can receive FSK and ASK modulated signals. The IC is designed for general purpose applications for example in the European bands at 433MHz and 868MHz or for similar applications in North America or Asia, e.g. at 315MHz or 915MHz. The receiver’s extended temperature and supply voltage ranges make the device a perfect fit for automotive or similar applications where harsh environmental conditions are expected. 39010 71121 Rev. 006 Page 1 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver Document Content 1 Theory of Operation ...................................................................................................4 1.1 General............................................................................................................................. 4 1.2 Technical Data Overview.................................................................................................. 4 1.3 Block Diagram .................................................................................................................. 5 1.4 Operating Modes .............................................................................................................. 6 1.5 LNA Selection................................................................................................................... 6 1.6 Mixer Section.................................................................................................................... 7 1.7 IF Filter ............................................................................................................................. 7 1.8 IF Amplifier ....................................................................................................................... 7 1.9 PLL Synthesizer ............................................................................................................... 7 1.10 Reference Oscillator ......................................................................................................... 8 1.11 Clock Output..................................................................................................................... 8 1.12 FSK Demodulator ............................................................................................................. 8 1.13 Baseband Data Path ........................................................................................................ 9 1.14 Data Filter ....................................................................................................................... 10 1.15 Data Slicer ...................................................................................................................... 10 1.15.1 1.15.2 1.16 2 Averaging Detection Mode..................................................................................................... 11 Peak Detection Mode ............................................................................................................. 11 Data Output and Noise Cancellation Filter ..................................................................... 12 Functional Description ............................................................................................13 2.1 Frequency Planning........................................................................................................ 13 2.2 Calculation of Frequency Settings.................................................................................. 14 2.3 Standard Frequency Plans ............................................................................................. 15 2.4 433/868MHz Frequency Diversity .................................................................................. 15 3 Pin Definitions and Descriptions ............................................................................16 4 Technical Data..........................................................................................................20 4.1 Absolute Maximum Ratings ............................................................................................ 20 4.2 Normal Operating Conditions ......................................................................................... 20 4.3 DC Characteristics.......................................................................................................... 21 4.4 AC System Characteristics ............................................................................................. 22 4.5 External Components ..................................................................................................... 23 39010 71121 Rev. 006 Page 2 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 5 Test Circuits .............................................................................................................24 5.1 Dual-Channel Application Circuit.................................................................................... 24 5.1.1 6 Test Circuit Component List of Figures 11 ................................................................................ 25 Package Description ................................................................................................26 6.1 Soldering Information ..................................................................................................... 26 7 Reliability Information .............................................................................................27 8 ESD Precautions ......................................................................................................27 9 Disclaimer .................................................................................................................28 39010 71121 Rev. 006 Page 3 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 1 Theory of Operation 1.1 General The MLX71121 receiver architecture is based on a double-conversion super-heterodyne approach. The two LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency is derived from a crystal (XTAL). As the first intermediate frequency (IF1) is very high, a reasonably high degree of image rejection is provided even without using an RF front-end filter. At applications asking for very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA. The second mixer MIX2 is an image-reject mixer. The receiver signal chain is setup by one (or two) low noise amplifier(s) (LNA1, LNA2), two down-conversion mixers (MIX1, MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by means of the positive and negative peak detectors (PKDET+/-). A digital post-processing of the sliced data signal can be performed by a noise cancellation filter (NCF) building block. The dual LNA configuration can be used for antenna space diversity or antenna frequency diversity or to setup an LNA cascade (to further improve the input sensitivity). The two LNAs can also be setup to feed the RF signal differentially. A sequencer circuit (SEQ) controls the timing during start-up. This is to reduce start-up time and to minimize power dissipation. A clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a microcontroller. The clock output is open drain and gets activated through a load connected to positive supply. 1.2 Technical Data Overview ! Input frequency ranges: 300 to 470MHz 610 to 930MHz ! Power supply range: 2.1 to 5.5V ! Temperature range: -40 to +125°C ! Shutdown current: 50 nA ! Operating current: 10.0 to 11.1mA ! FSK input sensitivity: -107dBm* (433MHz) ! ASK input sensitivity: -112dBm* (433MHz) ! Internal IF: 1.8MHz with 300kHz 3dB bandwidth ! FM/FSK deviation range: ±10kHz to ±100kHz ! Image rejection: st 65dB 1 IF (with external RF front-end filter) 25dB 2nd IF (internal image rejection) ! Maximum data rate: 50kps RZ (bi-phase) code, 100kps NRZ ! Spurious emission: < -54dBm ! Linear RSSI range: > 60dB ! Crystal reference frequency: 16 to 27MHz ! MCU clock frequency: 2.0 to 3.4MHz * at 4kbps NRZ, BER = 3⋅10-3, without SAW front-end-filter loss 39010 71121 Rev. 006 Page 4 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 24 14 2 LNA1 FSK MIX1 IFF MIX2 IFA LO2 FSK DEMOD SEQ BIAS 30 ENRX 26 PDN 21 OA2 DIV 8 CP 25 Fig. 1: PKDET_ SW2 RO LF 20 PFD VCO 31 TEST N2 counter 28 15 SLCSEL RFSEL N1 counter CLKO 7 ROI VEE 18 PDP 100k LNA2 PKDET+ 100k LO1 DFO SW1 32 8 100k OA1 100k LNASEL LNAI2 100k NCF DTAO 29 CINT 22 19 SLC 1 16 ASK VCC LNAI1 17 DF2 27 DF1 13 RSSI 12 IFSEL 11 VEE 10 MIXO 9 VCC 5 MIXN 4 MODSEL VEE 6 MIXP 3 LNAO2 Block Diagram LNAO1 1.3 23 MLX71121 block diagram The MLX71121 receiver IC consists of the following building blocks: • • • • • • • • • • • • • PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2. The PLL SYNTH consists of a fully integrated voltage-controlled oscillator (VCO), a distributed feedback divider chain (N1,N2), a phase-frequency detector (PFD) a charge pump (CP), a loop filter (LF) and a crystal-based reference oscillator (RO). Two low-noise amplifiers (LNA1, LNA2) for high-sensitivity RF signal reception First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency) Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF IF Filter (IFF) with a 1.8MHz center frequency and a 300kHz 3dB bandwidth IF amplifier (IFA) to provide a high voltage gain and an RSSI signal output FSK demodulator (FSK DEMOD) Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively Positive (PKDET+) and negative (PKDET-) peak detectors Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak detection mode. Noise cancellation filter (NCF) Sequencer circuit (SEQ) and biasing (BIAS) circuit Clock output (DIV8) 39010 71121 Rev. 006 Page 5 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 1.4 Operating Modes The receiver offers two operating modes selectable by setting the corresponding logic level at pin ENRX. ENRX Description 0 Shutdown mode 1 Receive mode Note: ENRX is pulled down internally. The receiver’s start-up procedure is controlled by a sequencer circuit. It performs the sequential activation of the different building blocks. It also initiates the pre-charging of the data filter and data slicer capacitors in order to reduce the overall start-up time and current consumption during the start-up phase. At ENRX = 0, the receiver is in shutdown mode and draws only a few nA. The bias system and the reference oscillator are activated after enabling the receiver by a positive edge at pin ENRX. The crystal oscillator (RO) is turned on first. Then the crystal oscillation amplitude builds up from noise. After reaching a certain amplitude level at pin ROI, the whole IC is activated and draws the full receive mode current consumption ICC. This event is used to start the pre-charging of the external data path capacitors. Pre-charging is finished after 5504 clock cycles. After that time the data output pin DTAO output is activated. ENRX ICC I RO ISDN valid data Hi-Z DTAO t on RO Hi-Z t SEQ t on RX Fig. 2: 1.5 Timing diagram of start-up and shutdown behavior LNA Selection The receiver features two identical LNAs. Each LNA is a cascode amplifier with a voltage gain of approximately 18dB. The actual gain depends on the antenna matching network at the inputs and the LC tank network between the LNA outputs and mixer input. LNA operation can be controlled by the LNASEL pin. LNASEL Description 0 LNA1 active, LNA2 shutdown Hi-Z LNA1 and LNA2 active 1 LNA1 shutdown, LNA2 active Pin LNASEL is internally pulled to VCC/2 during receive mode. Therefore both LNAs are active if LNASEL is left floating (Hi-Z state). 39010 71121 Rev. 006 Page 6 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 1.6 Mixer Section The mixer section consists of two mixers. Both are double-balanced mixers. The second mixer is built as an image rejection mixer. The first mixer’s inputs (MIXP and MIXN) are functionally the same. For single-ended drive, the unused input has to be tied to ground via a capacitor. A soft band-pass filter is placed between the mixers. RFSEL Description 0 Input frequency range 300 to 470MHz 1 Input frequency range 610 to 930MHz Pin RFSEL is used to select the required RF band. The LO frequencies and the proper sidebands for image suppression will be set accordingly. 1.7 IF Filter The MLX71121 comprises an internal IF filter with a -3dB bandwidth (B3dB) of 300kHz and a -40dB attenuation bandwidth (B40dB) of 1.4MHz. This filter contains three capacitively coupled biquad stages that represent resonant tanks at a filter center frequency (fcent) of 1.8MHz gain/dB 0 B 3dB -20 B 40dB -40 Fig. 3: IF filter tolerance scheme f IF2 f cent 1.8 IF Amplifier After having passed the IF filter, the signal is amplified by a high-gain limiting amplifier. It consists of several AC-coupled gain stages with a bandwidth of 400kHz to 11MHz. The overall small-signal pass-band gain is about 80dB. A received-signal-strength indicator (RSSI) signal is generated within the IF amplifier and is available at pin RSSI. 1.9 PLL Synthesizer The PLL synthesizer consists of a fully integrated voltage-controlled oscillator running at 400MHz to 640MHz, a distributed feedback divider chain, an edge-triggered phase-frequency detector, a charge pump, a loop filter and a crystal-based reference oscillator. The PLL is used for generating the LO signals. The LO1 is directly taken from the VCO output, and the LO2 is derived from the LO1 signal passing the N1 counter. Another counter N2 follows N1. The overall feedback divider ratio Ntot is fixed to 24. The values of N1 and N2 are depending on the selected RF band that can be chosen via pin RFSEL. RFSEL fLO1min [MHz] fLO1max [MHz] fLO2min [MHz] fLO2max [MHz] N1 N2 Ntot 0 400 640 100 160 4 6 24 1 400 640 200 320 2 12 24 39010 71121 Rev. 006 Page 7 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 1.10 Reference Oscillator A Colpitts crystal oscillator with integrated functional capacitors is used as the reference oscillator (RO) of the PLL synthesizer. The equivalent input capacitance CRO offered to the crystal at pin ROI is about 18pF. The crystal oscillator features an amplitude control loop. This is to assure a very stable frequency over the specified supply voltage and temperature range together with a short start-up time. A buffer amplifier with hysteresis is between RO and PFD. Also a clock divider follows the buffer. 1.11 Clock Output The clock output pin CKOUT is an open-drain output. For power saving reasons, the circuit is only active if an external pull-up resistor RCL is applied to the pin. Furthermore, RCL can be used to adjust the clock waveform. It forms an RC low-pass together with the capacitive load at the pin, the parasitics of the PCB and the input capacitance of the external circuitry (e.g. a microcontroller). The clock output feature is disabled if pin CKOUT is connected to ground or left open. VCC CLKO Control logic RO output RCL CL DIV8 Fig. 4: Clock output implementation 1.12 FSK Demodulator The integrated FSK demodulator is based on a phase-coincidence demodulator principle. An injectionlocked oscillator (ILO) is used as a frequency-dependent phase shifter. This topology features a good linearity of the frequency-phase relationship over the entire locking range. The type of demodulator has no built-in constraints regarding the modulation index. It also offers a wide carrier acceptance range. In addition, the demodulator provides an AFC loop for correcting the remaining free-running frequency error and drift effects, and also to remove possible frequency offsets between transmitter and receiver frequencies. The AFC loop features a dead band which means that the AFC loop is only closed if the demodulator output voltage leaves the linear region of the demodulator. Most of the time, the control loop is open. This leads to several advantages. The AFC loop bandwidth can be high and therefore the reaction time is short. Furthermore the demodulator itself has no low-end cut-off frequency. The FSK demodulator has a negative control slope, this means the output voltage decreases by increasing the IF2 frequency. This guarantees an overall positive slope because the mixer section converts the receive frequency to IF2 either with high-low or low-high side injection. The FSK demodulator is turned off during ASK demodulation. 39010 71121 Rev. 006 Page 8 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 1.13 Baseband Data Path The baseband data path can be divided into a data filter section and a data slicer section. DF1 MODSEL DF2 data filter ASK 100k FSK 100k DF0 OA1 SW1 data slicer PDP 100k PKDET+ S4 S1 100k SLC S2 PKDET _ S3 100k switches SLCSEL VCC S5 PDN S6 Fig. 5: OA2 Control logic Block diagram of the data path DTAO CINT The data filter input is either connected to the ASK or to the FSK demodulation output. Pin MODSEL can be used to set the internal switch SW1 accordingly. MODSEL Description 0 ASK demodulation 1 FSK demodulation For ASK demodulation, the RSSI signal of the IFA is used. During FSK demodulation, SW1 is connected to the FSK demodulator output. The SLCSEL pin is used to control the internal switches depending on operating and slicer mode. Pins DF1, DF2, DFO, SLC and DTAO are left floating during shutdown mode. So they are in a high-Z state. 39010 71121 Rev. 006 Page 9 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 1.14 Data Filter The data filter is formed by the operational amplifier OA1, two internal 100kΩ resistors and two external capacitors. It is implemented as a 2nd order Sallen-Key filter. The low pass filter characteristic rejects noise at higher frequencies and therefore leads to an increased sensitivity. CF1 CF2 DF1 DF2 data filter 100k 100k OA1 Fig. 6: DF0 Data filter The filter’s pole locations can be set by the external capacitors CF1 and CF2. The cut-off frequency fc has to be adjusted according to the transmission data rate R. It should be set to approximately 1.5 times the fastest expected data rate. For a Butterworth filter characteristic, the data filter capacitors can be calculated as follows. CF1 = 1 2 ⋅ π ⋅ 100k ⋅ f c CF2 = CF1 2 RRZ [kbit/s] RNRZ [kbit/s] fc [kHz] CF1 [pF] CF2 [pF] 0.6 1.2 0.9 2200 1000 1.2 2.4 1.8 1200 680 1.6 3.2 2.4 1000 470 2.4 4.8 3.6 680 330 3.3 6.6 5 470 220 4.8 9.6 7.2 330 150 6.0 12 9 220 100 1.15 Data Slicer The purpose of the data slicer is to convert the filtered data signal into a digital output. It can therefore be considered as an analog-to-digital converter. This is done by using the operational amplifier OA2 as a comparator that compares the data filter output with a threshold voltage. The threshold voltage can be derived in two different ways from the data signal. SLCSEL Description 0 Averaging detection mode 1 Peak detection mode 39010 71121 Rev. 006 Page 10 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver Averaging Detection Mode The simplest configuration is the averaging or RC integration method. Here an on-chip 100kΩ resistor together with an external slicer capacitor (CSL) are forming an RC low-pass filter. This way the threshold voltage automatically adjusts to the mean or average value of the analog input voltage. To create a stable threshold voltage, the cut-off frequency of the low pass has to be lower than the lowest signal frequency. τ AVG = 100k S4 S1 100k SLC S2 switches SLCSEL 1.5 R RZ PKDET _ S3 VCC CSL S5 PDN S6 A long string of zeros or ones, like in NRZ codes, can cause a drift of the threshold. That’s why a Manchester or other DC-free coding scheme works best. The peak detectors are disabled during averaging detection mode, and the output pins PDP and PDN are pulled to ground (S4, S6 are closed). OA2 Control logic DTAO CINT Fig. 7: Data path in averaging detection mode Peak Detection Mode Peak detection mode has a general advantage over averaging detection mode because of the part attack and slow release times. Peak detection should be used for all non DC-free codes like NRZ. In this configuration the threshold is generated by using the positive and negative peak detectors. The slicer comparator threshold is set to the midpoint between the high output and the low output of the data filter by an on-chip resistance divider. Two external capacitors (CP1, CP2) determine the release times for the positive and negative envelope. The two on-chip resistors provide a path for the capacitors to discharge. This allows the peak detectors to dynamically follow peak changes of the data filter output voltage. The attack times are very short due to the high peak detector load currents of about 500uA. The decay time constant mainly depends on the longest time period without bit polarity change. This corresponds to the maximum number of consecutive bits with the same polarity (NMAX). τ CP1/2 ≥ DECAY 100k τ DECAY PKDET+ data slicer data filter PDP S4 CP1 S1 100k SLC S2 switches SLCSEL PKDET _ S3 VCC 1.15.2 data filter 100k τ AVG 100k PDP 100k CSL ≥ data slicer PKDET+ 100k 1.15.1 VCC CP2 S5 PDN S6 OA2 Control logic DTAO CINT Fig. 8: Data path in peak detection mode N = MAX R NRZ If the receiver is in shutdown mode and peak detection mode is selected then the peak detectors are disabled and the output of the positive peak detector (PDP) is connected to VEE (S4 is closed) and the output of the negative peak detector (PDN) is connected to VCC (S5 is closed). This guarantees the correct biasing of CP1 and CP2 during start-up. 39010 71121 Rev. 006 Page 11 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 1.16 Data Output and Noise Cancellation Filter The data output pin DTAO delivers the demodulated data signal that can be further processed by a noise cancellation filter (NCF). The NCF can be disabled if pin CINT is connected to VEE. In this case the multiplexer (MUX) connects the receiver output DTAO directly to the data slicer output. MUX data slicer output DTAO Fig. 9: NCF Data output and noise filter CINT noise cancellation filter CF3 The noise cancellation filter can suppress random pulses in the data output which are shorter than tmin. CF3 = 15 ⋅ 10 -6 ⋅ t min = 15 ⋅ 10 −6 7.5 ⋅ 10 −6 = RNRZ RRZ The NCF can also operate as a muting circuit for RF input signals that are below sensitivity level if the bandwidth of the preceding data filter is selected much higher than the bandwidth of the NCF. This would be the case if no RF signal is present. In contrast to conventional muting (or squelch) circuits, this topology does not need the RSSI signal for level indication. The filtering process is done by means of an analogue integrator. The cut-off frequency of the NCF is set by the external capacitor connected to pin CINT. This capacitor CF3 should be set according to the maximum data rate. Below table provides some recommendations.. During receiver start-up a sequencer checks if pin CINT is connected to a capacitor or to ground. The maximum value of CF3 should not exceed 12nF. This defines the lowest data rate that can be processed if the noise cancellation filter is activated. RRZ [kbit/s] RNRZ [kbit/s] CF3[nF] 0.6 1.2 12 1.2 2.4 6.8 1.6 3.2 4.7 2.4 4.8 3.3 3.3 6.6 2.2 4.8 9.6 1.5 6.0 12 1.2 In shutdown mode pin DTAO is set to Hi-Z state. 39010 71121 Rev. 006 Page 12 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 2 Functional Description 2.1 Frequency Planning Because of the double conversion architecture that employs two mixers and two IF signals, there are four different combinations for injecting the LO1 and LO2 signals: • • • • receiving at fRF(high-high) receiving at fRF(high-low) receiving at fRF(low-high) receiving at fRF(low-low) LO1 high side and LO2 high side: LO1 high side and LO2 low side: LO1 low side and LO2 high side: LO1 low side and LO2 low side: As a result, four different radio frequencies (RFs) could yield one and the same second IF (IF2). Fig. 10 shows this for the case of receiving at fRF(high-high). In the example of Fig. 10, the image signals at fRF(lowhigh) and fRF(low-low) are suppressed by the bandpass characteristic provided by the RF front-end. The bandpass shape can be achieved either with a SAW filter (featuring just a couple of MHz bandwidth), or by the tank circuits at the LNA input and output (this typically yields 30 to 60MHz bandwidth). In any case, the high value of the first IF (IF1) helps to suppress the image signals at fRF(low-high) and fRF(low-low). The two remaining signals at IF1 resulting from fRF(high-high) and fRF(high-low) are entering the second mixer MIX2. This mixer features image rejection with so-called single-sideband (SSB) selection. This means either the upper or lower sideband of IF1 can be selected. In the example of Fig. 10, LO2 high-side injection has been chosen to select the IF2 signal resulting from fRF(high-high). f LO2 f RF f RF f LO2 f LO1 f RF f RF Fig. 10: The four receiving frequencies in a double conversion superhet receiver It can be seen from the block diagram of Fig. 1 that there is a fixed relationship between the LO signal frequencies (fLO1 , fLO2) and the reference oscillator frequency fRO. f LO1 = N 1 ⋅ f LO2 f LO2 = N 2 ⋅ f RO The operating frequency of the internal IF filter (IFF) and FSK demodulator (FSK DEMOD) are 1.8MHz. Therefore the second IF (IF2) is set to 1.8MHz as well. 39010 71121 Rev. 006 Page 13 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 2.2 Calculation of Frequency Settings The receiver has two predefined receive frequency plans which can be selected by the RFSEL control pin. Depending on the logic level of RFSEL pin the sideband selection of the second mixer and the counter settings for N1 and N2 are changed accordingly. RFSEL Injection fRFmin [MHz] fRFmax [MHz] N1 N2 0 high-low 300 470 4 6 1 low-high 610 930 2 12 The following table shows the relationships of several internal receiver frequencies for the two input frequency ranges. fRF [MHz] fIF1 fLO1 fLO2 fRO 300 to 470 f RF + N 1f IF2 N1 − 1 N 1 (f RF + f IF2 ) N1 − 1 f RF + f IF2 N1 − 1 f RF + f IF2 N 2 (N 1 − 1) 610 to 930 f RF − N 1f IF2 N1 + 1 N 1 (f RF + f IF2 ) N1 + 1 f RF + f IF2 N1 + 1 f RF + f IF2 N 2 (N 1 + 1) Given IF2 = 1.8MHz and the corresponding N1, N2 counter settings, above equations can be transferred into the following table. fRF [MHz] fIF1 fLO1 300 to 470 f RF + 7.2MHz 3 4(f RF + 1.8MHz ) 3 610 to 930 f RF − 3.6MHz 3 2(f RF + 1.8MHz ) 3 39010 71121 Rev. 006 Page 14 of 28 fLO2 f RF + 1.8MHz 3 fRO f RF + 1.8MHz 18 f RF + 1.8MHz 36 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 2.3 Standard Frequency Plans IF2 = 1.8MHz. RFSEL 0 1 2.4 fRF [MHz] fIF1 [MHz] fLO1 [MHz] fLO2 [MHz] fRO [MHz] 315 107.40 422.40 105.60 17.600000 433.92 147.04 580.96 145.24 24.206667 868.3 288.23 580.07 290.03 24.169444 915 303.80 611.20 305.60 25.466667 433/868MHz Frequency Diversity The receiver’s multi-band functionality can be used to operate at two different frequency bands just by changing the logic level at pin RFSEL and without changing the crystal. This feature is applicable for common use of the 433 and 868MHz bands. Below table shows the corresponding frequency plans. IF2 = 1.8MHz. RFSEL fRF [MHz] fIF1 [MHz] fLO1 [MHz] fLO2 [MHz] 0 433.25 146.82 580.07 145.02 1 868.3 288.23 580.07 290.03 39010 71121 Rev. 006 Page 15 of 28 fRO [MHz] 24.169444 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 3 Pin Definitions and Descriptions Pin No. 3 Name LNAO1 I/O Type Functional Schematic analog output LNAO1 Vbias Vbias LNAI1 analog input 1k LNAI1 LNA output 1 3 VCC 1 Description VEE LNA input 1 1 VEE ground 4 MIXP analog input 5 MIXN analog input negative supply voltage Vbias VCC MIXP MIXN 4 5 VEE 6 LNAO2 analog output LNAI2 analog input LNAO2 Vbias Vbias LNA output 2 6 1k LNAI2 MIX1 negative input VEE VCC 8 MIX1 positive input VCC 2k VEE 2k 2 VEE LNA input 2 8 VEE 7 VEE ground negative supply voltage 9 VCC supply positive supply voltage 10 MIXO analog output 11 VEE ground 12 IFAP analog input 13 IFAN analog input 14 MODSEL CMOS input not used pin left open mixer 2 output negative supply voltage IF amplifier positive input not used pins left open VCC VCC IF amplifier negative input modulation select input MODSEL 400 14 VEE 39010 71121 Rev. 006 VEE Page 16 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver Pin No. 15 Name SLCSEL I/O Type Functional Schematic CMOS input VCC Description slicer mode select input VCC SLCSEL 400 15 VEE VEE 16 DF2 analog I/O VCC VCC data filter connection 2 DF2 400 16 VEE analog I/O 100k DF1 VCC data filter connection 1 100k 17 DF1 400 17 VEE 18 DFO analog output VCC VCC data filter output DFO 400 18 VEE SLC analog input slicer reference input VCC 100k 19 SLC 400 100k 100k 19 VEE 20 PDP VCC analog output VCC peak detector positive output PDP 400 20 VEE 21 PDN analog output VCC peak detector negative output PDN 400 21 VEE 39010 71121 Rev. 006 Page 17 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver Pin No. Name I/O Type 22 VCC supply 23 CINT analog input Functional Schematic Description positive supply voltage capacitor for noise cancellation filter VCC pin must be connected to ground if noise cancellation filter is not used CINT 23 VEE 24 RSSI analog output receive signal strength indication VCC RSSI 400 51k 24 VEE VEE ROI analog input VCC reference oscillator input VCC 16k 25 ROI 25 VEE VEE 26 TEST CMOS input not used connect to ground 27 IFSEL CMOS input not used connect pin to ground 28 CLKO CMOS output test pin IF select input clock output VCC connect pull-up resistor to activate clock CLKO 28 VEE 29 DTAO VCC CMOS output VCC data output DTAO 220 29 VEE 30 ENRX CMOS input VCC VCC enable RX mode control ENRX 400 380k 30 VEE 39010 71121 Rev. 006 Page 18 of 28 VEE Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver Pin No. 31 Name RFSEL I/O Type Functional Schematic CMOS input VCC VCC Description receive frequency select input RFSEL 400 31 VEE LNASEL CMOS input LNA select input VCC 500k 32 VEE LNASEL 400 500k 32 VEE 39010 71121 Rev. 006 Page 19 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 4 4.1 Technical Data Absolute Maximum Ratings Operation beyond absolute maximum ratings may cause permanent damage of the device. Parameter Symbol Condition Min Max Unit Supply voltage VCC 0 7 V Input voltage VIN -0.3 VCC +0.3 V Storage temperature TSTG -55 150 °C Junction temperature TJ 150 °C Thermal Resistance RthJA 22 K/W Power dissipation Pdiss 0.12 W Electrostatic discharge VESD 4.2 HBM according to MIL STD 833D, method 3015.7 ±1 kV Normal Operating Conditions Parameter Symbol Supply voltage Operating temperature Input low voltage (CMOS) Input high voltage (CMOS) VCC TA VIL VIH Input frequency range fRF First IF range fIF1 LO1 range (VCO frequency) fLO1 LO2 range fLO2 XOSC frequency CLKO frequency FSK deviation fREF fCLK Data rate ASK RASK Data rate FSK 39010 71121 Rev. 006 Condition ENRX, SEL pins ENRX, SEL pins RFSEL=0 RFSEL=1 RFSEL=0 RFSEL=1 fLO1 = 24*fREF RFSEL=0, fLO2 = fLO1 / 4 RFSEL=1, fLO2 = fLO1 / 2 set by the crystal fCLK = fREF / 8 Δf RFSK bi-phase code NRZ bi-phase code NRZ Page 20 of 28 Min Max Unit 2.1 -40 5.5 125 0.3*VCC V 0.7*VCC 300 610 100 200 400 100 200 16 2.0 ±10 470 930 170 310 640 160 320 27 3.375 ±100 50 100 50 100 °C V V MHz MHz MHz MHz MHz MHz kHz kbps Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 4.3 DC Characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at TA= 23 °C and VCC = 3 V, all parameters based on test circuits as shown Fig. 11 to Fig. 12 Parameter Symbol Condition Min Typ Max Unit 50 200 nA 4 µA Operating Currents ENRX=0, TA = 85°C Shutdown current ISDN Supply current reference oscillator IRO ENRX=1, t < tonRO 1.5 mA Supply current, FSK IFSK ENRX=1, MODSEL=1 SLCSEL=0 LNASEL=0 or 1 10.2 mA Supply current, ASK IASK ENRX= 1, MODSEL= 0 SLCSEL=0 LNASEL=0 or 1 9.8 mA ENRX=0, TA = 125°C Digital Pin Characteristics (except of LNASEL) Input low voltage (CMOS) VIL ENRX, SEL pins Input high voltage (CMOS) VIH ENRX, SEL pins Pull down current ENRX pin IPDEN ENRX=1 Low level input current ENRX pin IINLEN High level input current Low level input current 0.3*VCC 0.7*VCC 2 V V 8 30 µA ENRX=0 1 µA IINHSEL SEL pins 1 µA IINLSEL SEL pins 1 µA Input voltage LNA1 active VLNASEL1 ENRX=1 0.1*VCC V Input voltage LNA2 active VLNASEL2 ENRX=1 LNASEL Pin Characteristics 0.9*VCC V DTAO Pin Characteristics Output low voltage VOL DTAO pin, ISINK = 600µA Output high voltage VOH DTAO pin, ISOURCE = 600µA 39010 71121 Rev. 006 Page 21 of 28 0.3*VCC 0.7*VCC V V Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 4.4 AC System Characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at TA= 23 °C and VCC = 3 V, all parameters based on test circuits as shown Fig. 11 Parameter Symbol Condition Min Typ Max Unit Receive Characteristics Input Sensitivity 1) MODSEL 315MHz FSK 433MHz 868MHz 915MHz 315MHz ASK 433MHz 868MHz 915MHz Pmin1 Pmin2 Pmin3 Pmin4 Pmin5 Pmin6 Pmin7 Pmin8 RFSEL -107 -107 -104 -102 -112 -112 -108 -105 0 1 1 0 0 1 dBm dBm Maximum input signal – FSK Pmax, FSK MODSEL=1 -10 dBm Maximum input signal – ASK Pmax, ASK MODSEL=0, M>20dB -10 dBm w/o SAW filter 20 25 dBm dB dB 18 dB 1.8 300 1.4 MHz kHz MHz Spurious emission Image rejection 1st IF Image rejection 2nd IF Pspur IR1 IR2 -54 LNA Parameters Voltage gain GLNA depends on external LC tank IF Filter Parameters Center frequency 3dB bandwidth 40dB bandwidth fcent B3dB B40dB IF Amplifier / RSSI Operating frequency RSSI dynamic range RSSI slope fIFA DRRSSI SRSSI 0.4 11 60 20 MHz dB mV/dB FSK Demodulator Input frequency range Carrier acceptance range fDEM ΔfDEM 1.8 ±80 Demodulator sensitivity SDEM 5 MHz kHz mV/ kHz 1) at 4kbps NRZ, BER ≤ 3⋅10-3, peak detector data slicer, LNASEL = 0 or 1 39010 71121 Rev. 006 Page 22 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver Parameter Symbol Condition Min Typ Max Unit 100 kHz Baseband Data Path Data filter bandwidth BDF Peak detector load current IPKD depending on CF1, CF2 500 µA Start-up Parameters Reference oscillator start-up time Sequencer time Receiver start-up time tonRO tSEQ tonRX depending on crystal parameters 5504 / fREF tonRO + tSEQ 200 350 650 µs 250 0.6 350 1 µs ms ±3 ppm/V Frequency Stability Frequency pulling by supply voltage 4.5 dfVCC External Components Parameter Symbol Condition Min Max Unit 16 10 27 15 5 60 MHz pF pF 12 nF 50 Ω pF Crystal Parameters Crystal frequency Load capacitance Static capacitance Series resistance f0 CL C0 R1 fundamental mode, AT Ω Noise Cancellation Filter Integrator capacitor CF3 depends on data rate Clock Output Pull-up resistor Load capacitance 39010 71121 Rev. 006 RCL 600 CL Page 23 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 5 Test Circuits 5.1 Dual-Channel Application Circuit • • for antenna-diversity applications for frequency-diversity applications FSK ASK VCC RCL CLKO ENRX RFSEL LNASEL output XTAL CB3 VCC C4 C5 ROI 25 VCC 22 IFAN MODSEL SLCSEL DF2 10 11 12 13 14 15 16 DF1 17 CF2 CB1 FSK ASK CP2 CB2 CP1 DFO 18 IFAP 9 C7 SLC 19 VEE VCC 8 CF3 PDP 20 32L QFN 5x5 6 LNAO2 LNAI2 PDN 21 MLX71121 MIXO 50 TEST 26 3 LNAO1 5 MIXN C9 IFSEL 27 CLKO 28 CINT 23 7 VEE L3 RSSI 24 2 VEE 4 MIXP C6 RSSI CRS CF1 VCC L2 1 LNAI1 DTAO 29 32 C3 ENRX 30 50 L1 RFSEL 31 CX C1 CB0 Fig. 11: Dual-channel circuit schematic, peak detectors activated 39010 71121 Rev. 006 Page 24 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver y 5.1.1 Part Test Circuit Component List of Figures 11 Size Value @ 315 MHz Value @ Value @ 433.92 MHz 868.3 MHz Value @ 915 MHz Tol. Description C1 0603 NIP NIP 3.3 pF 2.2 pF ±5% matching capacitor C3 0603 100 pF 100 pF 100 pF 100 pF ±5% LNA input filtering capacitor C4 0603 4.7 pF 3.9 pF 2.2 pF 1.8 pF ±5% LNA output tank capacitor C5 0603 100 pF 100 pF 100 pF 100 pF ±5% MIX1 positive input matching capacitor C6 0603 100 pF 100 pF 100 pF 100 pF ±5% MIX1 negative input matching capacitor C7 0603 NIP NIP 3.3 pF 2.2 pF ±5% matching capacitor C9 0603 100 pF 100 pF 100 pF 100 pF ±5% LNA input filtering capacitor CB0 0805 33 nF 33 nF 33 nF 33 nF ±10% decoupling capacitor CB1 0603 330 pF 330 pF 330 pF 330 pF ±10% decoupling capacitor CB2 0603 330 pF 330 pF 330 pF 330 pF ±10% decoupling capacitor CB3 0603 330 pF 330 pF 330 pF 330 pF ±10% decoupling capacitor CF1 0603 680 pF 680 pF 680 pF 680 pF ±10% data low-pass filter capacitor, for data rate of 4 kbps NRZ CF2 0603 330 pF 330 pF 330 pF 330 pF ±10% data low-pass filter capacitor, for data rate of 4 kbps NRZ CF3 0603 ±10% optional capacitor for noise cancellation filter CP1 0603 4.7 nF 4.7 nF 4.7 nF 4.7 nF ±10% positive PKDET capacitor, for data rate of 4 kbps NRZ CP2 0603 4.7 nF 4.7 nF 4.7 nF 4.7 nF ±10% negative PKDET capacitor, for data rate of 4 kbps NRZ CRS 0603 1 nF 1 nF 1 nF 1 nF ±10% RSSI output low pass capacitor, for data rate of 4 kbps NRZ CSL 0603 100 nF 100 nF 100 nF 100 nF ±10% data slicer capacitor, for data rate of 4 kbps NRZ CX 0603 27 pF 27 pF 12 pF 12 pF ±5% crystal series capacitor L1 0603 56 nH 27 nH 12 nH 12 nH ±5% matching inductor L2 0603 27 nH 15 nH 3.9 nH 3.3 nH ±5% LNA output tank inductor L3 0603 56 nH 27 nH 12 nH 12 nH ±5% matching inductor ±5% optional CLK output resistor, to clock output signal generated RCL 0603 XTAL SMD 5x3.2 Note: value according to the data rate connected to ground if noise filter not used for averaging detection mode only 10 kΩ 10 kΩ 10 kΩ 10 kΩ 17.60000 MHz 24.206667 MHz 24.169444 MHz 25.46667 MHz ±20ppm cal., ±30ppm temp. fundamental-mode crystal from Telcona, or equivalent part NIP – not in place, may be used optionally 39010 71121 Rev. 006 Page 25 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 6 Package Description The device MLX71121 is RoHS compliant. D A3 24 17 25 16 32 9 E A1 8 b 1 e A exp osed pad E2 L D2 The “exposed pad” is not connected to internal ground, it should not be connected to the PCB. Fig 13: 32L QFN 5x5 Quad all Dimension in mm min max D E D2 E2 A A1 A3 L e b 4.75 5.25 4.75 5.25 3.00 3.25 3.00 3.25 0.80 1.00 0 0.05 0.20 0.3 0.5 0.50 0.18 0.30 0.118 0.128 0.118 0.128 0.0315 0.0393 0 0.002 0.0079 0.0118 0.0197 0.0197 0.0071 0.0118 all Dimension in inch min max 6.1 0.187 0.207 0.187 0.207 Soldering Information • 39010 71121 Rev. 006 The device MLX71121 is qualified for MSL3 with soldering peak temperature 260 deg C according to JEDEC J-STD-20 Page 26 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 7 Reliability Information This Melexis device is classified and qualified regarding soldering technology, solderability and moisture sensitivity level, as defined in this specification, according to following test methods: Reflow Soldering SMD’s (Surface Mount Devices) • • IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2)” EIA/JEDEC JESD22-A113 “Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2)” Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices) • • EN60749-20 “Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat” EIA/JEDEC JESD22-B106 and EN60749-15 “Resistance to soldering temperature for through-hole mounted devices” Iron Soldering THD’s (Through Hole Devices) • EN60749-15 “Resistance to soldering temperature for through-hole mounted devices” Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices) • EIA/JEDEC JESD22-B102 and EN60749-21 “Solderability” For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of the Use of Certain Hazardous Substances) please visit the quality page on our website: http://www.melexis.com/quality_leadfree.aspx 8 ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. 39010 71121 Rev. 006 Page 27 of 28 Data Sheet Nov/07 MLX71121 300 to 930MHz FSK/FM/ASK Receiver 9 Disclaimer 1) The information included in this documentation is subject to Melexis intellectual and other property rights. Reproduction of information is permissible only if the information will not be altered and is accompanied by all associated conditions, limitations and notices. 2) Any use of the documentation without the prior written consent of Melexis other than the one set forth in clause 1 is an unfair and deceptive business practice. Melexis is not responsible or liable for such altered documentation. 3) The information furnished by Melexis in this documentation is provided ’as is’. Except as expressly warranted in any other applicable license agreement, Melexis disclaims all warranties either express, implied, statutory or otherwise including but not limited to the merchantability, fitness for a particular purpose, title and non-infringement with regard to the content of this documentation. 4) Notwithstanding the fact that Melexis endeavors to take care of the concept and content of this documentation, it may include technical or factual inaccuracies or typographical errors. Melexis disclaims any responsibility in connection herewith. 5) Melexis reserves the right to change the documentation, the specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. 6) Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the information in this documentation. 7) The product described in this documentation is intended for use in normal commercial applications. Applications requiring operation beyond ranges specified in this documentation, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. 8) Any supply of products by Melexis will be governed by the Melexis Terms of Sale, published on www.melexis.com. © Melexis NV. All rights reserved. For the latest version of this document, go to our website at: www.melexis.com Or for additional information contact Melexis Direct: Europe, Africa: Americas: Asia: Phone: +32 1367 0495 E-mail: [email protected] Phone: +1 603 223 2362 E-mail: [email protected] Phone: +32 1367 0495 E-mail: [email protected] ISO/TS 16949 and ISO14001 Certified 39010 71121 Rev. 006 Page 28 of 28 Data Sheet Nov/07