Peak Current Mode and Continuous Current Mode DC to DC Converter Modeling

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Peak Current Mode and Continuous
Current Mode DC-to-DC Converter
Modeling and Loop Compensation
Design Considerations
Van Yang,
Field Applications Engineer, Analog Devices, Inc.
Introduction
In many applications, such as computing, the power rail’s load transient
requirements are becoming more and more restrictive. Furthermore,
because it involves complex Laplace transfer function calculations, the
loop compensation design is often viewed as a difficult and time consuming task for many engineers.
L
RS
VO
RC
VIN
RL
CO
This article discusses, step by step, the average small signal modeling
of widely used peak current mode (PCM) and continuous current mode
(CCM) dc-to-dc converters. With the mathematical model, ADI’s ADIsimPE/
SIMPLIS, a switching circuit simulation tool is utilized to minimize the work
of complex calculations. Then a simplified model is shown for simpler and
faster loop compensation design and simulation. Finally, ADP2386EVAL
evaluation board test results are used to prove that the loop crossover
frequency, phase margin, and load transient response simulation results
were well matched with the test results.
Comp
R1
gm
PWM
R2
A (s)
VREF
PCM Average Small Signal Modeling
As Figure 1 shows, six blocks contribute to the current mode dc-to-dc
converter function: the feedback resistor divider, the compensator network, the current sensing and sampling, the comparator, the power stage,
and the output network. In the loop, the inductor current ramp signal is compared with the compensator error amplifier output, which feedbacks from
output voltage. The PWM signal is generated to drive the switches to modulate the inductor current. Inductor current flows into the output capacitor and
load. Out of these six blocks, the power stage is the only nonlinearized block
and it can be the most difficult block for dc-to-dc modeling.
Figure 1. Current-mode buck block diagram.
Modeling the power stage as a 3-terminal switch:
XX
Active switch mode (A)
XX
Common mode (C)
XX
Passive switch mode (P), as shown in Figure 2, we get the following
Equation 1:
iIN = iL d, VPC = vIN d ^ =^
^
iIN = ^iL D + ^
dIL, V
vIN D + ^
dVIN
PC
^
iL, i^IN,^d, ^
vIN, and ^
vPC
Visit analog.com
(1)
2
Peak Current Mode and Continuous Current Mode DC-to-DC Converter Modeling
and Loop Compensation Design Considerations
iIN = iL d, VPC = vIN d
iINaverage
= iL d, model,
VPC = only
vIN dvalid in continuous current mode, equivalent to
It’s an
a transformer with
turns
^ model
^ gets us^differential Equation 2:
^ ^ ratio^1:d. The
iIN = iL D^+ dI^
L, VPC = vIN D + dVIN
^
iIN = ^iL D + ^
dIL, VPC = vIN D + ^
dVIN (2)
^
^ ^^
i^
vIN, and ^
vPC have been employed into the
Small
signals
L, iIN, d, ^
^
^
^
iL, iIN
, d, vtoINbecome
, and vthe
PC average small signal model (ASSM). With
average
model
Comparator gain Fm is shown in Equation 5, Sn is the rising slope of induc1 slope compensation,
Vi – VOTs is the switch
VOperiod:
tor current, Se is the
Fm =
, Sn = V – V RT, Sf = V RT 1
i
O
(Se + Sn) Ts
L
LO
1
Fm =
, Sn = Vi – VO RT, Sf = VO RT
L
Fm = (Se + Sn) Ts , Sn =
RT, Sf = L RT
(Se + Sn) Ts
L
L
The gain function of the sampling effect is shown in Equation 6:
STs
s2
s
He(s) = STs ≈ s 22 + s + 1, wn = fs, Qn = – 2/
w
w
Q
eSTs
–
1
He(s) = STs ≈ s 2n2 + ns n + 1, wn = fs, Qn = – 2/ (6)
He(s) = eSTs – 1 ≈ w n2 + wnQn + 1, wn = fs, Qn = – 2/
eSTs – 1 w n wnQn
this model, the power stage can be linearized for analysis.
C
A
VIN × d
VIN
IL × d
C
R
1:D
P
Figure 2. Average small signal model for the 3-terminal switch.
Still using the PCM CCM buck as the example, the entire regulator has
been modeled into the Laplace transfer function block diagram, as shown
in Figure 3. There are two control loops: the voltage loop and the current
loop. In the current loop, inductor current is sensed by RT and sampled
into a ramp on the first negative input of the comparator. In the voltage
loop, output voltage ripple is sensed by the resistor divider with a gain of
K and sampled into the compensator network Av(s) as error voltage into
the comparator’s positive input. With the slope compensation ramp as the
second negative input signal, the comparator generates a regulated duty
cycle signal into the average small signal model of the power stage to
modulate the inductor current.
Vi
The gain function from input voltage to inductor current is shown in
Equation 7:
1
^
(SCO + R ) D i
L ^
(d = 0) = (SCO + 11 RO ) D
Gvi(s) = ^
iL ^
^
sL
O) D
Gvi(s) = ViINL (d
+ O + +Rs 2OLC
^= 0) = 1(SC
O
RsL
Gvi(s) = V^ (d = 0) =
O
1 + sL + s 22 LCO
IN
^
VIN
s LCO 8:
+ RO in+Equation
F
i (s) =loop
mG
di (s)H
e (s)R
The Tcurrent
gain
function
is1Tshown
Ti (s) = FmGdi (s)He (s)RT R O
Ti (s) = FmGdi (s)He (s)RT
The voltage loop gain function is shown in Equation 9:
Tv (s) = KAv (s)FmGdi (s)RO (s) Tv (s) = KAv (s)FmGdi (s)RO (s)
Tv (s) = KAv (s)FmGdi (s)RO (s)
Vc
+
iL
d
Fm
Gdi(s)
Vo
XX
Ro(s)
XX
–
He(s)
RT
(SC
(SCOORRCC ++ 1)
1) Ro
Ro SC
(RCC ++ RROO)) ++ 11
SCOO(R
LL
CC
FFmm==
T (s)
Secondly, design the compensator Av(s) to compensate the zeros and
poles of the open-loop gain Goc(s) to meet the loop gain design target.
(3)
An example is shown
in Figure 4 for the normal load condition when
R (s)
GOC (s) ≈
^
i^
VVinin (SC
iLL ^
(SCOORROO ++ 1)
1)
^
G
,, Gdidi(s)
(s)== ^ (V
(Vinin== 0)
0) ==
22
s
s
^
s
s
RROO 11 ++
dd
Qw
QwOO++ ww22
LC
High attenuation at high frequency for noise attenuation
^
GOC (s) v=comp
=1 + Ti (s)
vcomp
^
1 + Ti (s)
OO
11
VVii –– VVOO
VVOO
,, SSnn==
RRTT,, SSff ==
RRT
(Se
LL
LL T
(Se ++ Sn)
Sn) Ts
Ts
O
RO(s)
. In the low frequency domain, there are
He(s)RT
≈
Ti>>1, GOC (s)He(s)R
T
The gain function from PWM duty cycle to inductor current is shown in
Equation 4:
wwOO== ,, Q
Q==
LC
vO
FmGdi (s)RO
v
^
1 (s)R
+ TiO(s)
G
=mG
TvOC
(s)(s)
==
KAvcomp
(s)F
(s)O
v^
F1mdiG
O the
^
+diT(s)R
–20
slope
near
frequency
for higher phase margin
comp
i (s)
TdBv(s)
(s)
(s)F
G
GOC
==vKAv
= crossover
m di (s)R
O (s)
vcomp
^
1 + Ti (s)
(>45°)
GOCloop
(s) =bandwidth
v^O =for
Gditransient
(s)RO response
Fmfast
Wide
He(s)RT
The gain function from inductor current to output voltage is shown in
Equation 3:
RR
High dc loop gain
^ for low dc error
v^O ^ FmGdi (s)RO
GOC (s) =
vO= FmGdi (s)R
(11)
O
Figure 3. PCM CCM dc-to-dc control model block diagram.
11
(9)
vloop, only the compensator Av(s) and the feedback resistor
In a Tregulator
=
(s)
TR
O(s)
1
+
Tiv(s)
T
=
divider
K
are
GOC (s) 1≈customized
(s) by the designer. So in the loop design, two steps
R
O(s)
+
T
i
He(s)R
T
GOC (s) ≈Firstly,
are included.
disconnect
the resistor divider with the output to get
RO(s)
He(s)R
T
GOC (s) ≈gain,
the open-loop
as shown
in Equation 11:
K
Ro(s)
Ro(s)==
(8)
Tv (s)
(10)
T = Tv (s)
1
+
T
(s)
i
T = Tv (s)
(s)di (s)He (s)RT
(s)1=+FTmiG
Ti=
(s)
+=
Tconsiderations
iF
There are
four
theT dc-to-dc loop gain design target:
T1i (s)
(s)R
mGdi (s)Hefor
XX
Gvi(s)
(7)
The loop gain function is shown in Equation 10:
XX
Av(s)
(5)
(4)
one pole (1/2πRoCo) and one zero (1/2πRcCo) and one 2-order pole
(1/πfs) in the high frequency domain caused by the sampling effect
He(s). Compensator Av(s) is designed to enlarge the crossover frequency,
ensure a −20 dB slope near the crossover point, and to get more than
a 45° phase margin. The compensator has two poles and one zero; one pole
is used to compensate the open-loop gain capacitor ESR zero, the other
pole functions as an integrator to increase the loop dc gain, and the zero
pole compensates the open-loop load effect. The second-order pole at
high frequency (1/πfs) is beneficial for noise attenuation.
Visit analog.com Av (s)
The ADsimPE tool, powered by SIMetrix/SIMPLIS, is a personal edition circuit simulator ideally suited to evaluate linear and switching components
from Analog Devices. SIMetrix is very useful for linear circuits like op
amps, and SIMPLIS is targeted for switching components such as dc-to-dc
converters and PLLs. In Figure 5, a PCM CCM buck reference circuit has
been setup as the reference to check circuit behavior and model accuracy.
It’s a PCM sync buck regulator with 3.3 V input, 1.2 V output, and 1.2 MHz
switching frequency.
Integrator
One Zero
One Pole
Goc (s)
| T (s) |
<T (s)
As Figure 6 shows, in the left loop gain calculation results of the average
small signal model, the crossover frequency is 50 kHz and the phase margin is 90.35°. The SIMPLIS simulation result, as seen on the right side of
Figure 6, shows a 90.8° phase margin at a 47.6 kHz crossover frequency.
This proves that the ADIsimPE/SIMPLIS switching circuit simulation result
is matched with the complex ASSM calculation, which offers the designer
a fast way for loop design. However, the schematic, as shown in Figure 5,
is not very simple.
–90°
–180°
Figure 4. PCM CCM dc-to-dc loop design steps.
X1
Ideal
D4
S
+
IN
LG_IN
Current Sensing
40 m
H1
150 m
LG_OUT
200 1.5 µF IC = 1.2
C6
Ideal
D1
S2
E1
1
I3-pos
° L1
+
+
1.2 kΩ
R1
5m
R9
LG_IN
5
V6
0.6
V3
V4
QN
Q
D2
Ideal
1 kΩ
+
U2
U5
36 kΩ
R2
1.5 n
C1
6.8 pf
C2
PWM
U7
500 u
V2
R8
60 pF IC = 0
C4
D3
10 kΩ
R6
R
S
Slope Compensation
+
U3
10 kΩ
R10
G1
10 kΩ
R3
Ideal
1 kΩ
R5
60 pF IC = 0
C3
47.63999k
Y4
120
Y1
47.82854k
189.65782
90.803528
60
80
50
100
40
30
60
40
20
10
0
20
Gain (dB)
Phase (°)
60
Phase (°)
80
Gain (dB)
Gain and Phase Margin
10 kΩ
R4
Type II Compensator
Figure 5. PCM CCM buck SIMPLIS reference circuit.
–91.03286
40
20
–229.331m
0
–10
0
–20
+ AC 1
V5
1.1
V7
U4
LG_OUT
1.5 µF IC = 100 m
R7
3.3
V1
OUT
= OUT/IN
–20
20
–30
1
100
Frequency (Hz)
10k
Figure 6. ASSM calculation result and SIMPLIS simulation result.
100 200
500
1k
2k
5k 10k 20k 50k 100k 200k 500k 1M
Frequency (Hz)
Ref
3
VIN Mode
RO Continuous
+ 1)
VINCurrent Mode DC-to-DC Converter Modeling
(SCOand
Peak Current
≈
, wO =
Gdi(s) =
2
s 2 Considerations
and Loop R
Compensation
sL
O 1+ s
+Design
wO
QwO
R
1 Simplified
PCM
Average Small Signal Modeling
, Q=
LCO
Considering
And crossover frequency is much bigger than 1√LCo, therefore, the openloop gain function in Equation 13 could be further simplified as Equation 14:
L
theC crossover
O
frequency is much bigger than 1√LCo in the
application, an estimation could be performed for the complicated equations. For Equation 4, the gain function from PWM duty to inductor current,
could be simplified, as shown in Equation 12:
H(s) =
VIN
VIN
(SCORO + 1)
≈ VIN , wO =
Gdi(s) = VIN
(SCORO + 1)
2
RO 1 + s
F sGdi(s)
Gdi(s)iL= ^
2 ≈ sL , wO =
QwO + ms 2 w
R
H(s)
sL ≈
O2
+ =s1Qw
+
= Vc (VINO =10)
w
+ FOmGdi (s)H
O e(s)Rs
R
1
(12)
1 , Q = RL
1 LC
1
O, Q =
=
s2
RT LCO TsL(SCCLOn + Se) – Ts
1+S
+ 2
2
VINORT
From Figure 3, we could get the open-loop
T s2 gain function, which is compensator
output 1voltage to inductor current, as shown in Equation 13:
1
,
iLTs(S^n + Se) Ts FsmGdi(s)
RT
–
≈
H(s)
= iL (V^IN = 0) = + F2mGdi(s)
1 + sL
V L(S + Sf) =12L
+ FmGLdi (s)He(s)Rs ≈
H(s) = Vcc (VnIN = 0)
2
1 + FmTGsdi (s)He(s)Rs
1
1
1 Vi – VO T L(S +VSO1 ) T
2 =
T
Sn R
Sf n=+ Se)RT– Ts + ss 2 =
RTTs,L(S
=
1
+
S
RT L
s V n R Le
IN T
– 2s + 22
1+S
VIN RT
2
T s22
Ts
(13)
1
1
,
1
1
RT
Ts(Sn + Se) Ts
s ,
RT 1 + sL Ts(Sn + Se) – T
s + s2L
2L
L(S
+
S
)
–
+
n
f
1 + sL
L(Sn + Sf) 2L T2s2L
T s2
Vi – VO
VO
Sn = Vi – VO RT , Sf = VO RT
Sn = L RT , Sf = L RT
L
L
The result is that the open-loop ASSM could be simplified, as shown in
Figure 7, into a compensator output voltage controlled current source
flowing into an RLC network generating inductor current. This is a much
easier model to use for simulation or calculations than the original complicated equations.
L
iL
Ce
Vc/Ri
Re
C
R
Figure 7. Simplified ASSM open-loop circuit.
Using the Figure 5 reference circuit, calculate Re and Ce, then set up the
closed-loop simplified ASSM circuit in ADSimPE, as shown in Figure 8.
The SIMetrix simulation result is shown in the right half of Figure 8 with
the crossover frequency as 49 kHz and the phase margin is 90.5°, which
matches the ASSM calculation result and the SIMPLIS simulation result
shown in Section 2.
2L
Sf – Se ,
T2
, Ce = 2sL , α =
2
Se + Sn
Ts 1 + α – 1
LG_IN
IN
OUT
= OUT/IN
LG_OUT
LG_OUT
1.5 µF 2
sns
2L
Sf – Se
T s2
||C
Re1 = 1
2L 1 , Ce =
° L1 T2s 1, α =Re
– e(s)
Se
L
H(s)
= , α = SSefRo
2
+
SsL
Re=
=R
, sR
Cee=
n
1
+
C
2
R
||C
+
R
e
–
1
L
T e See + S
2+ α
TsT 1 +
150 m
n
sL
–
1
C3
2.64
+
200
µF
Re
Ts 1 + α
R6
(14)
1
Re||Ce
RT Re||Ce + sL + RO||CO
Se is the slope of the compensation slope’s positive edge. Take
Re =
1
1
1
Re||Ce
=
≈
RT 1 + sL 1 + sReCe RT Re||Ce + sL
Re
46.9 n
R5
1
Re||Ce
H (s)
RT Re||Ce + sL + RO||CO
C6
5m
R9
Y3
≈
1.2
R1
+ AC 1
V5
90
50
80
1
1
1
Re||Ce
H(s) = 1
= 1
1
Re||Ce ≈
0.6
H(s) = RT 1 + sL 1 + sReCe = RT Re||Ce + sL ≈
C RT Re||Ce + sL V3
RT 1 + sL 1 + RsR
ee e
500 µF
E1
Re
1
Re||Ce
Type II Compensator
1
Re||Ce
+ RO||CO
RT Re||Ce + sL
36 kΩ
G1
1
R2
RT Re||Ce + sL
+ RO||CO
6.8 pF
C2
Figure 8. Simplified ASSM simulation circuit and result.
1.5 n
C1
20
10
0
10 kΩ
R4
70
40
30
LG_IN
Y2
60
–10
–20
Phase (°)
4
Gain (dB)
60
50
40
30
20
10
100 200 400
10 kΩ
R3
1k
2k
4k
10k 20k 40k
Frequency (Hz)
100k 200k 400k
1m
Visit analog.com ADP2386 Modeling Simulation and Test Result
Figure 9 shows the schematic diagram of the ADP2386EVAL. For testing, the
board is set up under the conditions as shown in Table 1, row 1, below.
The internal slope compensation of the ADP2386 is adaptive with duty
0.6 fs
cycle, Se =
, and Equation 14 was used to get the simplified
2.5 (1 – D)
ASSM parameters as shown in Table 1, row 2. The output capacitor’s dc
bias spec drops about 30% at 3.3 V, so in the simplified ASSM simulation
the output capacitor value has been changed to 100 μF, not the 147 μF in
the evaluation board.
The ADP2386 is a synchronous PCM CCM buck regulator from
Analog Devices. It ranges from 20 V input voltage down to 0.6 V output
voltage at up to 6 A output current, with switching frequency ranges from
200 kHz to 1.2 MHz. The device’s versatility allows it to be used in stepdown applications and inverting buck-boost topologies without additional
cost and size. In this section, the ADP2386EVAL evaluation board will be
utilized to verify the model simulation results. Two tests are compared:
a loop test and a load transient test.
Table 1. ADP2386EVAL Test Condition and Simplified ASSM Parameters
VIN
12 V
VO
FS
IO
L
C
Compensator
3.3 V
600 kHz
3A
2.2 μH
147 μF/5 Ω
44.2 kΩ, 1.2 n, 4.7 p
Se
Sn
Sf
Re
Ce
Gm
0.2 V/μs
0.49 V/μs
0.18 V/μs
2.51 Ω
128 nF
580 μS
RT
123 mΩ
J2
VREG
J1
SYNC
1
J4
1
GND
J5
J3
PWG
1
1
1
R1
NC
GND
R2
100 kΩ
1 J6
2
3
EN
100 kΩ
R3
NC
C2
4.7 pF
J13
GND
J15
1
J11
SW
C12
NC
SW
2
1
GND
Figure 9. ADP2386EVAL schematic.
EN
PVIN4
PGOOD
RT
7
8
9 10 11 12
PGND6
EXP
1
17
J8
VIN
16
15
14
13
25
SW
C6
0.1 µF
C7
C8
10 µF/25 V
6 SW2
26 E_SW
18
10 µF/25 V
R9
NC
PGND5
1
BST
SW4
PGND4
C10 C11
SYNC
SS
2.2 µH
C9
PVIN3
PVIN1
ADP2386
4 GND
5 SW1
2
J7
VIN
PVIN2
VREG
PGND3
L1
3
PGND2
1
1 COMP
2 FB
PGND1
2
C4
NC
R8
NC
NC
VOUT
1
C5 1 µF
100 µF/6.3 V
VOUT
J10
1
47 µF/6.3 V
J9
R7
10 kΩ
2
1
U1 24 23 22 21 20 19
C3
R6
1200 pF 44.2 kΩ
SW3
R5
2.21 kΩ
R4
C1
22 nF
1
J12
GND
2
1
J14
GND
VIN = 12 V, VOUT = 3.3 V, IOUT = 6 A, fSW = 600 kHz
5
Peak Current Mode and Continuous Current Mode DC-to-DC Converter Modeling
and Loop Compensation Design Considerations
Figure 10 reveals the ADP2386EVAL loop simplified ASSM simulation and
test results. The left side is the simulation by ADIsimPD/SIMetrix—the
crossover frequency is 57 kHz, the phase margin is 71°. The right side is
the test result under AP model 300—the crossover frequency is 68.7 kHz
and the phase margin is 59.3°. Although there is a difference between
test results and model simulation, we know from the ADP2386’s data
sheet that its error amplifier gain is varying from 380 μS to 580 μS,
coupled with the inaccuracy of the inductor and output capacitor. So this
difference between the two results is acceptable.
For the load transient test, two tests are included. Test 1 is a test under
Table 1 compensator conditions with good phase margin and wide
crossover frequency. Test 2 is a test with the compensator changed to
100 pF/1.2 nF/44.2 kΩ, in which the crossover frequency is down to
39 kHz and phase margin down to 36°. Figure 11 shows the load transient
(0.5 A to 3 A, 0.2 A/μs) Test 1 simulation and test result. Overshoot peak is
tested to be 67 mV and the simulation result is 59 mV, with the transient
curves being well matched. Figure 12 shows the load transient (0.5 A to
3 A, 0.2 A/μs) Test 2 simulation and test result. The overshoot peak is
tested to be 109 mV and the simulation result is 86 mV, again with the
transient curves being very well matched.
Mag[B/A] (dB)
Y4
Y2
40
60
30
20
10
0
40
Phase (°)
20
–10
0
–20
–20
–30
1k
2k
4k
10 k
20 k 40 k
100 k 200 k 400 k
Frequency (Hz)
50.000
250.000
40.000
200.000
30.000
150.000
20.000
100.000
10.000
50.000
0.000
0.000
–10.000
–50.000
–20.000
–100.000
–30.000
–150.000
–40.000
–200.000
–50.000
1M
10 kHz
100 kHz
M1
68.77 kHz
0.037 dB
59.309 deg
M2
663.61 kHz
–37.592 dB
–98.896 deg
–250.000
2
1 MHz
M2–M1
594.84 kHz
–37.629 dB
–158.205 deg
T
TEK
999.5584 µs
a
b
1.0
0.5
0
Vo/V
–0.5
Y1
4
BW
4 1.00 A
20.0 µs
T
0.00000 s
500 M
100 k
4
1.015175 mS
15.61679 µs
1.5
I (R1-P)/A
–2.00 µs a –1.000 mV
11.20 µs b –68.00 mV
∆13.20 µs ∆67.00 mV
1 50.0 mV
1
1 kHz
Figure 10. ADP2386EVAL loop simulation and test results.
1
Phase [B/A] (°)
Data
Frequency
Magnitude
Phase
0.80
Time (m/s)
0.85
0.90
0.95
1.00
Ref A
1.05
1.10
1.15
1.20
1.25
5 µs/Div
3.3149321
3.32
3.31
3.30
3.29
3.28
3.27
3.26
–59.3893 mV
3.2555428
0.80
1.02 A
0.85
0.90
0.95
1.00
Time (m/s)
1.05
1.10
1.15
1.20
1.25
5 µs/Div
Ref A
Figure 11. ADP2386EVAL load transient Test 1 simulation and test results.
T
TEK
999.8218 µs
1
a
b
1 50.0 mV
1.0
0.5
0
–0.5
Y1
4
BW
4 1.00 A
20.0 µs
T
0.00000 s
500 M
100 k
4
1.02 A
1.014588 mS
14.6656µs
1.5
I (R1-P)/A
–2.000 µs a –1.000 mV
9.600 µs b –110.0 mV
∆11.60 µs ∆109.0 mV
Vo/V
6
Gain (dB)
0.80
0.85
Time (m/s)
0.90
0.95
1.00
Ref A
1.05
1.10
1.15
5 µs/Div
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.3149321
–86.2197 mV
3.2287124
0.80
0.85
Time (m/s)
Figure 12. ADP2386EVAL load transient Test 2 simulation and test results.
0.90
0.95
1.00
Ref A
1.05
1.10
1.15
5 µs/Div
Visit analog.com Conclusion
Loop compensation is often viewed as a very challenging design task
by engineers, especially in fast load transient applications. Based on the
widely used peak current control mode continous current buck device,
this article has summarized the average small signal mathmatical modeling and loop calculation, and the ADISimPE/Simplis fast and easy simulation technique. It also introduced a simplified average small signal model
and offered a simplified way of handling loop compensation design. The
ADP2386EVAL evaluation board loop and load transient bench test results
proved the accuracy of the simplified model and its simulation.
About the Author
Van Yang [[email protected]] is a field applications engineer
at Analog Devices. Inc., in Shanghai, China. He joined ADI in 2015
to support regional medical and industrial customers in China.
Prior to joining ADI, Van worked at Texas Instruments as an FAE
for four years. Van earned his master’s degree in communication
and information systems from Huazhong University of Science and
Technology in Wuhan, in 2011. In his spare time he is a super fan
of basketball and enjoys hiking.
References
1
ADP2386 Data Sheet.
2
ADP2386EVAL User Guider.
3
Brad Brand and Marian K. Kazimierczuk.“Sample and Hold Effect in PWM
DC-to-DC Converters with Peak Current Mode Control.” 0-7803-8251-X
10.1109/ISCAS.2004.1329944 Circuits and Systems, 2004. ISCAS 2004.
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