Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Reference Design: Dual-Output ADP1621 Sepic-Cùk Contents User Input Data & Solution Schematic .......................................................................................................................2 User Target Specs, Vout1 .......................................................................................................................................2 User Target Specs, Vout2 .......................................................................................................................................2 Default Design Target Specs, Vout1 .......................................................................................................................2 Default Design Target Specs, Vout2 .......................................................................................................................2 Notes: .................................................................................................................................................................2 Schematic ...............................................................................................................................................................3 Notes: .................................................................................................................................................................3 Bill of Materials...........................................................................................................................................................4 Notes: .................................................................................................................................................................4 Graphs ........................................................................................................................................................................5 Bode Plot ................................................................................................................................................................5 Efficiency ................................................................................................................................................................5 Cross Regulation .....................................................................................................................................................6 Transient Response ................................................................................................................................................7 Performance Data ......................................................................................................................................................9 Operational Estimates ............................................................................................................................................9 Temperatures .........................................................................................................................................................9 Layouts .................................................................................................................................................................... 10 Test board schematic ...................................................................................................................................... 10 Test board photograph .................................................................................................................................... 11 Test board top/bottom layout......................................................................................................................... 11 Rev A | 1 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk User Input Data & Solution Schematic User Target Specs, Vout1 Spec Vout1 Iout1 Tamb Vinmin Vinmax Target Value +15V 1.0 50 10 30 Actual Value 14.93 1.0 50 10 30 Units Volts Amps degC Volts Volts User Target Specs, Vout2 Spec Vout2 Iout2 Tamb Vinmin Vinmax Target Value -15V -1.0 50 10 30 Actual Value -14.90 -1.0 50 10 30 Units Volts Amps degC Volts Volts Default Design Target Specs, Vout1 Spec Vout1 ripple max Ioutstep1 Vout1 step error MaxHeight Target Value 0.150 0.5 0.300 25 Actual Value 0.030 0.5 0.190 7.4 Units Volts Apk Volts mm Default Design Target Specs, Vout2 Spec Vout2 ripple max Ioutstep2 Vout2 step error MaxHeight Target Value 0.150 0.5 0.300 25 Actual Value 0.017 0.5 0.305 7.4 Units Volts Apk Volts mm Notes: 1. Minimum load current of 50mA on each rail required to maintain cross regulation within +/-10% limits 2. Best regulation is achieved if load currents track. Rev A | 2 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Schematic 8 Cout (x4) Vo- T1 11 1 2 3 Vin Rh2 Rh1 Rin Rh3 Vin U2 Cin2 SDSN IN GND CS U1 COMP D1 4 5 6 10 FREQ PGND Rfreq ADP1621ARMZ 9 C2 Csn Rs Rc1 Cout (x8) C1 Cin3 PIN GATE Vo+ Q3 Cc1 FB D2 12 Cin1 (x2) Vcc GND OUT ADCMP356 7 Q1 Q2 Rsn Rsense RF1 RF2 Notes: 1. For load range of 0-0.5A, only Q1 is needed. For loads up to 1.0A, Q1 and Q2 are paralleled. 2. The (xn) on the capacitors refers to the number of capacitors of the given type to be paralleled. 3. U2 forms a precision UVLO circuit allowing the regulator to start at Vin=9.5V rising. 4. Rin/Q3 in conjunction with U1’s on-chip shunt regulator allow the ADP1621 to operate at up to Vin=36V. 5. Csn and Rsn snub voltage spikes due to T1 leakage inductance and C1/C2’s package inductance.. 6. If low-noise is required, an LC post-filter (100nH/1uF ceramic) can be added, but the compensation will need adjustment if the loop is closed around it. Rev A | 3 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Bill of Materials Disclaimer: 1. BOM prices shown are 1000 piece estimates in US Dollars that should be used for comparison purposes only. 2. It is the user’s responsibility to verify actual design performance through prototyping and test. Item # Des Mfg Part Number Component Specs Package Qty Area (mm^2) 1 U1 ADI ADP1621ARMZ Integrated Switching Regulator 2 U2 ADI ADCMP356 Comparator/Reference 3 T1 Coilcraft HP2-0116L 4 Q1,Q2 Vishay Si4850EY 5 Q3 Fairchild 6 D1,D2 7 Height (mm) Cost MSOP-10 1 14.7 1.1 1.32 SC70 1 5.3 1.1 0.31 5.7uH 6-winding transformer Shielded 1 274.0 7.4 3.02 60V, 42mohm N-ch SO8 2 37.2 1.1 0.32 MMBT3904 40V NPN Transistor SOT23 1 8.0 1.1 0.02 Diodes, Inc B360B 3A, 60V Schottky Diode SMB 2 42.6 2.4 0.34 Cout Murata GRM31CR61E106KA12 10uF, 25V, X5R 1206 12 61.4 1.6 1.20 8 Rsense Susumu RL1220T-R010-J 10mohm 5% 1/4W 805 1 3.2 0.8 0.044 9 Cin1 Murata GRM32ER71H475KA 4.7uF, 50V, X5R 1210 2 16.0 2.0 0.566 10 Cin2,Cin3 Murata GRM188R61A105K 1uF, 10V, X5R 603 1 1.3 0.8 0.01 11 C1,C2 Murata GRM32ER71H475K 4.7uF, 50V, X5R 1210 2 16.0 2.0 0.566 12 Rin 2.37 kohm, 1% resistor 603 1 1.3 0.4 0.005 13 Rs 200 ohm, 1% resistor 603 1 1.3 0.4 0.005 14 Rfreq 24.3 kohm, 1% resistor 603 1 1.3 0.4 0.005 15 Rc1 33.2k, 1% resistor 603 1 1.3 0.4 0.005 16 Cc1 10 nF, NPO/C0G 603 1 1.3 0.8 0.005 17 RF1 10 kohm, 1% resistor 603 1 1.3 0.4 0.005 18 RF2 113 kohm, 1% resistor 603 1 1.3 0.4 0.005 19 Rh1 10 kohm, 1% resistor 603 1 1.3 0.4 0.005 20 Rh2 681 ohm, 1% resistor 603 1 1.3 0.4 0.005 21 Rh3 1 Mohm, 1% resistor 603 1 1.3 0.4 0.005 22 Rsn 3.4 ohm 1% resistor 805 1 3.2 0.8 0.005 23 Csn 1nF, NPO/C0G 0603 1 1.3 0.4 Comp Area Total 497.2 Max Height 7.4 0.005 Cost $7.84 Notes: 1. Design optimized for 1A load. For 0.5A max load Q2 may be omitted. 2. D1 and D2 are sized to withstand up to a 3A short on either output to ground for 1 min. If more protection against overloads is needed, B560C diodes can be used and will withstand up to 10A short for 1 min. In either case, T1 will eventually overheat if the short is maintained indefinitely. Rev A | 4 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Graphs Bode Plot (from simulation) Legend: / Gain/phase @Vin=10V / Gain/phase @Vin=30V Efficiency (equal load on Vout1/Vout2) Rev A | 5 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Cross Regulation Rev A | 6 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Transient Response Vout1/Vout2 in response to 0.5A step on Vout1: Rev A | 7 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Vout1/Vout2 in response to 0.5A step on Vout2: Rev A | 8 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Performance Data Operational Estimates Spec PWM Frequency PFM Threshold Don Doff Iin Avg Vinmin 800 0.005 0.611 0.389 3.334 Vinmax 800 0.005 0.341 0.659 1.029 Units kHz A Ton/Tpd Toff/Tpd A Temperatures From measured data on two-layer board at 25.6C extrapolated to 50C Component U1 T1 Q1 Q2 D1 D2 Rsense Notes: Vinmin 88 103 132 135 94.9 94 103 Vinmax 105 115 152 152 99 100 113 Units degC degC degC degC degC degC degC Tja, degC/W 172 62 60 60 73 73 110 1. Q1 and Q2 are 175C rated parts. 2. T1 is rated for up to 40C rise over 85C. Rev A | 9 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Layouts Circuit was prototyped on 2-layer mill-routed copper board and tested to verify performance. The following schematic and layouts were used: Test board schematic (note Rf3, R1, and C10 were used for test purposes and are not in the final design. Rf3 should be a short, and R1 and C10 are no-pop.) Rev A | 10 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Test board photograph Test board top/bottom layout Rev A | 11 of 12 Design #FCDC01101 +/-15V ADP1621 Sepic-Cùk Reference designs are as supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of reference designs. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Reference designs are not authorized to be used in life support devices or systems. Rev A | 12 of 12