LT3641 Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer DESCRIPTION FEATURES n n n n n n n n n n n n High Voltage Buck Regulator: 4V to 42V Operating Range 1.3A Output Current Input Transient Protection to 55V Low Voltage Synchronous Buck Regulator: 2.5V to 5.5V Input Voltage Range 1.1A Output Current Synchronizable, Adjustable 350kHz to 2.5MHz Switching Frequency Programmable Power-On Reset Timer Programmable Window Mode Watchdog Timer Typical Quiescent Current: 290μA Short-Circuit Robust Programmable Soft-Start Low Shutdown Current: IQ < 1μA Thermal Shutdown Available in Thermally Enhanced 28-Lead (4mm × 5mm) QFN and 28-Lead TSSOP Packages The LT®3641 is a dual channel, current mode monolithic buck switching regulator with a power-on reset and a watchdog timer. Both regulators are synchronized to a single oscillator with an adjustable frequency (350kHz to 2.5MHz). At light loads, both regulators operate in low ripple Burst Mode® to maintain high efficiency and low output ripple. The high voltage channel is a nonsynchronous buck with an internal 2.4A top switch that operates from an input of 4V to 42V and input transient protection to 55V. The low voltage channel operates from an input of 2.5V to 5.5V. Internal synchronous power switches provide high efficiency without the need of external Schottky diode. Both channels have cycle-by-cycle current limit, providing protection against shorted outputs. The power-on reset and watchdog timeout periods are both adjustable using external capacitors. The window mode watchdog timer flags when the μP pulses group too close together or too far apart. APPLICATIONS n n The LT3641 is available in a 28-pin 4mm × 5mm QFN package and 28-pin TSSOP package. Both packages have an exposed pad for low thermal resistance. Industrial Power Supplies Automotive Electronic Control Units L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 2MHz 5V/0.8A and 3.3V/0.5A Step Down Regulators HV Channel Efficiency, 2MHz, VOUT1 = 5V 0.22μF 10μF 4.7μH EN/UVLO VIN SW SYNC WDE PGOOD2 BST SW1 301k DA FB1 VOUT1 5V/0.8A 22μF VIN = 12V μP VIN2 EN2 2.2μH SW2 226k CWDT CPOR 1.5nF RT GND SS2 1.5nF 32.4k FB2 SS1 49.9k 1nF VOUT2 3.3V/0.5A 22μF EFFICIENCY (%) LT3641 RST1 RST2 WDO WDI 80 75 3641 TA01a 85 80 75 70 70 0 1nF VIN2 = 5V 90 85 100k 100k 95 90 100k VOUT1 LV Channel Efficiency, 2MHz, VOUT2 = 3.3V EFFICIENCY (%) VIN 7V TO 42V* 0.2 0.4 0.6 0.8 1.0 VOUT1 CURRENT (A) 1.2 1.4 3641 TA01b 0 0.2 0.4 0.6 0.8 VOUT2 CURRENT (A) 1.0 1.2 3641 TA01c * FOR INPUT VOLTAGES ABOVE 42V RESTRICTIONS APPLY 3641fa 1 LT3641 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN, EN/UVLO Voltage (Note 7) .................................55V WDE Voltage .............................................................30V BST Above SW, SW1 Voltage ....................... –0.3V to 6V SW1 Above SW Voltage ............................... –0.3V to 6V VIN2, SYNC, EN2, PGOOD2, WDI, WDO, RST1, RST2, Voltages ....................... –0.3V to 6V SS1, SS2, FB1, FB2, RT, CWDT, CPOR Voltages………... ........................... –0.3V to 2.5V SW2 Voltage ................................ –0.3V to (VIN2 + 0.3V) Operating Junction Temperature Range (Note 2) LT3641E ................................................. –40°C to 125°C LT3641I .................................................. –40°C to 125°C LT3641H................................................. –40°C to 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature, FE Only (Soldering, 10 sec) .... 300°C PIN CONFIGURATION TOP VIEW 5 24 VIN2 FB1 6 23 GND RT 7 RST2 8 RST1 9 WDO 10 28 27 26 25 24 23 SYNC 1 22 SW2 SS1 2 21 VIN2 FB1 3 20 GND 22 VIN RT 4 21 BST RST2 5 20 SW RST1 6 19 SW1 WDO 7 CWDT 11 18 DA CPOR 12 17 NC WDE 13 16 GND WDI 14 15 GND 19 VIN 29 GND 18 BST 17 SW 16 SW1 CWDT 8 15 DA 9 10 11 12 13 14 CPOR 29 GND GND SS1 EN2 25 SW2 FE PACKAGE 28-LEAD PLASTIC TSSOP θJA = 30°C/W, θJC = 8°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB NC 26 GND 4 SS2 3 SYNC GND EN/UVLO FB2 27 EN2 GND 2 PGOOD2 PGOOD2 TOP VIEW WDI 28 SS2 EN/UVLO 1 WDE FB2 UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN θJA = 43°C/W, θJC = 3.4°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3641EFE#PBF LT3641EFE#TRPBF LT3641FE 28-Lead Plastic TSSOP –40°C to 125°C LT3641IFE#PBF LT3641IFE#TRPBF LT3641FE 28-Lead Plastic TSSOP –40°C to 125°C LT3641HFE#PBF LT3641HFE#TRPBF LT3641FE 28-Lead Plastic TSSOP –40°C to 150°C LT3641EUFD#PBF LT3641EUFD#TRPBF 3641 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LT3641IUFD#PBF LT3641IUFD#TRPBF 3641 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3641fa 2 LT3641 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted. PARAMETER TYP MAX VIN Undervoltage Lockout Threshold l 3.6 4 V VIN Undervoltage Release Threshold l 3.8 4.2 V 0.1 275 1 375 μA μA 1.26 1.3 Quiescent Current from VIN CONDITIONS MIN EN/UVLO = 0.3V Not Switching EN/UVLO Threshold Voltage 1.2 UNITS V EN/UVLO High Bias Current EN/UVLO = Threshold + 60mV 2 μA EN/UVLO Low Bias Current EN/UVLO = Threshold – 60mV 0.1 μA SYNC Input Frequency 0.35 SYNC Threshold Voltage 0.4 0.8 1 l l 1.75 450 2 500 2.35 550 l 1.24 Switching Frequency RT = 32.4k RT = 182k 2.5 MHz V MHz kHz 1.265 1.29 V FB1 Bias Current FB1 = 1.265V 30 100 nA FB1 Line Regulation 5V < VIN < 30V 0.001 ISW1 = 800mA 400 FB1 Voltage SW1 Minimum Off-Time SW1 VCESAT 70 SW1 Leakage Current SW1 Current Limit FB1 = 1V (Note 3) FB1 = 0.1V l DA Current limit FB1 = 1V (Note 4) FB1 = 0.1V l BST Pin Current ISW1 = 800mA EN2 Threshold μA 2.2 2.8 1.8 3.4 A A 1.35 1.7 1 2.2 A A 30 50 mA 2 2.7 V 2.3 2.5 V 5.5 V 1.13 1.18 1.23 V 50 80 110 mV 50 500 nA 600 615 mV 0 100 l Rising l EN2 Hysteresis EN2 Bias Current EN2 = EN2 Threshold l FB2 Voltage ns mV 1 l VIN2 Maximum Operating Voltage 100 0.1 Minimum BST-SW Voltage VIN2 Minimum Operating Voltage %/V 585 FB2 Bias Current FB2 = 0.6V FB2 Line Regulation 2.5V < VIN2 < 5.5V SW2 PMOS Current Limit (Note 5) l 1.5 SW2 NMOS Current Limit (Note 5) l 1.2 SW2 PMOS RDS(ON) ISW2 = 0.5A (Note 6) SW2 NMOS RDS(ON) ISW2 = 0.5A (Note 6) 0.01 nA %/V 1.9 2.2 1.6 2 275 A A mΩ 200 mΩ ΔFB2 to Enable PGOOD2 20 40 80 mV ΔFB2 Hysteresis to Disable PGOOD2 20 40 80 mV 200 320 mV PGOOD2 Voltage FB2 = 0.6V, IPGOOD2 = 1mA 3641fa 3 LT3641 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX SS1, SS2 Charge Current SS1 = 0.5V, SS2 = 0.5V 1.3 2.0 2.7 μA SS1 to FB1 Offset Voltage SS1 = 0.6V 5 30 mV SS2 to FB2 Offset Voltage SS2 = 0.3V 5 30 mV % RST1 Threshold as Percentage of VFB1 l 90 92 94 RST2 Threshold as Percentage of VFB1 l 88 91 94 Undervoltage to RST Assert Time 20 RST1, RST2, WDO Pull-Up Current RST1, RST2, WDO = 0V RST1, RST2, WDO Output Voltage IRST1, IRST2, IWDO = 2mA RST1, RST2 Timeout Period (tRST) CPOR = 220pF 5 l 8 UNITS % μs 15 30 μA 150 250 mV 9.5 11 ms Watchdog Start Delay Time (tDLY) CWDT = 820pF 14 16 18 ms Watchdog Upper Boundary (tWDU) CWDT = 820pF l 27 32 35 ms Watchdog Lower Boundary (tWDL) CWDT = 820pF l 1.68 2 2.2 ms WDI Pull-Up Current WDI = 1.2V WDI Voltage Threshold 0.55 0.85 WDI Low Minimum Pulse Width 300 ns WDI High Minimum Pulse Width 300 ns WDE Pull-Down Current 4 WDE = 2V WDE Threshold Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3641E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3641I is guaranteed and tested over the full –40°C to 125°C operating junction temperature range. The LT3641H is guaranteed and tested over the full –40°C to 150°C operating junction temperature range. Note 3: SW1, SW2 current limit is guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycle. μA 1.15 1 l 0.5 0.7 V μA 0.9 V Note 4: The oscillator cycle is extended when DA current exceeds its limit. DA current limit is flat over duty cycle. Note 5: If the SW2 NMOS current exceeds its limit at the start of an oscillator cycle, the PMOS will not be turned on in the cycle. Note 6: The QFN switch RDS(ON) is guaranteed by correlation to wafer level measurement. Note 7: Absolute Maximum Voltage at VIN and EN/UVLO pins is 55V for nonrepetitive 1 second transients, and 42V for continuous operation. Note 8: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 3641fa 4 LT3641 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. HV Channel Efficiency (2MHz, VOUT1 = 5V) HV Channel Efficiency (2MHz, VOUT1 = 3.3V) 90 LV Channel Efficiency (2MHz, VOUT2 = 1.2V) 90 95 90 85 VIN = 12V VIN = 16V 80 VIN = 24V 85 EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%) 85 80 75 75 70 65 0 0.2 0.4 0.6 0.8 1.0 VOUT1 CURRENT (A) 1.2 0 0 VIN2 = 5V 80 75 350 0.30 300 0.25 0.20 0.15 0.10 0.05 0.4 0.6 VOUT2 CURRENT (A) 0.8 0.8 0 1.0 250 200 150 100 10 20 30 0 –50 40 0 VIN VOLTAGE (V) 50 100 3641 G05 3641 G06 FB1 Voltage vs SS1 FB1 Voltage vs Temperature 1.4 1.35 1.2 150 TEMPERATURE (°C) 3641 G04 1.40 1.0 50 0.00 70 0.2 0.4 0.6 VOUT2 CURRENT (A) Quiescent Current vs Temperature 0.35 VIN QUIESCENT CURRENT (μA) VIN QUIESCENT CURRENT (mA) VIN2 = 3.3V 0.2 3641 G03 Quiescent Current vs VIN 90 EFFICIENCY (%) 70 3641 G02 LV Channel Efficiency (2MHz, VOUT2 = 1.8V) 0 VIN2 = 5V 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VOUT1 CURRENT (A) 3641 G01 85 80 75 VIN = 12V VIN = 24V VIN = 36V VIN = 48V 70 VIN2 = 3.3V FB2 Voltage vs Temperature 0.70 0.65 1.25 1.20 RST1 THRESHOLD 1.15 0.8 0.6 REGULATION 0.60 RST2 THRESHOLD 0.55 0.4 1.10 0.50 0.2 1.05 1.00 –50 1.0 FB2 VOLTAGE (V) REGULATION FB1 VOLTAGE (V) FB1 VOLTAGE (V) 1.30 0.0 0 50 100 150 0 0.5 1.0 1.5 2.0 SS1 VOLTAGE (V) TEMPERATURE (°C) 3641 G07 0.45 –50 0 50 100 150 TEMPERATURE (°C) 3641 G08 3641 G09 3641fa 5 LT3641 TYPICAL PERFORMANCE CHARACTERISTICS Switching Frequency vs Temperature FB2 Voltage vs SS2 0.52 SWITCHING FREQUENCY (MHz) 600 500 400 300 200 HV Channel Current Limit vs Duty Cycle 2.5 RT = 182k SW1 PEAK CURRENT LIMIT (A) 700 FB2 VOLTAGE (mV) TA = 25°C, unless otherwise noted. 0.51 0.50 0.49 2.0 1.5 1.0 0.5 100 0.48 –50 0 400 200 6000 800 1000 0.0 50 0 100 SW2 VOLTAGE DROP (mV) SW2 PEAK CURRENT LIMIT (A) 2.0 0.45 400 0.40 350 0.35 300 PMOS 200 NMOS 150 0 40 20 60 80 0 0.5 1 1.5 SWITCHING FREQUENCY (MHz) 0.5 0 0.2 0.4 0.6 0.8 1.0 1.2 VIN2 = 3.3V 2.0 3641 G16 30 25 1.5 VIN2 = 5V 1.0 0.5 20 15 10 5 0 0.2 0.4 0.6 0.8 1.0 VOUT2 CURRENT (A) VOUT1 CURRENT (A) 25 EN2 Current vs Voltage 0 0 20 30 EN2 CURRENT (μA) RT = 32.4k VIN = 24V 15 3641 G15 2.5 VIN = 16V 10 VIN VOLTAGE (V) LV Channel Switching Frequency (VOUT2 = 1.8V) VIN = 12V 5 3641 G14 HV Channel Switching Frequency (VOUT1 = 3.3V) 1.0 0 SW2 CURRENT (A) 3641 G13 1.5 0.15 0.05 0 2MHz 0.20 0.10 100 2.5MHz 0.25 50 DUTY CYCLE (%) 2.0 0.30 100 0 0.0 SWITCHING FREQUENCY (MHz) VOUT1 Minimum Load to Run at Full Frequency (VOUT1 = 3.3V) 450 250 100 3641 G12 LV Channel Switch Voltage Drop vs Current (VIN2 = 3.3V) 0.5 80 3641 G11 LV Channel Peak Current Limit vs Duty Cycle 1.0 60 DUTY CYCLE (%) 3641 G10 1.5 40 20 TEMPERATURE (°C) SS2 VOLTAGE (mV) 2.5 0 150 VOUT1 CURRENT (A) 0 0 0 2 4 6 EN2 VOLTAGE (V) 3641 G17 3641 G17a 3641fa 6 LT3641 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. SW1 10V/DIV SW1 10V/DIV IL1 0.5A/DIV IL1 0.5A/DIV SW2 5V/DIV SW2 5V/DIV IL2 0.5A/DIV IL2 0.5A/DIV 200ns/DIV VIN2 = VOUT1 VIN1 = 12V VOUT1 = 3.3V/0.5A VOUT2 = 1.8V/0.5A 3641 G18 500ns/DIV VIN2 = VOUT1 VIN1 = 12V VOUT1 = 3.3V/25mA VOUT2 = 1.8V/30mA 3641 G19 180 160 140 120 100 80 60 40 20 0 0 1000 2000 3000 4000 5000 CWDT CAPACITANCE (pF) 3641 G20 RST/WDO Pull-Up Current 35 20 30 RST/WDO PULL-UP CURRENT (μA) WATCHDOG UPPER BOUNDARY PERIOD (ms) Watchdog Upper Boundary Period vs Temperature 25 20 15 10 5 0 –50 Watchdog Upper Boundary Period vs CWDT Light Load Operation Waveforms WATCHDOG UPPER BOUNDARY PERIOD (ms) Full Frequency Waveforms 0 50 100 150 TEMPERATURE (°C) 3641 G21 15 10 5 0 0 1 1.5 0.5 RST/WDO VOLTAGE (V) 2 3641 G22 3641fa 7 LT3641 PIN FUNCTIONS (FE/QFN) FB2 (Pin 1/Pin 26): The low voltage converter regulates the FB2 pin to 600mV. Connect the feedback resistor divider tap to this pin to set output voltage. PGOOD2 (Pin 2/Pin 27): Open-drain logic output that starts to sink current when FB2 is in regulation. EN/UVLO (Pin 3/Pin 28): Pull this pin below 0.3V to shut down the LT3641. The 1.26V threshold can function as an accurate undervoltage lockout, preventing the LT3641 from operating until VIN voltage has reached the programmed level. SYNC (Pin 4/Pin 1): Driving the SYNC pin with an external clock signal synchronizes both converters to the applied frequency. The lowest external clock frequency should be 20% higher than the internal oscillator frequency. SS1 (Pin 5/Pin 2): The SS1 pin sets the FB1 voltage externally between 0V and 1.265V, providing soft-start and tracking. Tie this pin 1.5V or higher to use the internal 1.265V reference. A capacitor to ground at this pin sets the ramp time to regulated output voltage for the high voltage converter. Use a resistor divider to track another supply. FB1 (Pin 6/Pin 3): The high voltage converter regulates the FB1 pin to 1.265V. Connect the feedback resistor divider tap to this pin to set output voltage. RT (Pin 7/Pin 4): Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the internal oscillator frequency. RST2 (Pin 8/Pin 5): Open-drain logic output that remains asserted for the period set by the CPOR pin capacitor after FB2 goes above 550mV. RST1 (Pin 9/Pin 6): Open-drain logic output that remains asserted for the period set by the CPOR pin capacitor after FB1 goes above 1.165V. WDO (Pin 10/Pin 7): Open-drain logic output that remains asserted for the period set by the CPOR pin capacitor if WDE is enabled and WDI pin is not driven by an appropriate signal. CWDT (Pin 11/Pin 8): Connect a capacitor to ground at this pin to set watchdog timer. CPOR (Pin 12/Pin 9): Connect a capacitor to ground at this pin to set the power-on reset timer and WDO output timer. WDE (Pin 13/Pin 10): Watchdog Enable Pin. WDI (Pin 14/Pin 11): The WDI pin receives watchdog signals from a microprocessor. GND (Pins 15, 16, 23, 26, Exposed Pad Pin 29/Pins 12, 13, 20, 23, Exposed Pad Pin 29): Ground. These pins must be soldered to PCB ground. NC (Pin 17/Pin 14): Not Connected. This pin can be connected to ground. DA (Pin 18/Pin 15): The DA pin is used to sense the catch diode current for current limit and protection. Connect this pin to catch diode anode. SW1 (Pin 19/Pin 16): Output of the High Voltage Internal Power Switch. Connect this pin to the inductor and catch diode cathode. SW (Pin 20/Pin 17): The SW pin is used to charge the boost capacitor. Connect this pin to the boost capacitor. BST (Pin 21/Pin 18): The BST pin is used to provide a drive voltage, higher than VIN pin voltage, to the high voltage channel internal power switch. Connect an external boost diode to this pin. VIN (Pin 22/Pin 19): The VIN pin supplies current to the LT3641’s internal circuitry and to the high voltage channel internal power switch. This pin must be locally bypassed. VIN2 (Pin 24/Pin 21): The VIN2 pin supplies current to the internal power MOSFET of the low voltage converter and to the LT3641’s internal circuitry when VIN2 is above 3V. SW2 (Pin 25/Pin 22): Switch Node of the Low Voltage Converter. Connect this pin to an inductor. EN2 (Pin 27/Pin 24): Low Voltage Converter Enable Pin. The enable threshold is 100mV below FB1 target voltage. The disable threshold has 50mV hysteresis. The accurate threshold can function as an accurate undervoltage lockout. SS2 (Pin 28/Pin 25): The SS2 pin sets the FB2 voltage externally between 0V and 0.6V, providing soft-start and tracking. Tie this pin 0.8V or higher to use the internal 0.6V reference. A capacitor to ground at this pin sets the ramp time to regulated output voltage for the low voltage converter. Use a resistor divider to track another supply. 3641fa 8 LT3641 BLOCK DIAGRAM CIN VIN 2μA BST EN/ UVLO 100k + A4 – 5.5V – A3 + ENABLE CBST R S Q1 Q SW DRIVER + – VREF 1.265V A1 2μA R2 L1 SW1 SS1 VOUT1 DBST + – + gm1 VC1 Σ RAMP GENERATOR DA – A2 + OSCILLATOR VOUT1 D1 COUT1 FB1 + – R1 RT SYNC – + A8 Σ A5 + – VIN2 CIN2 2μA SS2 VOUT2 R4 + – + gm2 VC2 + A7 – R S Q SW2 LOGIC CIRCUIT 50mV + – VREF 600mV A6 – + PGOOD2 – + A9 + – 2μA CPOR VOUT2 COUT2 FB2 R3 L2 2μA RST1 RST2 WDE WDI 1.165V CWDT WATCHDOG TIMER POR TIMER EN2 WDO 3641 BD 3641fa 9 LT3641 TIMING DIAGRAMS Power-On Reset Timing FB tUV RST tRST Watchdog Timing WDI WDO tDLY t < tWDL tRST t < tWDU tWDL < t < tWDU tWDU tRST 3641 TD OPERATION The LT3641 is a dual channel, constant-frequency, current mode monolithic buck switching regulator with power-on reset and watchdog timer. Both channels are synchronized to a single oscillator with frequency set by RT. Operation can be best understood by referring to the Block Diagram. Buck Regulators The high voltage channel is a nonsynchronous buck regulator that operates from the VIN pin. The start of each oscillator cycle sets an SR latch and turns on the internal NPN power switch. An amplifier and comparator monitor the current flowing between the VIN and SW1 pins, turning the switch off when this current reaches a level determined by the voltage at VC1 node. An error amplifier measures the output voltage through an external resistor divider tied to the FB1 pin and servos the VC1 node. The reference of the error amplifier is determined by the lower of the internal reference and the voltage at the SS1 pin. If the error amplifier’s output increases, more current is delivered to the output; if it decreases, less current is delivered. An active clamp (not shown) on the VC1 node provides peak current limit. A DA pin current comparator extends the oscillator cycle until the catch diode current is below the valley current limit. Both the peak and valley current limits help to control the inductor current in fault conditions such as shorted output with high VIN. Both current limits are reduced when the voltage at the FB1 pin is below 0.2V. This current foldback helps to control the inductor current during start-up and overload. The NPN power switch driver operates from either the VIN pin or the BST pin. An external capacitor and diode are used to generate a voltage between the BST and SW pins. During the power-up of the LT3641, an internal 5mA current source charges the external BST capacitor. The regulator starts switching when the (BST-SW) voltage reaches the 2V threshold. The internal NPN power switch can be fully saturated for efficient operation when the (BST-SW) voltage is between 2.3V and 5.5V. The low voltage channel is a synchronous buck regulator that operates from the VIN2 pin. It starts switching only 3641fa 10 LT3641 OPERATION when the VIN2 pin voltage is above 2.3V, and the EN2 pin is above its threshold. The internal top power MOSFET is turned on each cycle at the beginning of each oscillator cycle, and turned off when the current flowing through the top MOSFET reaches a level determined by the voltage at the VC2 node. An error amplifier measures the output voltage through an external resistor divider tied to the FB2 pin and servos the VC2 node. The reference of the error amplifier is determined by the lower of the internal 600mV reference and the voltage at the SS2 pin. While the top MOSFET is off, the bottom MOSFET is turned on in an oscillator cycle until the inductor current starts to reverse. If the inductor current is higher than the valley current limit at the beginning of an oscillator cycle, the bottom MOSFET will remain on and prevent the top MOSFET from turning on until the overcurrent situation clears, limiting inductor current in shorted output fault. An internal regulator provides power to the control circuitry. The regulator draws most power from the VIN2 pin and a small portion of power from the VIN pin when the VIN2 pin voltage is higher than 3V. If the voltage at VIN2 pin is lower than 3V, the regulator draws all power from the VIN pin. The EN/UVLO pin is used to put the LT3641 in shutdown, reducing the input current to less than 1μA. The accurate 1.26V threshold of the EN/UVLO pin provides a programmable VIN undervoltage lockout through an external resistor divider tied to the EN/UVLO pin. A 2μA hysteresis current on the EN/UVLO pin prevents switching noise from shutting down the LT3641. The LT3641 has an overtemperature protection feature which disables switching in both channels when the junction temperature exceeds the overtemperature threshold. Junction temperature will exceed the maximum operating junction when overtemperature protection is active. Internal 2μA current sources charge the SS1 pin and the SS2 pin up to about 2V. Soft-start or output voltage tracking of the two channels can be independently implemented with capacitors from the SS1 pin and the SS2 pin to ground. Any undervoltage condition on the VIN pin triggers an internal latch that discharges the SS1 pin to below 100mV before it is released. If the EN2 pin goes below its threshold, or the VIN2 voltage falls below 2.2V, the SS2 pin will be discharged to below 100mV before it is released. To optimize efficiency, the LT3641 switches to low ripple Burst Mode operation in light load situations. Between switching pulses, control-circuitry current is minimized. A power good comparator with 40mV of hysteresis trips when the low voltage channel is enabled and the FB2 pin is above 550mV. The PGOOD2 pin is an open-drain output that is pulled low when both the outputs are in regulation. Power-On Reset and Watchdog Timer The LT3641 includes one power-on reset timer for each buck regulator and one common watchdog timer. Poweron reset and watchdog timers are both adjustable using external capacitors. Operation can be best understood by referring to the Timing Diagram. The RST1, RST2 and WDO pins are all open-drain outputs with weak internal pull-ups to about 2V. The RST1 and RST2 pins are pulled low when the LT3641 is enabled and VIN is above 3.6V. Once the FB1 pin rises above 1.165V, the high voltage channel reset timer is started and RST1 is released after the reset timeout period. The low voltage channel reset timer is started once the FB2 pin rises above 550mV, and releases RST2 after the reset timeout period. The watchdog circuit monitors a μP’s activity. As soon as RST2 is released, a delay timer is started. The watchdog timer is started after the delay timer times out. The LT3641 implements windowed watchdog function for higher system reliability. The watchdog timer detects falling edges on the WDI pin. If the falling edges are grouped too close together or too far apart, the WDO pin is pulled down and the reset timer is started. When the reset timer times out, WDO is released and the watchdog timer is again started after the delay period. 3641fa 11 LT3641 APPLICATIONS INFORMATION Setting the Output Voltages The internal reference voltage is 1.265V for the high voltage channel, and 600mV for the low voltage channel. The output voltages are set by resistor dividers according to the following formulas: ⎛ V ⎞ R2 = R1 • ⎜ OUT1 − 1⎟ ⎝ 1.265V ⎠ ⎛V ⎞ R4 = R3 • ⎜ OUT2 − 1⎟ ⎝ 0.6V ⎠ The high switching frequency also decreases the duty cycle range. The reason is that the LT3641 switches have finite minimum on- and off-times independent of the switching frequency. The top switch in the high voltage channel can turn on for a minimum of ~60ns and turn off for a minimum of ~70ns. The top switch in the low voltage channel can turn on for a minimum of ~110ns and turn off for a minimum of ~70ns. The minimum and maximum duty cycles are: DCMIN = fS • tON(MIN) Use 1% resistors in the resistor dividers. To avoid noise problems, R1 should be 100k or less, and R3 should be 50k or less. Reference designators refer to the Block Diagram. Switching Frequency The LT3641 uses a constant-frequency PWM architecture that can be programmed to switch from 350kHz to 2.2MHz by using a resistor tied from the RT pin to ground. Table 1 shows the necessary RT value for a desired switching frequency. Table 1. Switching Frequency vs RT Value DCMAX = 1 – fS • tOFF(MIN) where fS is the switching frequency, tON(MIN) is the minimum switch on-time, and tOFF(MIN) is the minimum switch off-time. These equations illustrate how duty cycle range increases when switching frequency decreases. The internal oscillator of the LT3641 can be synchronized to an external 350kHz to 2.5MHz positive clock signal on the SYNC pin. The RT value should be chosen such that the internal oscillator’s frequency is 20% lower than the lowest SYNC clock frequency (refer to Table 1). To avoid erratic operation, the LT3641 ignores the SYNC signal until the FB1 pin voltage is above 1.165V. When applying a SYNC signal, the rising edges reset the LT3641’s internal clock and initiate a switch cycle. The amplitude of the SYNC signal must be at least 2V. The SYNC pulse width must be at least 40ns. SWITCHING FREQUENCY (MHz) RT (k) 0.35 267 0.5 182 1 82.5 2 32.4 VIN Voltage Range 2.2 27.4 The LT3641’s minimum operating voltage is 3.6V typical. A higher minimum operating voltage can be accurately programmed with a resistor divider between the VIN pin and the EN/UVLO pin. The EN/UVLO threshold is 1.26V. When the LT3641 is enabled, a 2μA current flows out of the EN/UVLO pin generating hysteresis to prevent the switching action from falsely disabling the LT3641. Choose the divider resistances for appropriate hysteresis voltage. Selection of the operating frequency is mainly a trade-off between efficiency and component size. The advantage of high frequency operation is that smaller inductor and capacitor values may be used. The disadvantage is lower efficiency. 3641fa 12 LT3641 APPLICATIONS INFORMATION The high voltage nonsynchronous channel operates from the VIN pin. The minimum VIN voltage to regulate output voltage is: ⎛V +V ⎞ VIN(MIN) = ⎜ OUT1 D ⎟ − VD + VCE ⎝ DCMAX ⎠ VIN2 Voltage Range The low voltage synchronous channel operates from the VIN2 pin. The VIN2 pin can be connected to either an independent voltage supply or the high voltage channel output for a two-stage power regulator. The VIN2 voltage range is 2.3V ~ 5.5V Where VD is the forward voltage drop of the catch diode, VCE is the voltage drop of the internal NPN power switch, and DCMAX is the maximum duty cycle (refer to the Switching Frequency section). If VIN is below the calculated minimum voltage, output will lose regulation. The minimum VIN2 voltage to regulate output voltage at full frequency is: The maximum VIN should not exceed the absolute maximum rating. For fixed frequency operation, the maximum VIN is: Where DCMAX is the maximum duty cycle (refer to Switching Frequency section). If VIN2 is below the calculated minimum voltage, the low voltage channel starts to skip oscillator clock. In this case, the low voltage channel switching frequency will no longer be the programmed frequency. As the VIN2 voltage further decreases, the top MOSFET will remain on 100% duty cycle. In the case, the output starts to fall out of regulation. ⎛V +V ⎞ VIN(MAX) = ⎜ OUT1 D ⎟ − VD + VCE ⎝ DCMIN ⎠ Note that the high voltage buck will still regulate at an input voltage that exceeds VIN(MAX) (up to 42V). It will continue to regulate through transients up to 55V for one second. Note that the switching frequency will be reduced once the on-time required to satisfy the above equation is below 50ns (Figure 1). VIN2(MIN) ≈ VOUT2 DCMAX The maximum VIN2 for fixed frequency operation is: VIN2(MAX) ≈ VOUT2 DCMIN Where DCMIN is the minimum duty cycle (refer to the Switching Frequency section). For voltage that exceeds VIN2(MAX) (up to 5.5V), the low voltage channel exhibits pulse-skipping behavior, and the output ripple will increase. SW1 10V/DIV Inductor Selection IL1 0.5A/DIV 200ns/DIV VIN = 30V VOUT1 = 3.3V/0.2A 3641 F01 RT SET = 2MHz Figure 1. Lower Switching Frequency Occurs in High Voltage Channel When Required On-Time Is Below 50ns Inductor selection involves inductance, saturation current, series resistance (DCR) and magnetic loss. The inductance for the high voltage channel is: L1= 1.7 • VOUT1 + VD fS 3641fa 13 LT3641 APPLICATIONS INFORMATION where VOUT1 is high voltage channel output voltage, VD is the forward voltage drop of the catch diode, and fS is the switching frequency. For example, 3.3μH is a reasonable inductance for a 3.3V output with 2MHz switching frequency. Table 2. Inductor Vendors Once the inductance is selected, the inductor current ripple and peak current can be calculated: ΔIL1 = (VOUT1 + VD ) ⎛ V +V ⎞ • ⎜ 1– OUT1 D ⎟ ⎝ ⎠ VIN L1• fS IL(PEAK) = IOUT(MAX) + ΔIL 2 To guarantee sufficient output current, peak inductor current must be lower than the switch current limit (ILIM). The largest inductor current ripple occurs at the highest VIN. To guarantee current capacity, use VIN(MAX) in the above formula. The inductance for the low voltage channel is: L2 = 1.5 VOUT2 fS For a selected inductance, the inductor current ripple can be calculated: ΔIL2 = VOUT2 L2 • fS ⎛ ⎞ V • ⎜ 1– OUT2 ⎟ ⎝ VIN2 ⎠ For robust operation in fault conditions, the inductor saturation current should be higher than the upper limit of the corresponding top switch current limit. To keep the efficiency high, the inductor series resistance (DCR) should be as small as possible (must be < 0.1Ω), and the core material should be intended for the chosen operation frequency. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores; instead use ferrite, molypermalloy or Kool Mμ cores. Table 2 lists several vendors and suitable inductor series. VENDOR WEBSITE Murata www.murata.com TDK www.tdk.com TOKO www.toko.com Sumida www.sumida.com Cooper/Coiltronics www.cooperindustries.com Coilcraft www.coilcraft.com Vishay www.vishay.com NIC www.niccomp.com Würth Elektronik www.we-online.com Of course, such a simple design guide will not always result in the optimum inductors for the applications. A larger value inductor provides a slightly higher maximum load current and will reduce the output voltage ripple. A larger value inductor also results in higher efficiency in the condition of same DCR and same magnetic loss. However, for a same series of inductors, a larger value inductor has higher DCR. The trade-off between inductance and DCR is not always obvious. Use experiments to find optimum inductors. Low inductance may result in discontinuous mode operation, which is okay, but reduces maximum load current. For details of maximum output current and discontinuous mode operation, see the Linear Technology Application Note 44. For duty cycles greater than 50%, there is a minimum inductance required to avoid subharmonic oscillations. See the Linear Technology Application Note 19. Input Capacitor Bypass the VIN pin of the LT3641 with a ceramic capacitor of X7R (–55°C to 125°C) or X5R (–55°C to 85°C) type. Buck converters draw pulse current from the input supply. The input capacitor is required to reduce the resulting voltage ripple. Use a ceramic capacitor with: CIN ≥ 10μF fS where fS in the switching frequency in MHz. 3641fa 14 LT3641 APPLICATIONS INFORMATION A second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the LT3641. A ceramic input capacitor combined with trace or cable inductance forms a under damped tank circuit. If the LT3641 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT3641’s voltage rating. This situation can be easily avoided (see the Linear Technology Application Note 80). Output Capacitors and Output Ripple The output capacitor has two essential functions. In steady state, it determines the output voltage ripple. In transient, it stores energy in order to satisfy transient loads and stabilize the control loop. Ceramic capacitors have low equivalent series resistance (ESR) and provide the best ripple performance. A good starting value is: COUT1 = 150 VOUT • fS where fS is in MHz, and COUT is the recommended output capacitance in μF. Use X5R or X7R types. This choice will provide low output ripple and good transient response. A good starting value for the low voltage channel output capacitor is: COUT2 = 100 VOUT2 • fS In the case where VIN2 is connected to the high voltage channel output, the high voltage channel output capacitor can be used as the low voltage channel input capacitor. The required VIN2 input capacitor value is usually smaller than the high voltage output capacitor. Low ESR ceramic capacitors for VIN2 input and high voltage channel output could form resonant tank and cause jitter in certain operating area. Avoid VIN2 input capacitor if possible. When choosing a capacitor, look carefully through the data sheet to find out what the actual capacitance is under operating conditions (applied voltage and temperature). A physically larger capacitor or one with a higher voltage rating may be required. High performance tantalum or electrolytic capacitors can be used for the output capacitor. Low ESR is important, so choose one that is intended for use in switching regulators. Table 3 lists several capacitor vendors. Table 3. Capacitor Vendors PART SERIES VENDOR Ceramic, Polymer, Tantalum Panasonic/Sanyo www.panasonic.com Ceramic, Tantalum Kemet www.kemet.com Ceramic Murata www.murata.com Ceramic, Tantalum AVX www.avxcorp.com Ceramic Taiyo Yuden www.taiyo-yuden.com Catch Diode The high voltage channel requires an external catch diode to conduct current during switch off-time. Average forward current in normal operation can be calculated from: ID(AVG) = IOUT (VIN − VOUT ) VIN where IOUT is the output load current. Use a 1A or 2A rated Schottky diode. Peak reverse voltage is equal to the regulator input voltage. Use a diode with a reverse voltage rating greater than the input voltage. Table 4 lists several Schottky diodes and their manufacturers. Diodes Inc. PDS360 is recommended for high current, H-grade applications. Diodes Inc. DFLS260 can be used for smaller circuit footprint in non-H-grade applications. 3641fa 15 LT3641 APPLICATIONS INFORMATION Table 4. Diode Vendors PART NUMBER VR (V) IAVE (A) VF AT 1A (MV) VF AT 2A (MV) 20 40 1 1 530 595 VF AT 3A (MV) On Semiconductor MBRM120E MBRM140 capacitor charging scheme solves this start-up issue. Figure 2 shows that the minimum input voltage to start the high voltage channel nonsynchronous buck regulator of the LT3641 is very close to the minimum input voltage to regulate the output voltage for most of the load range. 5 Diodes Inc. 20 30 20 30 40 60 60 100 1 1 2 2 2 2 3 3 500 500 30 30 1 2 420 START 4 500 500 500 620 650 620 760 VIN VOLTAGE (V) B120 B130 B220 B230 DFLS240L DFLS260 PDS360 PDS3100 International Rectifier 10BQ030 20BQ030 RUN 3 2 1 470 470 0 0.001 BST and SW Pin Considerations The high voltage channel will not start until the (BST-SW) voltage is 2V or above. When the LT3641 is enabled, an internal ~5mA current source from VIN flows out of the BST pin. The SW pin is disconnected from the SW1 pin, and is pulled down by an internal current source to ground. The external boost capacitor can be charged up regardless of the output. When the (BST-SW) voltage reaches 2V, the SW pin is connected to the SW1 pin, and the high voltage channel starts switching. However, the internal bipolar power switch cannot be fully saturated until the (BST-SW) voltage is further charged to above 2.3V. To start up a traditional nonsynchronous buck regulator with very light load, the input voltage needs to be a couple of volts higher than the minimum running input voltage if the input voltage is ramping up slowly. The LT3641’s unique boost 1 3641 F03a (2a) FS = 2MHz 5 START 4 VIN VOLTAGE (V) The high voltage channel requires an external capacitor between the BST and SW pins and an external boost diode from a voltage source to the BST pin. In most cases, a 0.22μF capacitor will work well. Use a Schottky with fast reverse recovery for BST diode. The (BST-SW) voltage cannot exceed 5.5V, and must be more than 2.3V for best efficiency. Connect the boost diode to any voltage between 2.7V and 5.5V. The VIN2 pin is the best choice if the low voltage channel is used. 0.01 0.1 VOUT CURRENT (A) RUN 3 2 1 0 0.001 0.01 0.1 VOUT CURRENT (A) 1 3641 F03b (2b) FS = 500kHz Figure 2. High Voltage Channel Minimum Input Voltage for VOUT1 = 3.3V 3641fa 16 LT3641 APPLICATIONS INFORMATION Soft-Start The LT3641 has a soft-start pin for each channel. The feedback pin voltage is regulated to the lower of the corresponding SS pin and the internal references, which is 1.265V for the high voltage channel, and 600mV for the low voltage channel. A capacitor from the SS pin to ground is charged by an internal 2μA current source resulting in an output ramping linearly from 0V to the regulated voltage. The duration of the ramp is: tSS1 = CSS1 • tSS2 = CSS2 • 1.265V 2μA 600mV 2μA where tSS1 is the ramping time for the SS1 pin, tSS2 is the ramping time for the SS2 pin, CSS1 is the capacitance from the SS1 pin to ground, and CSS2 is the capacitance from the SS2 pin to ground. At power-up, a latch is set to discharge the SS1 pin. After the SS1 pin is discharged to below 100mV, the latch is reset. The internal 2μA current source starts to charge the SS1 pin when the (BST-SW) voltage is charged to above 2V. In the event of VIN undervoltage lockout, or the EN/UVLO pin being driven below 1.26V, the soft-start latch is set, triggering a start-up sequence. A latch is set to discharge the SS2 pin at power-up. After EN/UVLO is enabled, the VIN2 voltage is above 2.3V, the EN2 pin is enabled, and the SS2 pin is below 100mV, the latch is reset. The internal 2μA current source starts to charge the SS2 pin. In the event of the VIN2 pin falling below 2.2V, or the EN2 pin going below its threshold, the SS2 discharging latch is set, triggering a start-up sequence. EN/UVLO 2V/DIV VOUT1 2V/DIV VOUT2 1V/DIV PGOOD2 2V/DIV 500μs/DIV 3641 F04 VIN = 12V RT SET = 2MHz EN2 TIED TO FB2 Figure 3. Soft-Start of LT3641 Shorted-Output Protection If an inductor is chosen that will not saturate excessively, the LT3641 will tolerate a shorted output. For the high voltage channel, the DA current comparator extends the internal oscillator period until the catch diode current is below its limit. Both the top switch and the DA comparator have current foldback to help limit load current when the output is shorted to ground. The DA current limit is 1.7A when the FB1 voltage is above 0.2V, and is 1A when the FB1 voltage is below 0.2V. Figure 4 shows the high voltage channel operation under shorted output. Because of the low VIN2 voltage, the low voltage channel does not have current foldback. The low voltage channel does not extend the internal oscillator in shorted output condition allowing the high voltage channel to operate in constant frequency. If the bottom MOSFET current exceeds the NMOS current limit at the start of a clock cycle, the top MOSFET is kept off until the overcurrent situation clears. The inductor valley current is kept below the NMOS current limit to ensure robustness in shorted output condition (Figure 5). The SS pins can also be pulled up by external current sources or resistors for output tracking. The external pullup current should not exceed 100μA for either SS pin. Figure 3 shows the soft-start for a 3.3V and 1.8V application. 3641fa 17 LT3641 APPLICATIONS INFORMATION Reverse Protection SW1 20V/DIV IL1 1A/DIV 1μs/DIV 3641 F05 VIN = 55V VOUT1 = SHORT Figure 4. The High Voltage Channel Reduces Frequency to Protect Against Shorted Output with 55V Input SW1 20V/DIV PFM Operation SW2 2V/DIV To improve efficiency at light loads, the LT3641 automatically switches to pulse frequency modulation (PFM) operation which minimizes the switching loss and keeps the output voltage ripples small. IL2 1A/DIV 1μs/DIV 3641 F06 Because the two channels of the LT3641 may have different loads, the two channels can have different switching frequency (Figure 7). VIN2 = 5V VOUT2 = SHORT Figure 5. The Low Voltage Channel Operates in Valley Current Limit Mode to Protect Against Shorted Output IN In battery charging applications or in battery back-up systems, the output will be held high when the input to the LT3641 is absent. If the VIN pin is floated and the LT3641 is enabled, the LT3641’s internal circuitry will pull its quiescent current through the SW1 pin or the SW2 pin. This is fine if the system can tolerate a few mA in this state. If the LT3641 is disabled, the SW1 pin and the SW2 pin current will drop to essentially zero. However, if the VIN pin is grounded while the high voltage channel output is held high, an external diode is required at the VIN pin to prevent current being pulled out of the VIN pin. If the VIN2 pin is grounded while the low voltage channel output is held high, an external diode is required at the VIN2 pin to prevent current being pulled out of the VIN2 pin (Figure 6). VIN SW BST SW1 EN/UVLO DA FB1 OUT1 + – LT3641 SW2 IN2 VIN2 FB2 OUT2 + – GND 3641 F07 Figure 6. Diodes Prevent Shorted Inputs from Discharging a Battery Tied to the Outputs 3641fa 18 LT3641 APPLICATIONS INFORMATION Power-On Reset Timer SW1 10V/DIV Each channel of the LT3641 has a power-on comparator. Both comparators are enabled when the LT3641 is powered up and starts monitoring their corresponding feedback voltages. The threshold of power-on comparator is 1.15V for the high voltage channel, and 550mV for the low voltage channel. IL1 0.5A/DIV SW2 5V/DIV IL2 0.5A/DIV 3641 F08a 500ns/DIV VIN2 = VOUT1 VIN = 12V VOUT1 = 3.3V/25mA VOUT2 = 1.8V/30mA (7a) SW1 10V/DIV IL1 0.5A/DIV Both RST1 and RST2 are open-drain outputs with weak internal pull-ups (100k to ~2V). The DC characteristics of the RST1 and RST2 pull-down strength are shown in the Typical Performance Characteristics section. The weak pull-ups eliminate the need for external pull-ups when the rise time of these pins is not critical. The open-drain configuration allows wired-OR connections. The two power-on reset timers share one oscillator. The power-on reset timeout period, t RST (64 cycles on the CPOR pin), which is the same for the two channels, can be programmed by connecting a capacitor, CPOR, between the CPOR pin and ground: SW2 5V/DIV IL2 0.5A/DIV 3641 F08b 2μs/DIV VIN2 = VOUT1 VIN = 12V VOUT1 = 3.3V/25mA VOUT2 = 1.8V/20mA (7b) ⎛ s⎞ tRST = CPOR • 37 • 106 ⎜ ⎟ ⎝F⎠ For example, using a capacitor value of 8.2nF gives a 303ms reset timeout period. The accuracy of t RST will be limited by the accuracy and temperature coefficient of the capacitor CPOR. Extra parasitic capacitance on the CPOR pin, such as probe capacitance, can affect t RST. SW1 10V/DIV IL1 0.5A/DIV SW2 5V/DIV Watchdog IL2 0.5A/DIV 3641 F08c 2μs/DIV VIN2 = VOUT1 VIN = 12V VOUT1 = 3.3V/0mA VOUT2 = 1.8V/30mA (7c) Figure 7. PFM Operation The WDE pin is the enable pin for the watchdog. As soon as RST2 is released, the watchdog starts a delay period, tDLY, during which the input signal at the WDI pin is ignored for higher reliability. After the delay period, the watchdog starts detecting falling edges on the WDI pin. If the time between any two WDI falling edges is shorter than the watchdog lower boundary, tWDL, or longer than the watchdog upper boundary, tWDU, the WDO pin is pulled down for a period of t RST, which is the same as the power-on reset timeout period. When the WDO pin is released, the watchdog again starts the delay period. 3641fa 19 LT3641 APPLICATIONS INFORMATION The WDO is open-drain output with weak internal pull-up, similar to the RST pins. The delay period corresponding to 33 cycles on CWDT, the watchdog lower boundary (4 cycles on CWDT), and the watchdog upper boundary (64 cycles on CWDT) are all related and set by a capacitor, CWDT, between the CWDT pin and ground: tDLY ⎛ 33 ⎞ = t WDU • ⎜ ⎟ ⎝ 64 ⎠ t WDL = CWDT CPOR WD STARTS WD STARTS 64 CYCLES 64 CYCLES 64 CYCLES 64 CYCLES FB2 FB1 RST2 RST1 20ms/DIV 3641 F09a (8a) t WDU 16 ⎛ s⎞ t WDU = CWDT • 37 • 106 ⎜ ⎟ ⎝F⎠ CWDT CPOR The accuracy of the watchdog timer will be limited by the accuracy and temperature coefficient of the capacitor CWDT. Extra parasitic capacitance on the CWDT pin, such as probe capacitance, can affect the watchdog timer. Figure 8a shows the power-on reset timing. Having FB1 or FB2 high starts the CPOR oscillator. After t RST, the corresponding RST is released. When both RST1 and RST2 are released, the CWDT oscillator starts. Figure 8b shows the watchdog waveform with the WDI period between tWDL and tWDU. The WDI falling edge resets the CWDT oscillator. The CPOR oscillator is disabled and WDO remains high. Figure 8c shows the watchdog waveform with the WDI period longer than tWDU. WDO is asserted for a period of t RST when the watchdog upper boundary, tWDU, expires. The watchdog function can be disabled by tying WDE above its threshold. In this case, the CWDT pin can be left floating. If neither the watchdog function nor the poweron reset function is used, both the CWDT and CPOR pin can be left floating. WDI WDO 1ms/DIV 3641 F09b (8b) CWDT CPOR WDI WDO 50ms/DIV 3640 F09c (8c) Figure 8. Power-On Reset and Watchdog Timing The accuracy of the CPOR and CWDT capacitors determine the accuracy of the power-on reset timer and watchdog timer. The COG or NPO type of ceramic capacitors have zero temperature coefficient and good aging characteristics. Use COG or NPO type of capacitors with flat DC bias characteristic up to 1.5V on the CPOR and CWDT pins. 3641fa 20 LT3641 APPLICATIONS INFORMATION PCB Layout For proper operation and minimum EMI, care must be taken during the printed circuit board (PCB) layout. Figure 9 shows the recommended component placement with trace, ground plane and via locations. The input loop of the high voltage channel, which is formed by the VIN and SW1 pins, the external catch diode (D1), the input capacitor (CIN) and the ground, should be as small as possible. These external components should be placed on the same side of the circuit board as the LT3641, and their connections should be made on that layer. Place a local, unbroken ground plane below these components. The BST and SW nodes should be as small as possible. The boost capacitor (CBST) should be as close to the BST and SW pins as possible. The input loop of the low voltage channel is formed by the VIN2 pin, the input capacitor (CIN2) and the ground. Place CIN2 close to the VIN2 and the GND pin to minimize this loop. Place a local, unbroken ground plane below this input loop. Keep the FB1 and FB2 nodes small so that the ground traces will shield them from the switching nodes. The Exposed Pad on the bottom of the package must be soldered to the ground so that the pad acts as a heat sink. To keep thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the LT3641 to additional ground planes within the circuit board and on the bottom side. Sequencing Options In most LT3641 applications, the low voltage regulator generating OUT2 will operate from the output of the high voltage regulator generating OUT1. In this cascade circuit, channel 1 must start before channel 2. However, the LT3641 provides additional flexibility in programming the sequencing of the outputs. Figure 10 shows several possibilities. Figure 10a shows the easiest option. With EN2 tied to FB1, channel 2 will start when OUT1 is within 10% of its regulation point. COUT2 L2 CIN2 CIN CBST L1 COUT1 3641 F10 Figure 9. Recommended PCB Layout, FE28 Package Figure 10b shows a simple alternative. By tying EN2 to VIN2 , channel 2 starts as soon as its input reaches its minimum operating voltage of 2.3V. Figure 10c shows a circuit that handles two other common requirements. If the system requires the low voltage output to be in regulation before the higher voltage output (for example core voltage must appear before the I/O supply), then add a PMOS switch and drive its gate with the PGOOD2 pin, which will go low when both channels are in regulation. This provides a third output OUT3, which is present only when both OUT1 and OUT2 are in regulation. Figure 10c also takes care of a potential problem in cascaded power supply circuits. Because channel 2 is a switching regulator, it appears as negative impedance load to channel 1; as OUT1 decreases, the load required to supply the input of channel 2 increases. Since the channel 1 is current limited, you must be certain that it can supply both its own load and the power required by channel 2. The EN2 has an accurate threshold of 1.165V, and is used to program an undervoltage lockout for channel 2, allowing channel 1 to supply adequate power. 3641fa 21 LT3641 APPLICATIONS INFORMATION OUT1 FB1 OUT1 EN2 90% OUT2 VIN2 OUT1 (10a) OUT1 FB1 OUT1 EN2 VIN2 OUT2 2.3V OUT1 (10b) OUT1 FB1 OUT3 PGOOD2 VIN2 OUT1 OUT3 PROGRAMMED LEVEL OUT2 OUT1 90% EN2 (10c) 3641 F11 Figure 10. The EN2 and PGOOD2 Pins Allow Serial Sequencing Options 3641fa 22 LT3641 TYPICAL APPLICATIONS 2MHz 3.3V/1.3A and 1.8V/1A Buck Regulators VIN 5V TO 42V* 0.22μF 4.7μF 100k D2 301k EN/UVLO L1 3.3μH VIN SW BST SW1 SYNC DA FB1 WDE EN2 PGOOD2 LT3641 80.6k D1 49.9k VIN2 2.5V TO 5.5V VIN2 L2 1μH RST1 RST2 4.7μF SW2 100k WDO WDI VOUT1 3.3V/1.3A 22μF VOUT2 1.8V/1.1A 22μF FB2 CWDT CPOR RT GND SS2 SS1 32.4k 1.5nF 49.9k 1nF 1.5nF 1nF 3641 TA02 L1: VISHAY IHLP2020BZER3R3M01 L2: VISHAY IHLP1616ABER1R0M01 D1: DIODES PDS360 D2: CENTRAL SEMI CMDSH-4E * RESTRICTIONS APPLY FOR INPUT VOLTAGES ABOVE 42V 2MHz 5V/0.8A and 1.2V/1A Buck Regulators VIN 7V TO 42V* 0.22μF 4.7μF 100k D2 453k EN/UVLO L1 4.7μH VIN SW BST SW1 301k D1 WDI OUT1 100k 100k 100k 100k VOUT1 5V/0.8A SYNC DA FB1 WDE EN2 22μF 100k LT3641 WDI VIN2 L2 0.47μH PGOOD2 WDO SW2 49.9k RST1 RST2 CWDT VOUT2 1.2V/1A 22μF FB2 CPOR RT GND SS2 SS1 1.5nF 49.9k 1nF 1.5nF 32.4k 1nF 3641 TA03 L1: VISHAY IHLP2020BZER4R7M01 L2: VISHAY IHLP1616ABERR47M01 D1: DIODES DFLS260 D2: CENTRAL SEMI CMDD6263 * RESTRICTIONS APPLY FOR INPUT VOLTAGES ABOVE 42V 3641fa 23 LT3641 TYPICAL APPLICATIONS 2MHz 3V/0.8A and 0.6V/1A Buck Regulators 0.22μF D2 VIN 4V TO 42V* 4.7μF L1 3.3μH EN/UVLO VIN SW BST SW1 D1 SYNC DA FB1 WDE EN2 PGOOD2 LT3641 68.1k VOUT1 3V/0.8A 22μF 49.9k VIN2 L2 0.47μH RST1 RST2 SW2 WDO FB2 VOUT2 0.6V/1A 22μF WDI CWDT CPOR RT GND SS2 SS1 1nF 1.5nF 1.5nF 32.4k 1nF 3641 TA04 L1: VISHAY IHLP2020BZER3R3M01 L2: VISHAY IHLP1616ABERR47M01 D1: DIODES PDS360 D2: CENTRAL SEMI CMDSH2-3 * RESTRICTIONS APPLY FOR INPUT VOLTAGES ABOVE 42V 3641fa 24 LT3641 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE Package 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation EB 9.60 – 9.80* (.378 – .386) 4.75 (.187) 4.75 (.187) 28 2726 25 24 23 22 21 20 19 18 1716 15 6.60 ± 0.10 2.74 (.108) 4.50 ± 0.10 SEE NOTE 4 0.45 ± 0.05 EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 6.40 2.74 (.252) (.108) BSC 1.05 ± 0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN MILLIMETERS (INCHES) 3. DRAWING NOT TO SCALE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.25 REF 1.20 (.047) MAX 0° – 8° 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE28 (EB) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3641fa 25 LT3641 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 ± 0.05 4.50 ± 0.05 3.10 ± 0.05 2.50 REF 2.65 ± 0.05 3.65 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 3.50 REF 4.10 ± 0.05 5.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45 CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 ± 0.10 (2 SIDES) 3.50 REF 3.65 0.10 2.65 0.10 (UFD28) QFN 0506 REV B 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3641fa 26 LT3641 REVISION HISTORY REV DATE DESCRIPTION A 11/11 Added H-grade to Absolute Maximum Ratings, Order Information, and Note 2 PAGE NUMBER 2, 4 3641fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LT3641 TYPICAL APPLICATION 2MHz 3.3V/0.8A and 0.8V/1.2A Buck Regulators 0.22μF VIN 4V TO 42V* 4.7μF 3.3μH EN/UVLO VIN SW BST SW1 80.6k DA SYNC VOUT1 3.3V/0.8A 22μF FB1 49.9k EN2 PGOOD2 LT3641 VIN2 RST1 WDE RST2 SW2 0.47μH 16.5k WDO WDI VOUT2 0.8V/1.2A 22μF FB2 CWDT CPOR RT GND SS2 SS1 49.9k 1nF 32.4k 1nF 3641 TA05 * RESTRICTIONS APPLY FOR INPUT VOLTAGES ABOVE 42V RELATED PARTS PART NUMBER DESCRIPTION LT3640 35V, 55V Transient Protection, 1.3A High Voltage Channel and VIN: 4V to 35V, Transient to 55V, VOUT(MIN) = 0.6V, IQ = 290mA, 1μA, 4mm × 5mm QFN-28, TSSOP-28E Packages 1.1A Low Volume Channel COMMENTS LT3689 36V, 60V Transient Protection, 800mA, 2.2MHz High Efficiency MicroPower Step-Down DC/DC Converter with POR Reset and Watchdog Timer VIN: 3.6V to 36V, Transient to 60V, VOUT(MIN) = 0.8V, IQ = 75μA, ISD < 1μA, 3mm × 3mm QFN-16 Package LT3686/LT3686A 37V, 55VMAX, 1.2A, 2.5MHz High Efficiency Step-Down DC/ DC Converter VIN: 3.6V to 37V, Transient to 55V, VOUT(MIN) = 1.21V, IQ = 1.1mA, ISD < 1μA, 3mm × 3mm DFN-10 Package LT3682 36V, 60VMAX, 1A, 2.2MHz High Efficiency Micropower Step-Down DC/DC Converter VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 75μA, ISD < 1μA, 3mm × 3mm DFN-12 Package LT3971 38V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down DC/DC Converter with Only 2.8μA of Quiescent Current VIN: 4.2V to 38V, VOUT(MIN) = 1.2V, IQ = 2.8μA, ISD < 1μA, 3mm × 3mm DFN-10, MSOP-10E Packages LT3991 55V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down DC/DC Converter with Only 2.8μA of Quiescent Current VIN: 4.2V to 55V, VOUT(MIN) = 1.2V, IQ = 2.8μA, ISD < 1μA, 3mm × 3mm DFN-10, MSOP-10E Packages 3641fa 28 Linear Technology Corporation LT 1111 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2011