MX25L25835E MX25L25835E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1737 REV. 1.0, NOV. 29, 2011 1 MX25L25835E Contents 1. FEATURES.............................................................................................................................................................. 4 2. GENERAL DESCRIPTION..................................................................................................................................... 6 Table 1. Additional Features at each 128Mb Flash memory ......................................................................6 3. PIN CONFIGURATION............................................................................................................................................ 7 4. PIN DESCRIPTION.................................................................................................................................................. 7 5. BLOCK DIAGRAM................................................................................................................................................... 8 6. Memory Organization............................................................................................................................................. 9 Table 2. Memory Organization....................................................................................................................9 7. DEVICE OPERATION............................................................................................................................................ 10 8. DATA PROTECTION...............................................................................................................................................11 Table 3. Protected Area Sizes at each 128Mb Flash memory.................................................................12 Table 4. 4K-bit Secured OTP Definition at Each 128Mb Flash memory...................................................12 9. HOLD FEATURE.................................................................................................................................................... 13 9-1. Figure 2. Hold Condition Operation ........................................................................................................ 13 10. COMMAND DESCRIPTION................................................................................................................................. 14 Table 5. Command Sets............................................................................................................................14 10-1.Write Enable (WREN).............................................................................................................................. 17 10-2.Write Disable (WRDI).............................................................................................................................. 18 10-3.Read Identification (RDID)....................................................................................................................... 19 10-4.Read Status Register (RDSR)................................................................................................................. 20 10-5.Write Status Register (WRSR)................................................................................................................ 22 10-6.Read Data Bytes (READ)........................................................................................................................ 25 10-7.Read Data Bytes at Higher Speed (FAST_READ).................................................................................. 26 10-8.Dual Read Mode (DREAD)...................................................................................................................... 27 10-9.2 x I/O Read Mode (2READ)................................................................................................................... 28 10-10.Quad Read Mode (QREAD)................................................................................................................... 29 10-11.4 x I/O Read Mode (4READ).................................................................................................................. 30 10-12.Performance Enhance Mode................................................................................................................. 31 10-13.Performance Enhance Mode Reset (FFh)............................................................................................. 31 10-14.Burst Read............................................................................................................................................. 34 10-15.Sector Erase (SE).................................................................................................................................. 35 10-16.Block Erase (BE).................................................................................................................................... 36 10-17.Block Erase (BE32K)............................................................................................................................. 36 10-18.Chip Erase (CE)..................................................................................................................................... 37 10-19.Page Program (PP)................................................................................................................................ 38 10-20.4 x I/O Page Program (4PP).................................................................................................................. 39 10-21.Continuously program mode (CP mode)................................................................................................ 42 10-22.Deep Power-down (DP)......................................................................................................................... 44 10-23.Release from Deep Power-down (RDP), Read Electronic Signature (RES).......................................... 45 10-24.Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)........................................ 47 Table 6. ID Definitions at each 128 Mb Flash memory..............................................................................48 P/N: PM1737 REV. 1.0, NOV. 29, 2011 2 MX25L25835E 10-25.Enter Secured OTP (ENSO).................................................................................................................. 48 10-26.Exit Secured OTP (EXSO)..................................................................................................................... 48 10-27.Read Security Register (RDSCUR)....................................................................................................... 49 10-28.Write Security Register (WRSCUR)....................................................................................................... 51 10-29.Write Protection Selection (WPSEL)...................................................................................................... 51 10-30.Single Block Lock/Unlock Protection (SBLK/SBULK)............................................................................ 55 10-31.Read Block Lock Status (RDBLOCK).................................................................................................... 58 10-32.Gang Block Lock/Unlock (GBLK/GBULK).............................................................................................. 59 10-33.Clear SR Fail Flags (CLSR)................................................................................................................... 60 10-34.Enable SO to Output RY/BY# (ESRY)................................................................................................... 60 10-35.Disable SO to Output RY/BY# (DSRY).................................................................................................. 60 10-36.No Operation (NOP)............................................................................................................................... 60 10-37.Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................. 61 10-38.Read SFDP Mode (RDSFDP)................................................................................................................ 62 Table 7. Signature and Parameter Identification Data Values . ................................................................63 Table 8. Parameter Table (0): JEDEC Flash Parameter Tables................................................................64 Table 9. Parameter Table (1): Macronix Flash Parameter Tables.............................................................66 11. POWER-ON STATE............................................................................................................................................. 68 12. ELECTRICAL SPECIFICATIONS........................................................................................................................ 69 12-1.ABSOLUTE MAXIMUM RATINGS.......................................................................................................... 69 Table 10. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) . ........ 71 Table 11. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ......... 72 13. Timing Analysis.................................................................................................................................................. 74 13-1.RESET..................................................................................................................................................... 76 Table 12. Reset Timing..............................................................................................................................76 Table 13. Power-Up Timing ......................................................................................................................77 13-2.INITIAL DELIVERY STATE...................................................................................................................... 77 14. RECOMMENDED OPERATING CONDITIONS................................................................................................... 78 15. ERASE AND PROGRAMMING PERFORMANCE.............................................................................................. 80 16. DATA RETENTION.............................................................................................................................................. 80 17. LATCH-UP CHARACTERISTICS........................................................................................................................ 80 18. ORDERING INFORMATION................................................................................................................................ 81 19. PART NAME DESCRIPTION............................................................................................................................... 82 20. PACKAGE INFORMATION.................................................................................................................................. 83 21. REVISION HISTORY .......................................................................................................................................... 84 P/N: PM1737 REV. 1.0, NOV. 29, 2011 3 MX25L25835E 256M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY 111FEATURES GENERAL Stacked By Two 128Mb Flash Memories With 2 CS# • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four I/O mode) structure per 128Mb Flash memory • 4096 Equal Sectors with 4K bytes each (per 128Mb Flash memory) - Any Sector can be erased individually • 512 Equal Blocks with 32K bytes each (per 128Mb Flash memory) - Any Block can be erased individually • 256 Equal Blocks with 64K bytes each (per 128Mb Flash memory) - Any Block can be erased individually • Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance VCC = 2.7~3.6V - Normal read - 50MHz - Fast read - 1 I/O: 104MHz with 8 dummy cycles - 2 I/O: 70MHz with 4 dummy cycles for 2READ instruction; 70MHz with 8 dummy cycles for DREAD instruction - 4 I/O: 70MHz with 6 dummy cycles for 4READ instruction; 70MHz with 8 dummy cycles for QREAD instruction - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Byte program time: 12us (typical) - 8/16/32/64 byte Wrap-Around Burst Read Mode - Continuously Program mode (automatically increase address under word program mode) - Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 80s(typ.) / chip • Low Power Consumption - Low active read current: 19mA(max.) at 104MHz, 15mA(max.) at 66MHz and 10mA(max.) at 33MHz - Low active programming current: 25mA (max.) - Low active erase current: 25mA (max.) - Low standby current: 200uA (max.) - Deep power down current: 80uA (max.) • Typical 100,000 erase/program cycles • 20 years data retention P/N: PM1737 REV. 1.0, NOV. 29, 2011 4 MX25L25835E SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features Independently at each 128Mb Flash memory - BP0-BP3 block group protect - Flexible individual block protect when OTP WPSEL=1 - Additional 4K bits secured OTP for unique identifier • Auto Erase and Auto Program Algorithms - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse width (Any page to be programed should have page in the erased state first.) • Status Register Feature Independently at each 128Mb Flash memory • Electronic Identification - JEDEC 1-byte Manufacturer ID and 2-byte Device ID - RES command for 1-byte Device ID - REMS, REMS2 and REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID HARDWARE FEATURES • CS#1 & CS#2 - Both CS#1 and CS#2 are Chip Select inputs. CS#1 and CS#2 can select different 128Mb Flash memories • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O mode • HOLD#/SIO3 - To pause the device without deselecting the device or serial data Input or serial data Input/Output for 4 x I/O mode • RESET# - Hardware Reset Pin • PACKAGE - 16-pin SOP (300mil) - All devices are RoHS Compliant P/N: PM1737 REV. 1.0, NOV. 29, 2011 5 MX25L25835E 222GENERAL DESCRIPTION MX25L25835E is a 268,435,456 bits serial Flash memory, which is stacked by two 128Mb Flash memories. When it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4 for each 128Mb Flash memory. Each of 128Mb Flash memory features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. It is not allowed to access the device by enabling both CS#1 and CS#2 in the same time. As the result, two 128Mb Flash memories are independent and all the commands in COMMAND DESCRIPTION can only affect the selected 128Mb Flash memory. The terms "chip" in the Data Sheet only refer to the selected 128Mb Flash memory. MX25L25835E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on each 128Mb Flash memory and multi-I/O features. When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously Program mode. Erase command is executed on 4K-byte sector, 64Kbyte block, or each 128Mb Flash memory basis. To provide user with ease of interface, each 128 Mb Flash memory includes an independent status register to indicate the status of itself. The status read command can be issued to detect completion status of a program or erase operation via the WIP bit. When the device is not in operation and both CS#1 & CS#2 are high, the device is put in standby mode and draws less than 200uA DC current. The MX25L25835E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. TTTTTTTTTAdditional Features at each 128Mb Flash memory Additional Features Part Name MX25L25835E Protection and Security Read Performance Flexible or Individual block 4K-bit (or sector) secured OTP protection V V 1 I/O Read (104 MHz) 2 I/O Read (70 MHz) 4 I/O Read (70 MHz) Dual Read (70 MHz) Quad Read (70 MHz) V V V V V Additional Features Part Name MX25L25835E Identifier RES (command: AB hex) REMS (command: 90 hex) REMS2 (command: EF hex) REMS4 (command: DF hex) RDID (command: 9F hex) 17 (hex) C2 17 (hex) C2 17 (hex) C2 17 (hex) C2 20 18 (hex) P/N: PM1737 REV. 1.0, NOV. 29, 2011 6 MX25L25835E 444PIN DESCRIPTION 333PIN CONFIGURATION 16-PIN SOP (300mil) HOLD#/SIO3 VCC RESET# NC NC CS#2 CS#1 SO/SIO1 1 2 3 4 5 6 7 8 SYMBOL 16 15 14 13 12 11 10 9 DESCRIPTION Chip Select for First 128Mb Flash CS#1 memory Chip Select for Second 128Mb Flash CS#2 memory Serial Data Input (for 1xI/O)/ Serial Data SI/SIO0 Input & Output (for 2xI/O or 4xI/O mode) Serial Data Output (for 1xI/O)/Serial SO/SIO1 Data Input & Output (for 2xI/O or 4xI/O mode) SCLK Clock Input Write protection: connect to GND or WP#/SIO2 Serial Data Input & Output (for 4xI/O mode) To pause the device without deselecting HOLD#/ the device or Serial data Input/Output for SIO3 4 x I/O mode RESET# Hardware Reset Pin VCC + 3.3V Power Supply GND Ground NC No Connection SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2 Notes: 1. It is not allowed to enable both CS#1 and CS#2 at the same time. 2. The HOLD# and RESET# pins are internal pull high. P/N: PM1737 REV. 1.0, NOV. 29, 2011 7 MX25L25835E 555BLOCK DIAGRAM HOLD#/SIO3 RESET# HOLD#/SIO3 RESET# SCLK 128Mb Flash memory CS#2 WP#/SIO2 HOLD#/SIO3 SCLK SI/SIO0 RESET# 128Mb Flash memory CS#2 SO/SIO1 SI/SIO0 GND SO/SIO1 CS#1 SI/SIO0 SCLK CS#1 GND SO/SIO1 WP#/SIO2 P/N: PM1737 GND WP#/SIO2 REV. 1.0, NOV. 29, 2011 8 MX25L25835E 666Memory Organization TTTTTTTTTMemory Organization Block(64K-byte) Block(32K-byte) 511 255 4088 FF8000h FF8FFFh 4087 FF7000h FF7FFFh 4080 FF0000h FF0FFFh 4079 FEF000h FEFFFFh 254 FE8000h FE8FFFh 4071 FE7000h FE7FFFh FE0000h FE0FFFh … 508 4072 4064 individual block lock/unlock unit:64K-byte 31 1 24 018000h 018FFFh 23 017000h 017FFFh … 0 16 010000h 010FFFh 15 00F000h 00FFFFh 8 008000h 008FFFh 7 007000h 007FFFh 000000h 000FFFh individual 16 sectors lock/unlock unit:4K-byte … 0 0 Block(64K-byte) Block(32K-byte) Address Range Sector FFF000h FFFFFFh … 4095 511 255 4088 FF8000h FF8FFFh 4087 FF7000h FF7FFFh individual 16 sectors lock/unlock unit:4K-byte … 510 4080 FF0000h FF0FFFh 4079 FEF000h FEFFFFh … 509 254 FE8000h FE8FFFh 4071 FE7000h FE7FFFh FE0000h FE0FFFh … 508 4072 4064 individual block lock/unlock unit:64K-byte 31 3 01F000h 01FFFFh … individual block lock/unlock unit:64K-byte 01FFFFh … 1 128Mb Flash Memory with CS#2 01F000h … 3 2 individual block lock/unlock unit:64K-byte individual 16 sectors lock/unlock unit:4K-byte … 509 individual block lock/unlock unit:64K-byte FFFFFFh … 510 128Mb Flash Memory with CS#1 FFF000h … 4095 individual block lock/unlock unit:64K-byte Address Range Sector 1 018000h 018FFFh 23 017000h 017FFFh … 2 24 010000h 010FFFh 15 00F000h 00FFFFh … 1 16 0 008000h 008FFFh 7 007000h 007FFFh 000000h 000FFFh individual 16 sectors lock/unlock unit:4K-byte … 0 8 0 P/N: PM1737 REV. 1.0, NOV. 29, 2011 9 MX25L25835E MX25L25835E is stacked by two 128Mb Flash memories. It supports two CS# pins. CS#1 and CS#2 can select different 128Mb Flash memories. As the result, two 128Mb Flash memories are operating independently. It is not allowed to enable both CS#1 and CS#2 at the same time. The following three chapters (DEVICE OPERATION, DATA PROTECTION, HOLD Feature and COMMAND DESCRIPTION) will make a description of operating methods and features in each independent 128Mb Flash memory. 777DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next CS# falling edge. In standby mode, SO pin of the device is High-Z. 3. When correct command is inputted to this device, it enters active mode and remains in active mode until next CS# rising edge. 4. For standard single data rate serial mode, input data is shifted on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1. 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, DREAD, 4READ, W4READ, QREAD, RDBLOCK, RES, REMS, REMS2, and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, BE32K, CE, PP, CP, 4PP, RDP, DP, WPSEL, SBLK, SBULK, GBLK, GBULK, ENSO, EXSO, WRSCUR, ESRY, DSRY, NOP, RSTEN, RST, SBL and CLSR the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is neglected and will not affect the current operation of Write Status Register, Program, Erase. FFFFFFFFFFSerial Modes Supported (for Normal Serial mode) CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1737 REV. 1.0, NOV. 29, 2011 10 MX25L25835E 888DATA PROTECTION MX25L25835E is stacked by two 128Mb Flash memories. These two memories are independent. All the commands will only affect the selected 128Mb Flash memory. MX25L25835E is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before issuing other commands to change data. The WEL bit will return to reset stage under following situations: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP, 4PP) command completion - Continuously Program mode (CP) instruction completion - Sector Erase (SE) command completion - Block Erase (BE, BE32K) command completion - Chip Erase (CE) command completion - Single Block Lock/Unlock (SBLK/SBULK) instruction completion - Gang Block Lock/Unlock (GBLK/GBULK) instruction completion • Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Signature command (RES). I. Block lock protection at each 128Mb Flash memory - The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. - The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the system goes into four I/O mode, the feature of HPM will be disabled. - MX25L25835E provides individual block (or sector) write protect & unprotect. User may enter the mode with WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for individual block (or sector) unprotect. Under the mode, user may conduct whole chip protect with GBLK instruction and unlock the whole chip with GBULK instruction. Note: The term "chip" only refers to the selected 128Mb Flash memory. P/N: PM1737 REV. 1.0, NOV. 29, 2011 11 MX25L25835E TTTTTTTTTProtected Area Sizes at each 128Mb Flash memory Status bit Protection Area BP3 BP2 BP1 BP0 128Mb 0 0 0 0 0 (none) 0 0 0 1 1 (2 blocks, block 254th-255th) 0 0 1 0 2 (4 blocks, block 252nd-255th) 0 0 1 1 3 (8 blocks, block 248th-255th) 0 1 0 0 4 (16 blocks, block 240th-255th) 0 1 0 1 5 (32 blocks, block 224th-255th) 0 1 1 0 6 (64 blocks, block 192nd-255th) 0 1 1 1 7 (128 blocks, block 128th-255th) 1 0 0 0 8 (256 blocks, all) 1 0 0 1 9 (256 blocks, all) 1 0 1 0 10 (256 blocks, all) 1 0 1 1 11 (256 blocks, all) 1 1 0 0 12 (256 blocks, all) 1 1 0 1 13 (256 blocks, all) 1 1 1 0 14 (256 blocks, all) 1 1 1 1 15 (256 blocks, all) Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0. II. Additional 4K-bit secured OTP for unique identifier at each 128Mb Flash memory : to provide 4K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. Please refer to Table 4. 4K-bit Secured OTP Definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for security register bit definition and table of "4K-bit Secured OTP Definition at Each 128Mb Flash memory" for address range definition. Note 1: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Secured OTP mode, array access is not allowed. Note 2:The term "chip" only refers to the selected 128Mb Flash memory. TTTTTTTTT4K-bit Secured OTP Definition at Each 128Mb Flash memory Address range Size Standard Factory Lock xxx000~xxx00F 128-bit ESN (electrical serial number) xxx010~xxx1FF 3968-bit N/A P/N: PM1737 Customer Lock Determined by customer REV. 1.0, NOV. 29, 2011 12 MX25L25835E 999HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 2. 99999 Figure 2. Hold Condition Operation CS# SCLK HOLD# Hold Condition (standard) Hold Condition (non-standard) The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1737 REV. 1.0, NOV. 29, 2011 13 MX25L25835E 1111COMMAND DESCRIPTION TTTTTTTTTCommand Sets Read Commands I/O Read Mode 1 SPI 1 SPI 1 SPI Command (byte) READ (normal read) FAST READ (fast read data) RDSFDP 50 104 03 (hex) AD1(8) AD2(8) AD3(8) 0B (hex) AD1(8) AD2(8) AD3(8) Dummy(8) n bytes read out until CS# goes high Clock rate (MHz) 1st byte 2nd byte 3rd byte 4th byte 5th byte Action I/O Read Mode Command (byte) Clock rate (MHz) 1st byte 2nd byte 3rd byte 4th byte 5th byte Action n bytes read out until CS# goes high 4 SPI 4READ (4 x I/O read command) Note1 2 SPI 2READ (2 x I/O read command) Note1 2 SPI DREAD (1I / 2O read command) 4 SPI 104 70 70 54 5A (hex) AD1(8) AD2(8) AD3(8) Dummy(8) n bytes read out until CS# goes high BB (hex) AD1(4) AD2(4) AD3(4) Dummy(4) n bytes read out by 2 x I/O until CS# goes high 3B (hex) AD1(8) AD2(8) AD3(8) Dummy(8) E7 (hex) AD1(2) AD2(2) AD3(2) Dummy(4) Quad I/O read with 4 dummy cycles W4READ 4 SPI QREAD 70 70 EB (hex) AD1(2) AD2(2) AD3(2) Dummy(6) Quad I/O read with 6 dummy cycles 6B (hex) AD1(8) AD2(8) AD3(8) Dummy(8) P/N: PM1737 REV. 1.0, NOV. 29, 2011 14 MX25L25835E Other Commands Command (byte) 1st byte 2nd byte 3rd byte 4th byte Action Command (byte) 1st byte 2nd byte 3rd byte 4th byte Action Command (byte) 1st byte 2nd byte 3rd byte 4th byte Action WREN WRDI RDSR (read WRSR (write 4PP (quad SE BE 32K (block (write enable) (write disable) status register) status register) page program) (sector erase) erase 32KB) 06 (hex) 04 (hex) 05 (hex) 01 (hex) Values 38 (hex) 20 (hex) 52 (hex) AD1 AD1 AD1 AD2 AD2 AD2 AD3 AD3 AD3 sets the (WEL) resets the to read out the to write new quad input to to erase the to erase the write enable (WEL) write values of the values of the program the selected sector selected 32KB latch bit enable latch bit status register status register selected page block CP (Continuously program) D8 (hex) 60 or C7 (hex) 02 (hex) AD (hex) AD1 AD1 AD1 AD2 AD2 AD2 AD3 AD3 AD3 to erase the to erase whole to program the continuously selected 64KB chip selected page program block whole chip, the address is automatically increase BE (block erase 64KB) CE (chip erase) REMS (read RES (read electronic electronic ID) manufacturer & device ID) AB (hex) 90 (hex) x x x x x ADD (Note 2) to read out output the 1-byte Device Manufacturer ID ID & Device ID PP (page program) REMS2 (read electronic manufacturer & device ID) EF (hex) x x ADD output the Manufacturer ID & Device ID DP (Deep power down) B9 (hex) enters deep power down mode RDP (Release RDID from deep (read identificpower down) ation) AB (hex) 9F (hex) release from outputs JEDEC deep power ID: 1-byte down mode Manufacturer ID & 2-byte Device ID REMS4 (read electronic ENSO (enter manufacturer & secured OTP) device ID) DF (hex) B1 (hex) x x ADD output the to enter the Manufacturer 4K-bit secured ID & device ID OTP mode P/N: PM1737 REV. 1.0, NOV. 29, 2011 15 MX25L25835E Command (byte) EXSO (exit secured OTP) 1st byte 2nd byte 3rd byte 4th byte C1 (hex) RDSCUR (read security register) 2B (hex) to exit the 4Kbit secured OTP mode to read value of security register COMMAND (byte) GBULK (gang block unlock) NOP (No Operation) RSTEN (Reset Enable) RST (Reset Memory) 1st byte 2nd byte 3rd byte 4th byte Action 98 (hex) 00 (hex) 66 (hex) 99 (hex) Action COMMAND (byte) 1st byte 2nd byte 3rd byte 4th byte Action WRSCUR (write security register) 2F (hex) RDBLOCK SBULK (single (block protect block unlock) read) 36 (hex) 39 (hex) 3C (hex) AD1 AD1 AD1 AD2 AD2 AD2 AD3 AD3 AD3 to set the lock- individual block individual block read individual down bit as (64K-byte) or (64K-byte) or block or sector "1" (once lock- sector (4K-byte) sector (4K-byte) write protect down, cannot write protect unprotect status be update) SBLK (single block lock whole chip unprotect GBLK (gang block lock) 7E (hex) whole chip write protect WPSEL ESRY (enable SBL (Set Burst (Write Protect SO to output Length) Selection) RY/BY#) 77 (hex) 68 (hex) 70 (hex) Value to set Burst length to enter and to enable SO enable individal to output RY/ block protect BY# during CP mode mode DSRY (disable CLSR (Clear SO to output SR Fail Flags) RY/BY#) 80 (hex) 30 (hex) to disable SO clear security to output RY/ register bit 6 BY# during CP and bit 5 mode Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO1 which is different from 1 x I/O condition. Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 4: RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset. P/N: PM1737 REV. 1.0, NOV. 29, 2011 16 MX25L25835E 111111 Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, CP, SE, BE, BE32K, CE, WRSR, SBLK, SBULK, GBLK and GBULK, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. Note : CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFWrite Enable (WREN) Sequence (Command 06) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 06 High-Z SO P/N: PM1737 REV. 1.0, NOV. 29, 2011 17 MX25L25835E 111111 Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP, 4PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE, BE32K) instruction completion - Chip Erase (CE) instruction completion - Continuously Program mode (CP) instruction completion - Single Block Lock/Unlock (SBLK/SBULK) instruction completion - Gang Block Lock/Unlock (GBLK/GBULK) instruction completion Note : CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFWrite Disable (WRDI) Sequence (Command 04) CS# 0 1 2 3 4 5 6 7 SCLK Command SI SO 04 High-Z P/N: PM1737 REV. 1.0, NOV. 29, 2011 18 MX25L25835E 111111 Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix's Manufacturer ID and Device ID are listed as Table 6. ID Definitions at each 128 Mb Flash memory. The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out on SO→ to end RDID operation can use CS# to high at any time during data out. While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. Note : CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFRead Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer Identification SO High-Z Device Identification D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 MSB D3 D2 D1 D0 MSB P/N: PM1737 REV. 1.0, NOV. 29, 2011 19 MX25L25835E 111111 Read Status Register (RDSR) The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data out on SO. FFFFFFFFFFRead Status Register (RDSR) Sequence (Command 05) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05 SI SO High-Z Status Register Out D7 D6 D5 D4 D3 D2 D1 D0 MSB P/N: PM1737 REV. 1.0, NOV. 29, 2011 20 MX25L25835E The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and will reset WEL bit if it is applied to a protected memory area. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in Table 3) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. Status Register bit7 bit6 SRWD (status register write protect) QE (Quad Enable) 1= Quad 1=status Enable register write 0=not Quad disable Enable Non-volatile Non-volatile bit bit bit5 BP3 (level of protected block) bit4 BP2 (level of protected block) bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) (note 1) (note 1) Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation volatile bit volatile bit Note 1: see the Table 3 "Protected Area Size". Note 2: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. P/N: PM1737 REV. 1.0, NOV. 29, 2011 21 MX25L25835E 111111 Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in Table 3). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the statur register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register data on SI→ CS# goes high. FFFFFFFFFFWrite Status Register (WRSR) Sequence (Command 01) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI SO command Status Register In 01 D7 D6 D5 D4 D3 D2 D1 D0 MSB High-Z P/N: PM1737 REV. 1.0, NOV. 29, 2011 22 MX25L25835E The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP3 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 3. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note 1: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. Note 2: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system goes into four I/O mode, the feature of HPM will be disabled. P/N: PM1737 REV. 1.0, NOV. 29, 2011 23 MX25L25835E FFFFFFFFFFWRSR flow start WREN command RDSR command WREN=1? No Yes WRSR command Write status register data RDSR command WIP=0? No Yes RDSR command Read WEL=0, BP[3:0], QE, and SRWD data Verify OK? No Yes WRSR successfully WRSR fail P/N: PM1737 REV. 1.0, NOV. 29, 2011 24 MX25L25835E 111111 Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address on SI →data out on SO→ to end READ operation can use CS# to high at any time during data out. Note : CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFRead Data Bytes (READ) Sequence (Command 03) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command SI 03 24 ADD Cycles A23 A22 A21 A3 A2 A1 A0 MSB SO Data Out 1 High-Z Data Out 2 D7 D6 D5 D4 D3 D2 D1 D0 D7 MSB P/N: PM1737 MSB REV. 1.0, NOV. 29, 2011 25 MX25L25835E 111111 Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low→sending FAST_READ instruction code→3-byte address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Note : CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected FFFFFFFFFFRead at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Command SI SO 0B 8 Dummy Cycles 24 ADD Cycles A23 A22 A21 A3 A2 A1 A0 Data Out 1 High-Z Data Out 2 D7 D6 D5 D4 D3 D2 D1 D0 D7 MSB P/N: PM1737 REV. 1.0, NOV. 29, 2011 26 MX25L25835E 111111 Dual Read Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte address on SIO0→ 8-bit dummy cycle on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Note : CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFDual Read Mode Sequence (Command 3B) CS# 0 1 2 3 4 5 6 7 8 SCLK } Command SI/SIO0 SO/SIO1 30 31 32 9 3B } 24 ADD Cycle A23 A22 } 39 40 41 42 43 44 45 A1 A0 High Impedance 8 dummy cycle Data Out 1 Data Out 2 D6 D4 D2 D0 D6 D4 D7 D5 D3 D1 D7 D5 P/N: PM1737 REV. 1.0, NOV. 29, 2011 27 MX25L25835E 111111 2 x I/O Read Mode (2READ) The 2READ instruction enables double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end 2READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Note : CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFF2 x I/O Read Mode Sequence (Command BB) CS# 0 1 2 3 4 5 6 7 8 Command SI/SIO0 SO/SIO1 18 19 20 21 22 23 24 25 26 27 28 29 9 SCLK BB(hex) High Impedance 12 ADD Cycle 4 dummy cycle Data Out 1 Data Out 2 A22 A21 A2 A0 P2 P0 D6 D4 D2 D0 D6 D4 A23 A20 A3 A1 P3 P1 D7 D5 D3 D1 D7 D5 P/N: PM1737 REV. 1.0, NOV. 29, 2011 28 MX25L25835E 1111111 Quad Read Mode (QREAD) The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFQuad Read Mode Sequence (Command 6B) CS# 0 1 2 3 4 5 6 7 8 SCLK … Command SI/SO0 SO/SO1 WP#/SO2 HOLD#/SO3 29 30 31 32 33 9 6B … 24 ADD Cycles A23 A22 … High Impedance 38 39 40 41 42 A2 A1 A0 8 dummy cycles Data Data Out 1 Out 2 Data Out 3 D4 D0 D4 D0 D4 D5 D1 D5 D1 D5 High Impedance D6 D2 D6 D2 D6 High Impedance D7 D3 D7 D3 D7 P/N: PM1737 REV. 1.0, NOV. 29, 2011 29 MX25L25835E 11111114 x I/O Read Mode (4READ) The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before seding the 4READ instruction.The address is latched on rising edge of SCLK, and data of every four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. FFFFFFFFFFF4 x I/O Read Mode Sequence (Command EB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SCLK Command SI/SIO0 SO/SIO1 WP#/SIO2 NC/SIO3 EB High Impedance High Impedance High Impedance 6 ADD Cycles Performance Enhance Indicator (Note1, 2) 4 dummy cycles Data Data Out 1 Out 2 Data Out 3 A20 A16 A12 A8 A4 A0 P4 P0 D4 D0 D4 D0 D4 A21 A17 A13 A9 A5 A1 P5 P1 D5 D1 D5 D1 D5 A22 A18 A14 A10 A6 A2 P6 P2 D6 D2 D6 D2 D6 A23 A19 A15 A11 A7 A3 P7 P3 D7 D3 D7 D3 D7 Note: 1. Hi-impedance is inhibited for the two clock cycles. 2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode. P/N: PM1737 REV. 1.0, NOV. 29, 2011 30 MX25L25835E While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. 1111111 Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note Figure 14. 4 x I/O Read enhance performance mode sequence) Please be noticed that “EBh” “E7h” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of the first clock as address instead of command cycle. To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue ”FFh” command to exit enhance mode. Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending 4READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4Read instruction) → 24-bit random access address (Please refer to Figure 14. 4 x I/O Read Enhance Performance Mode Sequence). In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h. These commands will reset the performance enhance mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. 1111111 Performance Enhance Mode Reset (FFh) To conduct the Performance Enhance Mode Reset operation, FFh command code, 8 clocks, should be issued in 1I/ O sequence. If the system controller is being Reset during operation, the flash device will return to the standard SPI operation. Upon Reset of main chip, SPI instruction would be issued from the system. Instructions like Read ID (9Fh) or Fast Read (0Bh) would be issued. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. P/N: PM1737 REV. 1.0, NOV. 29, 2011 31 MX25L25835E FFFFFFFFFFF4 x I/O Read Enhance Performance Mode Sequence (Command EB) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 n SCLK 8 Bit Instruction WP#/SIO2 HOLD#/SIO3 Performance enhance indicator (Note) 4 dummy cycles Data Output address bit20, bit16..bit0 P4 P0 data bit4, bit0, bit4.... High Impedance address bit21, bit17..bit1 P5 P1 data bit5 bit1, bit5.... High Impedance address bit22, bit18..bit2 P6 P2 data bit6 bit2, bit6.... High Impedance address bit23, bit19..bit3 P7 P3 data bit7 bit3, bit7.... EBh SI/SIO0 SO/SIO1 6 Address cycles CS# n+1 ........... n+7 ...... n+9 ........... n+13 ........... SCLK 6 Address cycles Performance enhance indicator (Note) 4 dummy cycles Data Output SI/SIO0 address bit20, bit16..bit0 P4 P0 data bit4, bit0, bit4.... SO/SIO1 address bit21, bit17..bit1 P5 P1 data bit5 bit1, bit5.... WP#/SIO2 address bit22, bit18..bit2 P6 P2 data bit6 bit2, bit6.... HOLD#/SIO3 address bit23, bit19..bit3 P7 P3 data bit7 bit3, bit7.... Note: Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF P/N: PM1737 REV. 1.0, NOV. 29, 2011 32 MX25L25835E FFFFFFFFFFFPerformance Enhance Mode Reset for Fast Read Quad I/O Mode Bit Reset for Quad I/O CS# Mode 3 SCLK ０ 1 2 3 4 5 6 Mode 3 7 Mode ０ Mode ０ SIO0 FFh SIO1 Don’t Care SIO2 Don’t Care SIO3 Don’t Care P/N: PM1737 REV. 1.0, NOV. 29, 2011 33 MX25L25835E 1111111 Burst Read To set the Burst length, following command operation is required Issuing command: “77h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and disable with“1h”. Next 4 clocks is to define wrap around depth. Definition as following table: Data 1xh 1xh 1xh 1xh Wrap Around No No No No Wrap Depth X X X X Data 00h 01h 02h 03h Wrap Around Yes Yes Yes Yes Wrap Depth 8-byte 16-byte 32-byte 64-byte The wrap around unit is defined within the 256Byte page, with random initial address. It’s defined as “wrap-around mode disable” for the default state of the device. To exit wrap around, it is required to issue another “77” command in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change wrap around depth, it is requried to issue another “77” command in which data=“0xh”. SPI “EBh” “E7h” support wrap around feature after wrap around enable. The Device ID default without Burst read. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFBurst Read CS# 0 1 2 1 1 0 3 4 5 6 7 8 9 0 0 0 0 H H 10 11 12 13 H L L 14 15 SCLK SIO 0 P/N: PM1737 H L L REV. 1.0, NOV. 29, 2011 34 MX25L25835E 1111111 Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (Table 2) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the address byte been latchedin); otherwise, the instruction will be rejected and not executed. The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI →CS# goes high. The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. Note : CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFSector Erase (SE) Sequence (Command 20) CS# 0 1 2 3 4 5 6 7 8 9 SCLK … 24 ADD Cycles Command SI 29 30 31 A23 A22 20 … A2 A1 A0 MSB P/N: PM1737 REV. 1.0, NOV. 29, 2011 35 MX25L25835E 1111111 Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Table 2) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI → CS# goes high. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. 1111111 Block Erase (BE32K) The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (Table 2) is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 3-byte address on SI → CS# goes high. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit still be reset. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFBlock Erase (BE/EB32K) Sequence (Command D8/52) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 ADD Cycles Command SI D8/52 A23 A22 A2 A1 A0 MSB P/N: PM1737 REV. 1.0, NOV. 29, 2011 36 MX25L25835E 1111111 Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE timing, and clears 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the chip is protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset. Note 1: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. Note 2:Due to two 128 Flash memories are independent, Chip Erase instruction can only affect on the se128Mb Flash memory. The term "chip" only refers to the selected 128Mb Flash memory. FFFFFFFFFFFChip Erase (CE) Sequence (Command 60 or C7) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60 or C7 P/N: PM1737 REV. 1.0, NOV. 29, 2011 37 MX25L25835E 1111111 Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (the eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the requested page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFPage Program (PP) Sequence (Command 02) 2079 2078 2077 2076 2075 2074 28 29 30 31 32 33 34 35 36 37 38 39 2073 0 1 2 3 4 5 6 7 8 9 10 2072 CS# SCLK Command SI 02 24 ADD Cycles A23 A22 A21 MSB A3 A2 A1 A0 Data Byte 1 Data Byte 256 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB P/N: PM1737 REV. 1.0, NOV. 29, 2011 38 MX25L25835E 1111111 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3, which can raise programer performance and and the effectiveness of application of lower clock less than 20MHz. For system with faster clock, the Quad page program cannot provide more performance, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 20MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFF4 x I/O Page Program (4PP) Sequence (Command 38) CS# 0 1 2 3 4 5 6 7 8 524 525 9 10 11 12 13 14 15 16 17 SCLK Command 6 ADD cycles Data Byte 256 Data Data Byte 1 Byte 2 A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 D4 D0 SO/SIO1 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 D5 D1 WP#/SIO2 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 D6 D2 NC/SIO3 A23 A19 A15 A11 A7 A3 D7 D3 D7 D3 D7 D3 SI/SIO0 38 P/N: PM1737 REV. 1.0, NOV. 29, 2011 39 MX25L25835E The Program/Erase function instruction function flow is as follows: FFFFFFFFFFFProgram/Erase Flow(1) with read array data Start WREN command RDSR command* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command No WIP=0? Yes Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase fail Program/erase successfully CLSR(30h) command Program/erase another block? No Yes * * Issue RDSR to check BP[3:0]. * If WPSEL=1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1737 REV. 1.0, NOV. 29, 2011 40 MX25L25835E FFFFFFFFFFFProgram/Erase Flow(2) without read array data Start WREN command RDSR command* WREN=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command No WIP=0? Yes RDSCUR command P_FAIL/E_FAIL=1? Yes No Program/erase fail Program/erase successfully CLSR(30h) command Program/erase another block? No Yes * Issue RDSR to check BP[3:0]. * If WPSEL=1, issue RDBLOCK to check the block status. Program/erase completed P/N: PM1737 REV. 1.0, NOV. 29, 2011 41 MX25L25835E 1111111 Continuously program mode (CP mode) The CP mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction must execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0. The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 3-byte address on SI pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes are programmed → CS# goes high to low -> till last desired two data bytes are programmed → CS# goes high to low →sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. Three methods to detect the completion of a program cycle during CP mode: 1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode. 2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not. 3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the ESRY/DSRY commands are not accepted unless the completion of CP mode. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no change) and the WEL bit will still be reset. Note 1: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. Note 2: The term "chip" only refers to the selected 128Mb Flash memory. P/N: PM1737 REV. 1.0, NOV. 29, 2011 42 MX25L25835E FFFFFFFFFFFContinously Program (CP) Mode Sequence with Hardware Detection (Command AD) CS# 0 1 6 7 8 9 30 31 31 32 47 48 0 1 6 7 8 20 21 22 23 24 0 7 0 7 8 SCLK Command SI S0 AD (hex) 24-bit address data in Byte 0, Byte1 Valid Command (1) high impedance data in Byte n-1, Byte n 04 (hex) 05 (hex) status (2) Notes: (1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). (2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS# goes high will return the SO pin to tri-state. (3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) command (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP mode is ended. P/N: PM1737 REV. 1.0, NOV. 29, 2011 43 MX25L25835E 1111111 Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFF Deep Power-down (DP) Sequence (Command B9) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command SI B9 Stand-by Mode P/N: PM1737 Deep Power-down Mode REV. 1.0, NOV. 29, 2011 44 MX25L25835E 1111111 Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 11. Once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 6. ID Definitions at each 128Mb Flash memory. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current program/erase/write cycles in progress. The sequence is shown as Figure 26 & Figure 27. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power-down Mode. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFRelease from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command SI AB tRES2 24 ADD Cycles A23 A22 A21 … A3 A2 A1 A0 MSB SO Electronic Signature Out High-Z D7 D6 D5 D4 D3 D2 D1 D0 MSB Deep Power-down Mode P/N: PM1737 Stand-by Mode REV. 1.0, NOV. 29, 2011 45 MX25L25835E FFFFFFFFFFFRelease from Deep Power-down (RDP) Sequence (Command AB) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI SO AB High-Z Deep Power-down Mode P/N: PM1737 Stand-by Mode REV. 1.0, NOV. 29, 2011 46 MX25L25835E 1111111 Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) The REMS, REMS2 and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 28. The Device ID values are listed in Table 6. ID Definitions at each 128 Mb Flash memory. If the one-byte address is initially set to 01h, then the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFRead Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF) CS# 0 1 2 3 4 5 6 7 8 9 10 SCLK Command SI SO 90 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 24 ADD Cycles A23 A22 A21 A3 A2 A1 A0 Manufacturer ID High-Z Device ID D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB MSB MSB Notes: 1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 is don't care. 2. Instruction is either 90(hex) or EF(hex) or DF(hex). P/N: PM1737 REV. 1.0, NOV. 29, 2011 47 MX25L25835E TTTTTTTTTID Definitions at each 128 Mb Flash memory Command Type RDID MX25L25835E manufacturer ID C2 RES REMS/REMS2/REMS4 manufacturer ID C2 memory type 20 electronic ID 17 device ID 17 memory density 18 1111111 Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. While device is in 4K-bit Secured OTP mode, array access is not available. The additional 4K-bit Secured OTP is independent from main array, and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Please note that WRSR/WRSCUR/RDSFDP/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not acceptable during the access of secure OTP region, once Security OTP is lock down, only read related commands are valid. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. 1111111 Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. P/N: PM1737 REV. 1.0, NOV. 29, 2011 48 MX25L25835E 1111111 Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→ send ing RDSCUR instruction → Security Register data out on SO→ CS# goes high. FFFFFFFFFFFRead Security Register (RDSCUR) Sequence (Command 2B) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 2B SI SO High-Z Security Register Out 7 6 5 4 3 2 1 Security Register Out 0 7 6 5 4 3 2 1 0 7 MSB MSB The definition of the Security Register is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be updated any more. Continuously Program Mode (CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can indicate whether one or more of program operations fail, and can be reset by command CLSR (30h) Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate whether one or more of erase operations fail, and can be reset by command CLSR (30h) Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully. Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits. Note 1: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. Note 2: The term "chip" only refers to the selected 128Mb Flash memory. P/N: PM1737 REV. 1.0, NOV. 29, 2011 49 MX25L25835E Security Register Definition at Each 128Mb Flash memory bit7 bit6 bit5 WPSEL E_FAIL P_FAIL 0=normal WP mode 1=individual WP mode (default=0) 0=normal Erase succeed 1=indicate Erase failed (default=0) 0=normal Program succeed 1=indicate Program failed (default=0) non-volatile bit volatile bit OTP Read Only bit4 Continuously Program mode (CP mode) bit3 bit2 x x 0=normal Program mode 1=CP mode (default=0) reserved reserved volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit Read Only Read Only Read Only Read Only OTP Read Only P/N: PM1737 bit1 bit0 LDSO (lock-down 4K-bit 4K-bit Se- Secured OTP cured OTP) 0 = not lockdown 0 = nonfactory 1 = locklock down 1 = factory (cannot lock program/ erase OTP) REV. 1.0, NOV. 29, 2011 50 MX25L25835E 1111111 Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFWrite Security Register (WRSCUR) Sequence (Command 2F) CS# 0 1 2 3 4 5 6 7 SCLK Command SI SO 2F High-Z 1111111 Write Protection Selection (WPSEL) There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0, flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on BP mode, the individual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode is disabled. Every time after the system is powered-on, the Security Register bit 7 is checked. If WPSEL=1, then all the blocks and sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and GBULK instructions. Program or erase functions can only be operated after the Unlock instruction is executed. BP protection mode, WPSEL=0: ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7 of status register that can be set by WRSR command. Individual block protection mode, WPSEL=1: Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, the bit 7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block methods.Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. P/N: PM1737 REV. 1.0, NOV. 29, 2011 51 MX25L25835E Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits. The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual block protect mode → CS# goes high. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFWrite Protection Selection (WPSEL) Sequence (Command 68) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 68 WPSEL instruction function flow is as follows: FFFFFFFFFFFBP and SRWD if WPSEL=0 WP# pin BP3 BP2 BP1 BP0 SRWD 64KB 64KB (1) BP3~BP0 is used to define the protection group region. (The protected area size see Table2) 64KB (2) “SRWD=1 and WPB=0” is used to protect BP3~BP0. In this case, SRWD and BP3~BP0 of status register bits can not be changed by WRSR . . . 64KB P/N: PM1737 REV. 1.0, NOV. 29, 2011 52 MX25L25835E FFFFFFFFFFFThe individual block lock mode is effective after setting WPSEL=1 SRAM SRAM … … TOP 4KBx16 Sectors 4KB 4KB 4KB SRAM SRAM … 64KB SRAM … …… Uniform 64KB blocks 64KB SRAM … … Bottom 4KBx16 Sectors 4KB 4KB SRAM • Power-Up: All SRAM bits=1 (all blocks are default protected). All array cannot be programmed/erased • SBLK/SBULK (36h/39h): - SBLK (36h): Set SRAM bit=1 (protect) : array can not be programmed /erased - SBULK(39h): Set SRAM bit=0 (unprotect): array can be programmed /erased - All top 4KBx16 sectors and bottom 4KBx16 sectors and other 64KB uniform blocks can be protected and unprotected SRAM bits individually by SBLK/SBULK command set. • GBLK/ GBULK(7Eh/98h): - GBLK(7Eh):Set all SRAM bits=1,whole chip are protected and cannot be programmed / erased. - GBULK(98h):Set all SRAM bits=0,whole chip are unprotected and can be programmed / erased. - All sectors and blocks SRAM bits of whole chip can be protected and unprotected at one time by GBLK/GBULK command set. • RDBLOCK(3Ch): - use RDBLOCK mode to check the SRAM bits status after SBULK /SBLK/GBULK/GBLK command set. SBULK / SBLK / GBULK / GBLK / RDBLOCK Note: The term "chip" only refers to the selected 128Mb Flash memory. P/N: PM1737 REV. 1.0, NOV. 29, 2011 53 MX25L25835E FFFFFFFFFFFWPSEL Flow start RDSCUR(2Bh) command Yes WPSEL=1? No WPSEL disable, block protected by BP[3:0] WPSEL(68h) command RDSR command WIP=0? No Yes RDSCUR(2Bh) command WPSEL=1? No Yes WPSEL set successfully WPSEL set fail WPSEL enable. Block protected by individual lock (SBLK, SBULK, … etc). P/N: PM1737 REV. 1.0, NOV. 29, 2011 54 MX25L25835E 1111111 Single Block Lock/Unlock Protection (SBLK/SBULK) These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a specified block (or sector) of memory, using A23-A16 or (A23-A12) address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK). The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction → send 3 address bytes assign one block (or sector) to be protected on SI pin → CS# goes high. The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFSingle Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 Bit Address Cycles Command SI 36/39 A23 A22 A2 A1 A0 MSB P/N: PM1737 REV. 1.0, NOV. 29, 2011 55 MX25L25835E SBLK/SBULK instruction function flow is as follows: FFFFFFFFFFFBlock Lock Flow Start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBLK command ( 36h + 24bit address ) RDSR command WIP=0? No Yes RDBLOCK command ( 3Ch + 24bit address ) Data = FFh ? No Yes Block lock successfully Lock another block? Block lock fail Yes No Block lock completed P/N: PM1737 REV. 1.0, NOV. 29, 2011 56 MX25L25835E FFFFFFFFFFFBlock Unlock Flow start RDSCUR(2Bh) command WPSEL=1? No WPSEL command Yes WREN command SBULK command ( 39h + 24bit address ) RDSR command No WIP=0? Yes Unlock another block? Yes Unlock block completed? P/N: PM1737 REV. 1.0, NOV. 29, 2011 57 MX25L25835E 1111111 Read Block Lock Status (RDBLOCK) This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of protection lock of a specified block (or sector), using A23-A16 (or A23-A12) address bits to assign a 64K bytes block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3 address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFRead Block Protection Lock Status (RDBLOCK) Sequence (Command 3C) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command SI 3C 24 ADD Cycles A23 A22 A21 A3 A2 A1 A0 MSB SO Block Protection Lock status out High-Z D7 D6 D5 D4 D3 D2 D1 D0 MSB P/N: PM1737 REV. 1.0, NOV. 29, 2011 58 MX25L25835E 1111111 Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction → CS# goes high. The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. Note 1: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. Note 2: The term "chip" only refers to the selected 128Mb Flash memory. FFFFFFFFFFFGang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 7E/98 P/N: PM1737 REV. 1.0, NOV. 29, 2011 59 MX25L25835E 1111111 Clear SR Fail Flags (CLSR) The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed before program/erase another block during programing/erasing flow without read array data. The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. 1111111 Enable SO to Output RY/BY# (ESRY) The ESRY instruction is for outputting the ready/busy status to SO during CP mode. The sequence of issuing ESRY instruction is: CS# goes low → sending ESRY instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. 1111111 Disable SO to Output RY/BY# (DSRY) The DSRY instruction is for resetting ESRY during CP mode. The ready/busy status will not output to SO after DSRY issued. The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. 1111111 No Operation (NOP) The No Operation command only cancels a Reset Enable command. NOP has no impact on any other command. P/N: PM1737 REV. 1.0, NOV. 29, 2011 60 MX25L25835E 1111111 Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Reset operation is used as a system (software) reset that puts the device in normal operating Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). To reset the device, the host drives CS# low, sends the Reset-Enable command (66H), and drives CS# high. Next, the host drives CS# low again, sends the Reset command (99H), and drives CS# high. The Reset operation requires the Reset-Enable command followed by the Reset command. Any command other than the Reset command after the Reset-Enable command will disable the Reset-Enable. A successful command execution will reset the device to SPI stand-by read mode, which are their respective default states. A device reset during an active Program or Erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. Depending on the prior operation, the reset timing may vary. Recovery from a Write operation requires more latency time than recovery from other operations. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFSoftware Reset Recovery Stand-by Mode CS# 66 99 tRCR tRCP tRCE Mode tRCR: 200ns (Recovery Time from Read) tRCP: 20us (Recovery Time from Program) tRCE: 12ms (Recovery Time from Erase) P/N: PM1737 REV. 1.0, NOV. 29, 2011 61 MX25L25835E 1111111 Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→send RDSFDP instruction (5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS# to high at any time during data out. SFDP is a standard of JEDEC. JESD216. v1.0. Note: CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. FFFFFFFFFFFRead Serial Flash Discoverable Parameter (RDSFDP) Sequence (Command 5A) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 4 3 2 1 0 7 MSB MSB P/N: PM1737 6 5 4 3 2 1 0 7 MSB REV. 1.0, NOV. 29, 2011 62 MX25L25835E TTTTTTTTTSignature and Parameter Identification Data Values Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (Byte) (Bit) (h/b) note1 00h 07:00 53h Data (h) 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h 05h 15:08 01h 01h Number of Parameter Headers Start from 00h Contains 0xFFh and can never be changed 00h: it indicates a JEDEC specified header. 06h 23:16 01h 01h 07h 31:24 FFh FFh 08h 07:00 00h 00h Start from 0x00h 09h 15:08 00h 00h Start from 0x01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh 10h 07:00 C2h C2h Start from 0x00h 11h 15:08 00h 00h Start from 0x01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) Unused First address of JEDEC Flash Parameter table Contains 0xFFh and can never be changed it indicates Macronix manufacturer ID First address of Macronix Flash Parameter table Contains 0xFFh and can never be changed P/N: PM1737 REV. 1.0, NOV. 29, 2011 63 MX25L25835E TTTTTTTTTParameter Table (0): JEDEC Flash Parameter Tables Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not suport 4KB erase Write Granularity Write Enable Instruction Requested for Writing to Volatile Status Registers Add (h) DW Add Data (Byte) (Bit) (h/b) note1 01:00 01b 0: 1Byte, 1: 64Byte or larger 02 1b 0: Nonvolatitle status bit 1: Volatitle status bit (BP status register bit) 03 0b 30h 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode 31h Data (h) E5h 04 0b 07:05 111b 15:08 20h 16 1b 18:17 00b 19 0b 20 1b 20h (1-1-2) Fast Read (Note2) 0=not support 1=support Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved (1-2-2) Fast Read 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 1b (1-1-4) Fast Read 0=not support 1=support 22 1b 23 1b 33h 31:24 FFh 37h:34h 31:00 0FFFFFFFh 0=not support 1=support 32h Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states (Note3) Clocks) not support (1-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits (Note4) 38h (1-4-4) Fast Read Opcode 39h (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Ah (1-1-4) Fast Read Opcode 3Bh P/N: PM1737 04:00 0 0100b 07:05 010b 15:08 EBh 20:16 0 1000b 23:21 000b 31:24 6Bh F1h FFh 44h EBh 08h 6Bh REV. 1.0, NOV. 29, 2011 64 MX25L25835E Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of 000b: Mode Bits not support Mode Bits Add (h) DW Add Data (Byte) (Bit) (h/b) note1 3Ch (1-1-2) Fast Read Opcode 3Dh (1-2-2) Fast Read Number of Wait 0 0000b: Wait states(Dummy Clocks) states not support (1-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Eh (1-2-2) Fast Read Opcode 3Fh (2-2-2) Fast Read 0=not support 1=support Unused (4-4-4) Fast Read 0=not support 1=support 40h Unused 04:00 0 1000b 07:05 000b 15:08 3Bh 20:16 0 0100b 23:21 000b 31:24 BBh 00 0b 03:01 111b 04 0b 07:05 111b Data (h) 08h 3Bh 04h BBh EEh Unused 43h : 41h 31:08 FFFFFFh 0xFFh Unused 45h:44h 15:00 FFFFh 0xFFh 20:16 0 0000b 23:21 000b (2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (2-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 46h (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh 49h:48h 15:00 FFFFh 0xFFh 20:16 0 0000b 23:21 000b Unused 00h (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 4Ah (4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 0Fh 0Fh 4Fh 31:24 52h 52h 50h 07:00 10h 10h 51h 15:08 D8h D8h 52h 23:16 00h 00h 53h 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type don't exist Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type don't exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type don't exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type don't exist Sector Type 4 erase Opcode P/N: PM1737 00h REV. 1.0, NOV. 29, 2011 65 MX25L25835E TTTTTTTTTParameter Table (1): Macronix Flash Parameter Tables Description Comment Add (h) DW Add Data (Byte) (Bit) (h/b) note1 Data (h) Vcc Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 61h:60h 15:00 3600h 3600h Vcc Supply Minimum Voltage 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 63h:62h 31:16 2700h 2700h HW Reset# pin 0=not support 1=support 00 1b HW Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b SW Reset 0=not support 1=support 03 1b SW Reset Opcode Should be issue Reset Enable (66h) before Reset cmd. Program Suspend/Resume 0=not support 1=support 12 0b Erase Suspend/Resume 0=not support 1=support 13 0b 14 1b 15 1b 66h 23:16 77h 77h 67h 31:24 64h 64h 65h:64h Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode 11:04 1001 1001b C99Fh (99h) Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support 1=support 00 1b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 0b 09:02 0011 0110b (36h) 10 0b 11 1b Individual block lock Opcode Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not support 1=support Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 FFh FFh [31:00] 0xFFh 0xFFh Unused 6Bh:68h 6Fh:6Ch P/N: PM1737 C8D9h REV. 1.0, NOV. 29, 2011 66 MX25L25835E Note 1:h/b is hexadecimal or binary. Note 2:(x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3:Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4:Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5:4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6:Memory within the SFDP address space that has not yet been defined or used, default to all 0xFFh. Note 7:SFDP, this feature was reserved previously. This parameters (data) have been released and able to be utilized after being approved by BOD of JEDEC. P/N: PM1737 REV. 1.0, NOV. 29, 2011 67 MX25L25835E 1111POWER-ON STATE The device is at the following states after power-up: - Standby mode ( please note it is not Deep Power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage until the VCC reaches the following levels: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) P/N: PM1737 REV. 1.0, NOV. 29, 2011 68 MX25L25835E 1111ELECTRICAL SPECIFICATIONS 111111 ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Industrial grade -40°C to 85°C Storage Temperature -65°C to 150°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2.Specifications contained within the following tables are subject to change. 3.During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure below. FFFFFFFFFFFMaximum Positive Overshoot Waveform FFFFFFFFFFFMaximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25°C, f = 1.0 MHz SYMBOL PARAMETER CIN COUT MIN. TYP MAX. UNIT Input Capacitance 30 pF VIN = 0V Output Capacitance 30 pF VOUT = 0V P/N: PM1737 CONDITIONS REV. 1.0, NOV. 29, 2011 69 MX25L25835E FFFFFFFFFFFINPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level 0.8VCC 0.7VCC 0.3VCC 0.2VCC Output timing referance level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are <5ns FFFFFFFFFFFOUTPUT LOADING DEVICE UNDER TEST 2.7K ohm CL 6.2K ohm +3.3V DIODES=IN3064 OR EQUIVALENT CL=30/15pF Including jig capacitance P/N: PM1737 REV. 1.0, NOV. 29, 2011 70 MX25L25835E TTTTTTTTTTDC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) SYMBOL PARAMETER NOTES MIN. MAX. ILI Input Load Current 1 ±2 ILO Output Leakage Current 1 ±2 ISB1 VCC Standby Current 1 200 ISB2 Deep Power-down Current ICC1 VCC Read VIL VCC Program Current (PP) VCC Write Status Register (WRSR) Current VCC Sector Erase Current (SE) VCC Chip Erase Current (CE) Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage ICC2 ICC3 ICC4 ICC5 UNITS TEST CONDITIONS VCC = VCC Max, uA VIN = VCC or GND VCC = VCC Max, uA VOUT = VCC or GND uA VIN = VCC or GND, CS# = VCC 80 uA VIN = VCC or GND, CS# = VCC 22 mA fQ=70MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 19 mA f=104MHz SCLK=0.1VCC/0.9VCC, SO=Open 17 mA fT=70MHz (2 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 15 mA f=66MHz SCLK=0.1VCC/0.9VCC, SO=Open 10 mA f=33MHz, SCLK=0.1VCC/0.9VCC, SO=Open 25 mA Program in Progress, CS# = VCC 25 mA Program status register in progress, CS#=VCC 1 25 mA Erase in Progress, CS#=VCC 1 25 mA Erase in Progress, CS#=VCC 0.8 V 1 1 -0.5 0.7VCC VCC+0.4 0.4 VCC-0.2 V V IOL = 1.6mA V IOH = -100uA Notes : 1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds). 2.Typical value is calculated by simulation. 3.The value guaranteed by characterization, not 100% tested in production. 4.The term "chip" only refers to the selected 128Mb Flash memory. P/N: PM1737 REV. 1.0, NOV. 29, 2011 71 MX25L25835E TTTTTTTTTTAC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) Symbol Alt. Parameter fSCLK fC fRSCLK fR fT fQ fTSCLK f4PP tCH(1) tCLH tCL(1) tCLL tCLCH tCHCL tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tCSS tDSU tDH tSHSL(3) tCSH tSHQZ tDIS tHLCH tCHHH tHHCH tCHHL tHHQX tLZ tHLQZ tHZ tCLQV tV Min. Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR Clock Frequency for READ instructions Clock Frequency for 2READ/DREAD instructions Clock Frequency for 4READ/QREAD instructions (4) Clock Frequency for 4PP (Quad page program) Fast_Read Clock High Time Read Fast_Read Clock Low Time Read Clock Rise Time (3) (peak to peak) Clock Fall Time (3) (peak to peak) CS# Active Setup Time (relative to SCLK) CS# Not Active Hold Time (relative to SCLK) Data In Setup Time Data In Hold Time CS# Active Hold Time (relative to SCLK) CS# Not Active Setup Time (relative to SCLK) Read CS# Deselect Time Write/Erase/ Program 2.7V-3.6V Output Disable Time 3.0V-3.6V HOLD# Setup Time (relative to SCLK) HOLD# Hold Time (relative to SCLK) HOLD Setup Time (relative to SCLK) HOLD Hold Time (relative to SCLK) 2.7V-3.6V HOLD to Output Low-Z Loading=30pF 3.0V-3.6V 2.7V-3.6V HOLD# to Output High-Z Loading=30pF 3.0V-3.6V 1 I/O Loading: 10pF 2 I/O & 4 I/O Clock Low to Output Valid 1 I/O Loading: 15pF VCC=2.7V~3.6V 2 I/O & 4 I/O Loading: 30pF 1 I/O 2 I/O & 4 I/O tCLQX tHO Output Hold Time tWHSL(4) Write Protect Setup Time tSHWL(4) Write Protect Hold Time tDP CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature tRES1 Read CS# High to Standby Mode with Electronic Signature tRES2 Read P/N: PM1737 D.C. 4.5 9 4.5 9 0.1 0.1 5 5 2 3 5 5 15 Typ. Max. Unit 104 MHz 50 70 70/54 70 MHz MHz MHz MHz ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns 50 5 5 5 5 1 20 100 ns 10 8 10 8 10 8 5 ns ns ns ns ns ns ns ns ns ns ns 7.5 ns 6 8 7 8 10 ns ns ns ns ns ns ns us 100 us 100 us REV. 1.0, NOV. 29, 2011 72 MX25L25835E Symbol tW tBP tPP tSE tBE tBE tCE tWPS tWSR Alt. Parameter Write Status Register Cycle Time Byte-Program Page Program Cycle Time Sector Erase Cycle Time (4KB) Block Erase Cycle Time (32KB) Block Erase Cycle Time (64KB) Chip Erase Cycle Time Write Protection Selection Time Write Security Register Time Min. Typ. 40 12 1.4 60 0.5 0.7 80 Max. 100 300 5 300 2 2 200 1 1 Unit ms us ms ms s s s ms ms Notes: 1. tCH + tCL must be greater than or equal to 1/ fC. 2. The value guaranteed by characterization, not 100% tested in production. 3.Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 4. When dummy cycle=4, clock rate is 54MHz; When dummy cycle=6, clock rate is 70MHz. 5.CS# might be CS#1 or CS#2. It depends on which 128Mb Flash memory is selected. 6. The term "chip" only refers to the selected 128Mb Flash memory. P/N: PM1737 REV. 1.0, NOV. 29, 2011 73 MX25L25835E 1111Timing Analysis FFFFFFFFFFFSerial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO FFFFFFFFFFFOutput Timing CS# tCH SCLK tCLQV tCLQX tCL tCLQV tCLQX LSB SO SI tSHQZ ADDR.LSB IN P/N: PM1737 REV. 1.0, NOV. 29, 2011 74 MX25L25835E FFFFFFFFFFFHold Timing CS# tHLCH tCHHL tHHCH SCLK tCHHH tHLQZ tHHQX SO HOLD# FFFFFFFFFFFWP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01 SI SO High-Z P/N: PM1737 REV. 1.0, NOV. 29, 2011 75 MX25L25835E 111111 RESET Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After the reset cycle, the device is at the following state: - Standby mode - All the volatile bit such as WEL/WIP/SRAM lock bit will return to the default state as power on. If the device is under the programming or erasing, driving the reset# pin low will also terminate the operation and data could be lost. During the reset cycle, the SO data becomes high impedance and the current will be reduced to minimum. FFFFFFFFFFFRESET Timing CS# RESET# tRH tRS tRLRH tRHSL TTTTTTTTTTReset Timing Symbol tRLRH tRS tRH tRHSL Parameter Reset pulse width Reset set time Reset hold time Reset recovery time from read Reset recovery time from program Reset recovery time from erase Reset recovery time from WRSR Min. 10 15 15 Typ. Max. 200 20 20 tW Unit us ns ns ns us ms ms Notes: tW is the write status register cycle time. P/N: PM1737 REV. 1.0, NOV. 29, 2011 76 MX25L25835E FFFFFFFFFFFPower-up Timing VCC VCC(max) Chip Selection is Not Allowed (Note2) VCC(min) tVSL Device is fully accessible time Note 1: VCC (max.) is 3.6V and VCC (min.) is 2.7V. Note 2: All the chips should not be selected during Power-up. TTTTTTTTTTPower-Up Timing Symbol tVSL(1) Parameter VCC(min) to CS# low Min. 300 Max. Unit us Note: 1. The parameter is characterized only. 111111 INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1737 REV. 1.0, NOV. 29, 2011 77 MX25L25835E 1111RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure 52 and Figure 53 are for the supply voltages and the control signals at device powerup and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Notes: 1.CS# means both CS#1 and CS#2. FFFFFFFFFFFAC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tSHCH tCHSH SCLK tDVCH tCHCL tCHDX LSB IN MSB IN SI High Impedance SO Symbol tVR tCLCH Parameter VCC Rise Time Notes 1 Min. 20 Max. 500000 Unit us/V Notes: 1.Sampled, not 100% tested. 2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. 3. In Figure 52, CS# means both CS#1 and CS#2. P/N: PM1737 REV. 1.0, NOV. 29, 2011 78 MX25L25835E FFFFFFFFFFFPower-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK Notes: 1. In Figure 53, CS# means both CS#1 and CS#2. P/N: PM1737 REV. 1.0, NOV. 29, 2011 79 MX25L25835E 1111ERASE AND PROGRAMMING PERFORMANCE PARAMETER Write Status Register Cycle Time Sector Erase Time (4KB) Block Erase Time (32KB) Block Erase Time (64KB) Chip Erase Time Byte Program Time (via page program command) Page Program Time Erase/Program Cycle TYP. (1) 40 60 0.5 0.7 80 12 1.4 100,000 Max. (2) 100 300 2 2 200 300 5 UNIT ms ms s s s us ms cycles Notes: 1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern. 2. Under worst conditions of 85°C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. The term "chip" only refers to the selected 128Mb Flash memory. 1111DATA RETENTION PARAMETER Condition Min. Data retention 55˚C 20 Max. UNIT years 1111LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1737 MIN. -1.0V -1.0V -100mA MAX. 2 VCCmax VCC + 1.0V +100mA REV. 1.0, NOV. 29, 2011 80 MX25L25835E 1111ORDERING INFORMATION PART NO. MX25L25835EMI-10G CLOCK (MHz) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (uA) TEMPERATURE PACKAGE Remark 104 19 200 -40°C~85°C 16-SOP (300mil) RoHS Compliant P/N: PM1737 REV. 1.0, NOV. 29, 2011 81 MX25L25835E 1111PART NAME DESCRIPTION MX 25 L 25835E M I 10 G OPTION: G: RoHS Compliant SPEED: 10: 104MHz TEMPERATURE RANGE: I: Industrial (-40C to 85°C) PACKAGE: M: 300mil 16-SOP DENSITY & MODE: 25835E: 256Mb TYPE: L: 3V DEVICE: 25: Serial Flash P/N: PM1737 REV. 1.0, NOV. 29, 2011 82 MX25L25835E 2222PACKAGE INFORMATION P/N: PM1737 REV. 1.0, NOV. 29, 2011 83 MX25L25835E 2222REVISION HISTORY Revision No. Description 1.0 1. Removed "Advanced Information" Page P4 P/N: PM1737 Date NOV/29/2011 REV. 1.0, NOV. 29, 2011 84 MX25L25835E Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2011. All rights reserved. Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, NBiit, Macronix NBit, eLiteFlash, XtraROM, Phines, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE are trademarks or registered trademarks of Macronix International Co., Ltd. The names and brands of other companies are for identification purposes only and may be claimed as the property of the respective companies. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com 85