MX25R4035F, Wide Range, 4Mb, v1.2

MX25R4035F
MX25R4035F
ULTRA LOW POWER, 4M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Ultra Low Power Mode and High Performance Mode
• Wide Range VCC 1.65V-3.6V for Read, Erase and Program Operations
• Unique ID and Secure OTP Support
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Program Suspend/Resume & Erase Suspend/Resume
P/N: PM2222
1
REV. 1.2, NOV. 19, 2015
MX25R4035F
Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 6
Table 1. Additional Feature...........................................................................................................................7
3. PIN CONFIGURATIONS .......................................................................................................................................... 8
4. PIN DESCRIPTION................................................................................................................................................... 8
5. BLOCK DIAGRAM.................................................................................................................................................... 9
6. DATA PROTECTION............................................................................................................................................... 10
Table 2. Protected Area Sizes.................................................................................................................... 11
Table 3. 8K-bit Secured OTP Definition.....................................................................................................12
7. MEMORY ORGANIZATION.................................................................................................................................... 13
Table 4. Memory Organization...................................................................................................................13
8. DEVICE OPERATION............................................................................................................................................. 14
9. HOLD FEATURE..................................................................................................................................................... 16
10. COMMAND DESCRIPTION.................................................................................................................................. 17
Table 5. Command Set...............................................................................................................................17
10-1. Write Enable (WREN)............................................................................................................................... 20
10-2. Write Disable (WRDI)................................................................................................................................ 21
10-3. Read Identification (RDID)........................................................................................................................ 22
10-4. Read Electronic Signature (RES)............................................................................................................. 23
10-5. Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 24
10-6. ID Read..................................................................................................................................................... 25
Table 6. ID Definitions ...............................................................................................................................25
10-7. Read Status Register (RDSR).................................................................................................................. 26
10-8. Read Configuration Register (RDCR)....................................................................................................... 31
10-9. Write Status Register (WRSR).................................................................................................................. 32
Table 7. Protection Modes..........................................................................................................................33
10-10.Read Data Bytes (READ)......................................................................................................................... 36
10-11. Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 37
10-12.Dual Read Mode (DREAD)....................................................................................................................... 38
10-13.2 x I/O Read Mode (2READ).................................................................................................................... 39
10-14.Quad Read Mode (QREAD)..................................................................................................................... 40
10-15.4 x I/O Read Mode (4READ).................................................................................................................... 41
10-16.Burst Read................................................................................................................................................ 43
10-17.Performance Enhance Mode.................................................................................................................... 44
10-18.Sector Erase (SE)..................................................................................................................................... 46
10-19.Block Erase (BE32K)................................................................................................................................ 47
10-20.Block Erase (BE)...................................................................................................................................... 48
10-21.Chip Erase (CE)........................................................................................................................................ 49
10-22.Page Program (PP).................................................................................................................................. 50
10-23.4 x I/O Page Program (4PP)..................................................................................................................... 51
10-24.Deep Power-down (DP)............................................................................................................................ 52
10-25.Enter Secured OTP (ENSO)..................................................................................................................... 53
P/N: PM2222
2
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-26.Exit Secured OTP (EXSO)........................................................................................................................ 53
10-27.Read Security Register (RDSCUR).......................................................................................................... 53
Table 8. Security Register Definition..........................................................................................................54
10-28.Write Security Register (WRSCUR).......................................................................................................... 54
10-29.Program/Erase Suspend/Resume............................................................................................................ 55
Table 9. Readable Area of Memory While a Program or Erase Operation is Suspended..........................55
Table 10. Acceptable Commands During Program/Erase Suspend after tPSL/tESL.................................55
Table 11. Acceptable Commands During Suspend (tPSL/tESL not required)............................................56
10-30.Program Resume and Erase Resume...................................................................................................... 57
10-31.No Operation (NOP)................................................................................................................................. 58
10-32.Software Reset (Reset-Enable (RSTEN) and Reset (RST)).................................................................... 58
10-33.High Voltage Operation............................................................................................................................. 60
10-34.Read SFDP Mode (RDSFDP)................................................................................................................... 61
11. RESET................................................................................................................................................................... 62
Table 12. Reset Timing-(Power On)...........................................................................................................62
Table 13. Reset Timing-(Other Operation).................................................................................................62
12. POWER-ON STATE.............................................................................................................................................. 63
13. ELECTRICAL SPECIFICATIONS......................................................................................................................... 64
Table 14. Absolute Maximum Ratings........................................................................................................64
Table 15. Capacitance................................................................................................................................64
Table 16. DC Characteristics......................................................................................................................66
Table 17. AC Characteristics .....................................................................................................................68
14. OPERATING CONDITIONS.................................................................................................................................. 72
Table 18. Power-Up/Down Voltage and Timing..........................................................................................74
14-1. Initial Delivery State.................................................................................................................................. 74
15. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 75
16. LATCH-UP CHARACTERISTICS......................................................................................................................... 76
17. ORDERING INFORMATION................................................................................................................................. 77
18. PART NAME DESCRIPTION................................................................................................................................ 78
19. PACKAGE INFORMATION................................................................................................................................... 79
20. REVISION HISTORY ............................................................................................................................................ 84
P/N: PM2222
3
REV. 1.2, NOV. 19, 2015
MX25R4035F
Ultra Low Power 4M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 4,194,304 x 1 bit structure or 2,097,152 x 2 bits (two I/O mode) structure or 1048,576 x 4 bits (four I/O mode)
structure
• Equal Sectors with 4K byte each, or Equal Blocks with 32K/64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- Operation Voltage: 1.65V-3.6V for Read, Erase and Program Operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 104MHz with 4 dummy cycles, equivalent to 208MHz
- 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz
- Fast program and erase time
- 8/16/32/64 byte Wrap-Around Burst Read Mode
• Ultra Low Power Consumption
• Minimum 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase
instructions
• Additional 8K bits secured OTP
- Features unique identifier.
- Factory locked identifiable and customer lockable
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector or block
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Command Reset
• Program/Erase Suspend and Program/Erase Resume
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
• Support Unique ID (Please contact local Macronix sales for detail information)
P/N: PM2222
4
REV. 1.2, NOV. 19, 2015
MX25R4035F
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
• RESET#/SIO3 * or HOLD#/SIO3 *
- Hardware Reset pin or Serial input & Output for 4 x I/O read mode
or
- HOLD feature, to pause the device without deselecting the device or Serial input & Output for 4 x I/O read mode
* Depends on part number options
• PACKAGE
- 8-pin SOP (150mil/200mil)
- 8-land USON (2x3mm)
- 8-land WSON (6x5mm)
- 8-ball WLCSP (3-2-3 Ball Array)
- All devices are RoHS Compliant and Halogen-free
P/N: PM2222
5
REV. 1.2, NOV. 19, 2015
MX25R4035F
2. GENERAL DESCRIPTION
MX25R4035F is 4Mb bits Serial NOR Flash memory, which is configured as 524,288 x 8 internally. When it is in
four I/O mode, the structure becomes 1048,576 bits x 4 or 2,097,152 bits x 2.
MX25R4035F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus
while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial
data output (SO). Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits
input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and RESET#/HOLD# pin
become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25R4035F MXSMIO® (Serial Multi I/O) provides sequential read operation on the whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis. Erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or
whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
The MX25R4035F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
P/N: PM2222
6
REV. 1.2, NOV. 19, 2015
MX25R4035F
Table 1. Additional Feature
Protection and Security
MX25R4035F
Flexible Block Protection (BP0-BP3)
V
8K-bit security OTP
V
Fast Read
Performance
I/O
Dummy Cycle
Frequency
P/N: PM2222
Ultra Low Power Mode
(Configuration Register-2 bit1= 0)
High Performance Mode
(Configuration Register-2 bit1= 1)
1 I/O
1I/2O
2 I/O
1I/4O
4 I/O
1 I/O
1I/2O
2 I/O
1I/4O
4 I/O
8
8
4
8
6
8
8
4
8
6
33MHz
16MHz
16MHz
16MHz
16MHz 104MHz 104MHz 104MHz 104MHz 104MHz
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MX25R4035F
3. PIN CONFIGURATIONS
4. PIN DESCRIPTION
8-PIN SOP (150mil/200mil)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
8
7
6
5
SYMBOL
CS#
DESCRIPTION
Chip Select
Serial Data Input (for 1 x I/O)/ Serial
SI/SIO0
Data Input & Output (for 4xI/O read
mode)
Serial Data Output (for 1 x I/O)/ Serial
SO/SIO1
Data Input & Output (for 4xI/O read
mode)
SCLK
Clock Input
Write Protection Active Low or Serial
WP#/SIO2 Data Input & Output (for 4xI/O read
mode)
Hardware Reset Pin Active low or
RESET#/SIO3 * Serial Data Input & Output (for 4xI/O
read mode)
To pause the device without
HOLD#/SIO3 * deselecting the device or Serial Data
Input & Output (for 4xI/O read mode)
VCC
Power Supply
GND
Ground
VCC
RESET#/SIO3 * or HOLD#/SIO3 *
SCLK
SI/SIO0
8-LAND USON (2x3mm), WSON (6x5mm)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
8
7
6
5
VCC
RESET#/SIO3 * or HOLD#/SIO3 *
SCLK
SI/SIO0
3-2-3 Ball Array 8-BALL BGA (WLCSP) TOP View
1
2
* Depends on part number options.
3
Note:
1. RESET#, HOLD# and WP# with internal pull high
A
CS#
VCC
B
GND
C
RESET#/SIO3*
Dor HOLD#/SIO3* SO/SIO1
SI/SIO0
E
SCLK
circuit.
WP#/SIO2
* Depends on part number options.
P/N: PM2222
8
REV. 1.2, NOV. 19, 2015
MX25R4035F
5. BLOCK DIAGRAM
X-Decoder
Address
Generator
SI/SIO0
SO/SIO1
SIO2 *
SIO3 *
WP# *
RESET# *
HOLD# *
CS#
SCLK
Memory Array
Y-Decoder
Data
Register
Sense
Amplifier
SRAM
Buffer
Mode
Logic
State
Machine
HV
Generator
Clock Generator
Output
Buffer
* Depends on part number options.
P/N: PM2222
9
REV. 1.2, NOV. 19, 2015
MX25R4035F
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise.
• Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may
protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
issuing other commands to change data.
• Deep Power Down Mode: By entering deep power down mode, the flash device is under protected from writing
all commands except toggling the CS#. For more detail please see "10-24. Deep Power-down (DP)".
• Advanced Security Features: there are some protection and security features which protect content from
inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status
Register Write Protect (SRWD) bit. If the system goes into four I/O mode, the feature of HPM will be disabled.
P/N: PM2222
10
REV. 1.2, NOV. 19, 2015
MX25R4035F
Table 2. Protected Area Sizes
Protected Area Sizes (TB bit = 0)
Status bit
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protected Area Sizes (TB bit = 1)
Status bit
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protect Level
0 (none)
1 (1block, block 7th)
2 (2blocks, block 6th-7th)
3 (4blocks, block 4th-7th)
4 (8blocks, protect all)
5 (8blocks, protect all)
6 (8blocks, protect all)
7 (8blocks, protect all)
8 (8blocks, protect all)
9 (8blocks, protect all)
10 (8blocks, protect all)
11 (8blocks, protect all)
12 (8blocks, protect all)
13 (8blocks, protect all)
14 (8blocks, protect all)
15 (8blocks, protect all)
Protect Level
0 (none)
1 (1block, block 0th)
2 (2blocks, block 0th-1th)
3 (4blocks, block 0th-3th)
4 (8blocks, protect all)
5 (8blocks, protect all)
6 (8blocks, protect all)
7 (8blocks, protect all)
8 (8blocks, protect all)
9 (8blocks, protect all)
10 (8blocks, protect all)
11 (8blocks, protect all)
12 (8blocks, protect all)
13 (8blocks, protect all)
14 (8blocks, protect all)
15 (8blocks, protect all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1,
BP0) are 0.
P/N: PM2222
11
REV. 1.2, NOV. 19, 2015
MX25R4035F
II. Additional 8K-bit secured OTP for unique identifier: to provide 8K-bit One-Time Program area for setting
device unique serial number - Which may be set by factory or system maker.
The 8K-bit secured OTP area is composed of two rows of 4K-bit. Customer could lock the first 4K-bit OTP
area and factory could lock the other.
- Security register bit 0 indicates whether the 2nd 4K-bit is locked by factory or not.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Table 8. Security Register Definition"
for security register bit definition and table of "Table 3. 8K-bit Secured OTP Definition" for address range
definition.
- To program 8K-bit secured OTP by entering secured OTP mode (with ENSO command), and going through
normal program procedure, and then exiting secured OTP mode by writing EXSO command.
Note: Once lock-down whatever by factory or customer, the corresponding secured area cannot be changed any
more. While in 8K-bit Secured OTP mode, array access is not allowed.
Table 3. 8K-bit Secured OTP Definition
Address range
Size
Lock-down
xxx000~xxx1FF
4096-bit
Determined by Customer
xxx200~xxx3FF
4096-bit
Determined by Factory
P/N: PM2222
12
REV. 1.2, NOV. 19, 2015
MX25R4035F
7. MEMORY ORGANIZATION
Table 4. Memory Organization
Block
(64KB)
Block
(32KB)
7
15
|
14
6
13
|
12
5
11
|
10
4
9
|
8
3
7
|
6
2
5
|
4
1
3
|
2
0
1
|
0
P/N: PM2222
Sector
(4KB)
127
:
112
111
:
96
95
:
80
79
:
64
63
:
48
47
:
32
31
:
16
15
:
2
1
0
Address Range
07F000h
:
070000h
06F000h
:
060000h
05F000h
:
050000h
04F000h
:
040000h
03F000h
:
030000h
02F000h
:
020000h
01F000h
:
010000h
00F000h
:
002000h
001000h
000000h
07FFFFh
:
070FFFh
06FFFFh
:
060FFFh
05FFFFh
:
050FFFh
04FFFFh
:
040FFFh
03FFFFh
:
030FFFh
02FFFFh
:
020FFFh
01FFFFh
:
010FFFh
00FFFFh
:
002FFFh
001FFFh
000FFFh
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MX25R4035F
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until
next CS# falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters active mode and remains in active mode until next
CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDCR, RDSCUR, READ, FAST_READ, DREAD, 2READ, 4READ,
QREAD, RDSFDP, RES, REMS, the shifted-in instruction sequence is followed by a data-out sequence. After
any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE,
BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, SUSPEND, RESUME, NOP, RSTEN, RST, the CS#
must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6.While a Write Status Register, Program or Erase operation is in progress, access to the memory array is
neglected and will not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM2222
14
REV. 1.2, NOV. 19, 2015
MX25R4035F
Figure 2. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 3. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tCLQX
LSB
SO
SI
P/N: PM2222
tSHQZ
ADDR.LSB IN
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REV. 1.2, NOV. 19, 2015
MX25R4035F
9. HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select (CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial
Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low).
≈
SI/SIO0
≈ ≈
SO/SIO1
(internal)
SO/SIO1
(External)
Don’t care
Valid Data
Valid Data
High_Z
Bit 6
Bit 5
Bit 6
≈
≈ ≈
SO/SIO1
(internal)
SO/SIO1
(External)
High_Z
Bit 7
Bit 5
≈
≈
SI/SIO0
≈
HOLD#
≈ ≈
SCLK
Valid Data
Bit 6
Bit 7
CS#
Don’t care
Bit 7
≈
HOLD#
≈ ≈
SCLK
≈
CS#
≈
Figure 4. Hold Condition Operation
Don’t care
Valid Data
Bit 7
Bit 7
Valid Data
Bit 6
High_Z
Don’t care
Bit 5
Bit 6
Bit 5
Valid Data
Bit 4
High_Z
Bit 3
Bit 4
Bit 3
During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will keep
high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK) and
Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip Select (CS#) drives
high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the
HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
P/N: PM2222
16
REV. 1.2, NOV. 19, 2015
MX25R4035F
10. COMMAND DESCRIPTION
Table 5. Command Set
Read/Write Array Commands
I/O
1
1
2
2
DREAD
(1I / 2O read
command)
3B (hex)
ADD1
1st byte
03 (hex)
0B (hex)
2READ
(2 x I/O read
command)
BB (hex)
2nd byte
ADD1
ADD1
ADD1
Command
(byte)
READ
FAST READ
(normal read) (fast read data)
4
4
4READ
(4 x I/O read)
QREAD
(1I/4O read)
EB (hex)
6B (hex)
ADD1
ADD1
3rd byte
ADD2
ADD2
ADD2
ADD2
ADD2
ADD2
4th byte
ADD3
ADD3
ADD3
ADD3
ADD3
ADD3
Action
n bytes read
out until CS#
goes high
Dummy
n bytes read
out until CS#
goes high
I/O
1
4
Command
(byte)
PP
(page program)
1st byte
02 (hex)
4PP
(quad page
program)
38 (hex)
2nd byte
ADD1
3rd byte
ADD2
4th byte
ADD3
5th byte
Dummy
Dummy
Dummy
Dummy
n bytes read
n bytes read Quad I/O read n bytes read
out by 2 x I/O
out by Dual with 6 dummy out by Quad
output until
until CS# goes Output until
cycles
CS# goes high
high
CS# goes high
1
1
1
20 (hex)
BE 32K
(block erase
32KB)
52 (hex)
BE
(block erase
64KB)
D8 (hex)
ADD1
ADD1
ADD1
ADD1
ADD1
ADD2
ADD2
ADD2
ADD2
ADD2
ADD3
ADD3
ADD3
ADD3
SE
(sector erase)
1
1
CE
(chip erase)
RDSFDP
(Read SFDP)
60 or C7 (hex)
5A (hex)
ADD3
5th byte
Action
P/N: PM2222
to program the quad input to
to erase the
to erase the
to erase the to erase whole
chip
selected page program the selected sector selected 32KB selected block
selected page
block
17
Dummy
Read SFDP
mode
REV. 1.2, NOV. 19, 2015
MX25R4035F
Register/Setting Commands
Command
(byte)
WREN
(write enable)
WRDI
(write disable)
RDSR
(read status
register)
RDCR (read
configuration
register)
WRSR
(write status
register)
1st byte
06 (hex)
04 (hex)
05 (hex)
15 (hex)
01 (hex)
2nd byte
Values
3rd byte
Values
4th byte
Values
PGM/ERS
Suspend
(Suspends
Program/Erase)
75 or B0 (hex)
5th byte
Action
Command
(byte)
1st byte
sets the (WEL) resets the (WEL)
write enable latch write enable latch
bit
bit
PGM/ERS
Resume
(Resumes
Program/Erase)
7A or 30 (hex)
to read out the
values of the
status register
DP
(Deep power
down)
SBL
(Set Burst Length)
B9 (hex)
C0 (hex)
2nd byte
to read out the
values of the
configuration
register -1 &
configuration
register -2
to write new
values of the
configuration/
status register
program/erase
operation is
interrupted
by suspend
command
Value
3rd byte
4th byte
5th byte
Action
P/N: PM2222
to continue
performing the
suspended
program/erase
sequence
enters deep
power down
mode
to set Burst length
18
REV. 1.2, NOV. 19, 2015
MX25R4035F
ID/Reset Commands
Command
(byte)
1st byte
RDID
RES (read
(read identificelectronic ID)
ation)
9F (hex)
AB (hex)
REMS (read
RDSCUR
WRSCUR
electronic
ENSO (enter EXSO (exit
(read security (write security
manufacturer secured OTP) secured OTP)
register)
register)
& device ID)
90 (hex)
B1 (hex)
C1 (hex)
2B (hex)
2F (hex)
2nd byte
x
x
3rd byte
x
x
4th byte
x
ADD (Note 1)
5th byte
Action
COMMAND
(byte)
1st byte
outputs JEDEC to read out
output the
to enter the
to exit the
to read value to set the lockID: 1-byte
1-byte Device Manufacturer 8K-bit secured 8K-bit secured of security
down bit as
Manufacturer
ID
ID & Device ID OTP mode
OTP mode
register
"1" (once lockID & 2-byte
down, cannot
Device ID
be update)
NOP
RSTEN
(No Operation) (Reset Enable)
00 (hex)
66 (hex)
RST
(Reset
Memory)
99 (hex)
Release Read
Enhanced
FF (hex)
2nd byte
3rd byte
4th byte
5th byte
Action
All these
commands
FFh, 00h, AAh
or 55h will
escape the
performance
mode
(Note 3)
Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the
hidden mode.
Note 3: The RSTEN command must be executed before executing the RST command. If any other command is issued
in-between RSTEN and RST, the RST command will be ignored.
P/N: PM2222
19
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-1.Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
The SIO[3:1] are "don't care" .
Figure 5. Write Enable (WREN) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
SO
P/N: PM2222
06h
High-Z
20
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-2.Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
The SIO[3:1] are "don't care".
The WEL bit is reset by following situations:
- Power-up
- Reset# pin driven low
- Completion of Write Disable (WRDI) instruction - Completion of Write Status Register (WRSR) instruction
- Completion of Page Program (PP) instruction
- Completion of Quad Page Program (4PP) instruction
- Completion of Sector Erase (SE) instruction
- Completion of Block Erase 32KB (BE32K) instruction
- Completion of Block Erase (BE) instruction
- Completion of Chip Erase (CE) instruction
- Program/Erase Suspend
- Completion of Softreset command
- Completion of Write Security Register (WRSCUR) command
Figure 6. Write Disable (WRDI) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
Command
SI
SO
P/N: PM2222
04h
High-Z
21
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-3.Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix
Manufacturer ID and Device ID are listed as "Table 6. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 7. Read Identification (RDID) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Mode 0
Command
SI
9Fh
Manufacturer Identification
SO
High-Z
7
6
5
3
MSB
P/N: PM2222
2
1
Device Identification
0 15 14 13
3
2
1
0
MSB
22
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-4.Read Electronic Signature (RES)
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6.
ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction.
The SIO[3:1] are "don't care".
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly
if continuously send the additional clock cycles on SCLK while CS# is at low.
Figure 8. Read Electronic Signature (RES) Sequence
CS#
Mode 3 0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Mode 0
Command
SI
ABh
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
P/N: PM2222
23
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-5.Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values
are listed in "Table 6. ID Definitions".
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two
dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Macronix (C2h) and the device
ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte is 00h,
the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will
be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Figure 9. Read Electronic Manufacturer & Device ID (REMS) Sequence
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
4
5
6
7
8
Command
SI
9 10
2 Dummy Bytes
15 14 13
90h
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
7
6
5
4
3
2
1
Device ID
0
7
6
5
4
3
2
MSB
MSB
1
0
7
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
P/N: PM2222
24
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-6.ID Read
User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issuing
RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out on SO→ to end RDID
operation can drive CS# to high at any time during data out.
After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,
memory type, and device ID data byte will be output continuously, until the CS# goes high.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Table 6. ID Definitions
Command Type
Command
RDID
9Fh
RES
ABh
REMS
90h
P/N: PM2222
MX25R4035F
Manufacturer ID
C2
Manufacturer ID
C2
Memory type
28
Electronic ID
13
Device ID
13
25
Memory density
13
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-7.Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
The SIO[3:1] are "don't care".
Figure 10. Read Status Register (RDSR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
05h
SI
SO
High-Z
Status Register Out
7
6
5
4
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2222
3
Status Register Out
26
REV. 1.2, NOV. 19, 2015
MX25R4035F
For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 11. Program/Erase flow with read array data
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Read array data
(same address of PGM/ERS)
Verify OK?
No
Yes
Program/erase successfully
Program/erase
another block?
Program/erase fail
Yes
* Issue RDSR to check BP[3:0].
No
Program/erase completed
P/N: PM2222
27
REV. 1.2, NOV. 19, 2015
MX25R4035F
Figure 12. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
start
WREN command
RDSR command*
WEL=1?
No
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
RDSCUR command
Yes
P_FAIL/E_FAIL =1 ?
No
Program/erase fail
Program/erase successfully
Program/erase
another block?
No
Yes
* Issue RDSR to check BP[3:0].
Program/erase completed
P/N: PM2222
28
REV. 1.2, NOV. 19, 2015
MX25R4035F
Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit is a volatile bit that is set to “1” by the WREN instruction. WEL needs to be
set to “1” before the device can accept program and erase instructions, otherwise the program and erase instructions
are ignored. WEL automatically clears to “0” when a program or erase operation completes. To ensure that both WIP
and WEL are “0” and the device is ready for the next program or erase operation, it is recommended that WIP be
confirmed to be “0” before checking that WEL is also “0”. If a program or erase instruction is applied to a protected
memory area, the instruction will be ignored and WEL will clear to “0”.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware
protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR)
instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector
Erase (SE), Block Erase (BE/BE32K) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0,
the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default, which is un-protected.
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#,
RESET#/HOLD# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET#/HOLD# are disabled.
In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET/HOLD will be
disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection
(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The
SRWD bit defaults to be "0".
Status Register
bit7
SRWD (status
register write
protect)
bit6
QE
(Quad
Enable)
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
1=Quad
1=status
Enable
register write
(note 1)
(note 1)
0=not Quad
disable
Enable
Non-volatile Non-volatile Non-volatile Non-volatile
bit
bit
bit
bit
Note 1: see the "Table 2. Protected Area Sizes".
P/N: PM2222
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
(note 1)
(note 1)
Non-volatile
bit
Non-volatile
bit
29
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
REV. 1.2, NOV. 19, 2015
MX25R4035F
Configuration Register
The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured
after the CR bit is set.
TB bit
The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect
area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”,
which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory
device. To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.
L/H switch bit
The Low Power / High Performance bit is a volatile bit. User can change the value of L/H switch bit to keep Ultra
Low Power mode or High Performance mode. Please check Ordering Information for the L/H Switch default
support.
Configuration Register - 1
bit7
bit6
Reserved
Reserved
Reserved
Reserved
x
x
x
x
x
x
x
x
bit3
TB
(top/bottom
selected)
0=Top area
protect
1=Bottom
area protect
(Default=0)
OTP
bit5
Reserved
bit4
Reserved
bit3
Reserved
bit2
Reserved
Configuration Register - 2
bit7
bit6
Reserved
Reserved
bit5
bit4
bit2
bit1
bit0
Reserved
Reserved
Reserved
x
x
x
x
x
x
bit1
L/H Switch
0 = Ultra Low
power mode
1 = High
performance
mode
Volatile bit
bit0
Reserved
x
x
x
x
x
x
x
x
x
x
x
x
P/N: PM2222
30
x
x
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-8.Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read
at any time (even in program/erase/write configuration register condition). It is recommended to check the Write
in Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register
operation is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration
Register data out on SO.
The SIO[3:1] are don't care.
Figure 13. Read Configuration Register (RDCR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Mode 0
command
15h
SI
SO
High-Z
Configuration register-1 Out
Configuration register-2 Out
7
7
6
5
4
2
1
0
6
5
4
3
2
1
0
7
MSB
MSB
P/N: PM2222
3
31
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-9.Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2,
BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR
also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in
accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status
register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits, 16 bits or 24 bits data boundary; otherwise, the instruction will be
rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select
(CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in
progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the
Write Enable Latch (WEL) bit is reset. Please note that there is another parameter, "Write Status Register cycle time
for Mode Changing Switching (tWMS)", which is only for the self-timed of Mode Switching. For more detail please
check "Table 17. AC Characteristics".
Figure 14. Write Status Register (WRSR) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
Mode 0
SI
SO
P/N: PM2222
command
01h
High-Z
Configuration
Register -1 In
Status
Register In
7
6
5
4
3
2
1
0 15 14 13 12 11 10 9
Configuration
Register -2 In
8 23 22 21 20 19 18 17 16
MSB
32
REV. 1.2, NOV. 19, 2015
MX25R4035F
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software
protected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can
use software protected mode via BP3, BP2, BP1, BP0.
Table 7. Protection Modes
Mode
Software protection
mode (SPM)
Hardware protection
mode (HPM)
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
The SRWD, BP0-BP3 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2. Protected Area Sizes".
P/N: PM2222
33
REV. 1.2, NOV. 19, 2015
MX25R4035F
Figure 15. WRSR flow
start
WREN command
RDSR command
WEL=1?
No
Yes
WRSR command
Write status register
data
RDSR command
WIP=0?
No
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Verify OK?
No
Yes
WRSR successfully
P/N: PM2222
WRSR fail
34
REV. 1.2, NOV. 19, 2015
MX25R4035F
Figure 16. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01h
SI
SO
High-Z
Note: WP# must be kept high until the embedded operation finish.
P/N: PM2222
35
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-10. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on
SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.
Figure 17. Read Data Bytes (READ) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Mode 0
SI
command
03h
24-Bit Address
23 22 21
3
2
1
0
MSB
SO
Data Out 1
High-Z
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
P/N: PM2222
36
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-11.Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation
can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 18. Read at Higher Speed (FAST_READ) Sequence
CS#
SCLK
Mode 3
0
1
2
Mode 0
3
5
6
7
8
9 10
Command
SI
SO
4
28 29 30 31
24-Bit Address
23 22 21
0Bh
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
4
2
1
0
7
MSB
MSB
P/N: PM2222
3
37
6
5
4
3
2
1
0
7
MSB
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-12. Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched on
rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at
a maximum frequency fT. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation can use CS# to
high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 19. Dual Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
…
Command
SI/SIO0
SO/SIO1
P/N: PM2222
30 31 32
9
SCLK
3B
…
24 ADD Cycle
A23 A22
…
39 40 41 42 43 44 45
A1 A0
High Impedance
8 dummy
cycle
Data Out
1
Data Out
2
D6 D4 D2 D0 D6 D4
D7 D5 D3 D1 D7 D5
38
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-13. 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is latched
on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of
SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted out, so the whole memory can be read out
at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached.
Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous
1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address
interleave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end
2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 20. 2 x I/O Read Mode Sequence (Command BB)
CS#
0
1
2
3
4
5
6
7
8
SCLK
…
Command
SI/SIO0
SO/SIO1
18 19 20 21 22 23 24 25 26 27 28 29
9
BB(hex)
High Impedance
12 ADD Cycle
4 dummy
cycle
Data Out
1
Data Out
2
A22 A20
…
A2 A0 P2 P0
D6 D4 D2 D0 D6 D4
A23 A21
…
A3 A1 P3 P1
D7 D5 D3 D1 D7 D5
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
P/N: PM2222
39
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-14. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single QREAD
instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing
QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address
on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can
use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 21. Quad Read Mode Sequence (Command 6B)
CS#
0
1
2
3
4
5
6
7
8
…
Command
SI/SIO0
SO/SIO1
SIO2
SIO3
P/N: PM2222
29 30 31 32 33
9
SCLK
6B
…
24 ADD Cycles
A23 A22
…
High Impedance
38 39 40 41 42
A2 A1 A0
8 dummy cycles
Data Data
Out 1 Out 2
Data
Out 3
D4 D0 D4 D0 D4
D5 D1 D5 D1 D5
High Impedance
D6 D2 D6 D2 D6
High Impedance
D7 D3 D7 D3 D7
40
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-15. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address
interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out.
Another sequence of issuing 4READ instruction especially useful in random access is: CS# goes low→sending
4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling
bit P[7:0]→ 4 dummy cycles →data out still CS# goes high → CS# goes low (reduce 4 Read instruction) →24-bit
random access address.
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0];
likewise P[7:0]=FFh, 00h, AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape
from performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
P/N: PM2222
41
REV. 1.2, NOV. 19, 2015
MX25R4035F
Figure 22. 4 x I/O Read Mode Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Mode 3
SCLK
Mode 0
Command
EBh
6 ADD Cycles
Performance
enhance
indicator (Note)
4 Dummy
Cycles
Data
Out 1
Data
Out 2
Data
Out 3
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0 D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1 D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2 D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3 D7 D3
SIO0
Mode 0
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
P/N: PM2222
42
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-16. Burst Read
This device supports Burst Read.
To set the Burst length, following command operation is required
Issuing command: “C0h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and
disable with“1h”.
Next 4 clocks is to define wrap around depth. Definition as following table:
Data
00h
01h
02h
03h
1xh
Wrap Around
Yes
Yes
Yes
Yes
No
Wrap Depth
8-byte
16-byte
32-byte
64-byte
X
The wrap around unit is defined within the 256Byte page, with random initial address. It’s defined as “wrap-around
mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0” command
in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change
wrap around depth, it is requried to issue another “C0” command in which data=“0xh”. “EBh” supports wrap around
feature after wrap around enable. The device id default without Burst read.
Figure 23. Burst Read
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
D7
D6
10
11
12
13
14
15
SCLK
Mode 0
SIO
P/N: PM2222
C0h
43
D5
D4
D3
D2
D1
D0
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-17. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles.
“EBh” command supports enhance mode. The performance enhance mode is not supported in dual I/O mode.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” command to exit enhance mode.
Notice: Performance Enhance can only be operated in high performance mode.
P/N: PM2222
44
REV. 1.2, NOV. 19, 2015
MX25R4035F
Figure 24. 4 x I/O Read enhance performance Mode Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
n
SCLK
Mode 0
Data
Out 2
Data
Out n
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Command
EBh
SIO0
6 ADD Cycles
Performance
enhance
indicator (Note)
4 Dummy
Cycles
Data
Out 1
CS#
n+1
...........
n+7 ...... n+9
........... n+13
...........
Mode 3
SCLK
6 ADD Cycles
Performance
enhance
indicator (Note)
4 Dummy
Cycles
Data
Out 1
Data
Out 2
Data
Out n
SIO0
A20 A16 A12 A8 A4 A0 P4 P0
D4 D0 D4 D0
D4 D0
SIO1
A21 A17 A13 A9 A5 A1 P5 P1
D5 D1 D5 D1
D5 D1
SIO2
A22 A18 A14 A10 A6 A2 P6 P2
D6 D2 D6 D2
D6 D2
SIO3
A23 A19 A15 A11 A7 A3 P7 P3
D7 D3 D7 D3
D7 D3
Mode 0
Note:
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
P/N: PM2222
45
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-18. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization") is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address
byte been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→
CS# goes high.
The SIO[3:1] are "don't care".
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the
sector.
Figure 25. Sector Erase (SE) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
SI
24-Bit Address
Command
23 22
20h
2
1
0
MSB
P/N: PM2222
46
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-19. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block (see "Table 4. Memory
Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte has been latched-in); otherwise, the instruction will be rejected
and not executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte
address on SI → CS# goes high.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during
the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the block is protected by BP3~0, the array data will be protected (no change) and the WEL bit still be
reset.
Figure 26. Block Erase 32KB (BE32K) Sequence (Command 52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
52h
2
1
0
MSB
P/N: PM2222
47
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-20. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory Organization")
is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest
eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→
CS# goes high.
The SIO[3:1] are "don't care".
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the tBE
timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block
is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block.
Figure 27. Block Erase (BE) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Mode 0
SI
Command
24-Bit Address
23 22
D8h
2
1
0
MSB
P/N: PM2222
48
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-21. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#
must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.
The SIO[3:1] are "don't care".
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the
tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only
executed when BP3, BP2, BP1, BP0 all set to "0".
Figure 28. Chip Erase (CE) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
SI
P/N: PM2222
Command
60h or C7h
49
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-22. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address
bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed
page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected
page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page
and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be
programmed at the request address of the page. There will be no effort on the other data bytes of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high.
The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the
latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
The SIO[3:1] are "don't care".
Figure 29. Page Program (PP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02h
SI
Data Byte 1
24-Bit Address
2076
Command
2075
Mode 0
4
1
0
MSB
MSB
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
SCLK
Data Byte 2
SI
7
6
MSB
P/N: PM2222
5
4
3
2
Data Byte 3
1
0
7
6
5
4
MSB
3
2
Data Byte 256
1
0
7
6
5
4
3
2
MSB
50
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-23. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before
sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and
SIO3 as address and data input, which can improve programmer performance and the effectiveness of application.
The 4PP operation frequency supports as fast as f4PP. The other function descriptions are as same as standard
page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
Figure 30. 4 x I/O Page Program (4PP) Sequence
CS#
Mode 3
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21
SCLK
Mode 0
SIO0
P/N: PM2222
Command
38h
6 ADD cycles
Data Data Data Data
Byte 1 Byte 2 Byte 3 Byte 4
A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 D4 D0 D4 D0
SIO1
A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 D5 D1 D5 D1
SIO2
A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 D6 D2 D6 D2
SIO3
A23 A19 A15 A11 A7 A3
51
D7 D3 D7 D3
D7 D3 D7 D3
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-24. Deep Power-down (DP)
The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep Power
down mode, in which the quiescent current is reduced from ISB1 to ISB2.
The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS# must
go high at the byte boundary (after exactly eighth bits of the instruction code have been latched-in); otherwise the
instruction will not be executed. SIO[3:1] are "don't care".
After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-down
mode and the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions will be ignored.
CS# must not be pulsed low until the device has been in Deep Power-down mode for a minimum of tDPDD. The
device exits Deep Power-down mode and returns to Stand-by mode if CS# pulses low for tCRDP or if the device is
power-cycled or hardware reset. After CS# goes high, there is a delay of tRDP before the device transitions from
Deep Power-down mode back to Stand-by mode.
Figure 31. Deep Power-down (DP) Sequence and Release from Deep Power-down Sequence
tCRDP
CS#
tDP
Mode 3
0
1
2
3
4
5
6
tDPDD
tRDP
7
SCLK
Mode 0
SI
Command
B9h
Stand-by Mode
P/N: PM2222
Deep Power-down Mode
52
Stand-by Mode
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-25. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 8K-bit secured OTP mode. While the device is in 8K-bit Secured
OTP mode, array access is not available. The additional 8K-bit secured OTP is independent from main array, and
may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow
standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated
again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
The SIO[3:1] are "don't care".
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once
security OTP is lock down, only read related commands are valid.
10-26. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 8K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
The SIO[3:1] are "don't care".
10-27. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
The SIO[3:1] are "don't care".
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the secured OTP area is locked by factory or not.
When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for
customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 1st 4K-bit
Secured OTP area cannot be updated any more.
Program Suspend Status bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation.
Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend
command, PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Erase Suspend Status bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may
use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command,
ESB is set to "1". ESB is cleared to "0" after erase operation resumes.
P/N: PM2222
53
REV. 1.2, NOV. 19, 2015
MX25R4035F
Program Fail Flag bit. The Program Fail bit shows the status of the last Program operation. The bit will be set to "1"
if the program operation failed or the program region was protected. It will be automatically cleared to "0" if the next
program operation succeeds. Please note that it will not interrupt or stop any operation in the flash memory.
Erase Fail Flag bit. The Erase Fail bit shows the status of last Erase operation. The bit will be set to "1" if the erase
operation failed or the erase region was protected. It will be automatically cleared to "0" if the next erase operation
succeeds. Please note that it will not interrupt or stop any operation in the flash memory.
Table 8. Security Register Definition
bit7
Reserved
bit6
bit5
E_FAIL
P_FAIL
0=normal
Erase
succeed
0=normal
Program
succeed
1=indicate
Erase failed
(default=0)
1=indicate
Program
failed
(default=0)
non-volatile
bit
volatile bit
volatile bit
Reserved
Read Only
Read Only
Reserved
bit4
bit3
bit2
Reserved
ESB (Erase
Suspend
status)
PSB
(Program
Suspend
status)
0=Erase
is not
suspended
Reserved
1=Erase is
suspended
(default=0)
volatile bit
bit1
bit0
LDSO
Secured OTP
(lock-down Indicator bit
1st 4K-bit
(2nd 4K-bit
Secured
Secured
OTP)
OTP)
0 = not
0=Program
0=
lockdown
is not
1 = lock-down nonfactory
suspended
lock
(cannot
1 = factory
program/
1=Program
erase
lock
is suspended
OTP)
(default=0)
volatile bit
volatile bit
non-volatile
bit
non-volatile
bit
Read Only
Read Only
OTP
Read Only
10-28. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction
is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)
for customer to lock-down the 1st 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the 1st 4K-bit Secured
OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The SIO[3:1] are "don't care".
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM2222
54
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-29. Program/Erase Suspend/Resume
The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to
the memory array. After the program or erase operation has entered the suspended state, the memory array can
be read except for the page being programmed or the sector or block being erased ("Table 9. Readable Area of
Memory While a Program or Erase Operation is Suspended").
Table 9. Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation
Readable Region of Memory Array
Page Program
All but the Page being programmed
Sector Erase (4KB)
All but the 4KB Sector being erased
Block Erase (32KB)
All but the 32KB Block being erased
Block Erase (64KB)
All but the 64KB Block being erased
When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL ("Figure 33.
Suspend to Read/Program Latency") before the Write Enable Latch (WEL) bit clears to “0” and the PSB or ESB sets
to “1”, after which the device is ready to accept one of the commands listed in "Table 10. Acceptable Commands
During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 17. AC Characteristics" for
tPSL and tESL timings. "Table 11. Acceptable Commands During Suspend (tPSL/tESL not required)" lists the
commands for which the tPSL and tESL latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST
can be issued at any time after the Suspend instruction.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check the suspend status. The PSB (Program Suspend
Bit) sets to “1” when a program operation is suspended. The ESB (Erase Suspend Bit) sets to “1” when an erase
operation is suspended. The PSB or ESB clears to “0” when the program or erase operation is resumed.
Table 10. Acceptable Commands During Program/Erase Suspend after tPSL/tESL
Command Name
Command Code
READ
03h
FAST READ
0Bh
DREAD
3Bh
QREAD
6Bh
2READ
BBh
4READ
EBh
RDSFDP
5Ah
RDID
9Fh
REMS
90h
SBL
C0h
ENSO
B1h
EXSO
C1h
WREN
06h
RESUME
7Ah or 30h
PP
02h
4PP
38h
P/N: PM2222
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
55
REV. 1.2, NOV. 19, 2015
MX25R4035F
Table 11. Acceptable Commands During Suspend (tPSL/tESL not required)
Command Name
Command Code
WRDI
04h
RDSR
05h
RDCR
15h
RDSCUR
2Bh
RES
ABh
RSTEN
66h
RST
99h
NOP
00h
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Figure 32. Resume to Suspend Latency
CS#
Resume Command
tPRS / tERS
Suspend Command
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
P/N: PM2222
56
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-29-1. Erase Suspend to Program
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended. Page
Programming is permitted in any unprotected memory except within the sector of a suspended Sector Erase
operation or within the block of a suspended Block Erase operation. The Write Enable (WREN) instruction must be
issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed to
finish before the suspended erase can be resumed. The Status Register can be polled to determine the status of
the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the Page Program
operation is in progress and will both clear to “0” when the Page Program operation completes.
Figure 33. Suspend to Read/Program Latency
CS#
Suspend Command
tPSL / tESL
Read/Program Command
tPSL: Program latency
tESL: Erase latency
Notes:
1. Please note that Program only available after the Erase-Suspend operation
2. To check suspend ready information, please read security register bit2(PSB) and bit3(ESB)
10-30. Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before
issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page Program
operation in progress.
Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1” and
the PSB or ESB is cleared to “0”. The program or erase operation will continue until finished ("Figure 34. Resume
to Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or tERS
must be observed before issuing another Suspend instruction ("Figure 32. Resume to Suspend Latency").
Please note that the Resume instruction will be ignored if the Serial NOR Flash is in “Performance Enhance Mode”.
Make sure the Serial NOR Flash is not in “Performance Enhance Mode” before issuing the Resume instruction.
Figure 34. Resume to Read Latency
CS#
P/N: PM2222
Resume Command
tSE / tBE / tPP
Read Command
57
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-31. No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect any
other command.
The SIO[3:1] are don't care.
10-32. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the
Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will
be invalid.
The SIO[3:1] are "don't care".
If the Reset command is executed during program or erase operation, the operation will be disabled, the data under
processing could be damaged or lost.
The reset time is different depending on the last operation. Longer latency time is required to recover from a
program operation than from other operations.
P/N: PM2222
58
REV. 1.2, NOV. 19, 2015
MX25R4035F
Figure 35. Software Reset Recovery
Stand-by Mode
66
CS#
99
tReady2
Mode
Note: Refer to "Table 13. Reset Timing-(Other Operation)" for tREADY2 data.
Figure 36. Reset Sequence
tSHSL
CS#
SCLK
Mode 3
Mode 3
Mode 0
Mode 0
Command
SIO0
P/N: PM2222
Command
99h
66h
59
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-33. High Voltage Operation
The flash device supports High Voltage Operation. This opeartion allows user can have better performance in
following Program/Erase operation.
To enable High Voltage Opeartion, WP#/SIO2 need to apply Vhv during whole operation. If the voltage can not
sustain in Vhv range, the Program/Erase opeation might be failed. CS# can only go low after tVSL1+tVhv +tVhv2
timing during High Voltage Operation. WP# can only start to go low after whole Erase/Program Operation has been
done.
To check the operation status, user may check the status of WIP bit.
Figure 37. High Voltage Operation Diagram
Vcc (min.)
Vcc
GND
GND
tVSL1
Vhv
(7V ~ 8V)
WP#
tVhv2
Vcc
tVhv2
tVhv(Note 1)
CS#
Vcc
tVhv(Note 2)
GND
GND
Vcc
Vcc
Standby Mode
GND
GND
Note 1: Please note that the CS# can only go low after tVSL1+tVhv +tVhv2 timing during High Voltage Operation.
Note 2: Please note that the WP# can only start to go low after whole Erase/Program Operation has been done.
To check the operation status, user may check the status of WIP bit.
Note 3: tVhv(min.) = 250ns, tVSL 1(min.) = 800us; tVhv2(min.) = 0ns
Note 4: Vhv range is 7V(min.) ≤ Vhv ≤ 8(max.)
Note 5: The High Voltage Operation can only work during Vcc(min.) ≤ Vcc ≤ 2.0V
P/N: PM2222
60
REV. 1.2, NOV. 19, 2015
MX25R4035F
10-34. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→send RDSFDP instruction
(5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP
operation can use CS# to high at any time during data out.
SFDP is a JEDEC Standard, JESD216B.
For SFDP register values detail, please contact local Macronix sales channel for Application Note.
Figure 38. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
5Ah
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
3
2
1
0
7
MSB
MSB
P/N: PM2222
4
61
6
5
4
3
2
1
0
7
MSB
REV. 1.2, NOV. 19, 2015
MX25R4035F
11. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at
the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data
could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to
minimum.
Figure 39. RESET Timing
CS#
tRHSL
SCLK
tRH tRS
RESET#
tRLRH
tREADY1 / tREADY2
Table 12. Reset Timing-(Power On)
Symbol Parameter
tRHSL Reset# high before CS# low
tRS
Reset# setup time
tRH
Reset# hold time
tRLRH Reset# low pulse width
tREADY1 Reset Recovery time
Min.
10
15
15
10
35
Typ.
Max.
Unit
us
ns
ns
us
us
Min.
10
15
15
10
40
35
310
12
25
100
40
Typ.
Max.
Unit
us
ns
ns
us
us
us
us
ms
ms
ms
ms
Table 13. Reset Timing-(Other Operation)
Symbol
tRHSL
tRS
tRH
tRLRH
Parameter
Reset# high before CS# low
Reset# setup time
Reset# hold time
Reset# low pulse width
Reset Recovery time (During instruction decoding)
Reset Recovery time (for read operation)
Reset Recovery time (for program operation)
tREADY2 Reset Recovery time(for SE4KB operation)
Reset Recovery time (for BE32K/64K operation)
Reset Recovery time (for Chip Erase operation)
Reset Recovery time (for WRSR operation)
P/N: PM2222
62
REV. 1.2, NOV. 19, 2015
MX25R4035F
12. POWER-ON STATE
The device is at the following states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage until the VCC reaches the following levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the "Figure 46. Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to
any command. The data corruption might occur during this stage if a write, program, erase cycle is in progress.
P/N: PM2222
63
REV. 1.2, NOV. 19, 2015
MX25R4035F
13. ELECTRICAL SPECIFICATIONS
Table 14. Absolute Maximum Ratings
Rating
Value
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-65°C to 150°C
Applied Input Voltage
-0.5V to VCC+0.5V
Applied Output Voltage
-0.5V to VCC+0.5V
VCC to Ground Potential
MX25R (1.65V-3.6V)
-0.5V to 4.0V
NOTICE:
1.Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.
Figure 41. Maximum Positive Overshoot Waveform
Figure 40. Maximum Negative Overshoot Waveform
20ns
0V
VCC+1.0V
-1.0V
VCC
20ns
Table 15. Capacitance
TA = 25°C, f = 1.0 MHz
Symbol Parameter
CIN
COUT
P/N: PM2222
Min.
Typ.
Max.
Unit
Input Capacitance
6
pF
VIN = 0V
Output Capacitance
8
pF
VOUT = 0V
64
Conditions
REV. 1.2, NOV. 19, 2015
MX25R4035F
Figure 42. Input Test Waveforms and Measurement Level
Input timing reference level
0.8VCC
0.7VCC
0.3VCC
0.2VCC
Output timing reference level
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 43. Output Loading
25K ohm
DEVICE UNDER
TEST
CL
VCC
25K ohm
CL=15/30pF Including jig capacitance
P/N: PM2222
65
REV. 1.2, NOV. 19, 2015
MX25R4035F
Table 16. DC Characteristics
Ultra Low Power Mode (Configuration Register-2 bit1= 0):
Symbol Parameter
Notes
Min.
Typ.
Max.
Units
Test Conditions
ILI
Input Load Current
1
±2
uA
VCC = VCC Max,
VIN = VCC or GND
ILO
Output Leakage Current
1
±2
uA
VCC = VCC Max,
VOUT = VCC or GND
ISB1
VCC Standby Current
1
5
24
uA
VIN = VCC or GND,
CS# = VCC
ISB2
Deep Power-down
Current
0.1
0.5
uA
2.8
4.5
mA
2.2
4
mA
2.2
4
mA
3.5
6
mA
3.1
6
mA
1
3.1
6
mA
Erase in Progress,
CS#=VCC
1
3.1
6
mA
Erase in Progress,
CS#=VCC
7
8
V
-0.5
0.2VCC
V
0.8VCC
VCC+0.4
V
0.2
V
IOL = 100uA
V
IOH = -100uA
ICC1
VCC Read
VIL
VCC Program Current
(PP)
VCC Write Status
Register (WRSR) Current
VCC Sector/Block (64K)
Erase Current
(SE/BE)
VCC Chip Erase Current
(CE)
High Voltage Applied at
WP# pin
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
ICC2
ICC3
ICC4
ICC5
Vhv
1
1
VCC-0.2
VIN = VCC or GND,
CS# = VCC
f=16MHz (4x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
f=33MHz
SCLK=0.1VCC/0.9VCC,
SO=Open
f=16MHz (2x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress,
CS# = VCC
Program status register in
progress, CS#=VCC
Test Condition, VCC=2.0V
Notes :
1. Device operation range: 1.65V-3.6V, Typical values at VCC = 1.8V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM2222
66
REV. 1.2, NOV. 19, 2015
MX25R4035F
High Performance Mode (Configuration Register-2 bit1= 1):
Symbol Parameter
Notes
Min.
Typ.
Max.
Units Test Conditions
ILI
Input Load Current
1
±2
uA
VCC = VCC Max,
VIN = VCC or GND
ILO
Output Leakage Current
1
±2
uA
VCC = VCC Max,
VOUT = VCC or GND
Iwph
Leakage Current while
WP# at Vhv
30
uA
VCC < 2.1V
ISB1
VCC Standby Current
9
40
uA
VIN = VCC or GND,
CS# = VCC
ISB2
Deep Power-down
Current
0.1
0.5
uA
VIN = VCC or GND,
CS# = VCC
4.2
6.5
mA
5
8
mA
3.9
6.5
mA
6.5
9.5
mA
5.8
10
mA
3.5
10
mA
1
3.5
10
mA
Erase in Progress,
CS#=VCC
1
4
10
mA
Erase in Progress,
CS#=VCC
7
8
V
ICC1
ICC2
ICC3
ICC4
ICC5
VCC Read
VCC Program Current
(PP)
VCC Write Status
Register (WRSR) Current
VCC Sector/Block (64K)
Erase Current
(SE/BE)
VCC Chip Erase Current
(CE)
1
1
1
f=104MHz
SCLK=0.1VCC/0.9VCC,
SO=Open
f=104MHz (2x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
f=33MHz (4x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
f=104MHz (4x I/O)
SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress,
CS# = VCC
Program status register in
progress, CS#=VCC
Vhv
High Voltage Applied at
WP# pin
VIL
Input Low Voltage
-0.5
0.2VCC
V
VIH
Input High Voltage
0.8VCC
VCC+0.4
V
VOL
Output Low Voltage
0.2
V
IOL = 100uA
VOH
Output High Voltage
V
IOH = -100uA
VCC-0.2
Test Condition, VCC=2.0V
Notes :
1. Device operation range: 1.65V-3.6V, Typical values at VCC = 1.8V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
P/N: PM2222
67
REV. 1.2, NOV. 19, 2015
MX25R4035F
Table 17. AC Characteristics
Ultra Low Power Mode (Configuration Register-2 bit1= 0):
Symbol
fSCLK
fRSCLK
fTSCLK
f4PP
tCH(1)
tCL(1)
tCLCH(9)
tCHCL(9)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ(9)
tCLQV
tCLQX
tHLCH*
tCHHH*
tHHCH*
tCHHL*
tHHQX*
tHLQZ *
tWHSL(3)
(3)
tSHWL
tDP
tDPDD
tCRDP
tRDP
tW
tWMS
Alt. Parameter
Min.
Typ.(2) Max. Unit
Clock Frequency for the following instructions:
D.C.
33 MHz
fC FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP, RES,
WREN, WRDI, RDID, RDSR, WRSR(7)
fR Clock Frequency for READ instructions
33 MHz
fT Clock Frequency for 2READ/DREAD instructions
16 MHz
fQ Clock Frequency for 4READ/QREAD instructions
16 MHz
Clock Frequency for 4PP (Quad page program)
33 MHz
Others (fSCLK)
45% x (1/fSCLK)
ns
tCLH Clock High Time
Normal Read (fRSCLK)
13
ns
Others (fSCLK)
45% x (1/fSCLK)
ns
tCLL Clock Low Time
Normal Read (fRSCLK)
13
ns
Clock Rise Time (peak to peak)
0.1
V/ns
Clock Fall Time (peak to peak)
0.1
V/ns
tCSS CS# Active Setup Time (relative to SCLK)
5
ns
CS# Not Active Hold Time (relative to SCLK)
5
ns
tDSU Data In Setup Time
2
ns
tDH Data In Hold Time
3
ns
CS# Active Hold Time (relative to SCLK)
5
ns
CS# Not Active Setup Time (relative to SCLK)
5
ns
From Read to next Read
15
ns
tCSH CS# Deselect Time
From Write/Erase/Program
30
ns
to Read Status Register
tDIS Output Disable Time
8
ns
Loading: 30pF
12
ns
Clock
Low
to
Output
Valid
tV Loading: 30pF/15pF
Loading: 15pF
10
ns
tHO Output Hold Time
0
ns
HOLD# Active Setup Time (relative to SCLK)
HOLD# Active Hold Time (relative to SCLK)
HOLD# Not Active Setup Time (relative to SCLK)
HOLD# Not Active Hold Time (relative to SCLK)
tLZ HOLD# to Output Low-Z
tHZ HOLD# to Output High-Z
8
8
8
8
10
10
ns
ns
ns
ns
ns
ns
Write Protect Setup Time
10
ns
Write Protect Hold Time
10
ns
CS# High to Deep Power-down Mode
Delay Time for Release from Deep Power-Down Mode
once entering Deep Power-Down Mode
CS# Toggling Time before Release from Deep Power-Down
Mode
Recovery Time for Release from deep power down mode
Write Status Register Cycle Time
Write Status Register Cycle Time for Mode Switching
10
us
30
us
20
ns
35
40
20
us
ms
us
* Depends on part number options.
P/N: PM2222
68
REV. 1.2, NOV. 19, 2015
MX25R4035F
Ultra Low Power Mode - Continued:
Symbol
tESL(8)
tPSL(8)
tPRS (4)
tERS (5)
tBP
tPP
tSE
tBE32K
tBE
tCE
P/N: PM2222
Alt. Parameter
Erase Suspend Latency
Program Suspend Latency
Latency between Program Resume and next Suspend
Latency between Erase Resume and next Suspend
Byte-Program
Byte-Program (Applied Vhv at WP# pin)
Page Program Cycle Time
Page Program Cycle Time (Applied Vhv at WP# pin)
Sector Erase Cycle Time
Sector Erase Cycle Time (Applied Vhv at WP# pin)
Block Erase (32KB) Cycle Time
Block Erase (32KB) Cycle Time (Applied Vhv at WP# pin)
Block Erase (64KB) Cycle Time
Block Erase (64KB) Cycle Time (Applied Vhv at WP# pin)
Chip Erase Cycle Time
Chip Erase Cycle Time (Applied Vhv at WP# pin)
69
Min.
0.3
0.3
Typ.(2)
Max.
60
60
40
32
3.2
0.6
58
36
0.4
0.22
0.8
0.43
7.5
2.7
100
100
10
3.6
240
210
1.75
1.05
3.5
2.1
15
8
Unit
us
us
us
us
us
us
ms
ms
ms
ms
s
s
s
s
s
s
REV. 1.2, NOV. 19, 2015
MX25R4035F
High Performance Mode (Configuration Register-2 bit1= 1):
Alt. Parameter
Min.
Typ.(2) Max.
Clock Frequency for the following instructions:
D.C.
104
fSCLK
fC FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP,
RES, WREN, WRDI, RDID, RDSR, WRSR(7)
fRSCLK
fR Clock Frequency for READ instructions
33
fT Clock Frequency for 2READ/DREAD instructions
104
fTSCLK
fQ Clock Frequency for 4READ/QREAD instructions
104
f4PP
Clock Frequency for 4PP (Quad page program)
104
Others
(fSCLK)
45%
x
(1/fSCLK)
tCH(1)
tCLH Clock High Time
Normal Read (fRSCLK)
13
Others (fSCLK)
45% x (1/fSCLK)
tCL(1)
tCLL Clock Low Time
Normal Read (fRSCLK)
13
tCLCH(9)
Clock Rise Time (peak to peak)
0.1
tCHCL(9)
Clock Fall Time (peak to peak)
0.1
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
5
tCHSL
CS# Not Active Hold Time (relative to SCLK)
5
tDVCH tDSU Data In Setup Time
2
tCHDX
tDH Data In Hold Time
3
tCHSH
CS# Active Hold Time (relative to SCLK)
5
tSHCH
CS# Not Active Setup Time (relative to SCLK)
5
From Read to next Read
15
tSHSL tCSH CS# Deselect Time
From Write/Erase/Program
30
to Read Status Register
tSHQZ(9) tDIS Output Disable Time
8
8
Clock Low to Output Valid Loading: 30pF
tCLQV
tV
Loading: 30pF/15pF
Loading: 15pF
6
tCLQX
tHO Output Hold Time
0
tHLCH*
HOLD# Active Setup Time (relative to SCLK)
8
tCHHH*
HOLD# Active Hold Time (relative to SCLK)
8
tHHCH*
HOLD# Not Active Setup Time (relative to SCLK)
8
tCHHL*
HOLD# Not Active Hold Time (relative to SCLK)
8
tHHQX*
tLZ HOLD# to Output Low-Z
10
tHLQZ * tHZ HOLD# to Output High-Z
10
tWHSL (3)
Write Protect Setup Time
10
tSHWL (3)
Write Protect Hold Time
10
tDP
CS# High to Deep Power-down Mode
10
Delay Time for Release from Deep Power-Down Mode
tDPDD
30
once entering Deep Power-Down Mode
CS# Toggling Time before Release from Deep PowertCRDP
20
Down Mode
Recovery Time for Release from deep power down
tRDP
35
mode
tW
Write Status Register Cycle Time
30
tWMS
Write Status Register Cycle Time for Mode Switching
20
Symbol
Unit
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
ns
us
ms
us
* Depends on part number options.
P/N: PM2222
70
REV. 1.2, NOV. 19, 2015
MX25R4035F
High Performance Mode - Continued:
Symbol
tESL(8)
tPSL(8)
tPRS (4)
tERS (5)
tBP
tPP
tSE
tBE32K
tBE
tCE
Alt. Parameter
Erase Suspend Latency
Program Suspend Latency
Latency between Program Resume and next Suspend
Latency between Erase Resume and next Suspend
Byte-Program
Byte-Program (Applied Vhv at WP# pin)
Page Program Cycle Time
Page Program Cycle Time (Applied Vhv at WP# pin)
Sector Erase Cycle Time
Sector Erase Cycle Time (Applied Vhv at WP# pin)
Block Erase (32KB) Cycle Time
Block Erase (32KB) Cycle Time (Applied Vhv at WP# pin)
Block Erase (64KB) Cycle Time
Block Erase (64KB) Cycle Time (Applied Vhv at WP# pin)
Chip Erase Cycle Time
Chip Erase Cycle Time (Applied Vhv at WP# pin)
Min.
0.3
0.3
Typ.(2)
Max.
40
40
32
32
0.85
0.6
40
36
0.24
0.22
0.48
0.43
3
2.7
100
100
4
3.6
240
210
1.5
1.05
3
2.1
9
8
Unit
us
us
us
us
us
us
ms
ms
ms
ms
s
s
s
s
s
s
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Program operation may be interrupted as often as system request. The minimum timing of tPRS must be
observed before issuing the next program suspend command. However, in order for an Program operation to
make progress, tPRS ≥ 100us must be included in resume-to-suspend loop(s). Not 100% tested.
5. Erase operation may be interrupted as often as system request. The minimum timing of tERS must be observed
before issuing the next erase suspend command. However, in order for an Erase operation to make progress,
tERS ≥ 200us must be included in resume-to-suspend loop(s). The details are described in Macronix application
notes. Not 100% tested.
6.Test condition is shown as "Figure 42. Input Test Waveforms and Measurement Level", "Figure 43. Output
Loading".
7. WRSR speed max. is 33MHz when issuing WRSR for performance mode switch no matter High Performance
Mode to Ultra Low Power Mode or Ultra Low Power Mode to High Performance Mode.
8. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
9. The value guaranteed by characterization, not 100% tested in production.
P/N: PM2222
71
REV. 1.2, NOV. 19, 2015
MX25R4035F
14. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 44. AC Timing at Device Power-Up" and "Figure 45. Power-Down Sequence" are
for the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is
ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 44. AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tSLCH
tCHSL
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
LSB IN
MSB IN
SI
High Impedance
SO
Symbol
tVR
tCLCH
Parameter
VCC Rise Time
Notes
1
Min.
20
Max.
500000
Unit
us/V
Notes :
1.Sampled, not 100% tested.
2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"Table 17. AC Characteristics".
P/N: PM2222
72
REV. 1.2, NOV. 19, 2015
MX25R4035F
Figure 45. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
Figure 46. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL
Device is fully accessible
VWI
time
P/N: PM2222
73
REV. 1.2, NOV. 19, 2015
MX25R4035F
Figure 47. Power Up/Down and Voltage Drop
For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing.
Please check the table below for more detail.
VCC
VCC (max.)
Chip Select is not allowed
VCC (min.)
tVSL
Full Device
Access
Allowed
VPWD (max.)
tPWD
Time
Table 18. Power-Up/Down Voltage and Timing
Symbol Parameter
tVSL
VCC(min.) to device operation
VWI
Write Inhibit Voltage
VPWD
tPWD
tVR
MX25R (1.65V-3.6V)
Deep Power Mode
VCC voltage needed to below VPWD for
ensuring initialization will occur
others
The minimum duration for ensuring initialization will occur
VCC Rise Time
Min.
800
1.1
300
20
Max.
1.5
0.4
0.9
500000
Unit
us
V
V
V
us
us/V
Note: These parameters are characterized only.
14-1.Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM2222
74
REV. 1.2, NOV. 19, 2015
MX25R4035F
15. ERASE AND PROGRAMMING PERFORMANCE
Ultra Low Power Mode (Configuration Register-2 bit1= 0):
Parameter
Min.
Typ. (1)
Write Status Register Cycle Time
Max. (2)
Unit
40
ms
Sector Erase Cycle Time (4KB)
58
240
ms
Sector Erase Cycle Time (4KB) (Applied Vhv at WP# pin)
36
210
ms
Block Erase Cycle Time (32KB)
0.4
1.75
s
Block Erase Cycle Time (32KB) (Applied Vhv at WP# pin)
0.22
1.05
s
Block Erase Cycle Time (64KB)
0.8
3.5
s
Block Erase Cycle Time (64KB) (Applied Vhv at WP# pin)
0.43
2.1
s
Chip Erase Cycle Time
7.5
15
s
Chip Erase Cycle Time (Applied Vhv at WP# pin)
2.7
8
s
Byte Program Time
40(4)
100
us
32
100
us
10
ms
3.6
ms
Byte Program Time (Applied Vhv at WP# pin)
Page Program Time
3.2
Page Program Time (Applied Vhv at WP# pin)
(4)
0.6
Erase/Program Cycle
100,000
cycles
High Performance Mode (Configuration Register-2 bit1= 1):
Parameter
Min.
Typ. (1)
Write Status Register Cycle Time
Max. (2)
Unit
30
ms
Sector Erase Cycle Time (4KB)
40
240
ms
Sector Erase Cycle Time (4KB) (Applied Vhv at WP# pin)
36
210
ms
Block Erase Cycle Time (32KB)
0.24
1.5
s
Block Erase Cycle Time (32KB) (Applied Vhv at WP# pin)
0.22
1.05
s
Block Erase Cycle Time (64KB)
0.48
3
s
Block Erase Cycle Time (64KB) (Applied Vhv at WP# pin)
0.43
2.1
s
3
9
s
2.7
8
s
100
us
100
us
4
ms
3.6
ms
Chip Erase Cycle Time
Chip Erase Cycle Time (Applied Vhv at WP# pin)
(4)
Byte Program Time
32
Byte Program Time (Applied Vhv at WP# pin)
32
Page Program Time
0.85
Page Program Time (Applied Vhv at WP# pin)
(4)
0.6
Erase/Program Cycle
100,000
cycles
Notes:
1. Typical erase assumes the following conditions: 25°C, typical operation voltage and all zero pattern.
2. Under worst conditions of 85°C and minimum operation voltage.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming
command.
4. Typical program assumes the following conditions: 25°C, typical VCC, and checkerboard pattern.
P/N: PM2222
75
REV. 1.2, NOV. 19, 2015
MX25R4035F
16. LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
-1.0V
2 VCCmax
Input Voltage with respect to GND on SO
-1.0V
VCC + 1.0V
-100mA
+100mA
Current
Includes all pins except VCC. Test conditions: VCC = typical operation voltage, one pin at a time.
P/N: PM2222
76
REV. 1.2, NOV. 19, 2015
MX25R4035F
17. ORDERING INFORMATION
Voltage
Package
Temperature
RESET# /
HOLD# pin
Default Mode
1.65V-3.6V
8-SOP (150mil)
-40°C to 85°C
RESET#
Ultra Low Power Mode
MX25R4035FM2IL0 * 1.65V-3.6V
8-SOP (200mil)
-40°C to 85°C
RESET#
Ultra Low Power Mode
8-USON (2x3mm)
-40°C to 85°C
RESET#
Ultra Low Power Mode
MX25R4035FBDIL0 * 1.65V-3.6V 3-2-3 8-BALL WLCSP
-40°C to 85°C
RESET#
Ultra Low Power Mode
MX25R4035FZUIH0
1.65V-3.6V
8-USON (2x3mm)
-40°C to 85°C
RESET#
High Performance Mode
MX25R4035FM1IH1
1.65V-3.6V
8-SOP (150mil)
-40°C to 85°C
HOLD#
High Performance Mode
MX25R4035FZUIH1
1.65V-3.6V
8-USON (2x3mm)
-40°C to 85°C
HOLD#
High Performance Mode
MX25R4035FBDIH1 * 1.65V-3.6V 3-2-3 8-BALL WLCSP
-40°C to 85°C
HOLD#
High Performance Mode
MX25R4035FZNIH1
-40°C to 85°C
HOLD#
High Performance Mode
PART NO.
MX25R4035FM1IL0
MX25R4035FZUIL0
1.65V-3.6V
1.65V-3.6V
8-WSON (6x5mm)
* Advanced Information
P/N: PM2222
77
REV. 1.2, NOV. 19, 2015
MX25R4035F
18. PART NAME DESCRIPTION
MX 25R 4035F M1
I
L
0
OPTION 2:
0: RESET#
1: HOLD#
OPTION 1:
L: Ultra Low Power Mode (Default)
H: High Performance Mode (Default)
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M1: 8-SOP(150mil)
M2: 8-SOP(200mil)
ZU: 8-USON (2x3mm)
ZN: 8-WSON (6x5mm)
BD: 3-2-3 8-WLCSP
DENSITY & MODE:
4035F: 4Mb
DEVICE:
25R: Wide Range VCC Serial NOR Flash (1.65V-3.6V)
P/N: PM2222
78
REV. 1.2, NOV. 19, 2015
MX25R4035F
19. PACKAGE INFORMATION
P/N: PM2222
79
REV. 1.2, NOV. 19, 2015
MX25R4035F
P/N: PM2222
80
REV. 1.2, NOV. 19, 2015
MX25R4035F
P/N: PM2222
81
REV. 1.2, NOV. 19, 2015
MX25R4035F
P/N: PM2222
82
REV. 1.2, NOV. 19, 2015
MX25R4035F
CS#
VCC
GND
RESET#
/SIO3 *
SI/SIO0
SO/SIO1
WP#/SIO2
SCLK
* RESET#/SIO3 or HOLD#/SIO3
Depends on part number options
Please contact local Macronix sales channel for complete package dimensions.
P/N: PM2222
83
REV. 1.2, NOV. 19, 2015
MX25R4035F
20. REVISION HISTORY
Revision No.Description
0.01
1. Added WLCSP package and Part No.
2. Removed the AC table note of 4READ/QREAD clock rate within 4Mb address
Page
P5,8,81,82,86
P72~75
Date
MAR/06/2015
0.02
1. Added 2.3V-3.6V and 1.65V-2.0V option
2. Added HOLD# option
3. Removed L/H Switch bit descriptions (defualt value)
4. Updated parameters for DC/AC Characteristics 5. Updated Erase and Programming Performance 6. Updated SFDP table to JEDEC SFDP Rev. B Table
All
All
P30
P66-71
P75
P61
MAY/14/2015
0.03
1. Added MX25R4035FZUIHU Part No.
P77
1.0
1. Removed "Advanced Information" to align with the All
product status
2. Optimized Fast Read Clock Frequency in High Performance P4,7,67,70
Mode
3. Revised Deep Power-down (DP) descriptions and figure.
P52
4. Added "Figure 37. High Voltage Operation Diagram"P60
5. Removed tRES2
P23,68,70
6. Modified VWI (2.3V-3.6V option)
P74
7. Modified REMS description
P24
8. Optimized typical tPRS/tERS values and descriptions
P69,71
9. Modified ISB1 value
P66,67
10. Removed Performance Enhance Mode Reset
AUG/10/2015
1.1
1. Removed 2.3V-3.6V and 1.65V-2.0V option
2. Modified ISB1 value (High Performance Mode)
3. Updated Erase/Program Cycle value definition 4. Modified tPRS/tERS descriptions
5. Updated Ordering Information
6. Added 8-land WSON (6x5mm) package
All
P67
P4,75
P71
P77
P5,8,77,78,82
SEP/18/2015
1.2
1. Removed "*Advanced Information" of MX25R4035FZNIH1 &P77
MX25R4035FZUIH0
2. Added MX25R4035FM1IH1 & MX25R4035FZUIH1 Part No. P77
3. Content modification P29,40,68,70
NOV/19/2015
P/N: PM2222
84
JUN/05/2015
REV. 1.2, NOV. 19, 2015
MX25R4035F
Except for customized products which have been expressly identified in the applicable agreement, Macronix's products
are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications
only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property
damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any
and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and
regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen
therefrom.
Copyright© Macronix International Co., Ltd. 2015. All rights reserved, including the trademarks and tradename thereof,
such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit,
eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix
vEE, Macronix MAP, Rich Au­dio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if
any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
85