ECLinPS Max (SiGe) SPICE Modeling Kit

AND8157/D
ECLinPS MAX (SiGe)
SPICE Modeling Kit
Prepared by: Casey Stys and Paul Shockman
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APPLICATION NOTE
Objective
Table 1. Schematics and Netlist Nomenclature
The objective of this kit is to provide sufficient circuit
schematic and SPICE parameter information to perform
system level interconnect modeling for devices in
ON Semiconductor’s high performance ECLinPS MAX
(SiGe) logic family. The family has output edge rates as low
as 50 ps and power supply levels of as low as 2.5 V.
Parameter
The kit is not intended to provide information
necessary to perform circuit level or device behavioral
LOGIC modeling on the ECLinPS MAX devices.
Schematic Information
The kit contains representative input and output
schematics, netlists and waveforms for SPICE modeling and
simulating the ECLinPS MAX family devices INPUT and
OUTPUT structures. This application note will be modified
as new devices are added. Table 1 describes the
nomenclature used for modeling the schematic and netlist
for ECLinPS MAX devices.
Function Description
VCC
2.5 / 3.3 V for LVPECL and 0 V for LVNECL
VEE
−2.5 / −3.3 V for LVNECL and 0 V for LVPECL
VCS
Internally Generated Voltage
(VEE + 0.915 V ± 50 mV)
IN
True (+) Input to BUFFER
IN
Inverted (−) Input to BUFFER
Q
True (+) Output of BUFFER
Q
Inverted (−) Output of BUFFER
INT
Internal True (+) Input to Output Buffer
INT
Internal Invert (−) Input to Output Buffer
The subcircuit models, such as input or output buffers,
ESD and package simulate only device input or output paths.
When used with interconnect models, a complete signal path
may be modeled as shown in Figure 1.
BUFFER
PACKAGE
PACKAGE
ESD
BUFFER
INTERCONNECT
ESD
INPUT BUFFER
OUTPUT BUFFER
Figure 1. Interconnect Model Template
For device modeling, the behavioral LOGIC or gate functionality is not modeled (see Figure 2. DEVICE Model Template)
 Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 1
1
Publication Order Number:
AND8157/D
AND8157/D
DEVICE
PACKAGE
BUFFER
BUFFER
ESD
PACKAGE
FUNCTIONAL LOGIC
NOT MODELED
ESD
OUTPUT BUFFER
INPUT BUFFER
Figure 2. DEVICE Model Template
Package
SPICE Netlist
Models for various package types have been included to
improve the accuracy of the system interconnect model
(Table 2).
The netlists are organized as a subcircuit. In each
subcircuit model netlist, the model name should be followed
by a list of external node interconnects. When copying a
“SUBCKT” netlist files to your text editor, use
Adobe Acrobat Reader 4.0 or higher to ensure proper
character conversion.
Table 2. Available Package Models
Package
Model
SOIC−8
Appendix B (Figure 11 and Table 4)
TSSOP−8
Appendix B (Figure 12 and Table 5)
QFN−16
Figure 9
SPICE Parameter Information
The package model represents the parasitics as they are
measured at a significant distance from an AC ground pin.
The package models should be placed on all external inputs
of an input model, all external outputs of an output model
and the VCC line. Since the current in the VEE pin is a
constant, a package model for VEE pin is not necessary. Note
an internal VCS voltage does not require a package model.
To speed up the simulation process, simplified package
models have been used.
In addition to the schematics and netlists there is a listing
of the SPICE parameters for the transistors and diodes
referenced in the schematics and netlists found provided in
APPENDIX A. These parameters represent a typical case
device of the transistor or diode. Varying the typical
parameters will affect the DC and AC performance of the
structures and is not recommended. Modeling of device
actual delay time is not the intention of this document.
The performance levels may be varied by methods and
discussed in the next section. The resistors referenced in the
schematics are polysilicon and have negligible parasitic
capacitance in the real circuit. The schematics display only
devices needed in the SPICE netlists.
Input Buffer
Modeling Information
The input buffer schematics and netlists present the
various input structures for ECLinPS MAX family devices.
The schematics and netlists include ESD and package
model parasitics for accuracy.
The bias drivers for the devices are not included as they
are unnecessary for interconnect simulations and their use
results in a large increase in model complexity and
simulation time. The internal reference voltages (VBB,
VCS, etc.) should be modeled with ideal constant voltage
sources. Output and input levels of ECLinPS MAX devices
generally vary in a one to one ratio with the power supply;
and remain relatively constant over temperature. Note the
VCS supply is always relative to VEE, the most negative
supply. The output schematics and SPICE parameters
include a typical waveform, for simulation correlation.
Inclusion of ESD and package models typically will add
about 5.0 ps − 7.0 ps to the output waveform rise and fall
time. Simple adjustments made to the models may permit
Output Buffer
Output buffer schematics and netlists models are
provided. The package model parasitics has been added for
accuracy. The output buffer models typically show internal
differential inputs driven by INT and INT. Outputs should
always be simulated with both output lines properly
terminated, even when only one line or single ended use is
intended. This will balance the output buffer’s load.
For correlation, a typical output waveform seen at the
input of the receiver, is shown in Figure 10.
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AND8157/D
MR INPUT BUFFERS at the voltage divider BIAS feeding
one side of the differential. This remains at VCC/2 forcing
the detect threshold to ratiometrically change with VCC.
When left floating open, the EN and SELx inputs will be
forced to a default state of LOW by the internal 75 k
pulldown resistor to VEE, relative to the VCC/2 BIAS
voltage on the other side of the differential. The MR input,
when left floating open, will be forced to a default state of
HIGH by the internal 75 k pullup resistor to VCC.
output characteristics to emulate conditions at or near the
performance corners of the data sheet specifications.
Consistent, repeatable cross–point voltages of 50% should
be maintained.
To Adjust Rise and Fall Times, tr and tf
Produce the desired variant rise and fall times output slew
rates by adjusting collector load resistors. This VCS voltage
determines the tail current in the output differential affecting
the tr and tf of the output.
6L11 and 6L16
To Adjust the VOH
Inputs, when left floating open, will not be forced to a
determined default state. Precautionary considerations may
be needed to prevent spontaneous self oscillation of the
device.
Adjust the VOH and VOL level together by varying VCC.
The output levels will follow changes in VCC at a 1:1 ratio.
To Adjust the VOL
Adjust the VOL level independently of the VOH level by
adjusting increasing the collector load resistance. Note the
VOH level will also by affected due to an IBASE * R drop
across the collector load resistor. The VOL can be changed
by varying the VCS supply which will also affect gate current
through the current source resistor.
Summary
The information included in this kit provides adequate
information to run a SPICE level system interconnect
simulation. The block diagram in Figure 2 illustrates a
typical situation, which can be modeled using the
information in this kit.
Device Specifics
6L239
An exception to the general rule of “levels are relative to
VCC” is found in the internal input node of EN, SELx, and
Z0 = 50 Z0 = 50 Minimum Trace Delay
Line Delay
Driver Output
Receiver Input
VTT
Figure 3. Typical Application for I/O SPICE Modeling Kit
Device input or output models are presented in Table 3.
Table 3. ECLinPS MAX Input/Output Buffer Selector Guide
Device
NB6L11
NB6L16
NB6L239
NB6N239S
Function
Pin
Description
Model
2.5 V / 3.3 V Multilevel Input to Differential
LVNECL/LVPECL 1:2 Clock or Data Fanout Buffer/Translator
6, 7
INPUT
INBUF_01
1, 2, 3,4
OUTPUT
OBUF_01
2.5 V / 3.3 V Multilevel Input to Differential
LVNECL/LVPECL Clock or Data
Receiver/Buffer/Translator
2, 3
INPUT
INBUF_01
6, 7
OUTPUT
OBUF_01
2.5 V / 3.3 V Any Differential Clock IN to
Differential LVPECL OUT DIV by
1/2/4/8/16 Clock Divider
5, 6, 7, 14, 15
EN and SELx INPUT
EN_SEL
16
MR INPUT
MR
1, 2, 3
CLKs and VDT INPUT
CLK_IN
9, 10, 11, 12
OUTPUT
OBUF_01
5, 6, 7, 14, 15
Single Ended Inputs
INBUF_01
16
MR INPUT
MR
2, 3
CLKs and VDT INPUT
INBUF_01
9, 10, 11, 12
LVDS OUTPUT
OBUF_02
3.3 V, 3.0 GHz Any Differential Clock IN
to LVDS OUT DIV by 1/2/4/8
1/2/4/8, DIV by
2/4/8/16 Clock Divider
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AND8157/D
INBUF_01 INPUT BUFFER
Input Buffer
QFN Package
ESD and OPEN PIN
DEFAULT BIAS
VCC
VCC
D101u
R101
39.5m
D
L101
753.3pH
101
ESD
103
C101a
C101b
D101d
51.12f
62.48f
ESD
R103u
75 k R105
93
R107
375
R108
375
107
108
Q101
Q102
TNSGB
TNSGB
109
105
R103d
37.5 k
VEE
VCC
VEE
D102u
R102
39.5m
D
L102
753.3 pH
102
ESD
104
C102a
C102b
D102d
51.12f
62.48f
ESD
R104u
37.5 k R106
93
106
R104d
75 k
Q103a
TNSGB
VCS
VEE
VEE
110
600 A
3.3 V LVPECL MODE OPERATION
D
V1 = 1.5
V2 = 2.0
TD = 1.0 n
TR = 0.025 n
TF = 0.025 n
PW = 0.475 n
PER = 1.0 n
V1 V1 = 2.0
V2 = 1.5
+
TD = 1.0 n
TR = 0.025 n
−
TF = 0.025 n
PW = 0.475 n
PER = 1.0 n
VEE
D
VCC
V2
+
−
VEE
VEE
VCC +
VCS
VCS +
0.855 VDC −
3.3 VDC −
0
VEE
VEE
Figure 4. INBUF_01 Input Buffer
V_V1
D 0
V_V2
DB 0
V_VCC
VCC 0 3.3Vdc
V_VCS
VCS 0 .855Vdc
+PULSE 1.5 2.0 1n 0.025n 0.025n 0.475n 1n
+PULSE 2.0 1.5 1n 0.025n 0.025n 0.475n 1n
.SUBCKT INBUF_01
C_C101a
0 101 51.12f
C_C101b
0 103 62.48f
C_C102a
0 102 51.12f
C_C102b
0 104 62.48f
D_D101d
0 103 ESD
D_D101u
103 VCC ESD
D_D102d
0 104 ESD
D_D102u
104 VCC ESD
L_L101
101 103 753.3pH
L_L102
102 104 753.3pH
Q_Q101
107 105 109 TNSGB
Q_Q102
108 106 109 TNSGB
Q_Q103a
109 VCS 110 TNSGB
Q_Q103b
109 VCS 110 TNSGB
R_R101
101 D 39.5m
R_R102
102 DB 39.5m
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VEE
R109
100
Q103b
TNSGB
AND8157/D
R_R103d
103 0 37.5K
R_R103u
VCC 103 75K
R_R104d
104 0 75K
R_R104u
VCC 104 37.5K
R_R105
103 105 93
R_R106
104 106 93
R_R107
107 VCC 375
R_R108
108 VCC 375
R_R109
0 110 100
.END INBUF_01
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AND8157/D
EN AND SELx INPUT BUFFER
Input Buffer
16 pin QFN
Package
ESD and Open Pin
Default BIAS
VCC
VCC
R104
750
D101u
In
101
R101
39.5m
102
D102u
ESD
ESD
L101
753.3pH
R103
93
103
C101a
C101b
51.12f
62.48f
D101d
ESD
D102d
ESD
VEE
V1 = 2.0
V2 = 1.25
TD = 1.0 n
TR = 0.025 n
TF = 0.025 n
PW = 0.475 n
PER = 1.0 n
−
TNSGB
107
VEE
VCC
VCC
In
+
Q102
TNSGB
R102
75 k
VEE
In
104
105
Q101
R105
750
R106
18k
VCS
VEE
VCC +
VCS +
3.3Vdc −
0.855Vdc −
R107
18k
VCS
Q103
TNSGB
109
VEE
VEE
0
VEE
3.3 V LVPECL MODE OPERATION
VEE
300 A
R108
200
BIAS
VEE
Figure 5. EN and SELx Input Buffer
V_In
IN 0
V_VCC
VCC 0 3.3Vdc
V_VCS
VCS 0 0.855Vdc
+PULSE 2.0 1.25 1n 0.025n 0.025n 0.475n 1n
.SUBCKT ENb_SEL
C_C101a
0 102 51.12f
C_C101b
0 103 62.48f
D_D101d
0 103 ESD
D_D101u
103 VCC ESD
D_D102d
0 103 ESD
D_D102u
103 VCC ESD
L_L101
102 103 753.3pH
Q_Q101
105 104 107 TNSGB
Q_Q102
106 108 107 TNSGB
Q_Q103
107 VCS 109 TNSGB
R_R101
102 IN 39.5m
R_R102
103 0 75K
R_R103
103 104 93
R_R104
105 VCC 750
R_R105
106 VCC 750
R_R106
VCC 108 18K
R_R107
108 0 18K
R_R108
0 108 200
.END ENb_SEL
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106
108
AND8157/D
MR INPUT BUFFER
Input Buffer
QFN Package
ESD and OPEN PIN
DEFAULT BIAS
VCC
VCC
D101u
In
R101
39.5m 102
L101
753.3pH
C101a
C101b
51.12f
62.48f
VCC
ESD
103
R102
75 k R103
93
R104
375
105
Q101
Q102
TNSGB TNSGB
104
107
D101d
108
ESD
VEE
VEE
VEE
In
VCC
R106
18k
VCS
VEE
In
V1 = 0.8
+
V2 = 2.0
TD = 1.0 n
−
TR = 0.025 n
TF = 0.025 n
PW = 0.475 n
PER = 1.0 n VEE
VCC +
VCS +
3.3Vdc −
0.855Vdc −
R107
18k
VEE
0
Q103a
TNSGB
VCS
109
VEE
VEE
600 A
3.3 V LVPECL MODE OPERATION
BIAS
VEE
Figure 6. MR Input Buffer
+PULSE 0.8 2.0 1n 0.025n 0.025n 0.475n 1n
V_V1
IN 0
V_VCC
VCC 0 3.3Vdc
V_VCS
VCS 0 .855Vdc
.SUBCKT MRb
C_C101a
0 102 51.12f
C_C101b
0 103 62.48f
D_D101d
0 103 ESD
D_D101u
103 VCC ESD
L_L101
102 103 753.3pH
Q_Q101
105 104 108 TNSGB
Q_Q102
VCC 107 108 TNSGB
Q_Q103a
108 VCS 109 TNSGB
Q_Q103b
108 VCS 109 TNSGB
R_R101
102 IN 39.5m
R_R102
VCC 103 75K
R_R103
103 104 93
R_R104
105 VCC 375
R_R106
VCC 107 18K
R_R107
107 0 18K
R_R108
0 109 100
.END .MRb
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R108
100
Q103b
TNSGB
AND8157/D
CLKS AND VTD INPUT BUFFER
ESD and
Termination
Input Buffer
VCC
VCC
16 Pin QFN
Package
In
101
R101
39.5m
R109
750
D105u
ESD
L101
753.3pH
103
VCC
104
C101a
C101b
51.12f
62.48f
R106
1600
107
R105
1600
R110
750
109
110
Q101
TNSGB
Q102
TNSGB
D106d
ESD
111
VEE
VTD
D101u
D102u
ESD
ESD
D103d
D104d
ESD
ESD
VEE
VCC
In
VCC
R104
50
D107u
ESD
L102
753.3pH
R102
102 39.5m 105
R103
50
R107
1600
106
C102a
51.12f
C102b
D108d
ESD
R108
1600
108
Q103a
TNSGB
VCS
62.48f
112
VEE
600 A
VEE
16 pin QFN
Package
In
Q103b
TNSGB
R111
200
VEE
In
VCC
VCC +
In V1 = 2.1
V1 = 2.3
+
+ V
V2 = 2.1
V2 = 2.3
IN
−
TD = 1.0 n
TD = 1.0 n
−
−
3.3Vdc
TR = 0.025 n
TR = 0.025 n
TF = 0.025 n
TF = 0.025 n
PW = 0.475 n
PW = 0.475 n
PER = 1.0 n
VEE PER = 1.0 n VEE
VEE
VTD
VCS
VCS +
0.915Vdc
−
1.3Vdc
3.3 V LVPECL MODE OPERATION
Figure 7. CLKs and VTD Input Buffer
+PULSE 2.1 2.3 1n 0.025n 0.025n 0.475n 1n
+PULSE 2.3 2.1 1n 0.025n 0.025n 0.475n 1n
V_TD
TD 0 1.3Vdc
V_VCC
VCC 0 3.3Vdc
V_VCS
VCS 0 0.915Vdc
V_VIN
IN 0
V_VINb
INB 0
.SUBCKT CLK_IN
C_C101a
0 103 51.12f
C_C101b
0 104 62.48f
C_C102a
0 105 51.12f
C_C102b
0 106 62.48f
D_D101u
TD VCC ESD
D_D102u
TD VCC ESD
D_D103d
0 TD ESD
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+
VTD
VEE
VEE
−
VEE
0
AND8157/D
D_D104d
0 TD ESD
D_D105u
104 VCC ESD
D_D106d
0 104 ESD
D_D107u
106 VCC ESD
D_D108d
0 106 ESD
L_L101
103 104 753.3pH
L_L102
105 106 753.3pH
Q_Q101
109 107 111 TNSGB
Q_Q102
110 108 111 TNSGB
Q_Q103a
111 VCS 112 TNSGB
Q_Q103b
111 VCS 112 TNSGB
R_R101
103 IN 39.5m
R_R102
105 INB 39.5m
R_R103
104 TD 50
R_R104
TD 106 50
R_R105
104 107 1600
R_R106
VCC 107 1600
R_R107
106 108 1600
R_R108
VCC 108 1600
R_R109
109 VCC 750
R_R110
110 VCC 750
R_R111
0 112 200
.END CLK_IN
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AND8157/D
INBUF_01 INPUT BUFFER
Input Buffer
ESD and OPEN PIN
DEFAULT BIAS
QFN Package
VCC
VCC
D101u
R101
39.5m
D
101
L101
753.3pH
ESD
103
C101a
C101b
D101d
51.12f
62.48f
ESD
D
R105
93
D102u
L102
753.3pH
102
105
Q102
TNSGB TNSGB
R103d
37.5k
C102a
C102b
51.12f
62.48f
R104u
37.5 k
ESD
104
D102d
ESD
109
R106
93
106
R104d
75 k
VEE
VEE
VCS
Q103a
TNSGB
3.3 V LVPECL MODE OPERATION
D
R108
375
108
R107
375
107
Q101
VEE
VCC
VEE
R102
39.5m
R103u
75 k
D
VCC
VEE
+
V1 V1 = 2.0
V2 V
V1 = 1.5
+
+
CC
V2 = 1.5
V2 = 2.0
−
3.3Vdc
−
−
TD = 1.0 n
TD = 1.0 n
TR = 0.025 n
TR = 0.025 n
TF = 0.025 n
TF = 0.025 n
PW = 0.475 n
PW = 0.475 n
PER = 1.0 n VEE
PER = 1.0 n VEE
VEE
VCS
VCS
VEE
Figure 8. INBUF01 Input Buffer
V_V1
D 0
V_V2
DB 0
V_VCC
VCC 0 3.3Vdc
V_VCS
VCS 0 .855Vdc
+PULSE 1.5 2.0 1n 0.025n 0.025n 0.475n 1n
+PULSE 2.0 1.5 1n 0.025n 0.025n 0.475n 1n
.SUBCKT INBUF_01
C_C101a
0 101 51.12f
C_C101b
0 103 62.48f
C_C102a
0 102 51.12f
C_C102b
0 104 62.48f
D_D101d
0 103 ESD
D_D101u
103 VCC ESD
D_D102d
0 104 ESD
D_D102u
104 VCC ESD
L_L101
101 103 753.3pH
L_L102
102 104 753.3pH
Q_Q101
107 105 109 TNSGB
Q_Q102
108 106 109 TNSGB
Q_Q103a
109 VCS 110 TNSGB
Q_Q103b
109 VCS 110 TNSGB
R_R101
101 D 39.5m
R_R102
102 DB 39.5m
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110
R109
100
+
−
.855Vdc
0
600 A
Q103b
TNSGB
VEE
AND8157/D
R_R103d
103 0 37.5K
R_R103u
VCC 103 75K
R_R104d
104 0 75K
R_R104u
VCC 104 37.5K
R_R105
103 105 93
R_R106
104 106 93
R_R107
107 VCC 375
R_R108
108 VCC 375
R_R109
0 110 100
.END INBUF_01
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AND8157/D
OBUF_01 OUTPUT BUFFER DRIVING 6L239 CLKS AND VTD INPUT BUFFER
Output Buffer
Output
ESD
VCC
QFN Package
VCC
R2
360
R1
360
D10u
Q5
TNSGC
1
ESD
2
5
Q1
TNSGC
Q2
7
D10d
Q4
In
Termination
R10
39.5m
ESD
L10
753.3pH
T1
QB
C10a
C10b
51.12f
62.48f
99
VEE
TNSGB TNSGB
InB
VEE
VCC
3
VEE
D111u
VCS1
Q3
TNSGB
2.5 mA
ESD
6
4
R11
39.5m
8
D111d
R3
20
ESD
L11
753.3pH
T2
Q
C11a
C11b
51.12f
62.48f
100
R5
50
VEE
R4
50
VEE
VTT
VEE
Input Buffer V
CC
VCC
16 Pin QFN Package
ESD and Termination VCC
A
T101
R101
39.5m
101
103
L101
753.3pH
C101b
51.12f
62.48f
VEE
T102
102
R102
39.5m
104
R105
1600
ESD
105
C101a
VCC
D102u
ESD
D103d
ESD
D104d
ESD
VEE
L102
753.3pH
51.12f
62.48f
111
VCC
R104 D107u
ESD
106
C102b
TNSGB TNSGB
R103 ESD
50
50
C102a
110
109
Q101 Q102
R106
1600
107
D106d
D101u
VTD ESD
R107
1600
R108
1600
108
D108d
Q103a
TNSGB
112
VCS2
ESD
VEE
VEE
V1 = 2.5
V2 = 2.3
TD = 1.0 n
TR = 0.025 n
TF = 0.025 n
PW = 0.475 n
PER = 1.0 n
3.3 V LVPECL MODE OPERATION
In
VCC VEE
V1
V1 = 2.3
V2 = 2.5
TD = 1.0 n
TR = 0.025 n
TF = 0.025 n
PW = 0.475 n
PER = 1.0 n
+
−
VEE
0
V2
+
VEE
+
+
VCS1
0.917Vdc −
VCC −
3.3Vdc
−
0
VCS1
0
0
VEE
VCS2
+
VCS2
0.915Vdc −
VEE
VTD
VTT
+
VTT
1.3Vdc −
+
VTD
1.3Vdc −
VEE
Figure 9. OBUF_01 Output Buffer driving 6L239 CLKs and VTD Input Buffer
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VEE
Q103b
TNSGB
R111
200
600 A
VEE
VEE
In
R110
750
R109
750
D105u
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V_V1
IN 0
V_V2
INB 0
V_VCC
VCC 0 3.3Vdc
V_VCS1
VCS1 0 0.917Vdc
V_VCS2
VCS2 0 0.915Vdc
V_VTD
VTD 0 1.3Vdc
V_VTT
VTT 0 1.3Vdc
+PULSE 2.3 2.5 1n 0.025n 0.025n 0.475n 1n
+PULSE 2.5 2.3 1n 0.025n 0.025n 0.475n 1n
.SUBCKT OBUF_01
C_C10a
0 7 51.12f
C_C10b
0 QB 62.48f
C_C11a
0 8 51.12f
C_C11b
0 Q 62.48f
D_D10d
0 5 ESD
D_D10u
5 VCC ESD
L_L10
7 QB 753.3pH
L_L11
8 Q 753.3pH
Q_Q1
1 IN 3 TNSGB
Q_Q2
2 INB 3 TNSGB
Q_Q3
3 VCS1 4 TNSGB
Q_Q4
VCC 2 6 TNSGC
Q_Q5
VCC 1 5 TNSGC
R_R1
1 VCC 360
R_R10
5 7 39.5m
R_R11
6 8 39.5m
R_R2
2 VCC 360
R_R3
0 4 20
R_R4
99 VTT 50
R_R5
100 VTT 50
T_T1
QB 0 99 0 Z0=50 TD=80ps
T_T2
Q 0 100 0 Z0=50 TD=80ps
.END OBUF_01
.SUBCKT CLK_INBUF
C_C101a
0 103 51.12f
C_C101b
0 105 62.48f
C_C102a
0 104 51.12f
C_C102b
0 106 62.48f
D_D101u
VTD VCC ESD
D_D102u
VTD VCC ESD
D_D103d
0 VTD ESD
D_D104d
0 VTD ESD
D_D105u
105 VCC ESD
D_D106d
0 105 ESD
D_D107u
106 VCC ESD
D_D108d
0 106 ESD
D_D111d
0 6 ESD
D_D111u
6 VCC ESD
L_L101
103 105 753.3pH
L_L102
104 106 753.3pH
Q_Q101
109 107 111 TNSGB
Q_Q102
110 108 111 TNSGB
Q_Q103a
111 VCS2 112 TNSGB
Q_Q103b
111 VCS2 112 TNSGB
R_R101
103 101 39.5m
R_R102
104 102 39.5m
R_R103
105 VTD 50
R_R104
VTD 106 50
R_R105
105 107 1600
R_R106
VCC 107 1600
R_R107
106 108 1600
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AND8157/D
R_R108
VCC 108 1600
R_R109
109 VCC 750
R_R110
110 VCC 750
R_R111
0 112 200
T_T101
99 0 101 0 Z0=50 TD=80ps
T_T102
100 0 102 0 Z0=50 TD=80ps
.END CLK_INBUF
2.200 V
2.000 V
1.800 V
1.600 V
1.517 V
7.60 ns
7.80 ns
V(T101:B+) V(102)
8.00 ns
8.20 ns
Time
8.40 ns
8.60 ns
8.80 ns
Figure 10. Typical OBUF_01 OUTPUT Waveform driving 6L239 CLK/CLK INPUT BUFFER
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AND8157/D
OBUF_02 OUTPUT BUFFER DRIVING STANDARD LVDS TERMINATION
LVDS Output Buffer
Internal
Nodes
Output
ESD
VCC
Q1
TNSGB
InD
QFN Package
VCC
Q2
TNSGB
Q5
TNSGB
InD
D10u
ESD
Q6
TNSGB
R10
39.5m
L10
753.3 pH
5
R1
45
D10d
ESD
R2
45
C10a
51.12f
C10b
62.48f
4
3
VEE
Q9
TNSGB
InX
Q10
TNSGB
2
VEE
VCC
D111u
ESD
InX
R11
39.5m
Q11
TNSGB
VCS1
D111d
ESD
1
R3
10
4.0 mA
L11
753.3 pH
C11a
51.12f
VEE
VEE
VEE
50 Ohm T−Lines
100 ps Delay
Q
C11b
62.48f
LVDS
Termination
T1
99
V
R90
100
VEE
Q
T2
100
V
VEE
3.3V LVPECL MODE OPERATION at 1.66 GHz
InD
InD
InX
InX
VCC
V1 = 2.4
V2 = 1.85
TD = 1.0 n
TR = 0.2 n
TF = 0.2 n
PW = 0.2 n
PER = 0.8 n
+ V1
−
0
+
V1 = 1.85
V2 = 2.4
−
TD = 1.0 n
TR = 0.2 n
TF = 0.2 n
PW = 0.2 n
PER = 0.8 n
0
V2
+ V3
V1 = 1.45
V2 = 0.9
−
TD = 1.0 n
TR = 0.2 n
TF = 0.2 n
PW = 0.2 n
PER = 0.8 n
0
+
V1 = 0.9
V2 = 1.45
−
TD = 1.0 n
TR = 0.2 n
TF = 0.2 n
PW = 0.2 n
PER = 0.8 n
0
V4
VEE
+
VCC
−
3.3Vdc
VCS1
+
VCS1
0.931Vdc −
0
0
Figure 11. OBUF_02 Output Buffer driving standard LVDS termination
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VTT
+
VTT
1.3Vdc −
0
0
AND8157/D
V_V1
V_V2
V_V3
V_V4
V_VCC
V_VCS1
V_VTT
+PULSE
+PULSE
+PULSE
+PULSE
IND 0
INDB 0
INX 0
INXB 0
VCC 0 3.3Vdc
VCS1 0 .931Vdc
VTT 0 1.3Vdc
0.9 1.45 1n 0.2n 0.2n 0.2n
1.45 0.9 1n 0.2n 0.2n 0.2n
1.85 2.4 1n 0.2n 0.2n 0.2n
2.4 1.85 1n 0.2n 0.2n 0.2n
.8n
.8n
.8n
.8n
.SUBCKT OBUF_02
C_C10a
0 N66098 51.12f
C_C10b
0 QB 62.48f
C_C11a
0 N09146 51.12f
C_C11b
0 Q 62.48f
D_D10d
0 4 ESD
D_D10u
4 VCC ESD
D_D111d
0 3 ESD
D_D111u
3 VCC ESD
L_L10
N66098 QB 753.3pH
L_L11
N09146 Q 753.3pH
Q_Q1
VCC IND 5 TNSGB
Q_Q10
4 INX 2 TNSGB
Q_Q11
2 VCS1 1 TNSGB
Q_Q2
VCC IND 5 TNSGB
Q_Q5
VCC INDB N293875 TNSGB
Q_Q6
VCC INDB N293875 TNSGB
Q_Q9
3 INXB 2 TNSGB
R_R1
3 5 45
R_R10
4 N66098 39.5m
R_R11
3 N09146 39.5m
R_R2
4 N293875 45
R_R3
0 1 10
R_R90
100 99 100
T_T1
QB 0 99 0 Z0=50 TD=100ps
T_T2
Q 0 100 0 Z0=50 TD=100ps
.END OBUF_02
1.398 V
1.300 V
1.200 V
1.100 V
1.017 V
9.9 ns
10.0 ns
V(100) V(99)
10.1 ns
10.2 ns
10.3 ns
10.4 ns
10.5 ns
10.6 ns
10.7 ns
10.8 ns
10.9 ns
Time
Figure 12. Typical OBUF_02 OUTPUT BUFFER Waveform driving standard LVDS termination
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AND8157/D
APPENDIX A
************* Transistor and Diode Models for ECLinPS MAX **************
.MODEL TNSGB NPN (IS=2.18e−17 BF=179 NF=1 VAF=96.5 IKF=2.42e−02
+ ISE=3.83e−16 NE=2.5 BR=20.4 VAR=2.76 IKR=1.98e−03 ISC=2.91e−17
+ NC=1.426 RB=55 IRB=1.12e−04 RBM=48 RE=6 RC=11 CJE=7.98e−15
+ VJE=.8867 MJE=.2868 TF=2.00e−12 ITF=0.4e−02 XTF=0.7 VTF=0.6 PTF=20 TR=0.5e−9
+ CJC=4.55e−15 VJC=0.632 MJC=0.301 XCJC=0.3 CJS=4.71e−15 VJS=.4193 MJS=0.256
+ EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9)
*****************************************************************************
.MODEL TNSGC NPN (IS=1.47e−16 BF=180 NF=1 VAF=96.3 IKF=1.62e−01
+ ISE=2.96e−15 NE=2.5 BR=20.2 VAR=2.76 IKR=1.34e−02 ISC=2.14e−16
+ NC=1.426 RB=25 IRB=1.50e−03 RBM=4 RE=1 RC=7 CJE=6.34e−14
+ VJE=.8867 MJE=.2868 TF=2.00e−12 ITF=0.25e−01 XTF=0.7 VTF=0.35 PTF=20 TR=0.5e−9
+ CJC=4.08e−14 VJC=0.632 MJC=0.301 XCJC=.3 CJS=11.12e−15 VJS=.4193 MJS=0.256
+ EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9)
*****************************************************************************
.MODEL
ESD
D
(IS=9.99E−21
CJO=6.52E−14
RS=50.1
VJ=.82
*****************************************************************************
M=.25
BV=35)
APPENDIX B
RWB
0.05 MID
RWB
0.039 W
OUT
IN
MID
IN
LWB
1.36 nH
LD
0.547 nH
OUT
LWB
1.36 nH
LD
0.547 nH
C
0.188 pF
C
0.188 pF
Figure 13. Schematic Model of 8 ld SOIC Packge
Figure 14. Schematic Model of 8 ld TSSOP Packge
Table 4.
Table 5.
Package: 8−Lead SOIC (D)
Package: 8−Lead TSSOP (DT)
Component
Value
Component
Value
RWB
0.05 RWB
.039 LWB
1.36 nH
LWB
1.36 nH
LD
.547 nH
LD
.547 nH
C
0.188 pF
C
.188 pF
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AND8157/D
ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).
Adobe and Acrobat are registered trademarks of Adobe Systems Incorporated.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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AND8157/D