CAT9557 8-Bit I2C-Bus and SMBus I/O Port with Reset Description The CAT9557 is a device which provides parallel input/output port expansion for SMBus and I2C−bus applications. The CAT9557 consists of an 8−bit input port register, 8−bit output port register, and an I2C−bus/SMBus interface. It has low current consumption and a high−impedance open−drain output pin, IO0. The system master can enable the CAT9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the CAT9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the CAT9557 in the event of a time−out by asserting a LOW in the reset input. The power−on reset puts the registers in their default state and initializes the I2C−bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without turning off the power to the part. http://onsemi.com 1 SOIC−16 W SUFFIX CASE 751BG Features • • • • • • • • • • • • • • • Operating Power Supply Voltage Range of 2.3 V to 5.5 V 5 V Tolerant Inputs/Outputs 400 kHz I2C Bus Compatible Low Stand−by Current 8 General Purpose Input/Output Expander/Collector Input/Output Configuration Register Active High Polarity Inversion Register Internal Power−on Reset Noise Filter on SCL/SDA Inputs Active Low RESET Input 3 Address Pins Allowing up to 8 Devices on the I2C−bus/SMBus High−impedance Open−drain on IO0 Power−up with All Channels Configured as Inputs 16−lead SOIC and TSSOP, and 16−pad TQFN (4 x 4 mm) Packages These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Applications • White Goods (Dishwashers, Washing Machines) • Handheld Devices (Cell Phones, PDAs, Digital Cameras) • Data Communications (Routers, Hubs and Servers) © Semiconductor Components Industries, LLC, 2011 March, 2011 − Rev. 0 1 TSSOP−16 Y SUFFIX CASE 948AN TQFN−16 HV4 SUFFIX CASE 510AE MARKING DIAGRAMS See detailed marking information on page 2 of this data sheet. PIN CONNECTIONS See detailed pin connections information on page 2 of this data sheet. ORDERING INFORMATION Package Shipping† CAT9557WI−GT2 SOIC−16 (Pb−Free) 2,000 / Tape & Reel CAT9557YI−GT2 TSSOP−16 (Pb−Free) 2,000 / Tape & Reel CAT9557HV4I−GT2 TQFN−16 (Pb−Free) 2,000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 Publication Order Number: CAT9557/D CAT9557 A2 5 13 IO6 12 IO5 IO0 6 11 IO4 IO1 7 10 IO3 VSS 8 9 IO2 9557 AAAA *YWW 16 15 14 13 12 11 10 9 VDD RESET IO7 IO6 IO5 IO4 IO3 IO2 13 RESET 1 2 3 4 5 6 7 8 A0 1 12 IO7 9557 AAAA *YWW A1 2 A2 3 11 IO6 10 IO5 IO0 4 9 IO4 IO3 8 *4B CAT9557WI YMAAAA A1 4 SCL SDA A0 A1 A2 IO0 IO1 VSS 14 IO7 14 VDD 15 RESET IO2 7 SDA 2 IO1 5 16 VDD 16 SDA terminal 1 index area SCL 1 A0 3 TQFN 15 SCL TSSOP VSS 6 SOIC Transparent top view Special Marking Notes Special Marking Notes *: Assembly Location Code 4: NiPdAu Lead Finish B: Product Revision fixed as “B” CAT9557W: Product Code I: Temperature Range (Industrial) Y: Production Year (Last Digit) M: Production Month (One Digit): 1−9, (Jan−Sep), O, N, D (Oct−Dec) AAAA: Last 4 Characters of Assembly Lot Number 9557: AAAA: *: Y: WW: Product Code Last 4 Characters of Assembly Lot Number Assembly Location Code Production Year (Last Digit) Production Week (Two Digits) Pb−free Microdot Figure 1. Pin Connections Table 1. PIN FUNCTION DESCRIPTION Pin No (SO16, TSSOP16) Pin No (TQFN16) Pin Name 1 15 SCL Serial Clock Line Description 2 16 SDA Serial Data Line 3 1 A0 Address Input 0 4 2 A1 Address Input 1 5 3 A2 Address Input 2 6 4 IO0 Input/Output 0 (open−drain) 7 5 IO1 Input/Output 1 8 6 (Note 1) VSS Supply Ground 9 7 IO2 Input/Output 2 10 8 IO3 Input/Output 3 11 9 IO4 Input/Output 4 12 10 IO5 Input/Output 5 13 11 IO6 Input/Output 6 14 12 IO7 Input/Output 7 15 13 RESET 16 14 VDD Active LOW Reset Input Supply Voltage 1. TQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to the supply ground for proper device operation. For enhanced thermal, electrical, and board−level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. http://onsemi.com 2 CAT9557 CAT9557 A0 A1 A2 IO0 IO1 IO2 8−bit SCL SDA INPUT FILTER I2C−BUS/SMBus CONTROL write pulse IO3 INPUT/ OUTPUT PORTS IO4 IO5 IO6 read pulse VDD VSS IO7 POWER−ON RESET RESET Figure 2. Block Diagram of CAT9557 Data from Shift Register Configuration Register Data from Shift Register D Q Output Port Register Data FF Write Configuration Pulse Write Pulse CK Q D Q FF IO0 CK Q2 Output Port Register ESD Protection Diode VSS Input Port Register D Q Input Port Register Data FF CK Read Pulse Polarity Inversion Register Data from Shift Register D Q FF Write Polarity Pulse CK On power−up or reset, all registers return to default values. Figure 3. Simplified Schematic of IO0 http://onsemi.com 3 Polarity Inversion Register Data CAT9557 Output Port Register Data Data from Shift Register Configuration Register Data from Shift Register D VDD Q1 Q FF Write Configuration Pulse CK D Q Q FF IO1 to IO7 CK Write Pulse Q2 Output Port Register ESD Protection Diode VSS Input Port Register D Input Port Register Data Q FF CK Read Pulse Polarity Inversion Register Data from Shift Register D Polarity Inversion Register Data Q FF Write Polarity Pulse CK On power−up or reset, all registers return to default values. Figure 4. Simplified Schematic of IO1 to IO7 Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units −0.5 to +6 V −0.5 to +5.5 V DC Output Current on I/O1 to I/O7 pins (Vo = 0 to VDD) ±50 mA DC Output Current on I/O0 pin (Vo = 0 to VDD) +50 mA DC Output Current on I/O0 to I/O7 pins (VI < 0) −20 mA DC Input Current (VI < 0) −20 mA DC Input Current on I/O1 to I/O7 pins (VI < 0 or VI > VDD) ±20 mA DC Input Current on I/O0 pin (VI < 0) −20 mA VDD Supply Current 85 mA VSS Supply Current 100 mA VDD with Respect to Ground Voltage on Any Input Pin with Respect to Ground Package Power Dissipation Capability (TA = 25°C) 1.0 W Junction Temperature +150 °C Storage Temperature −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 4 CAT9557 Table 3. RELIABILITY CHARACTERISTICS Parameter Symbol Reference Test Method Min Units ESD Susceptibility VZAP (Note 2) JEDEC Standard JESD 22 2000 V Latch−up ILTH (Notes 2, 3) JEDEC Standard 17 100 mA 2. This parameter is tested initially and after a design or process change that affects the parameter. 3. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VDD +1 V. Table 4. D.C. OPERATING CHARACTERISTICS (VDD = 2.3 V to 5.5 V; VSS =0 V; TA = -40°C to +85 °C; unless otherwise specified.) Rating Symbol Conditions Min Typ Max Unit 2.3 − 5.5 V SUPPLIES Supply voltage VDD Supply current IDD Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz − 19 25 mA LOW−level standby current IstbL Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs − 0.25 3 mA HIGH−level standby current IstbH Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs − 0.25 1 mA Additional standby current DIstb Standby mode; VDD = 5.5 V; every LED I/O at VI = 4.3 V; fSCL = 0 kHz − 0.8 1 mA Power−on reset voltage (Note 4) VPOR No load; VI = VDD or VSS − 1.65 2.1 V INPUT SCL, RESET; INPUT/OUTPUT SDA LOW−level input voltage VIL −0.5 − +0.3VDD V HIGH−level input voltage VIH 0.7VDD − VDD V LOW−level output current IOL VOL = 0.4 V; VDD = 2.3 V 3 − − mA Leakage current IL VI = VDD or VSS −1 − +1 mA Input capacitance (Note 5) Ci VI = VSS − 6 10 pF I/Os LOW−level input voltage VIL −0.5 − +0.8 V HIGH−level input voltage VIH 2.0 − 5.5 V LOW−level output current (Note 6) IOL VOL = 0.5 V, VDD = 2.3 V 8 10 − mA HIGH−level output current (Note 7) IOH Except pin IO0; VOH = 2.4 V; VDD = 3 V −4 − − mA Pin IO0; VOH = 4.6 V − − 1 mA VDD = 5.5 V; VI = VSS − − −100 mA Input leakage current ILI Input capacitance (Note 5) Ci − − 5 pF Output capacitance (Note 5) Co − − 5 pF LOW−level input voltage VILA −0.5 − +0.8 V HIGH−level input voltage VIHA 2.0 − 5.5 V Input leakage current ILIA −1 − +1 mA SELECT INPUTS A0, A1, A2 4. 5. 6. 7. VDD must be lowered to 0.2 V in order to reset part. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit. The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit. http://onsemi.com 5 CAT9557 Table 5. A.C. CHARACTERISTICS (VDD = 2.3 V to 5.5 V; TA = −40°C to +85°C, unless otherwise specified.) (Note 8) Standard−mode I2C−bus Parameter Symbol Conditions Min Max Fast−mode I2C−bus Min Max Unit SCL clock frequency fSCL 0 100 0 400 kHz Bus free time between a STOP and START condition (Note 9) tBUF 4.7 − 1.3 − ms Hold time (repeated) START condition tHD;STA 4.0 − 0.6 − ms Set−up time for a repeated START condition tSU;STA 4.7 − 0.6 − ms Set−up time for STOP condition tSU;STO 4.0 − 0.6 − ms Data hold time tHD;DAT 0 − 0 − ns Data valid acknowledge time (Note 10) tVD;ACK − 1 − 0.9 ms Data valid time (Note 11) tVD;DAT − 1 − 0.9 ms Data set−up time tSU;DAT 250 − 100 − ns LOW period of the SCL clock tLOW 4.7 − 1.3 − ms HIGH period of the SCL clock tHIGH 4.0 − 0.6 − ms Fall time of both SDA and SCL signals (Notes 9 and 12) tf − 300 − 300 ns Rise time of both SDA and SCL signals (Notes 9 and 12) tr − 1000 − 300 ns tSP − 50 − 50 ns pin IO0 − 250 − 250 ns pins IO1 to IO7 Noise pulse width suppressed at the SCL and SDA inputs (Note 9) PORT TIMING Data output valid time tv(Q) − 200 − 200 ns Data input set−up time tsu(D) 0 − 0 − ns Data input hold time th(D) 200 − 200 − ns Reset pulse width tw(rst) 6 − 6 − ns Reset recovery time trec(rst) 0 − 0 − ns trst 400 − 400 − ns RESET TIMING Reset time 8. Test conditions according to “AC Test Conditions” table. 9. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 10. tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. 11. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. 12. Cb = total capacitance of one bus line in pF. Table 6. A.C. TEST CONDITIONS Input Rise and Fall time ≤ 10 ns CMOS Input Voltages 0.2 VDD to 0.8 VDD CMOS Input Reference Voltages 0.3 VDD to 0.7 VDD TTL Input Voltages 0.4 V to 2.4 V TTL Input Reference Voltages 0.8 V, 2.0 V Output Reference Voltages 0.5 VDD Output Load: SDA, INT Current Souce IOL = 3 mA; CL = 100 pF Output Load: I/Os Current Source: IOL/IOH = 10 mA; CL = 50 pF http://onsemi.com 6 CAT9557 SDA tBUF tr tLOW tHD;STA tf tSP SCL P tHD;STA S tHD;DAT tHIGH tSU;DAT tSU;STO tSU;STA Sr P Figure 5. Definition of Timing on the I2C−bus ACK or read cycle START SCL SDA 30% trst RESET 50% 50% 50% trec(rst) tw(rst) trst I/O configured 50% as inputs IOn Figure 6. Definition of RESET Timing http://onsemi.com 7 CAT9557 PIN DESCRIPTION SCL: Serial Clock A0, A1, A2: Device Address Inputs The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull−up resistor if it is driven by an open drain output. These inputs are used for extended addressing capability. The A0, A1, A2 pins should be hardwired to VDD or VSS. When hardwired, up to eight CAT9557s may be addressed on a single bus system. The levels on these inputs are compared with corresponding bits, A2, A1, A0, from the slave address byte. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire−ORed with other open drain or open collector outputs. A pull−up resistor must be connected from SDA line to VDD. The value of the pull−up resistor, RP, can be calculated based on minimum and maximum values from Figures 7 and 8 (see Note 13). I/O0 to I/O7: Input / Output Ports Any of these pins may be configured as input or output. The simplified schematic of I/O0 is shown in Figure 3 and the simplified schematic of I/O1 to I/O7 is shown in Figure 4. When an I/O is configured as an input, the output transistor Q2 from I/O0 or the output transistors Q1 and Q2 from any of the I/O1 to I/O7 are off for that particular I/O. If the I/O pin is configured as an output, the open drain output stage of I/O0 or the push−pull output stage of I/O1 to I/O7 is enabled. Care should be taken if an external voltage is applied to an I/O pin configured as an output due to the low impedance paths that exist between the pin and either VDD or VSS. RESET Input A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The CAT9557 registers and SMBus/I2C−bus state machine will be held in their default state until the RESET input is once again HIGH. This input requires a pull−up resistor to VDD if no active connection is used. 8 IOL = 3 mA @ VOLmax RPmax, MAXIMUM RP VALUE (KW) RPmin, MINIMUM RP VALUE (KW) 2.5 2.0 1.5 1.0 0.5 0 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 6 5 4 3 2 1 0 5.6 Fast Mode I2C Bus / tr max − 300 ns 7 0 50 100 150 200 250 300 350 400 450 VDD, SUPPLY VOLTAGE (V) CBUS, BUS CAPACITANCE (pF) Figure 7. Minimum RP Value vs. Supply Voltage Figure 8. Maximum RP Value vs. Bus Capacitance 13. According to the Fast Mode I2C bus specification, for bus capacitance up to 200 pF, the pull up device can be a resistor. For bus loads between 200 pF and 400 pF, the pull−up device can be a current source (Imax = 3 mA) or a switched resistor circuit. http://onsemi.com 8 CAT9557 FUNCTIONAL DESCRIPTION The CAT9557 general purpose input / output (GPIO) peripherals provide up to eight I/O ports, controlled through an I2C compatible serial interface. The CAT9557 supports the I2C Bus data transmission protocol. This I2C Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT9557 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. when SCL is HIGH. The device monitors the SDA and SCL lines and will not respond until this condition is met. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Device Addressing After the bus Master sends a START condition, a slave address byte is required to enable the CAT9557 for a read or write operation. The four most significant bits of the slave address are fixed as binary 0011 (Figure 10). The device uses the next three bits as address bits. The address bits A2, A1 and A0 are used to select which device is accessed from maximum eight devices on the same bus. These bits must compare to their hardwired input pins. The 8th bit following the 7−bit slave address is the R/W bit that specifies whether a read or write operation is to be performed. When this bit is set to “1”, a read operation is initiated, and when set to “0”, a write operation is selected. Following the START condition and the slave address byte, the CAT9557 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT9557 then performs a read or a write operation depending on the state of the R/W bit. To conserve power, no internal pull−up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. I2C Bus Protocol The features of the I2C bus protocol are defined as follows: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition (Figure 9). START and STOP Conditions The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA SCL SDA START CONDITION STOP CONDITION Figure 9. START/STOP Condition SLAVE ADDRESS 0 0 1 1 A2 FIXED A1 A0 PROGRAMMABLE HARDWARE SELECTABLE Figure 10. CAT9557 Slave Address http://onsemi.com 9 R/W CAT9557 Acknowledge Table 9. REGISTER 1 − Output Port Register Bit Allocation After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 9). The CAT9557 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8−bit byte. When the CAT9557 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT9557 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a STOP condition to return the CAT9557 to the standby power mode and place the device in a known state. Protocol Function Input port register 0x01 Read/write byte Output port register 0x02 Read/write byte Polarity inversion register 0x03 Read/write byte Configuration register The command byte is the first byte to follow the device address byte during a write/read bus transaction. The register command byte acts as a pointer to determine which register will be written or read. The input port register is a read only port. It reflects the incoming logic levels of the I/O pins, regardless of whether the pin is defined as an input or an output by the configuration register. Writes to the input port register are ignored. The default value, X, is determined by the externally applied logic level. 7 6 5 4 3 2 1 0 Symbol I7 I6 I5 I4 I3 I2 I1 I0 Default x x x x x x x x 4 3 2 1 0 O4 O3 O2 O1 O0 Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol N7 N6 N5 N4 N3 N2 N1 N0 Default 1 1 1 1 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol C7 C6 C5 C4 C3 C2 C1 C0 Default 1 1 1 1 1 1 1 1 Power−On Reset Operation When power is applied to VDD, an internal Power−On Reset (POR) holds the CAT9557 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the CAT9557 registers and I2C−bus/SMBus state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. Table 8. REGISTER 0 − Input Port Register Bit Allocation Bit 5 O5 The output port register sets the outgoing logic levels of the I/O ports, defined as outputs by the configuration register. Bit values in this register have no effect on I/O pins defined as inputs. Reads from the output port register reflect the value that is in the flip−flop controlling the output, not the actual I/O pin value. The polarity inversion register allows the user to invert the polarity of the input port register data. If a bit in this register is set (“1”) the corresponding input port data is inverted. If a bit in the polarity inversion register is cleared (“0”), the original input port polarity is retained. The configuration register sets the directions of the ports. Set the bit to “1” in the configuration register to enable the corresponding port pin as an input with a high impedance output driver. If a bit in this register is cleared (“0”), the corresponding port pin is enabled as an output. At power−up, the I/Os are configured as inputs. Data is transmitted to the CAT9557 registers using the write mode shown in Figure 11 and Figure 12. The CAT9557 registers are read according to the timing diagrams shown in Figure 13 and Figure 14. Once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte will be sent. Table 7. REGISTER COMMAND BYTE Read byte 6 O6 Table 11. REGISTER 3 − Configuration Register Bit Allocation Refer to Figure 2. Block Diagram of CAT9557. The CAT9557 consists of an input port register, an output port register, a polarity inversion register and a configuration register. Table 7 shows the register address table. Tables 8 to 11 list Register 0 through Register 3 information. 0x00 7 O7 Table 10. REGISTER 2 − Polarity Inversion Register Bit Allocation Registers and Bus Transactions Command (hex) Bit Symbol http://onsemi.com 10 CAT9557 SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 0 0 1 command byte 0 1 A2 A1 A0 A R/W START condition 0 0 0 0 0 STOP condition data to port 0 0 1 A DATA 1 A acknowledge from slave acknowledge from slave P acknowledge from slave write to port tv(Q) data out from port DATA 1 VALID Figure 11. Write to Output Port Register SCL 1 2 3 4 5 6 7 8 9 slave address S SDA 0 0 1 command byte 1 A2 A1 A0 0 A R/W START condition 0 0 0 0 0 0 STOP condition data to register 1 1/0 acknowledge from slave A DATA A acknowledge from slave P acknowledge from slave Figure 12. Write to I/O Configuration or Polarity Inversion Registers slave address SDA S 0 0 1 command byte 1 A2 A1 A0 0 A A R/W START condition acknowledge from slave acknowledge from slave slave address (cont.) S 0 0 1 data from register 1 A2 A1 A0 1 (repeated) START condition (cont.) A DATA (first byte) R/W acknowledge from slave data from register A acknowledge from master DATA (last byte) no acknowledge from master at this moment master−transmitter becomes master−receiver and slave−receiver becomes slave−transmitter Figure 13. Read from Register http://onsemi.com 11 NA P STOP condition CAT9557 no acknowledge from master slave address SDA S 0 0 1 data from port 1 A2 A1 A0 1 START condition A R/W data from port A DATA 1 acknowledge from slave NA P DATA 4 acknowledge from master STOP condition read from port th(D) data into port tsu(D) DATA 1 DATA 2 DATA 3 DATA 4 Remark: This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. Figure 14. Read Input Port Register APPLICATIONS INFORMATION VDD (5 V) VDD MASTER CONTROLLER SCL SDA 1.8 kW 620 W 2 kW 1.8 kW VDD 2 kW RESET 100 kW (x 4) CAT9557 IO0 SCL SDA INT. IO1 RESET IO2 IO3 VDD IO4 VSS TEMPERATURE SENSOR IO5 A2 IO6 A1 A0 IO7 BEEPER KEYPAD 2N3904 Device address configured as 0011 100x for this example. IO0, IO2, IO3 configured as outputs. IO1, IO4, IO5 configured as inputs. IO6, IO7 are not used. Figure 15. Typical Application http://onsemi.com 12 CAT9557 Minimizing IDD when the I/Os are Used to Control LEDs When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 15. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 16 shows a high value resistor in parallel with the LED. Figure 17 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. VDD VDD LED 3.3 V 100 kW VDD IOn 5V LED IOn Figure 16. High Value Resistor in Parallel with the LED Figure 17. Device Supplied by a Lower Vol http://onsemi.com 13 CAT9557 PACKAGE DIMENSIONS TQFN16, 4x4 CASE 510AE−01 ISSUE A A D DETAIL A E2 E PIN#1 ID PIN#1 INDEX AREA TOP VIEW SIDE VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 BOTTOM VIEW e b 0.20 REF b 0.25 0.30 0.35 D 3.90 4.00 4.10 D2 2.00 −−− 2.25 E 3.90 4.00 4.10 E2 2.00 −−− 2.25 e L D2 A1 L DETAIL A 0.65 BSC 0.45 −−− A 0.65 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-220. A1 A3 FRONT VIEW http://onsemi.com 14 CAT9557 PACKAGE DIMENSIONS SOIC−16, 150 mils CASE 751BG−01 ISSUE O E1 E SYMBOL MIN NOM MAX A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 D 9.80 9.90 10.00 0.25 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 1.27 BSC e h 0.25 0.50 L 0.40 1.27 θ 0º 8º PIN#1 IDENTIFICATION TOP VIEW D h q A e b A1 c L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 15 CAT9557 PACKAGE DIMENSIONS TSSOP16, 4.4x5 CASE 948AN−01 ISSUE O b SYMBOL MIN NOM A E1 E MAX 1.10 A1 0.05 0.15 A2 0.85 0.95 b 0.19 0.30 c 0.13 0.20 D 4.90 5.10 E 6.30 6.50 E1 4.30 4.50 e 0.65 BSC L 1.00 REF L1 0.45 0.75 θ 0º 8º e PIN#1 IDENTIFICATION TOP VIEW D A2 A c θ1 A1 L1 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 16 L CAT9557 Example of Ordering Information (Notes 14 to 17) Prefix Device # Suffix CAT 9557 W Business Group ID Product Number 9557 I −G T2 Temperature Range I = Industrial (−40°C to +85°C) Lead Finish G: NiPdAu Tape & Reel T: Tape & Reel 2: 2,000 / Reel Package W: SOIC−16 Y: TSSOP−16 HV4: TQFN−16 14. All packages are RoHS−compliant (Lead−free, Halogen−free). 15. The standard finish is NiPdAu. 16. The device used in the above example is a CAT9557WI−GT2 (CAT9557, SOIC−16, Industrial Temperature, NiPdAu, Tape & Reel, 2,000/Reel). 17. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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