Not Recommended for New Design CAT523 Dual Digitally Programmable Potentiometer (DPP) with 256 Taps and Microwire Interface FEATURES DESCRIPTION Two 8-bit DPPs configured as programmable voltage sources in DAC-like applications Common reference inputs Non-volatile NVRAM memory wiper storage Output voltage range includes both supply rails 2 independently addressable buffered output wipers 1 LSB accuracy, high resolution Serial microwire-like interface Single supply operation: 2.7V - 5.5V Setting read-back without effecting outputs The CAT523 is a dual, 8-bit digitally-programmable potentiometer (DPP) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for systems capable of self calibration, and applications where equipment which is either difficult to access or in a hazardous environment, requires periodic adjustment. The two independently programmable DPPs have a common output voltage range which includes both supply rails. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DPP’s output. For Ordering Information details, see page 14. APPLICATIONS Automated product calibration. Remote control adjustment of equipment Offset, gain and zero adjustments in selfcalibrating and adaptive control systems. Tamper-proof calibrations. DAC (with memory) substitute Control of the CAT523 is accomplished with a simple 3-wire, Microwire-like serial interface. A Chip Select pin allows several CAT523's to share a common serial interface and communication back to the host controller is via a single serial data line thanks to the CAT523’s Tri-Stated Data Output pin. A RDY/BSY ¯¯¯¯ output working in concert with an internal low voltage detector signals proper operation of non-volatile NVRAM memory Erase/Write cycle. PIN CONFIGURATION PDIP 14-Lead (L) SOIC 14-Lead (W) VDD 1 14 VREFH CLK 2 13 VOUT1 RDY/¯¯¯¯ BSY 3 12 VOUT2 4 CAT523 11 NC 5 10 NC DO 6 9 VREFL PROG 7 8 GND CS DI © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice The CAT523 is available in the 0°C to 70°C Commercial and -40°C to + 85°C Industrial operating temperature ranges and offered in 14-pin plastic DIP and SOIC mount packages. 1 Doc. No. MD-2005 Rev. I CAT523 Not Recommended for New Design FUNCTIONAL DIAGRAM CS 7 PROGRAM CONTROL 5 2 SERIAL CONTROL 4 24kΩ 3 13 VOUT1 – + 12 VOUT2 – SERIAL DATA OUTPUT REGISTER CAT523 6 8 DO 9 GND Doc. No. MD-2005 Rev. I + 24kΩ CLK 14 24kΩ DI 1 24kΩ PROG VREFH WIPER CONTROL REGISTERS AND NVRAM RDY/BSY VDD VREFL 2 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT523 ABSOLUTE MAXIMUM RATINGS Parameters Ratings Supply Voltage(1) VDD to GND Inputs CLK to GND CS to GND DI to GND ¯¯¯¯ to GND RDY/BSY PROG to GND VREFH to GND VREFL to GND Units -0.5 to +7 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 V V V V V V V V Parameters Outputs D0 to GND VOUT 1– 4 to GND Operating Ambient Temperature Commercial (‘C’ or Blank suffix) Industrial (‘I’ suffix) Junction Temperature Storage Temperature Lead Soldering (10 sec max) Ratings Units -0.5 to VDD +0.5 V -0.5 to VDD +0.5 V 0 to +70 °C -40 to +85 +150 -65 to +150 +300 °C °C °C °C RELIABILITY CHARACTERISTICS Symbol Parameter Test Method Min VZAP(2) ILTH(2)(3) Max Units ESD Susceptibility MIL-STD-883, Test Method 3015 2000 V Latch-Up JEDEC Standard 17 100 mA POWER SUPPLY Symbol Parameter Conditions IDD1 Supply Current (Read) IDD2 Supply Current (Write) VDD Min Typ Max Units Normal Operating — 400 600 µA Programming, VDD = 5V — 1600 2500 µA VDD = 3V — 1000 1600 µA 2.7 — 5.5 V Min Typ Max Units Operating Voltage Range LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD — — 10 µA IIL Input Leakage Current VIN = 0V — — -10 µA VIH High Level Input Voltage 2 — VDD V VIL Low Level Input Voltage 0 — 0.8 V LOGIC OUTPUTS Symbol Parameter Conditions Min Typ Max Units VOH High Level Output Voltage IOH = -40µA VDD -0.3 — — V VIL Low Level Output Voltage IOL = 1mA, VDD = +5V — — 0.4 V IOL = 0.4mA, VDD = +3V — — 0.4 V Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 3 Doc. No. MD-2005 Rev. I CAT523 Not Recommended for New Design POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol RPOT Parameter Conditions Potentiometer Resistance See note 3 Min Typ Max 24 RPOT to RPOT Match — Units kΩ ±0.5 Pot Resistance Tolerance ±1 % ±20 % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin 0 VDD - 2.7 V Resolution 0.4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 Ω IOUT Buffer Output Current 3 mA TCRPOT TC of Pot Resistance 300 ppm/ºC CH/CL Potentiometer Capacitances 8/8 pF AC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Minimum CS Low Time 150 — — ns tCSS CS Setup Time 100 — — ns tCSH CS Hold Time 0 — — ns tDIS DI Setup Time 50 — — ns 50 — — ns Digital tCSMIN CL = 100pF (1) tDIH DI Hold Time tDO1 Output Delay to 1 — — 150 ns tDO0 Output Delay to 0 — — 150 ns tHZ Output Delay to High-Z — 400 — ns tLZ Output Delay to Low-Z — 400 — ns tBUSY — 4 5 ms PROG Setup Time 150 — — ns tPROG Minimum Pulse Width 700 — — ns tCLKH Minimum CLK High Time 500 — — ns tCLKL Minimum CLK Low Time 300 — — ns Clock Frequency DC — 1 MHz CLOAD = 10pF, VDD = +5V — 3 10 µs CLOAD = 10pF, VDD = +3V — 6 10 µs tPS fC Erase/Write Cycle Time Analog tDS DPP Settling Time to 1 LSB Notes: (1) All timing measurements are defined at the point of signal crossing VDD / 2. (2) These parameters are periodically sampled and are not 100% tested. (3) The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between VREFH and VREFL of 6kΩ +20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value. Doc. No. MD-2005 Rev. I 4 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT523 A.C. TIMING DIAGRAM to 1 2 3 4 5 tCLK H CLK tCSS tCLK L t CSH CS tCSMIN tDIS DI tDIH t DO0 tLZ DO tHZ tDO1 PROG t PS tPROG RDY/BSY tBUSY to © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 1 2 3 5 4 5 Doc. No. MD-2005 Rev. I CAT523 Not Recommended for New Design PIN DESCRIPTION Pin Name 1 VDD Power supply positive 2 CLK Clock input pin 3 ¯¯¯¯ RDY/BSY 4 CS Chip select 5 DI Serial data input pin 6 DO Serial data output pin 7 PROG 8 GND Power supply ground 9 VREFL Minimum DAC output voltage 10 NC No Connect 11 NC No Connect 12 VOUT2 DPP output channel 2 13 VOUT1 DPP output channel 1 14 VREFH Maximum DPP output voltage DPP addressing is as follows: Function Ready/Busy output A0 A1 VOUT1 0 0 VOUT2 1 0 EEPROM Programming Enable Input DEVICE OPERATION Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. The CAT523 is a dual 8-bit configured digitally programmable potentiometer (DPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. CHIP SELECT Chip Select (CS) enables and disables the CAT523’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. DIGITAL INTERFACE The CAT523 employs a 3 wire, Microwire-like, serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all ope– rations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DPP address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Doc. No. MD-2005 Rev. I DPP OUTPUT CLOCK The CAT523’s clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. 6 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT523 ¯¯¯¯ will remain high following the program RDY/BSY command indicating a failure to record the desired data in non-volatile memory. No clock is necessary upon system power-up. The CAT523’s internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. DATA OUTPUT Data is output serially by the CAT523, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 523s to share a single serial data line and simplifies interfacing multiple 523s to a microprocessor. VREF VREF, the voltage applied between pins VREFH & VREFL, sets the DPP’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH & VREFL are connected across the power supply rails. When using less than the full supply voltage VREFH is restricted to voltages between VDD and VDD/2 and VREFL to voltages between GND and VDD/2. WRITING TO MEMORY Programming the CAT523’s non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bitfollowed by a two bit DPP address and eight data bits are clocked into the DPP control register via the DI pin. Data enters on the clock’s rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. Programming is achieved by bringing PROG high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DAC control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of ramping the programming voltage for data transfer to the nonvolatile memory cells. The CAT523’s non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 100 years without being refreshed. ¯¯¯¯¯ READY/BUSY When saving data to non-volatile memory, the ¯¯¯¯) signals the start and Ready/Busy output (RDY/BSY duration of the non-volatile erase/write cycle. Upon receiving a command to store data (PROG goes high) ¯¯¯¯ goes low and remains low until the RDY/BSY programming cycle is complete. During this time the CAT523 will ignore any data appearing at DI and no data will be output on DO. ¯¯¯¯ is internally ANDed with a low voltage RDY/BSY detector circuit monitoring VDD. If VDD is below the minimum value required for non-volatile programming, Figure 1. Writing to Memory to 1 2 3 4 5 6 A0 A1 D0 D1 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA DI 1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 PROG RDY/BSY DPP OUTPUT © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice CURRENT DPP VALUE NEW DPP VALUE NEW DPP VALUE NON-VOL ATILE VOLATILE NON-VOL ATILE 7 Doc. No. MD-2005 Rev. I CAT523 Not Recommended for New Design READING DATA Each time data is transferred into a DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP’s output. This feature allows µPs to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. TEMPORARILY CHANGE OUTPUT The CAT523 allows temporary changes in DPP’s output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. Figure 3 shows the control and data signals needed to effect a temporary output change. DPP wiper settings may be changed as many times as required and can be made to any of the two DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all two DPPs will return to the output values stored in non-volatile memory. Since this value is the same as that which had been there previously no change in the DPP’s output is noticed. Had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle’s conclusion. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP wiper control register prior to programming. This is because the CAT523’s internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no PROG signal is received. Figure 3. Temporary Change in Output Figure 2. Reading from Memory to 1 2 3 4 5 6 7 8 9 10 11 12 to CS 1 2 3 4 5 6 A0 A1 D0 D1 D0 D1 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA DI 1 A0 A1 DI CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D6 1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA D7 DO D2 D3 D4 D5 PROG PROG RDY/BSY DPP OUTPUT RDY/BSY CURRENT DPP VALUE DPP OUTPUT NON-VOL ATILE Doc. No. MD-2005 Rev. I 8 CURRENT DPP VALUE NEW DPP VALUE CURRENT DPP VALUE NON-VOL ATILE VOLATILE NON-VOL ATILE © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT523 APPLICATION CIRCUITS +5V VI RI DPP INPUT RF DPP OUTPUT VDPP +15V CONTROL & DATA CAT523 VDPP OP 07 -15V VOUT = LSB VOUT + VREFL GND MSB – VREFH VDD VDPP ( RI + RF ) - VI R F RI For R I = RF VOUT = 2VDPP - VI 1111 1111 1000 0000 0111 1111 0000 0001 0000 0000 ANALOG OUTPUT CODE x (VFS - VZERO) + VZERO = 255 VFS = 0.99VREF VREF = 5V VZERO = 0.01VREF RI = RF 255 × 0.98VREF + 0.01VREF = 0.990 VREF 255 128 × 0.98VREF + 0.01VREF = 0.502VREF 255 127 × 0.98VREF + 0.01VREF = 0.498 VREF 255 1 × 0.98VREF + 0.01VREF = 0.014 VREF 255 0 × 0.98VREF + 0.01VREF = 0.010 VREF 255 VOUT = +4.90V VOUT = +0.02V VOUT = -0 .02V VOUT = -4.86V VOUT = -4.90V Bipolar DPP Output V+ I > 2mA +5V RI RF +15V VREFH VDD CONTROL & DATA VDD VOUT + CAT523 GND VREF = 5.00V – CONTROL & DATA OP 07 -15V VREFL VREFH CAT523 GND LT 1029 VREFL R VOUT = (1 + F ) VDPP RI Digitally Trimmed Voltage Reference Amplified DPP Output 28 ÷ 32V 15kΩ 10µF 10kΩ 1N5231B VDD CONTROL & DATA VREFH 5.1V CAT523 GND + VREFL – MPT3055EL LM 324 OUTPUT 1.00kΩ 4.02kΩ 10µF 35V 0 - 25V @ 1A Digitally Controlled Voltage Reference © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 9 Doc. No. MD-2005 Rev. I CAT523 +5V Not Recommended for New Design +5V VREF VDD VDD VREFH FINE ADJUST DPP 127RC 127RC RC = CAT523 +V RC COARSE ADJUST DPP RC = VREFH FINE ADJUST DPP CAT523 GND +VREF VOFFSET – VREFL RC COARSE ADJUST DPP + GND VREFL R0 = R0 (+VREF) - (VOFFSET+) 1µA (-VREF) + (VOFFSET+) 1µA VOFFSET +V + -VREF VREF – 256 x 1µA -V Fine adjust gives ±1 LSB change in VOFFSET when VOFFSET = VREF/2 Coarse-Fine Offset Control by Averaging DPP Outputs for Dual Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs for Single Power Supply Systems +5V 2.2kΩ VDD VREFH 4.7µF LM385-2.5 ISINK = 2 - 255mA +15V DPP1 + 1mA steps 2N7000 – +5V CONTROL & DATA 10kΩ 10kΩ CAT523 39Ω 1W 39Ω 1W DPP2 + 5µA steps 2N7000 – GND VREFL 5MΩ 5MΩ 3.9kΩ 10kΩ 10kΩ – TIP30 + Current Sink with 4 Decades of Resolution Doc. No. MD-2005 Rev. I 10 -15V © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT523 +15V 51kΩ + TIP29 – 10kΩ 10kΩ 5MΩ 39Ω 1W +5V VREFH VDD 5MΩ DPP1 39Ω 1W – CONTROL & DATA CAT523 BS170P + 5MΩ 5MΩ 1mA steps 3.9kΩ DPP2 GND – VREFL + BS170P 5µA steps LM385-2.5 -15V ISOURCE = 2 ÷ 255mA Current Source with 4 Decades of Resolution © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 11 Doc. No. MD-2005 Rev. I CAT523 Not Recommended for New Design PACKAGE OUTLINE DRAWINGS PDIP 14-Lead (L)(1)(2) SYMBOL MIN A 3.56 5.33 A1 0.38 2.92 3.30 4.95 b 0.36 0.45 0.55 b1 1.15 1.52 1.77 c 0.21 0.26 0.35 D 18.67 19.05 19.68 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e TOP VIEW MAX A2 E1 D NOM 2.54 BSC eB 7.88 L 2.99 10.92 3.30 3.81 E A2 A c A1 e L b b1 eB SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-001. Doc. No. MD-2005 Rev. I 12 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT523 SOIC 14-Lead (W)(1)(2) E1 SYMBOL MIN A 1.35 A1 0.10 0.25 b 0.33 0.51 c 0.19 D 8.55 E E1 E NOM MAX 1.75 0.25 8.65 8.75 5.80 6.00 6.20 3.80 3.90 4.00 e 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º PIN#1 IDENTIFICATION TOP VIEW h D θ A e b c L A1 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-012. © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 13 Doc. No. MD-2005 Rev. I CAT523 Not Recommended for New Design EXAMPLE OF ORDERING INFORMATION Prefix Device # Suffix CAT 523 W Optional Company ID I Temperature Range I = Industrial (-40ºC to 85ºC) Product Number 523 T2 Tape & Reel T: Tape & Reel 2: 2000/Reel Package L: PDIP W: SOIC Notes: (1) (2) (3) All packages are RoHS compliant (Lead-free, Halogen-free). Standard lead finish is Matte-Tin. This device used in the above example is a CAT523WI-T2 (SOIC, Industrial Temperature, Tape & Reel). ORDERING PART NUMBER CAT523LI CAT523WI Doc. No. MD-2005 Rev. I 14 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT523 REVISION HISTORY Date 16-Mar-04 Revision D Description Updated Potentiometer Characteristics 12-Jul-04 E Updated Functional Diagram Updated Potentiometer Characteristics Added Note 3 under Potentiometer/AC Characteristics tables 26-Jul-07 F Add Package Outline Drawings Updated Example of Ordering Information Added MD- to document number 08-Oct-07 G Change title Update Writing to Memory 15-Jul-08 H Add “Not Recommended for New Design” to the top of all pages 24-Nov-08 I Change logo and fine print to ON Semiconductor ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 15 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Doc. No. MD-2005 Rev. I