Ordering number : ENA1265A LV51135T CMOS IC 2-Cell Lithium-Ion Secondary Battery Protection IC http://onsemi.com Overview The LV51135T is a protection IC for 2-cell lithium-ion secondary batteries. Features • Monitoring function for each cell: Detects overcharge and over-discharge conditions and controls the charging and discharging operation of each cell. Over-charge detection accuracy ±25mV Over-discharge detection accuracy ±100mV The hysteresis of over-discharge detection voltage is cancelled by connection of a load after overcharging has been detected. Detects over-currents, load shorting, and excessively high voltage of a charger. Normal operation mode typ. 6.0μA Stand by mode max. 0.2μA Charging is enabled even when the cell voltage is 0V by giving a voltage between the VDD pin and V- pin. • High detection voltage accuracy: • Hysteresis cancel function: • Discharge current monitoring function: • Low current consumption: • 0V cell charging function: Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Power supply voltage Symbol Conditions VDD V- Input voltage Ratings Unit -0.3 to +12 V VDD-28 to VDD+0.3 V Charger minus voltage Output voltage Cout pin voltage Vcout VDD-28 to VDD+0.3 V Dout pin voltage Vdout VSS-0.3 to VDD+0.3 V Allowable power dissipation Pd max Independent IC 170 mW Operating ambient temperature Topr -30 to +80 °C Storage temperature Tstg -40 to +125 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Semiconductor Components Industries, LLC, 2013 August, 2013 81011HKPC/71608MS 20080603-S00001 No.A1265-1/8 LV51135T Electrical Characteristics at Ta = 25°C, unless especially specified. Parameter Symbol Conditions Operation input voltage Vcell Voltage between VDD and VSS 0V cell charging minimum operation Vmin Voltage between VDD-V- under VDD-VSS =0 Ratings min typ Unit max 1.5 10 V 1.5 V voltage Over-charge detection voltage Over-charge release voltage Vd1 Vr1 4.225 4.250 4.275 V Ta=0 to 45°C *1 4.215 4.250 4.285 V V- ≤ Vd3 4.000 4.050 4.100 V V- > Vd3 4.150 4.260 V Over-charge detection delay time td1 VDD-Vc=3.5V→4.5V, Vc-VSS=3.5V 0.5 1.0 1.5 s Over-charge release delay time tr1 VDD-Vc=4.5V→3.5V, Vc-VSS=3.5V 20.0 40.0 60.0 ms Over-discharge detection voltage Vd2 2.30 2.40 2.50 V Over-discharge release hysteresis Vh2 10.0 20.0 42.0 mV 50 100 150 ms ms voltage Over-discharge detection delay time Over-discharge release delay time td2 0.5 1.0 1.5 Over-current detection voltage Vd3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.130 0.150 0.170 V Over-current release hysteresis voltage Vh3 VDD-Vc=3.5V, Vc-VSS=3.5V 5.0 10.0 20.0 mV Over-current detection delay time td3 VDD-Vc=3.5V, Vc-VSS=3.5V 10.0 20.0 30.0 ms Over-current release delay time tr3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.5 1.0 1.5 ms Vd4 VDD-Vc=3.5V, Vc-VSS=3.5V 1.0 1.3 1.6 V Short circuit detection voltage tr2 VDD-Vc=3.5V→2.2V, Vc-VSS=3.5V VDD-Vc=2.2V→3.5V, Vc-VSS=3.5V Short circuit detection delay time td4 VDD-Vc=3.5V, Vc-VSS=3.5V 0.125 0.250 0.500 ms Excessive charger detection voltage Vd5 Between VDD-Vc=3.5V, Vc-VSS=3.5V Voltage between V- and VSS -0.60 -0.45 -0.30 V Excessive charge detection release Vh5 VDD-Vc=3.5V, Vc-VSS=3.5V 25.0 50.0 100.0 mV Stand-by release voltage Vstb Between VDD-Vc=2.0V, Vc-VSS=2.0V Voltage between V- and VSS VDD×0.4 VDD×0.5 VDD×0.6 Excessive charger detection delay time td5 VDD-Vc=3.5V, Vc-VSS=3.5V *2 0.5 1.5 3.0 ms tr5 hysteresis voltage Excessive charger release delay time V VDD-Vc=3.5V, Vc-VSS=3.5V 0.5 1.5 3.0 ms Internal resistance (VM-VDD) RDD After over-discharge is detected. 100 200 400 kΩ Internal resistance (VM-VSS) RSS After over-current or short-circuit is detected. 15 30 60 kΩ Cout Nch ON voltage VOL1 IOL=50μA, VDD-Vc=4.4V, Vc-VSS=4.4V Cout Pch ON voltage VOH1 IOL=50μA, VDD-Vc=3.9V, Vc-VSS=3.9V Dout Nch ON voltage VOL2 IOL=50μA, VDD-Vc=2.2V, Vc-VSS=2.2V Dout Pch ON voltage VOH2 IOL=50μA, VDD-Vc=3.9V, Vc-VSS=3.9V 0.5 VDD-0.5 V V 0.5 V VDD-0.5 V Vc input current Ivc VDD-Vc=3.5V, Vc-VSS=3.5V 0.0 1.0 μA Current consumption IDD VDD-Vc=3.5V, Vc-VSS=3.5V 6.0 13.0 μA Istb VDD-Vc=2.2V, Vc-VSS=3.5V 0.2 μA Vtest VDD-Vc=3.5V, Vc-VSS=3.5V VDD×0.5 VDD×0.6 V Stand-by current T-terminal input ON voltage VDD×0.4 *1 The Ratings of the table above is a design targets and are not measured. *2 Under over-discharge state, delay operation starts after release of over-discharge. No.A1265-2/8 LV51135T Package Dimensions unit : mm (typ) 3245B Pd max -- Ta Allowable power dissipation, Pd max -- mW 200 3.0 0.5 3.0 4.9 8 1 (0.53) 2 0.65 0.125 1.1MAX (0.85) 0.25 Independent IC 170 150 100 68 50 0 -30 -20 0 20 40 60 80 100 0.08 Ambient temperature, Ta -- °C SANYO : MSOP8(150mil) Pin Assignment Dout T 8 7 1 2 VDD Cout Vc Sense 6 5 3 V- 4 Top view VSS Pin Functions Pin No. 1 Symbol VDD Description VDD pin 2 Cout Overcharge detection output pin 3 V- Charger minus voltage input pin 4 VSS VSS pin 5 Sense Sense pin 6 Vc Intermediate between both cell voltage input pin 7 T Pin to shorten detection time (“H”:Shortening mode, “L” or “Open”:Normal mode) 8 Dout Overdischarge detection output pin No.A1265-3/8 LV51135T Block Diagram Sence 5 VDD 1 Level shift + - + + - Vc 6 td5,tr5 2 Cout td1,tr1 Delay control logic + - td2,tr2 8 Dout + + - td3,tr3 + - 4 VSS 3 V- td4 7 T No.A1265-4/8 LV51135T Functional Description Over-charge detection If either of the cell voltage is equal to or more than the over-charge detection voltage, stop further charging by turning “L” the Cout pin and turning off external Nch MOS FET after the over-charge detection delay time. This delay time is set by the internal counter. The over-charge detection comparator has the hysteresis function. Note that this hysteresis can be cancelled by connecting the load after detection of over-charge detection. and it becomes small hysteresis comparator has its own. Once over-charge detection is made, over-current detection is not made to prevent incorrect operations. Note that short-circuit can be detected. Over-charge release If both cell voltages become equal to or less than the over-charge release voltage when VM voltage is equal to or less than Vd3, or when VM voltage is more than Vd3 with load connected, the Cout pin returns to “H” after the overcharge release delay time set by the internal counter. When VM voltage is more than Vd3 with load connected and either cell or both cell voltages are equal to or more than the over-charge release voltage, the Cout pin does not return to “H”. But the load current flows through the parasitic diode of external Nch MOS FET on Cout, consequently each cell voltage becomes equal to or less than over-charge release voltage, the Cout pin returns to “H.” after the over-charge release delay time. However, excessive voltage charger is connected as mentioned below, Cout pin does not return to “H” because excessive charger detection starts after over-charge release operation. Over-discharge detection When either cell voltage is equal to or less than over-discharge voltage, the IC stops further discharging by turning the Dout pin “L” and turning off external Nch MOS FET after the over-charge detection delay time. The IC goes into stand-by mode after detecting over-discharge and its consumption current is kept at about 0A. After over-discharge detection, the V- pin will be connected to VDD pin via internal resistor (typ 200kΩ). Over-discharge release Release from over-discharge is made by only connecting charger. If the V- pin voltage becomes equal to or lower than the stand-by release voltage by connecting charger after detecting over-discharge, The IC is released from the stand-by state to start cell voltage monitoring. While both cell voltages are equal to or less than over-discharge voltages, charging will be made through the parasitic diode of external Nch FET on Dout pin. If both cell voltages become equal to or more than the over-discharge detection voltage by charging, the Dout pin returns to “H” after the over-discharge release delay time set by the internal counter. Over-current detection When excessive current flows through the battery, the V- pin voltage rises by the ON resister of external MOS FET and becomes equal to or more than the over-current detection voltage, the Dout pin turns to “L” after the over-current detection delay time and the external Nch MOS FET is turned off to prevent excessive current in the circuit. The detection delay time is set by the internal counter. After detection, the V- pin will be connected to VSS via internal resistor (typ. 30kΩ). It will not go into stand-by mode after detecting over-current. Short circuit detection If greater discharging current flows through the battery and the V- pin voltage becomes equal to or more than the short-circuit detection voltage, it will go into short-circuit detection state after the short circuit delay time shorter than the over-current detection delay time. When short-circuit is detected, just like the time of over-current detection, the Dout pin turns to “L” and external Nch MOS FET is turned off to prevent high current in the circuit. The V- pin will be connected to VSS after detection via internal resistor (typ. 30kΩ). It will not go into stand-by mode after detecting short circuit. Over-current/short-detection release After detecting over-current or short circuit, the internal resistor (typ. 30kΩ) between V- pin and VSS pin becomes effective. If the load resistor is removed, the V- pin voltage will be pulled down to the VSS level. Thereafter, the IC will be released from the over-current/short-circuit detection state when the V- pin voltage becomes equal to or less than the over-current detection voltage, and the Dout pin returns to “H” after over-current release delay time set by the internal counter. No.A1265-5/8 LV51135T Excessive charger detection/release If the voltage between V- pin and VSS pin becomes equal to or less than the excessive charger detection voltage by connecting a charger, no charging can be made by turning the Cout pin “L” after delay time and turning off the external Nch MOS FET. If that voltage returns to equal to or more than the excessive charger detection voltage during detection delay time, the excessive charger detection will be stopped. If the voltage between V- pin and VSS pin becomes equal to or more than the excessive charger detection voltage after excessive charger detection, the Cout returns to “H” after delay time. The detection/return delay time is set internally. If Dout pin is “L”, charging will be made through the parasitic diode of external Nch FET on Dout pin. In that case, the voltage between V- pin and VSS pin is nearly -Vf which is less than the excessive-charger detection voltage, therefore no excessive charger detection will be made during over-discharge, over-current and short-circuit detection. Furthermore, if excessive voltage charger is connected to the over-discharged battery, no excessive charger detection is made while the Dout pin is “L”. But the battery is continued charging through the parasitic diode. If the battery voltage rises to the over-discharge detection voltage and the voltage between V- pin and VSS pin remains equal to or less than the excessive charger detection voltage, the delay operation will be started after Dout pin turns to “H.” 0V cell charging operation If voltage between VDD and V becomes equal to or more than the 0V cell charging lowest operation voltage when the cell voltage is 0V, the Cout pin turns to “H” and charging is enabled. Shorten the test time By turning T pin to the VDD , the delay times set by the internal counter can be cut. If T pin is “open”, “L” the delay times are normal. Delay time not set by the counter just like as short circuit detection delay cannot be controlled by this pin. In some circuit-board layout, an excessive current at the load short might cause this IC be in miss operation like as in standby mode due to VSS line impedance. Therefore we recommend that the T pin is connected to the VSS pin. Operation in case of detection overlap Operation in case of detection overlap Overlap state State after detection During over-charge Over-discharge Over-charge detection is preferred. If over- When over-charge state is made first, V- is detection detection is made discharge state continues even after over- released. When over-discharge is detected after charge detection, over-discharge detection is over-charge state is made, the IC does not go into the stand-by mode. Note that V- is resumed. connected to VDD via 200kΩ. Over-current (*1) Both detections can be made in parallel. (*2) When over-current state is made first, V- is detection is made Over-charge detection continues even when the connected to VSS via 30kΩ. When over-charge state is made first, V- is released. over-current state is made first. If the overcharge state is made first, over-current detection is interrupted. During over-discharge Over-charge detection Over-discharge detection is interrupted and The IC does not go into the stand-by mode detection is made over-charge detection is preferred. When overdischarge state continues even after over- when over-discharge state is made after overcharge detection. Note that V- is connected to charge state is made, over-discharge detection VDD via 200kΩ. is resumed. Over-current (*3) Both detections can be made in parallel. (*4) If over-current state is made first, V- will be detection is made Over-discharge detection continues even when connected to VSS via 30kΩ. If over-discharge detection is made next, V- will be disconnected the over-current state is made first. But overcurrent detection is interrupted when the over- (*1) from VSS and connected to VDD via 200kΩ to get into stand-by mode. If over-discharge state is made first, V- will be connected to VDD via 200kΩ to get into standby state. (*2) (*3) (*4) discharge state is made first. During over-current detection Over-charge detection is made Over-discharge detection is made (Note) Short-circuit detection can be made independently. Excessive charger detection cannot be made during over-discharge, over-current and short-circuit detection. And its delay time starts after the Dout pin returns to “H”. No.A1265-6/8 LV51135T Timing Chart [Cout Output System] Charger connection Hysteresis cancellation by load connection Load connection Charger connection Load connection Over-charger connection Charger connection Load connection Vd1 Vr1 Charging recovery depends on charger voltage when connecting charger. VDD Vd2 VDD Discharging via FETparasite Di Vd4 V- Discharging via FETparasite Di Vd3 VSS Vd5 VDD td1 Cout tr1 td1 tr1 td5 tr5 VOver-charge detection state Over-charge detection state Over-charger detection state [Dout Output System] Load connection Charger connection Load connection Load connection Over-current occurrence Load connection Over-charger connection Load short-circuit occurrence Vd1 Vr1 VDD Vd2 To standby To standby VDD Vd4 V- Vd3 VSS Vd5 Charging via FETparasite Di VDD Dout td2 tr2 td3 tr3 td4 tr3 td2 tr2 VSS Over-discharge detection state Over-current detection state Short-circuit detection state VDD Cout V- Over-charger detection upon charging over-discharged battery is activated after return from over-charge. td5 No.A1265-7/8 LV51135T Application Circuit Example + R4 R1 C1 VDD Sense C3 T R2 Vc C2 VSS LV51135T V- VSS Dout Cout R3 − Components Recommended value max unit R1, R2 100 500 Ω R3 2k 4k Ω R4 100 1k Ω C1, C2, C3 0.1μ 1μ F * These numbers don't mean to guarantee the characteristic of the IC. * In addition to the components in the upper diagram, it is necessary to insert a capacitor with enough capacity between VDD and VSS of the IC as near as possible to stabilize the power supply voltage to the IC. * It is advisable to connect the T pin with the VSS pin. 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