5-Channel ESD Protection Array

PACDN009
5-Channel ESD Protection
Array
Product Description
The PACDN009 is a diode array designed to provide 5 channels of
ESD protection for electronic components or sub−systems. Each
channel consists of a pair of diodes which steers an ESD current pulse
to either the positive (VP) or negative (VN) supply. The PACDN009
protects against ESD pulses up to 15 kV Human Body Model
(100 pF capacitor discharging through a 1.5 kW resistor), and 8 kV
contact discharge, per International Standard IEC 61000−4−2.
This device is particularly well−suited for portable electronics
(e.g., cellular phones, PDAs, notebook computers) because of its
small package footprint, high ESD protection level, and low loading
capacitance. It is also suitable for protecting video output lines and I/O
ports in computers and peripherals and is ideal for a wide range of
consumer electronics products.
The PACDN009 is supplied in an 8−lead MSOP package and is
available with RoHS compliant lead−free finishing.
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MSOP 8
MR SUFFIX
CASE 846AB
ELECTRICAL SCHEMATIC
8
7
6
5
3
4
VP
Features
VN
 Five Channels of ESD Protection
 8 kV Contact, 15 kV Air ESD Protection per Channel





(IEC 61000−4−2 Standard)
15 kV of ESD Protection per Channel (HBM)
Low Loading Capacitance (3 pF Typical)
Low Leakage Current is Ideal for Battery−Powered Devices
Available in Miniature 8−Pin MSOP Package
These Devices are Pb−Free and are RoHS Compliant
N.C.
1
2
MARKING DIAGRAM
Applications







Consumer Electronic Products
Cellular Phones
PDAs
Notebook Computers
Desktop PCs
Digital Cameras and Camcorders
VGA (Video) Port Protection for Desktop and Portable PCs
009R
009R
= PACDN009MR
ORDERING INFORMATION
Device
Package
Shipping†
PACDN009MR
MSOP 8
(Pb−Free)
4000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 4
1
Publication Order Number:
PACDN009/D
PACDN009
TYPICAL APPLICATION CIRCUIT
3
7
PACDN009
1 4 5
0.22 mF*
6 8
Expansion
Connector
I/O Port
Buffers
Handheld/PDA ESD Protection
* Capacitor should be placed as close as possible to Pin7.
PACKAGE / PINOUT DIAGRAMS
Top View
1
2
3
CH2
4
009R
CH1
N.C.
VN
8
7
6
CH5
VP
CH4
5
CH3
PACDN009
8−Lead MSOP Package
Table 1. PIN DESCRIPTIONS
Pin
Name
Type
Description
1
CH1
I/O
2
N.C.
−
3
VN
GND
4
CH2
I/O
ESD Channel
5
CH3
I/O
ESD Channel
6
CH4
I/O
ESD Channel
7
VP
Supply
8
CH5
I/O
ESD Channel
No Connect
Negative Voltage Supply Rail or Ground Reference Rail
Positive Voltage Supply Rail
ESD Channel
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2
PACDN009
SPECIFICATIONS
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
Supply Voltage (VP − VN)
6.0
V
Diode Forward DC Current (Note 1)
20
mA
−40 to +85
C
Operating Temperature Range
Storage Temperature Range
DC Voltage at any Channel Input
−65 to +150
C
(VN − 0.5) to (VP + 0.5)
V
200
mW
Package Power Rating
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Only one diode conducting at a time.
Table 3. STANDARD OPERATING CONDITIONS
Parameter
Operating Temperature Range
Operating Supply Voltage (VP − VN)
Rating
Units
−40 to +85
C
0 to 5.5
V
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Conditions
IP
Supply Current
(VP − VN) = 5.5 V
VF
Diode Forward Voltage
IF = 20 mA
ILEAK
CIN
VESD
VCL
1.
2.
3.
4.
Parameter
Min
ESD Protection
Peak Discharge Voltage at any
Channel Input, in System
a) Human Body Model,
MIL−STD−883, Method 3015
b) Contact Discharge per
IEC 61000−4−2
c) Air Discharge per IEC 61000−4−2
Channel Clamp Voltage
Positive Transients
Negative Transients
Max
Units
10
mA
0.95
V
0.1
1.0
mA
3
5
pF
0.65
Channel Leakage Current
Channel Input Capacitance
Typ
@ 1 MHz, VP = 5 V,
VN = 0 V, VIN = 2.5 V
(Note 2)
kV
(Note 2)
(Note 3)
15
(Note 4)
8
(Note 4)
15
@ 15 kV ESD HBM
VP + 13.0
VN − 13.0
V
All parameters specified at TA = 25C unless otherwise noted. VP = 5 V, VN = 0 V unless noted.
From I/O pins to VP or VN only. VP bypassed to VN with a 0.22 mF ceramic capacitor (see Application Information for more details).
Human Body Model per MIL−STD−883, Method 3015, CDischarge = 100 pF, RDischarge = 1.5 kWVP = 5.0 V, VN grounded.
Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 5.0 V, VN grounded.
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3
PACDN009
PERFORMANCE INFORMATION
Input Capacitance vs. Input Voltage
Figure 1. Typical Variation of CIN vs. VIN
(VP = 5 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN)
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Figure 2, which illustrates an example of a positive ESD pulse striking
an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on
the line being protected is:
V CL + FwdVoltageDropofD 1 ) V SUPPLY ) L 1
d(I ESD)ńdt ) L 2
d(I ESD)ńdt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be
approximated by DIESD/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit
a much higher output impedance to fast transient current spikes. In the VCL equation above, the VSUPPLY term, in reality, is
given by (VDC + IESD x ROUT), where VDC and ROUT are the nominal supply DC output voltage and effective output impedance
of the power supply respectively. As an example, a ROUT of 1 W would result in a 10 V increment in VCL for a peak IESD of
10 A.
If the inductances and resistance described above are close to zero, the rail−clamp ESD protection diodes will do a good job
of protection. However, since this is not possible in practical situations, a bypass capacitor must be used to absorb the very high
frequency ESD energy. So for any brand of rail−clamp ESD protection diodes, a bypass capacitor should be connected between
the VP pin of the diodes and the ground plane (VN pin of the diodes) as shown in the Application Circuit diagram below. A value
of 0.22 mF is adequate for IEC−61000−4−2 level 4 contact discharge protection (8 kV). Ceramic chip capacitors mounted with
short printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have
poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate
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4
PACDN009
the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be
slightly higher than the maximum supply voltage.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Notes AP209, “Design Considerations for ESD Protection” and AP219, “ESD
Protection for USB 2.0 Systems”.
L2
POSITIVE SUPPLY RAIL
VP
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
PATH OF ESD CURRENT PULSE IESD
D1
D2
VN
ONE
CHANNEL
OF
PACDN009
LINE BEING
PROTECTED
L1
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
CHANNEL
INPUT
VCL
20 A
0A
GROUND RAIL
CHASSIS GROUND
Figure 2. Application of Positive ESD Pulse between Input Channel and Ground
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5
PACDN009
Figure 3. PCB Layout Recommendation
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6
PACDN009
PACKAGE DIMENSIONS
MSOP8
CASE 846AB−01
ISSUE O
D
HE
PIN 1 ID
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
E
e
b 8 PL
0.08 (0.003)
M
T B
S
A
DIM
A
A1
b
c
D
E
e
L
HE
S
SEATING
−T− PLANE
0.038 (0.0015)
A
A1
MILLIMETERS
NOM
MAX
−−
1.10
0.08
0.15
0.33
0.40
0.18
0.23
3.00
3.10
3.00
3.10
0.65 BSC
0.40
0.55
0.70
4.75
4.90
5.05
MIN
−−
0.05
0.25
0.13
2.90
2.90
INCHES
NOM
−−
0.003
0.013
0.007
0.118
0.118
0.026 BSC
0.016
0.021
0.187
0.193
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
0.028
0.199
L
c
SOLDERING FOOTPRINT*
8X
1.04
0.041
0.38
0.015
8X
3.20
0.126
6X
0.65
0.0256
4.24
0.167
5.28
0.208
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
PACDN009/D