TFF11145HN Low phase noise LO generator for VSAT applications Rev. 1 — 28 March 2013 Product data sheet 1. General description The TFF11145HN is a Ku band frequency generator intended for low phase noise Local Oscillator (LO) circuits for Ku band VSAT transmitters and transceivers. The specified phase noise complies with IESS-308 from Intelsat. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 2. Features and benefits Phase noise compliant with IESS-308 (Intelsat) in combination with appropriate source LO generator with VCO range from 14.50 GHz to 14.80 GHz Input signal 57 MHz to 925 MHz Divider settings 16, 32, 64, 128 or 256 Output level 6 dBm; stability 2 dB Third or fourth order PLL Internally stabilized voltage references for loop filter 3. Applications VSAT up converters Local oscillator signal generation 4. Quick reference data Table 1. Quick reference data Operating conditions of Table 10 apply. Symbol Parameter Min Typ Max Unit VCC supply voltage Conditions 3.0 3.3 V ICC supply current - 100 130 fo(RF) RF output frequency 14.50 - n(synth) synthesizer phase noise divider value = 64; at 100 kHz offset; reference phase noise is 149 dBc/Hz at 100 kHz offset - 97 92 dBc/Hz RLout output return loss measured at demo board and de-embedded to footprint - 10 - dB - - sup(sp)ref reference spurious suppression measured at divider value = 256 3.6 mA 14.80 GHz 70 dBc TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications 5. Ordering information Table 2. Ordering information Type number Package TFF11145HN Name Description Version HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 4 0.85 mm SOT616-1 6. Marking Table 3. Marking codes Type number Marking code TFF11145HN T145 7. Block diagram NSL0 NSL1 NSL2 4 5 6 VTUNE CPOUT 3 VREGVCO 2 1 10 pF 100 kΩ pull up LCKDET 7 100 kΩ pull up 100 kΩ pull up 30 pF VCC(DIV) (3.3 V) lock: 2.5 V no lock: 0 V WINDOW DETECTOR 2.7 V 24 GND3(BUF) 100 kΩ pull down GND1(REF) IN(REF)_P 8 23 VCC(BUF) VCO 9 PFD CP RBUF_N 50 Ω RBUF_P 50 Ω 22 VTUNE CPOUT BUF2_P BUF1_P DIVIDER IN(REF)_N GND2(REF) VCC(REF) 21 10 NSL0 NSL1 NSL2 20 11 12 19 13 VCC(DIV) Fig 1. 14 15 GND(DIV) n.c. 16 n.c. 17 BUF2_N BUF1_N GND2(BUF) 18 GND1(BUF) VCC(BUF) 001aal724 Block diagram TFF11145HN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 2 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications 8. Functional diagram NSL0 NSL1 NSL2 VTUNE 4 5 6 CPOUT 3 VREGVCO 2 10 pF 1 30 pF LCKDET GND1(REF) IN(REF)_P 7 lock: 2.5 V no lock: 0 V LOCK DETECTOR 2.7 V 24 23 8 VCO 9 PFD CP VTUNE CPOUT OUTPUT BUFFER 22 GND3(BUF) BUF2_P BUF1_P DIVIDER IN(REF)_N 10 21 NSL0 NSL1 NSL2 PLL GND2(REF) VCC(REF) 20 11 12 19 14 13 VCC(DIV) Fig 2. TFF11145HN Product data sheet GND(DIV) 15 n.c. 16 n.c. 17 BUF2_N BUF1_N GND2(BUF) 18 GND1(BUF) VCC(BUF) 001aal725 Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 3 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications 9. Pinning information 19 GND2(BUF) 20 BUF1_N 21 BUF2_N 22 BUF1_P terminal 1 index area 23 BUF2_P 24 GND3(BUF) 9.1 Pinning 14 GND(DIV) NSL2 6 13 VCC(DIV) VCC(REF) 12 5 GND2(REF) 11 15 n.c. NSL1 IN(REF)_N 10 16 n.c. 4 9 3 NSL0 IN(REF)_P VTUNE 8 18 VCC(BUF) 17 GND1(BUF) 7 2 LCKDET 1 CPOUT GND1(REF) VREGVCO 001aal726 Transparent top view Fig 3. Pin configuration for HVQFN24 9.2 Pin description Table 4. Symbol Pin description Pin Description VREGVCO 1 Regulated output voltage for VCO loop filter. Connect loop filter to this pin. CPOUT 2 Charge pump output. VTUNE 3 Tuning voltage for VCO. NSL0 4 Divider setting, LSB. Leave open for “1”, connect to GND for “0”. See Table 8. NSL1 5 Divider setting. Leave open for “1”, connect to GND for “0”. See Table 8. NSL2 6 Divider setting, MSB. Leave open for “1”, connect to GND for “0”. See Table 8. LCKDET 7 Lock detect. Lock = 2.5 V; out of lock = 0 V. See Table 6. GND1(REF) 8 Ground for REF input. Connect this pin to the exposed diepad landing. IN(REF)_P 9 Reference signal, non-inverting input. Couple this AC to the source. IN(REF)_N 10 Reference signal, inverting input. Couple this AC to the source. GND2(REF) 11 VCC(REF) 12 Supply of the internal regulated voltages. Decouple this pin against GND2(REF) (pin 11). VCC(DIV) 13 Supply of the divider and PFD/CP. Decouple this pin against GND(DIV) (pin 14). GND(DIV) 14 Ground of the divider. Connect this pin to the exposed diepad landing. n.c. 15 not connected n.c. 16 not connected GND1(BUF) 17 TFF11145HN Product data sheet Ground for REF input. Connect this pin to the exposed diepad landing. Ground for RF output. Connect this pin to the exposed diepad landing. All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 4 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications Table 4. Pin description …continued Symbol Pin Description VCC(BUF) 18 Supply voltage for the RF output buffer. Decouple this pin against GND2(BUF) (pin 19). GND2(BUF) 19 Ground for RF output. Connect this pin to the exposed diepad landing. BUF1_N 20 RF output. BUF2_N 21 RF output. BUF1_P 22 RF output. BUF2_P 23 RF output. GND3(BUF) 24 Ground for RF output. Connect this pin to the exposed diepad landing. 10. Functional description The TFF11145HN consists of the following blocks: • • • • • PLL Output buffer Lock detector Reference input Divider settings The functionality of the blocks will be discussed below. 10.1 PLL The PLL is formed by the VCO, DIVIDER (possible settings: 16, 32, 64, 128 and 256 (see Table 8)) and a PFD/CP. The tune voltage is referred to the band gap regulated voltage: VREGVCO (pin 1). The loop filter can be set to type 2 or type 3. If a type 2 filter is used, the pins CPOUT (pin 2) and VTUNE (pin 3) must be interconnected. A 10 pF capacitor is placed internally between pins CPOUT (pin 2) and VREGVCO (pin 1), and a 30 pF capacitor is placed between pins VTUNE (pin 3) and VREGVCO (pin 1). See Figure 4 and Figure 5. Values for the loop filter components are given in Table 5. The VCO input voltage range is between 0.1 and 0.9 VO(reg)VCO. TFF11145HN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 5 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications C2 C1 R1 C2 C1 R1 R2 C3 VTUNE 3 CPOUT 2 VREGVCO 1 VTUNE 3 CPOUT 2 10 pF VREGVCO 1 10 pF 30 pF 30 pF 2.7 V 2.7 V 001aal728 001aal727 Fig 4. Type 2 loop filter Table 5. Fig 5. Type 3 loop filter Component values used for characterization fi(ref) Divider value C1 (nF) (pF) (pF) () () 56.641 to 57.813 256 27 82 33 470 560 113.281 to 115.625 128 18 82 33 330 560 226.563 to 231.250 64 18 120 33 270 560 453.125 to 462.500 32 33 270 33 120 560 906.250 to 925.000 16 68 560 33 68 560 (MHz) C2 C3 R1 R2 10.2 Output buffer The output consists of a differential pair with 50 collector resistors RBUF_P and RBUF_N. If only one output is used, terminate the non used output with the same impedance as the load (see Figure 8) 10.3 Lock detector The lock detector is the output of a window detector. The window detector compares the output voltage over the charge pump. This voltage is identical to VTUNE when a type 2 loop filter is used (see Figure 4). In case of a type 3 loop filter this voltage is filtered by R2/C3 (see Figure 5). Due to this filtering the attack and decay time will decrease. The lower window detector threshold voltage is 7 % of the output voltage on VREGVCO (pin 1), the upper window detector threshold voltage is 93 % of the output voltage on VREGVCO (pin 1). The hysteresis is 0.1 V. The output is 2.5 V CMOS compliant. The values are shown in Table 6. The timing diagram is shown in Figure 6. At start-up the LCKDET (pin 7) will be LOW until the circuit has acquired lock. TFF11145HN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 6 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications Table 6. Logical value and physical value for lock detect (LCKDET) Logical value Physical value Lock detect state 0 0V out of lock 1 2.5 V lock LCKDET (pin 7) has a pull-down resistor of 100 k to GND1(REF) (pin 8). IN(REF)_P/N(t) t upper window detector threshold (93% of VO(reg)VCO) hysteresis voltage (0.1 V) VTUNE(t) low window detector threshold (7% of VO(reg)VCO) hysteresis voltage (0.1 V) t IN LOCK 2.2 V LCKDET(t) 0.4 V OUT OF LOCK (0 V) t timeline section 1 2 3 4 attack time(1) value determined by closed loop opertation PLL VTUNE actual PLL status PLL is in lock LCKDET > 2.2 V remarks Drift to maximum voltage = lowest frequency of VCO undetermined behavior around maximum voltage 6 decay time(1) undetermined behavior around maximum voltage PLL is out of lock PLL is out of lock PLL is out of lock LCKDET remains > 2.2 V because loop filter is still charged 5 voltage is forced by loop to closed loop value of PLL value is determined by closed loop operation PLL PLL is in lock PLL is in lock window detector LCKDET < 0.4 V window detector detects that detects that VTUNE < upper VTUNE > upper window detector window detector threshold − 0.1 V. threshold. LCKDET changes LCKDET changes from < 0.4 V to from > 2.2 V to > 2.2 V during the < 0.4 V during the decay time attack time LCKDET > 2.2 V 001aal986 (1) The attack time and decay time are typically 10 s and are mainly depending on the drift of the VCO tuning voltage. Fig 6. Timing diagram lock detector 10.4 Reference input (IN(REF)_P, IN(REF)_N) The reference input is a differential pair and is internally biased. The input is high ohmic. The input signal must be AC coupled. If used in a single ended mode, the not used input must be terminated with the same impedance as the driving source. An example of the differential source and two single ended loads are shown in Figure 7. An example of a single ended application is shown in Figure 8. TFF11145HN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 7 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications Note that the phase noise of the output signal is also determined by the phase noise of the reference signal. The reference frequency range is equal to the output frequency / division value. Note that the output frequency is guaranteed from 8.20 GHz to 8.60 GHz. 10.5 Divider settings (NSL2, NSL1, NSL0) The divider can be set to 16, 32, 64, 128 and 256 (See Table 8). The logic levels for NSL0 (pin 4), NSL1 (pin 5) and NSL2 (pin 6) are given in Table 7. The pins have a pull-up resistor of 100 k to VCC(DIV) (pin 13). The device is only guaranteed when NSL2, NSL1 and NSL0 are predefined at start-up (no change of divider value is allowed during operation). Table 7. Logical and physical value for divider setting (NSL2, NSL1, NSL0) Logical value Physical value 0 GND 1 open or VCC The truth table is shown in Table 8. Table 8. Divider setting as function of NSL2, NSL1 and NSL0 Setting number NSL2 NSL1 NSL0 Divider value 0 0 0 0 16 1 0 0 1 32 2 0 1 0 64 3 0 1 1 128 4 1 0 0 256 5 1 0 1 [1] 6 1 1 0 [1] 7 1 1 1 [1] [1] Test mode, divider output will be disabled. 11. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VI TFF11145HN Product data sheet input voltage Conditions Min on pin NSL0 0.5 +5 V on pin NSL1 0.5 +5 V on pin NSL2 0.5 +5 V on pin IN(REF)_P 0.5 +5 V on pin IN(REF)_N 0.5 +5 V on pin VCC(REF) 0.5 +5 V on pin VCC(DIV) 0.5 +5 V on pin VCC(BUF) 0.5 +5 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 Max Unit © NXP B.V. 2013. All rights reserved. 8 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications Table 9. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Pi on pin IN(REF)_P 4 +10 dBm on pin IN(REF)_N 4 +10 dBm input power Tj junction temperature 40 +125 C Tstg storage temperature 40 +125 C VESD electrostatic discharge voltage Human Body Model (HBM); According JEDEC standard 22-A114E - 2.5 kV Charged Device Model (CDM); According to JEDEC standard 22-C101B - 1 kV 12. Recommended operating conditions Table 10. Operating conditions NSL0 (pin 4), NSL1 (pin 5) and NSL2 (pin 6) not changed during operation. Loop filter component values as depicted in Table 5 are used. Symbol Parameter Conditions Tamb ambient temperature Z0 characteristic impedance n(ref) reference phase noise Min Typ Max Unit 40 +25 +85 C - 50 - divider value = 16 [1] - - 134 dBc/Hz divider value = 32 [1] - - 143 dBc/Hz divider value = 64 [1] - - 149 dBc/Hz divider value = 128 [1] - - 150 dBc/Hz divider value = 256 [1] - - 151 dBc/Hz - 925 MHz 0 dBm fi(ref) reference input frequency fi(ref) = fo(RF) / divider value 57 Pi(ref) reference input power 10 - [1] Required reference phase noise is set 10 dB below equivalent input phase noise. 13. Thermal characteristics TFF11145HN Product data sheet Table 11. Thermal characteristics Symbol Parameter Rth(j-sp) thermal resistance from junction to solder point Conditions All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 Typ Unit 25 K/W © NXP B.V. 2013. All rights reserved. 9 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications 14. Characteristics Table 12. Characteristics Operating conditions of Table 10 apply. Symbol Parameter VCC ICC Conditions Min Typ Max Unit supply voltage 3.0 3.3 3.6 V supply current - 100 130 mA fo(RF) RF output frequency 14.50 - 14.80 GHz VO(reg)VCO VCO regulator output voltage 2.5 2.7 2.9 V Icp charge pump current - 1 - mA KO VCO steepness - 0.73 - GHz/V n(VCO) VCO phase noise at 10 MHz offset - 130 - dBc/Hz n(synth) synthesizer phase noise divider value = 64; at 100 kHz offset; reference phase noise is 149 dBc/Hz at 100 kHz offset - 97 92 dBc/Hz 8 - 4 dBm PLL [1] Output buffer [2] Po output power measured single ended RLout output return loss measured at demo board and de-embedded to footprint - 10 - dB sup(sp)ref reference spurious suppression measured at divider value = 256 - - 70 dBc H(LO) LO harmonic rejection - 10 - dBc Lock detector VOL LOW-level output voltage IO = 1 mA - - 0.4 V VOH HIGH-level output voltage IO = 1 mA 2.2 - - V Rpd pull-down resistance 70 100 130 k Divider setting (NSL0, NSL1, NSL2) Rpu pull-up resistance 70 100 130 k VIL LOW-level input voltage - - 0.8 V VIH HIGH-level input voltage 2.0 - - V [1] The typical ratio of the maximum KO in relation to the minimum KO is 1.25. [2] Output stage is a differential pair with 50 collector impedances. Output power is measured per output pin for the fundamental tone only. Output is DC coupled and is AC coupled in on-board. TFF11145HN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 10 of 17 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x R1 1 nF GND = 0 open or 3.3 V = 1 NSL2 6 NSL1 5 R2 C3 NSL0 4 VTUNE 3 CPOUT 2 VREGVCO 1 10 pF 100 kΩ pull up LCKDET 7 100 kΩ pull up 30 pF VCC(DIV) (3.3 V) lock: 2.5 V no lock: 0 V WINDOW DETECTOR 2.7 V 24 GND3(BUF) 100 kΩ pull down GND1(REF) 8 23 BUF2_P VCC(BUF) 1 pF 10 nF 50 Ω VCO IN(REF)_P 9 Z0(dif) = 100 Ω PFD CP CPOUT RBUF_N 50 Ω Z0 = 50 Ω RBUF_P 50 Ω 22 BUF1_P VTUNE 50 Ω DC block 50 Ω LOAD 100 Ω DC block 50 Ω 10 nF DIVIDER IN(REF)_N 10 21 BUF2_N NSL0 NSL1 NSL2 REFERENCE SOURCE 1 pF GND2(REF) 11 20 BUF1_N Z0 = 50 Ω 50 Ω 50 Ω LOAD 3.3 V VCC(REF) 12 19 14 15 16 17 GND(DIV) n.c. n.c. GND1(BUF) VCC(BUF) 18 11 of 17 © NXP B.V. 2013. All rights reserved. 001aal730 Fig 7. Application diagram with differential source for IN(REF) and both outputs driving a load, loop filter is type 3 TFF11145HN 13 VCC(DIV) GND2(BUF) Low phase noise LO generator for VSAT applications Rev. 1 — 28 March 2013 All information provided in this document is subject to legal disclaimers. OUT-OF-LOCK PROCESSING BLOCK 100 kΩ pull up NXP Semiconductors 15. Application information TFF11145HN Product data sheet C2 C1 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TFF11145HN Product data sheet C2 C1 R1 1 nF GND = 0 open or 3.3 V = 1 NSL2 6 NSL1 5 R2 C3 NSL0 4 VTUNE 3 CPOUT 2 VREGVCO 1 10 pF 100 kΩ pull up LCKDET 7 100 kΩ pull up 30 pF VCC(DIV) (3.3 V) lock: 2.5 V no lock: 0 V WINDOW DETECTOR 2.7 V 24 GND3(BUF) 100 kΩ pull down GND1(REF) 8 23 BUF2_P VCC(BUF) 1 pF 50 Ω Z0 = 50 Ω 10 nF VCO IN(REF)_P 9 PFD CP CPOUT RBUF_N 50 Ω Z0 = 50 Ω RBUF_P 50 Ω 22 BUF1_P VTUNE 50 Ω DC block 51 Ω 10 nF REFERENCE SOURCE not used input terminated with same impedance DIVIDER IN(REF)_N 10 21 BUF2_N NSL0 NSL1 NSL2 24 Ω 1 pF GND2(REF) 11 3.3 V 50 Ω LOAD DC block 20 BUF1_N VCC(REF) 12 19 14 15 16 17 GND(DIV) n.c. n.c. GND1(BUF) VCC(BUF) not used output terminated with same impedance GND2(BUF) 18 12 of 17 © NXP B.V. 2013. All rights reserved. 001aal731 Fig 8. Application diagram with single ended source for IN(REF) and single ended load, loop filter is type 3 TFF11145HN 13 VCC(DIV) 51 Ω Low phase noise LO generator for VSAT applications Rev. 1 — 28 March 2013 All information provided in this document is subject to legal disclaimers. OUT-OF-LOCK PROCESSING BLOCK 100 kΩ pull up TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications 16. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm A B D SOT616-1 terminal 1 index area A A1 E c detail X e1 C 1/2 e e 7 12 y y1 C v M C A B w M C b L 13 6 e e2 Eh 1/2 1 e 18 terminal 1 index area 24 19 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.1 3.9 2.25 1.95 4.1 3.9 2.25 1.95 0.5 2.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT616-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Package outline SOT616-1 (HVQFN24) TFF11145HN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 13 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications 17. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor CP Charge Pump Ku band K-under band LSB Least Significant Bit MSB Most Significant Bit PFD Phase Frequency Detector PLL Phase-Locked Loop VCO Voltage Controlled Oscillator VSAT Very Small Aperture Terminal 18. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes TFF11145HN v.1 20130328 Product data sheet - - TFF11145HN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 14 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. TFF11145HN Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 15 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TFF11145HN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 March 2013 © NXP B.V. 2013. All rights reserved. 16 of 17 TFF11145HN NXP Semiconductors Low phase noise LO generator for VSAT applications 21. Contents 1 2 3 4 5 6 7 8 9 9.1 9.2 10 10.1 10.2 10.3 10.4 10.5 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Output buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Lock detector . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reference input (IN(REF)_P, IN(REF)_N) . . . . 7 Divider settings (NSL2, NSL1, NSL0). . . . . . . . 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 9 Thermal characteristics . . . . . . . . . . . . . . . . . . 9 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application information. . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 28 March 2013 Document identifier: TFF11145HN