ON Semiconductor Confidential Design Note – DN06072/D 9-18V Input, 10A DC-DC PWM Buck Controller + FET Device NCP3020 Application Input Voltage Output Voltage Output Current Topology Test Equipment 9-18V 3.3V 0.01-10A Buck Table 1: Buck Power Supply Characteristic Input Voltage Output Voltage Output Current Oscillator Frequency Output Voltage Ripple Load Regulation Iout = 0.02-10A) Vin= 9V NCP3020 Iout = 0.02-10A) Vin= 18V NCP3020 Min 9 3.25 .01 270 Typ 12 3.265 1 300 86 Max 18 3.28 10 330 0.99 0.78 Unit V V A kHz mVpk-pk mV/A Key Features Circuit Description This circuit is proposed for a wide varying +12V input (9V-18V) where there is a need to step-down the voltage to +3.3V @ 10A. The requirement specified a large electrolytic input capacitance and also to utilize electrolytic capacitors on the output. Target efficiency is >85%. The PCB for the NCP3020 is a 2-layer board for use in applications up to 50W. The synchronous buck converter uses voltage mode control, which can be compensated externally with a transconductance amplifier. The soft start time is fixed. The NCP3020 demonstration board is a flexible design allowing the use of electrolytic capacitors or ceramic capacitors. It also allows the use of SO8-FL or D-PAK MOSFETs. High Efficiency Adjustable Current Limit Output Overvoltage and Output Undervoltage protection Short Circuit Protection Fixed Switching Frequency Rev 0, January 2011 ON Semiconductor Confidential Performance The following figures show typical performance of the NCP3020 demonstration boards. Efficiency (%) Efficiency Vs I-Out 95 90 85 80 75 70 65 60 9 V-In 12 V-In 15 V-In 18 V-In 0 2 4 6 8 10 I-Out (A) Figure 1: NCP3020 Efficiency at 9V-18.0V with a 3.3V Output Voltage V-Out (V) Load Regulation 3.3 3.29 3.28 3.27 3.26 3.25 3.24 3.23 3.22 9 V-In 12 V-In 15 V-In 18 V-In MIN MAX 0 2 4 6 8 I-Out (A) Figure 2: NCP3020 Load Regulation Rev 0, January 2011 10 ON Semiconductor Confidential 0A Line Regulation 1A 3.3 2A 3.29 3A V-Out (V) 3.28 4A 3.27 5A 3.26 6A 3.25 7A 3.24 8A 3.23 9A 3.22 10A 9 10 11 12 13 14 15 16 V-In (V) Figure 3: NCP3020 Line Regulation Rev 0, January 2011 17 18 MAX MIN ON Semiconductor Confidential Schematics Figure 4: NCP3020 Schematic Rev 0 - January, 2011 ON Semiconductor Confidential Table 2: NCP3020 BOM © 2011 ON Semiconductor. Disclaimer: ON Semiconductor is providing this design note “AS IS” and does not assume any liability arising from its use; nor does ON Semiconductor convey any license to its or any third party’s intellectual property rights. This document is provided only to assist customers in evaluation of the referenced circuit implementation and the recipient assumes all liability and risk associated with its use, including, but not limited to, compliance with all regulatory standards. ON Semiconductor may change any of its products at any time, without notice. Design note created by Tim Kaske and Jim Hill, e-mail: [email protected] ; [email protected] Rev 0 - January, 2011