MC26LS30 Dual Differential (EIA−422−A)/ Quad Single−Ended (EIA−423−A) Line Drivers The MC26LS30 is a low power Schottky set of line drivers which can be configured as two differential drivers which comply with EIA−422−A standards, or as four single−ended drivers which comply with EIA−423−A standards. A mode select pin and appropriate choice of power supplies determine the mode. Each driver can source and sink currents in excess of 50 mA. In the differential mode (EIA−422−A), the drivers can be used up to 10 Mbaud. A disable pin for each driver permits setting the outputs into a high impedance mode within a +10 V common mode range. In the single−ended mode (EIA−423−A), each driver has a slew rate control pin which permits setting the slew rate of the output signal so as to comply with EIA−423−A and FCC requirements and to reduce crosstalk. When operated from symmetrical supplies (+5.0 V), the outputs exhibit zero imbalance The MC26LS30 is available in a 16−pin surface mount package. Operating temperature range is −40°C to +85°C. http://onsemi.com MARKING DIAGRAM 16 SO−16 D SUFFIX CASE 751B 16 1 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week PIN CONNECTIONS • Operates as Two Differential EIA−422−A Drivers, or Four • • • • • • • • Single−Ended EIA−423−A Drivers High Impedance Outputs in Differential Mode Short Circuit Current Limit In Both Source and Sink Modes ±10 V Common Mode Range on High Impedance Outputs ±15 V Range on Inputs Low Current PNP Inputs Compatible with TTL, CMOS, and MOS Outputs Individual Output Slew Rate Control in Single−Ended Mode Replacement for the AMD AM26LS30 and National Semiconductor DS3691 Pb−Free Packages are Available Representative Block Diagrams Single−Ended Mode EIA−423−A SR−A Input A Input B Out C SR−D Input D Out D Gnd Input C/ Enable CD Input D VEE 12 SR−C 11 Output C Out C Input D Out D 5 6 10 Output D 9 SR−D 7 8 ORDERING INFORMATION Package Shipping† SO−16 48 Units/Rail MC26LS30DG SO−16 (Pb−Free) 48 Units/Rail MC26LS30DR2 SO−16 2500 Tape & Reel SO−16 (Pb−Free) 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Enable CD VCC−1 VEE−8 13 SR−B (Top View) MC26LS30DR2G Semiconductor Components Industries, LLC, 2005 March, 2005 − Rev. 2 15 Output A 14 Output B Out B Out B SR−C Input C Out A Input A 16 SR−A Input A 2 Input B/ 3 Enable AB Mode 4 MC26LS30D Enable AB Out A SR−B VCC 1 Device Differential Mode EIA−422−A MC26LS30D AWLYWW Gnd−5 Mode−4 1 Publication Order Number: MC26LS30/D MC26LS30 MAXIMUM OPERATING CONDITIONS (Pin numbers refer to SO−16 package only.) Rating Symbol Value Unit Power Supply Voltage VCC VEE −0.5, +7.0 −7.0, +0.5 Vdc Input Voltage (All Inputs) Vin −0.5, +20 Vdc Applied Output Voltage when in High Impedance Mode (VCC = 5.0 V, Pin 4 = Logic 0, Pins 3, 6 = Logic 1) Vza ±15 Vdc Output Voltage with VCC, VEE = 0 V Vzb ±15 Output Current IO Self limiting − Junction Temperature TJ −65, +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Devices should not be operated at these limits. The “Recommended Operating Conditions” table provides conditions for actual device operation. RECOMMENDED OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Power Supply Voltage (Differential Mode) VCC VEE +4.75 −0.5 5.0 0 +5.25 +0.3 Vdc Power Supply Voltage (Single−Ended Mode) VCC VEE +4.75 −5.25 +5.0 −5.0 +5.25 −4.75 Input Voltage (All Inputs) Vin 0 − +15 Applied Output Voltage (when in High Impedance Mode) Vza −10 − +10 Applied Output Voltage, VCC = 0 Vzb −10 − +10 Output Current IO −65 − +65 mA Operating Ambient Temperature (See text) TA −40 − +85 °C All limits are not necessarily functional concurrently. http://onsemi.com 2 Vdc MC26LS30 ELECTRICAL CHARACTERISTICS (EIA−422−A differential mode, Pin 4 0.8 V, −40°C TA 85°C, 4.75 V VCC 5.25 V, VEE = Gnd, unless otherwise noted. Pin numbers refer to SO−16 package only.) Characteristic Output Voltage (see Figure 1) Differential, RL = ∞, VCC = 5.25 V Differential, RL = 100 Ω, VCC = 4.75 V Change in Differential Voltage, RL = 100 Ω (Note 4) Offset Voltage, RL = 100 Ω Change in Offset Voltage*, RL = 100 Ω Symbol Min Typ Max Unit VOD1 VOD2 ∆VOD2 VOS ∆VOS − 2.0 − − − 4.2 2.6 10 2.5 10 6.0 − 400 3.0 400 Vdc Vdc mVdc Vdc mVdc IOLK IOZ −100 −100 0 0 +100 +100 µA ISC− ISC− ISC+ ISC+ −150 −150 60 50 −95 − 75 − −60 −50 150 150 mA VIL VIH IIH IIHH IIL IIX VIK − 2.0 − − −200 − −1.5 − − 0 0 −8.0 0 − 0.8 − 40 100 − − − Vdc Vdc µA − 16 30 Output Current (each output) Power Off Leakage, VCC = 0, −10 V VO +10 V High Impedance Mode, VCC = 5.25 V, −10 V VO +10 V Short Circuit Current (Note 2) High Output Shorted to Pin 5 (TA = 25°C) High Output Shorted to Pin 5 (−40°C TA +85°C) Low Output Shorted to +6.0 V (TA = 25°C) Low Output Shorted to +6.0 V (−40°C TA +85°C) Inputs Low Level Voltage High Level Voltage Current @ Vin = 2.4 V Current @ Vin = 15 V Current @ Vin = 0.4 V Current, 0 Vin 15 V, VCC = 0 Clamp Voltage (Iin = −12 mA) Power Supply Current (VCC = +5.25 V, Outputs Open) (0 Enable VCC) ICC Vdc mA TIMING CHARACTERISTICS (EIA−422−A differential mode, Pin 4 0.8 V, TA = 25°C, VCC = 5.0 V, VEE = Gnd, (Notes 1 and 3) unless otherwise noted.) Characteristic 1. 2. 3. 4. 5. Symbol Min Typ Max Unit Differential Output Rise Time (Figure 3) tr − 70 200 ns Differential Output Fall Time (Figure 3) ns tf − 70 200 Propagation Delay Time − Input to Differential Output Input Low to High (Figure 3) Input High to Low (Figure 3) tPDH tPDL − − 90 90 200 200 Skew Timing (Figure 3) tPDH to tPDL for Each Driver Max to Min tPDH Within a Package Max to Min tPDL Within a Package tSK1 tSK2 tSK3 − − − 9.0 2.0 2.0 − − − Enable Timing (Figure 4) Enable to Active High Differential Output Enable to Active Low Differential Output Enable to 3−State Output From Active High Enable to 3−State Output From Active Low tPZH tPZL tPHZ tPLZ − − − − 150 190 80 110 300 350 350 300 ns ns ns All voltages measured with respect to Pin 5. Only one output shorted at a time, for not more than 1 second. Typical values established at +25°C, VCC = +5.0 V, VEE = −5.0 V. Vin switched from 0.8 to 2.0 V. Imbalance is the difference between VO2 with Vin 0.8 V and VO2 with Vin 2.0 V. http://onsemi.com 3 MC26LS30 ELECTRICAL CHARACTERISTICS (EIA−423−A single−ended mode, Pin 4 2.0 V, −40°C TA 85°C, 4.75 V VCC , |VEE 5.25 V, (Notes 1 and 3) unless otherwise noted). Characteristic Symbol Min Typ Max Unit Output Voltage (VCC = VEE = 4.75 V) Single−Ended Voltage, RL = ∞ (Figure 2) Single−Ended Voltage, RL = 450 Ω, (Figure 2) Voltage Imbalance (Note 5), RL = 450 Ω VO1 VO2 ∆VO2 4.0 3.6 − 4.2 3.95 0.05 6.0 6.0 0.4 Slew Control Current (Pins 16, 13, 12, 9) ISLEW − ±120 − µA IOLK −100 0 +100 µA ISC+ ISC+ ISC− ISC− 60 50 −150 −150 80 − −95 − 150 150 −60 −50 mA Inputs Low Level Voltage High Level Voltage Current @ Vin = 2.4 V Current @ Vin = 15 V Current @ Vin = 0.4 V Current, 0 Vin 15 V, VCC = 0 Clamp Voltage (Iin = −12 mA) VIL VIH IIH IIHH IIL IIX VIK − 2.0 − − −200 − −1.5 − − 0 0 −8.0 0 − 0.8 − 40 100 − − − Vdc Vdc µA Power Supply Current (Outputs Open) VCC = +5.25 V, VEE = −5.25 V, Vin = 0.4 V ICC IEE − −22 17 −8.0 30 − Vdc Output Current (Each Output) Power Off Leakage, VCC = VEE = 0, −6.0 V VO +6.0 V Short Circuit Current (Output Short to Ground, Note 2) Vin 0.8 V (TA = 25°C) Vin 0.8 V (−40°C TA +85°C) Vin 2.0 V (TA = 25°C) Vin 2.0 V (−40°C TA +85°C) Vdc mA TIMING CHARACTERISTICS (EIA−423−A single−ended mode, Pin 4 2.0 V, TA = 25°C, VCC = 5.0 V, VEE = −5.0 V, (Notes 1 and 3) unless otherwise noted.) Characteristic 1. 2. 3. 4. 5. Symbol Min Typ Max Unit Output Timing (Figure 5) Output Rise Time, CC = 0 Output Fall Time, CC = 0 Output Rise Time, CC = 50 pF Output Fall Time, CC = 50 pF tr tf tr tf − − − − 65 65 3.0 3.0 300 300 − − ns Rise Time Coefficient (Figure 16) Crt − 0.06 − Propagation Delay Time, Input to Single Ended Output (Figure 5) Input Low to High, CC = 0 Input High to Low, CC = 0 tPDH tPDL − − 100 100 300 300 Skew Timing, CC = 0 (Figure 5) tPDH to tPDL for Each Driver Max to Min tPDH Within a Package Max to Min tPDL Within a Package tSK4 tSK5 tSK6 − − − 15 2.0 5.0 − − − µs µs/pF ns ns All voltages measured with respect to Pin 5. Only one output shorted at a time, for not more than 1 second. Typical values established at +25°C, VCC = +5.0 V, VEE = −5.0 V. Vin switched from 0.8 to 2.0 V. Imbalance is the difference between VO2 with Vin 0.8 V and VO2 with Vin 2.0 V. http://onsemi.com 4 MC26LS30 Table 1 Inputs Outputs Operation VCC VEE Mode A B C D A B C D Differential (EIA−422−A) (EIA 422 A) +5.0 Gnd 0 0 0 0 0 0 0 1 X 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 1 X 0 1 Z 1 0 1 1 0 Z 0 1 0 1 0 0 1 0 Z 0 1 1 0 1 Z S ge Single−Ended ded (EIA−423−A) (EIA 423 A) +5.0 50 −5.0 50 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 X X X X X X Z Z Z Z X X = Don’t Care Z = High Impedance (Off) VCC VCC RL/2 Vin (0.8 or 2.0 V) Vin (0.8 or 2.0 V) VOD2 RL RL/2 VOS Mode = 1 Mode = 0 Figure 1. Differential Output Test S.G. 500 pF +3.0 V 1.5 V 1.5 V Vin 100 VO Figure 2. Single−Ended Output Test VCC Vin CL VEE 0V tPDH VOD tPDL 90% 50% 10% 90% 50% Vout 10% tr NOTES: 1. S.G. set to: f 1.0 MHz; duty cycle = 50%; tr, tf, 10 ns. 2. tSK1 = tPDH−tPDL for each driver. 3. tSK2 computed by subtracting the shortest tPDH from the longest tPDH of the 2 drivers within a package. 4. tSK3 computed by subtracting the shortest tPDL from the longest tPDL of the 2 drivers within a package. Figure 3. Differential Mode Rise/Fall Time and Data Propagation Delay http://onsemi.com 5 tf MC26LS30 +3.0 V VCC Vin 0 or 3.0 V 500 pF VSS 0V tPHZ 450 Ω En Vin RL 1.5 V 1.5 V 0.1 VSS/RL (Vin = Hi) tPZH VSS/RL 0.5 VSS/RL Output Current S.G. tPLZ (Vin = Lo) 0.1 VSS/RL VSS/RL 0.5 VSS/RL tPZL NOTES: 1. S.G. set to: f 1.0 MHz; duty cycle = 50%; tr, tf, 10 ns. 2. Above tests conducted by monitoring output current levels. Figure 4. Differential Mode Enable Timing +2.5 V VCC 450 VEE S.G. 1.5 V Vin CC Vin 1.5 V 0V tPDH 500 pF VO Vout 90% 50% 10% tr NOTES: 1. S.G. set to: f 100 kHz; duty cycle = 50%; tr, tf, 10 ns. 2. tSK4 = tPDH−tPDL for each driver. 3. tSK5 computed by subtracting the shortest tPDH from the longest tPDH of the 4 drivers within a package. 4. tSK6 computed by subtracting the shortest tPDL from the longest tPDL of the 4 drivers within a package. Figure 5. Single−Ended Mode Rise/Fall Time and Data Propagation Delay http://onsemi.com 6 tPDL 90% 50% 10% tf MC26LS30 40 4.0 I B , BIAS CURRENT (mA) VOD , OUTPUT VOLTAGE (V) 5.0 3.0 Differential Mode Mode = 0, VCC = 5.0 V 2.0 0.8 or 2.0 V 1.0 0 0 10 Differential Mode Mode = 0 Supply Current = Bias Current + Load Current 30 20 VCC = 5.25 V IO V OD 20 30 40 IO, OUTPUT CURRENT (mA) 50 10 60 20 0 Figure 6. Differential Output Voltage versus Load Current 100 120 Figure 7. Internal Bias Current versus Load Current +100 +5.0 VCC = 0 +60 Iin INPUT CURRENT A) I SC, SHORT CIRCUIT CURRENT (mA) 40 60 80 TOTAL LOAD CURRENT (mA) Normally Low Output +20 −20 Normally High Output Differential Mode Mode = 0, VCC = 5.0 V −60 −100 0 1.0 2.0 3.0 4.0 Vza, APPLIED OUTPUT VOLTAGE (V) 5.0 0 −5.0 VCC = 5.0 V −10 Pins 2 to 4, 6, 7 −5.0 V VEE 0 Differential or Single−Ended Mode −15 −20 −25 −1.0 6.0 1.0 3.0 5.0 7.0 9.0 11 13 15 Vin, INPUT VOLTAGE (V) (Pin numbers refer to SO−16 package only.) Figure 8. Short Circuit Current versus Output Voltage Figure 9. Input Current versus Input Voltage −3.25 VOL, OUTPUT VOLTAGE (V) VOH , OUTPUT VOLTAGE (V) 4.5 4.0 Single−Ended Mode Mode = 1 VCC = 5.0 V, VEE = −5.0 V Vin = 1 3.5 3.0 0 −10 −20 −30 −40 IOH, OUTPUT CURRENT (mA) −50 −3.75 −4.75 −60 Single−Ended Mode Mode = 1 VCC = 5.0 V, VEE = −5.0 V Vin = 0 −4.25 0 Figure 10. Output Voltage versus Output Source Current 10 20 30 40 IOL, OUTPUT CURRENT (mA) 50 Figure 11. Output Voltage versus Output Sink Current http://onsemi.com 7 60 MC26LS30 22 0 Single Ended Mode Mode = 1 VCC = 5.0 V, VEE = −5.0 V Supply Current = Bias Current + IOH I B− , BIAS CURRENT (mA) I B+ , BIAS CURRENT (mA) 26 18 14 −5.0 −10 Vin = LoVin = Hi −15 Vin = LoVin = Hi 10 240 160 80 0 −80 −160 −20 240 −240 Single−Ended Mode Mode = 1 VCC = 5.0 V, VEE = −5.0 V Supply Current = Bias Current + IOL 160 IOL IOH TOTAL LOAD CURRENT (mA) Figure 12. Internal Positive Bias Current versus Load Current 110 I SC + (mA) Normally Low Output 20 Normally Low Output 90 70 Single or Differential Mode VCC = 5.0 V, VEE = −5.0 V or Gnd −20 50 Normally High Output −4.0 I SC − (mA) Single−Ended Mode Mode = 1 VCC = 5.0 V, VEE = −5.0 V −2.0 2.0 0 Vza, APPLIED OUTPUT VOLTAGE (V) 4.0 6.0 −90 Normally High Output to Ground −100 −110 −40 Figure 14. Short Circuit Current versus Output Voltage −20 0 20 40 60 TA, AMBIENT TEMPERATURE (°C) Figure 15. Short Circuit Current versus Temperature 1.0 k t r , t f , RISE/FALL TIME ( µ s) I SC , SHORT CIRCUIT CURRENT (mA) 60 −100 −6.0 −240 Figure 13. Internal Negative Bias Current versus Load Current 100 −60 80 0 −80 −160 IOL IOH TOTAL LOAD CURRENT (mA) Single−Ended Mode Mode = 1 VCC = 5.0 V, VEE = −5.0 V 100 10 1.0 10 1.0 k 100 CC, CAPACITANCE (pF) Figure 16. Rise/Fall Time versus Capacitance http://onsemi.com 8 10 k 85 MC26LS30 APPLICATIONS INFORMATION (Pin numbers refer to SO−16 package only.) Description of Figure 10 will vary directly with VCC, and the graph of Figure 11 will vary directly with VEE. A “high” output can only source current, while a “low” output can only sink current (except short circuit current − see Figure 14). The outputs will be in a high impedance mode only if VCC 1.1 V. Changing VEE to 0 V does not set the outputs to a high impedance mode. Leakage current over a common mode range of ±10 V is typically less than 1.0 µA. The outputs have short circuit current limiting, typically less than 100 mA over a voltage range of ±6.0 V (see Figure 14). Short circuits should not be allowed to last indefinitely as the IC may be damaged. Capacitors connected between Pins 9, 12, 13, and 16 and their respective outputs will provide slew rate limiting of the output transition. Figure 16 indicates the required capacitor value to obtain a desired rise or fall time (measured between the 10% and 90% points). The positive and negative transition times will be within ≈ ±5% of each other. Each output may be set to a different slew rate if desired. The MC26LS30 is a dual function line driver − it can be configured as two differential output drivers which comply with EIA−422−A Standard, or as four single−ended drivers which comply with EIA−423−A Standard. The mode of operation is selected with the Mode pin (Pin 4) and appropriate power supplies (see Table 1). Each of the four outputs is capable of sourcing and sinking 60 to 70 mA while providing sufficient voltage to ensure proper data transmission. As differential drivers, data rates to 10 Mbaud can be transmitted over a twisted pair for a distance determined by the cable characteristics. EIA−422−A Standard provides guidelines for cable length versus data rate. The advantage of a differential (balanced) system over a single−ended system is greater noise immunity, common mode rejection, and higher data rates. Where extraneous noise sources are not a problem, the MC26LS30 may be configured as four single−ended drivers transmitting data rates to 100 Kbaud. Crosstalk among wires within a cable is controlled by the use of the slew rate control pins on the MC26LS30. Inputs The five inputs determine the state of the outputs in accordance with Table 1. All inputs (regardless of the operating mode) have a nominal threshold of +1.3 V, and their voltage must be kept within a range of 0 V to +15 V for proper operation. If an input is taken more than 0.3 V below ground, excessive currents will flow, and the proper operation of the drivers will be affected. An open pin is equivalent to a logic high, but good design practices dictate that inputs should never be left open. Unused inputs should be connected to ground. The characteristics of the inputs are shown in Figure 9. Mode Selection (Differential Mode) In this mode (Pins 4 and 8 at ground), only a +5.0 V supply ±5% is required at VCC. Pins 2 and 7 are the driver inputs, while Pins 10, 11, 14 and 15 are the outputs (see Block Diagram on page 1). The two outputs of a driver are always complementary and the differential voltage available at each pair of outputs is shown in Figure 6 for VCC = 5.0 V. The differential output voltage will vary directly with VCC. A “high” output can only source current, while a “low” output can only sink current (except for short circuit current − see Figure 8). The two outputs will be in a high impedance mode when the respective Enable input (Pin 3 or 6) is high, or if VCC 1.1 V. Output leakage current over a common mode range of ± 10 V is typically less than 1.0 µA. The outputs have short circuit current limiting, typically, less than 100 mA over a voltage range of 0 to +6.0 V (see Figure 8). Short circuits should not be allowed to last indefinitely as the IC may be damaged. Pins 9, 12, 13 and 16 are not normally used when in this mode, and should be left open. Power Supplies VCC requires +5.0 V, ±5%, regardless of the mode of operation. The supply current is determined by the IC’s internal bias requirements and the total load current. The internally required current is a function of the load current and is shown in Figure 7 for the differential mode. In the single−ended mode, VEE must be −5.0 V, ±5% in order to comply with EIA−423−A standards. Figures 12 and 13 indicate the internally required bias currents as a function of total load current (the sum of the four output loads). The discontinuity at 0 load current exists due to a change in bias current when the inputs are switched. The supply currents vary ≈ ± 2.0 mA as VCC and VEE are varied from 4.75 V to 5.25 V . Sequencing of the supplies during power−up/ power−down is not required. Bypass capacitors (0.1 µF minimum on each supply pin) are recommended to ensure proper operation. Capacitors reduce noise induced onto the supply lines by the switching action of the drivers, particularly where long P.C. board tracks are involved. Additionally, the capacitors help absorb (Single−Ended Mode) In this mode (Pin 4 ≥ 2.0 V) VCC requires +5.0 V, and VEE requires −5.0 V, both ±5.0%. Pins 2, 3, 6, and 7 are inputs for the four drivers, and Pins 15, 14, 11, and 10 (respectively) are the outputs. The four drivers are independent of each other, and each output will be at a positive or a negative voltage depending on its input state, the load current, and the supply voltage. Figures 10 & 11 indicate the high and low output voltages for VCC = 5.0 V, and VEE = −5.0 V. The graph http://onsemi.com 9 MC26LS30 PD [ 3.0 V 60 mA 2 ] (5.25 V 18 mA) PD 454 mW transients induced onto the drivers’ outputs from the external cable (from ESD, motor noise, nearby computers, etc.). The junction temperature calculates to: TJ 85°C (0.454 W 120°C W) 139°C for the SOIC package. Operating Temperature Range The maximum ambient operating temperature, listed as +85°C, is actually a function of the system use (i.e., specifically how many drivers within a package are used) and at what current levels they are operating. The maximum power which may be dissipated within the package is determined by: Since the maximum allowable junction temperature is not exceeded in any of the above cases, either package can be used in this application. 2) Single−Ended Mode Power Dissipation For the single−ended mode, the power dissipated within the package is calculated from: PDmax TJmax TA RJA PD (IB VCC) (IB VEE) [ (IO (VCC VOH) ] (each driver) where RθJA = package thermal resistance which is typically: The above equation assumes IO has the same magnitude for both output states, and makes use of the fact that the absolute value of the graphs of Figures 10 and 11 are nearly identical. IB+ and IB− are obtained from the right half of Figures 12 and 13, and (VCC − VOH) can be obtained from Figure 10. Note that the term (VCC − VOH) is constant for a given value of IO and does not vary with VCC. For an application involving the following conditions: TA = +85°C, IO = −60 mA (each driver), VCC = 5.25 V, VEE = −5.25 V, the suitability of the package types is calculated as follows. The power dissipated is: 120°C/W for the SOIC (D) package, TJmax = max. allowable junction temperature (150°C) TA = ambient air temperature near the IC package. 1) Differential Mode Power Dissipation For the differential mode, the power dissipated within the package is calculated from: PD [ (VCC VOD) IO ] (each driver) (VCC IB) where: VCC = the supply voltage VOD = is taken from Figure 6 for the known value of IO IB = the internal bias current (Figure 7) As indicated in the equation, the first term (in brackets) must be calculated and summed for each of the two drivers, while the last term is common to the entire package. Note that the term (VCC −VOD) is constant for a given value of IO and does not vary with VCC. For an application involving the following conditions: TA = +85°C, IO = −60 mA (each driver), VCC = 5.25 V, the suitability of the package types is calculated as follows. The power dissipated is: PD (24 mA 5.25 V) (3.0 mA 5.25 V) [ 60 mA 1.45 V 4.0 ] PD 490 mW The junction temperature calculates to: TJ 85°C (0.490 W 120°C W) 144°C for the SOIC package. Since the maximum allowable junction temperature is not exceeded in any of the above cases, either package can be used in this application. http://onsemi.com 10 MC26LS30 SYSTEM EXAMPLES (Pin numbers refer to SO−16 package only.) Differential System minimum voltage across any receiver inputs is never less than 200 mV. The ground terminals of each driver and receiver in Figure 18 must be connected together by a dedicated wire (or the shield) in the cable so as to provide a common reference. Chassis grounds or power line grounds should not be relied on for this common connection as they may generate significant common mode differences. Additionally, they usually do not provide a sufficiently low impedance at the frequencies of interest. An example of a typical EIA−422−A system is shown in Figure 17. Although EIA−422−A does not specifically address multiple driver situations, the MC26LS30 can be used in this manner since the outputs can be put into a high impedance mode. It is, however, the system designer’s responsibility to ensure the Enable pins are properly controlled so as to prevent two drivers on the same cable from being “on” at the same time. The limit on the number of receivers and drivers which may be connected on one system is determined by the input current of each receiver, the maximum leakage current of each “off” driver, and the DC current through each terminating resistor. The sum of these currents must not exceed the capability of the “on” driver (≈60 mA). If the cable is of any significant length, with receivers at various points along its length, the common mode voltage may vary along its length, and this parameter must be considered when calculating the maximum driver current. The cable requirements are defined not only by the AC characteristics and the data rate, but also by the DC resistance. The maximum resistance must be such that the minimum voltage across any receiver inputs is never less than 200 mV. The ground terminals of each driver and receiver in Figure 17 must be connected together by a dedicated wire (or the shield) in the cable to provide a common reference. Chassis grounds or power line grounds should not be relied on for this common connection as they may generate significant common mode differences. Additionally, they usually do not provide a sufficiently low impedance at the frequencies of interest. Additional Modes of Operation If compliance with EIA−422−A or EIA−423−A Standard is not required in a particular application, the MC26LS30 can be operated in two other modes. 1) The device may be operated in the differential mode (Pin 4 = 0) with VEE connected to any voltage between ground and −5.25 V. Outputs in the low state will be referenced to VEE, resulting in a differential output voltage greater than that shown in Figure 6. The Enable pins will operate the same as previously described. 2) The device may be operated in the single−ended mode (Pin 4 = 1) with VEE connected to any voltage between ground and −5.25 V. Outputs in the high state will be at a voltage as shown in Figure 10, while outputs in a low state will be referenced to VEE. Termination Resistors Transmission line theory states that, in order to preserve the shape and integrity of a waveform traveling along a cable, the cable must be terminated in an impedance equal to its characteristic impedance. In a system such as that depicted in Figure 17, in which data can travel in both directions, both physical ends of the cable must be terminated. Stubs leading to each receiver and driver should be as short as possible. In a system such as that depicted in Figure 18, in which data normally travels in one direction only, a terminator is theoretically required only at the receiving end of the cable. However, if the cable is in a location where noise spikes of several volts can be induced onto it, then a terminator (preferably a series resistor) should be placed at the driver end to prevent damage to the driver. Leaving off the terminations will generally result in reflections which can have amplitudes of several volts above VCC or several volts below ground or VEE. These overshoots/undershoots can disrupt the driver and/or receiver, create false data, and in some cases, damage components on the bus. Single−Ended System An example of a typical EIA−423−A system is shown in Figure 18. Multiple drivers on a single data line are not possible since the drivers cannot be put into a high impedance mode. Although each driver is shown connected to a single receiver, multiple receivers can be driven from a single driver as long as the total load current of the receivers and the terminating resistor does not exceed the capability of the driver (≈60 mA). If the cable is of any significant length, with receivers at various points along its length, the common mode voltage may vary along its length, and this parameter must be considered when calculating the maximum driver current. The cable requirements are defined not only by the AC characteristics and the data rate, but also by the DC resistance. The maximum resistance must be such that the http://onsemi.com 11 MC26LS30 En TTL R R TTL TTL D En TTL D RT En TTL D TTL R En TTL R D TTL En TTL D RT En D TTL TTL Twisted Pair R NOTES: 1. Terminating resistors RT should be located at the physical ends of the cable. 2. Stubs should be as short as possible. 3. Receivers = AM26LS32, MC3486, SN75173 or SN75175. 4. Circuit grounds must be connected together through a dedicated wire. Figure 17. EIA−422−A Example CC TTL D RT + R − TTL RT + R − TTL RT + R − TTL RT + R − TTL CC TTL D CC TTL D CC TTL D MC26LS30 AM26LS32, MC3486, SN75173, or SN75175 Figure 18. EIA−423−A Example http://onsemi.com 12 MC26LS30 PACKAGE DIMENSIONS SO−16 D SUFFIX CASE 751B−05 ISSUE J −A− 16 9 1 8 −B− P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 MC26LS30 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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