Features • High-performance, Low-power 32-bit Atmel® AVR® Microcontroller • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instructions – Read-modify-write Instructions and Atomic Bit Manipulation – Performance • Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State) • Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State) – Memory Protection Unit (MPU) • Secure Access Unit (SAU) providing User-defined Peripheral Protection picoPower® Technology for Ultra-low Power Consumption Multi-hierarchy Bus System – High-performance Data Transfers on Separate Buses for Increased Performance – 12 Peripheral DMA Channels improve Speed for Peripheral Communication Internal High-speed Flash – 256Kbytes, 128Kbytes, and 64Kbytes Versions – Single-cycle Access up to 25MHz – FlashVault Technology Allows Pre-programmed Secure Library Support for End User Applications – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User-defined Configuration Area Internal High-speed SRAM, Single-cycle Access at Full Speed – 32Kbytes (256Kbytes and 128Kbytes Flash) and 16Kbytes (64Kbytes Flash) Interrupt Controller (INTC) – Autovectored Low-latency Interrupt Service with Programmable Priority External Interrupt Controller (EIC) Peripheral Event System for Direct Peripheral to Peripheral Communication System Functions – Power and Clock Manager – SleepWalking Power Saving Control – Internal System RC Oscillator (RCSYS) – 32 KHz Oscillator – Multipurpose Oscillator, Phase Locked Loop (PLL), and Digital Frequency Locked Loop (DFLL) Windowed Watchdog Timer (WDT) Asynchronous Timer (AST) with Real-time Clock Capability – Counter or Calendar Mode Supported Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency Universal Serial Bus (USBC) – Full Speed and Low Speed USB Device Support – Multi-packet Ping-pong Mode Six 16-bit Timer/Counter (TC) Channels – External Clock Inputs, PWM, Capture, and Various Counting Capabilities 36 PWM Channels (PWMA) – 12-bit PWM with a Source Clock up to 150MHz Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Independent Baudrate Generator, Support for SPI – Support for Hardware Handshaking 32-bit Atmel AVR Microcontroller ATUC256L3U ATUC128L3U ATUC64L3U ATUC256L4U ATUC128L4U ATUC64L4U Summary 32142DS–06/2013 ATUC64/128/256L3/4U • One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals – Up to 15 SPI Slaves can be Addressed • Two Master and Two Slave Two-wire Interfaces (TWI), 400kbit/s I2C-compatible • One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution – Internal Temperature Sensor • Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module • • • • • • • – Hardware-assisted Atmel® AVR® QTouch® and Atmel® AVR® QMatrix Touch Acquisition – Supports QTouch and QMatrix Capture from Capacitive Touch Sensors QTouch Library Support – Capacitive Touch Buttons, Sliders, and Wheels – QTouch and QMatrix Acquisition Audio Bitstream DAC (ABDACB) Suitable for Stereo Audio Inter-IC Sound (IISC) Controller – Compliant with Inter-IC Sound (I2S) Specification On-chip Non-intrusive Debug System – Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace – aWire Single-pin Programming Trace and Debug Interface, Muxed with Reset Pin – NanoTrace Provides Trace Capabilities through JTAG or aWire Interface 64-pin TQFP/QFN (51 GPIO Pins), 48-pin TQFP/QFN/TLLGA (36 GPIO Pins) Six High-drive I/O Pins (64-pin Packages), Four High-drive I/O Pins (48-pin Packages) Single 1.62-3.6V Power Supply 2 32142DS–06/2013 ATUC64/128/256L3/4U 1. Description The Atmel® AVR® ATUC64/128/256L3/4U is a complete system-on-chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a highperformance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern and real-time operating systems. The Secure Access Unit (SAU) is used together with the MPU to provide the required security and integrity. Higher computation capability is achieved using a rich set of DSP instructions. The ATUC64/128/256L3/4U embeds state-of-the-art picoPower technology for ultra-low power consumption. Combined power control techniques are used to bring active current consumption down to 174µA/MHz, and leakage down to 220nA while still retaining a bank of backup registers. The device allows a wide range of trade-offs between functionality and power consumption, giving the user the ability to reach the lowest possible power consumption with the feature set required for the application. The Peripheral Direct Memory Access (DMA) controller enables data transfers between peripherals and memories without processor involvement. The Peripheral DMA controller drastically reduces processing overhead when transferring continuous and large data streams. The ATUC64/128/256L3/4U incorporates on-chip Flash and SRAM memories for secure and fast access. The FlashVault technology allows secure libraries to be programmed into the device. The secure libraries can be executed while the CPU is in Secure State, but not read by non-secure software in the device. The device can thus be shipped to end customers, who will be able to program their own code into the device to access the secure libraries, but without risk of compromising the proprietary secure code. The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each external interrupt has its own interrupt request and can be individually masked. The Peripheral Event System allows peripherals to receive, react to, and send peripheral events without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low power sleep modes. The Power Manager (PM) improves design flexibility and security. The Power Manager supports SleepWalking functionality, by which a module can be selectively activated based on peripheral events, even in sleep modes where the module clock is stopped. Power monitoring is supported by on-chip Power-on Reset (POR), Brown-out Detector (BOD), and Supply Monitor (SM). The device features several oscillators, such as Phase Locked Loop (PLL), Digital Frequency Locked Loop (DFLL), Oscillator 0 (OSC0), and system RC oscillator (RCSYS). Either of these oscillators can be used as source for the system clock. The DFLL is a programmable internal oscillator from 20 to 150MHz. It can be tuned to a high accuracy if an accurate reference clock is running, e.g. the 32KHz crystal oscillator. The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable. The Asynchronous Timer (AST) combined with the 32KHz crystal oscillator supports powerful real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in counter or calendar mode. 3 32142DS–06/2013 ATUC64/128/256L3/4U The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it to a known reference clock. The Full-speed USB 2.0 device interface (USBC) supports several USB classes at the same time, thanks to the rich end-point configuration. The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. The Pulse Width Modulation controller (PWMA) provides 12-bit PWM channels which can be synchronized and controlled from a common timer. 36 PWM channels are available, enabling applications that require multiple PWM outputs, such as LCD backlight control. The PWM channels can operate independently, with duty cycles set individually, or in interlinked mode, with multiple channels changed at the same time. The ATUC64/128/256L3/4U also features many communication interfaces, like USART, SPI, and TWI, for communication intensive applications. The USART supports different communication modes, like SPI Mode and LIN Mode. A general purpose 8-channel ADC is provided, as well as eight analog comparators (AC). The ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel. The analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using the QTouch technology. Capacitive touch sensors use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. The CAT module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced. All touch sensors can be configured to operate autonomously without software interaction, allowing wakeup from sleep modes when activated. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys as well as Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications. The Audio Bitstream DAC (ABDACB) converts a 16-bit sample value to a digital bitstream with an average value proportional to the sample value. Two channels are supported, making the ABDAC particularly suitable for stereo audio. The Inter-IC Sound Controller (IISC) provides a 5-bit wide, bidirectional, synchronous, digital audio link with external audio devices. The controller is compliant with the Inter-IC Sound (I2S) bus specification. The ATUC64/128/256L3/4U integrates a class 2+ Nexus 2.0 On-chip Debug (OCD) System, with non-intrusive real-time trace and full-speed read/write memory access, in addition to basic runtime control. The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers. The single-pin aWire interface allows all features available through the JTAG interface to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals. 4 32142DS–06/2013 ATUC64/128/256L3/4U 2. Overview Block Diagram Figure 2-1. Block Diagram EVTO_N TCK TDO TDI TMS DATAOUT JTAG INTERFACE DATA INTERFACE M M S AVR32UC CPU NEXUS CLASS 2+ OCD aWire RESET_N INSTR INTERFACE MEMORY INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N MEMORY PROTECTION UNIT M SAU S S POWER MANAGER CLOCK CONTROLLER SLEEP CONTROLLER REGISTERS BUS PERIPHERAL DMA CONTROLLER HSB-PB BRIDGE A DMA PA PB GENERALPURPOSE I/Os HSB-PB BRIDGE B 256/128/64 KB FLASH M S CONFIGURATION CAPACITIVE TOUCH MODULE DMA 8EP USART0 USART1 USART2 USART3 DMA USB 2.0 Interface S SPI DMA DP LOCAL BUS 32/16 KB SRAM S/M HIGH SPEED BUS MATRIX DM LOCAL BUS INTERFACE FLASH CONTROLLER 2.1 TWI MASTER 0 TWI MASTER 1 RESET CONTROLLER DIS VDIVEN CSA[16:0] CSB[16:0] SMP SYNC RXD TXD CLK RTS, CTS SCK MISO, MOSI NPCS[3..0] RCSYS TWCK RC32K RC120M XIN32 XOUT32 OSC32K XIN0 XOUT0 OSC0 SYSTEM CONTROL INTERFACE TWD TWALM TWCK DMA RC32OUT DFLL TWI SLAVE 0 TWI SLAVE 1 PLL TWD TWALM GENERAL PURPOSE I/Os GCLK_IN[2..0] GCLK[9..0] PA PB DMA ADP[1..0] 8-CHANNEL ADC INTERFACE TRIGGER AD[8..0] DMA INTERRUPT CONTROLLER INTER-IC SOUND CONTROLLER ISCK IWS ISDI ISDO IMCK DMA ADVREFP AUDIO BITSTREAM DAC DAC0, DAC1 CLK NMI EXTERNAL INTERRUPT CONTROLLER PWMA[35..0] PWM CONTROLLER EXTINT[5..1] AC INTERFACE ACBP[3..0] ACBN[3..0] ACAP[3..0] ACAN[3..0] ACREFN GLUE LOGIC CONTROLLER OUT[1..0] IN[7..0] ASYNCHRONOUS TIMER WATCHDOG TIMER FREQUENCY METER DACN0, DACN1 TIMER/COUNTER 0 TIMER/COUNTER 1 A[2..0] B[2..0] CLK[2..0] 5 32142DS–06/2013 ATUC64/128/256L3/4U 2.2 Configuration Summary Table 2-1. Configuration Summary Feature Flash SRAM ATUC256L3U ATUC128L3U ATUC64L3U ATUC256L4U ATUC128L4U ATUC64L4U 256KB 128KB 64KB 256KB 128KB 64KB 32KB 16KB 32KB 16KB GPIO 51 36 High-drive pins 6 4 External Interrupts 6 TWI 2 USART 4 Peripheral DMA Channels 12 Peripheral Event System 1 SPI 1 Asynchronous Timers 1 Timer/Counter Channels 6 PWM channels 36 Frequency Meter 1 Watchdog Timer 1 Power Manager 1 Secure Access Unit 1 Glue Logic Controller 1 Oscillators Digital Frequency Locked Loop 20-150MHz (DFLL) Phase Locked Loop 40-240MHz (PLL) Crystal Oscillator 0.45-16MHz (OSC0) Crystal Oscillator 32KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115kHz (RCSYS) RC Oscillator 32kHz (RC32K) ADC 8-channel 12-bit Temperature Sensor 1 Analog Comparators 8 Capacitive Touch Module 1 JTAG 1 aWire 1 USB 1 Audio Bitstream DAC 1 0 IIS Controller 1 0 Max Frequency Packages 50MHz TQFP64/QFN64 TQFP48/QFN48/TLLGA48 6 32142DS–06/2013 ATUC64/128/256L3/4U 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section . ATUC64/128/256L4U TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 PA21 PB10 RESET_N PB04 PB05 GND VDDCORE VDDIN PB14 PB13 PA01 PA02 12 11 10 9 8 7 6 5 4 3 2 1 PA05 PA00 PA06 PA22 PB03 PB02 PB00 PB12 PA03 PA08 PA09 GND 7 32142DS–06/2013 ATUC64/128/256L3/4U ATUC64/128/256L4U TLLGA48 Pinout 37 36 35 34 33 32 31 30 29 28 27 26 25 PA15 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-2. PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 24 23 22 21 20 19 18 17 16 15 14 38 39 40 41 42 43 44 45 46 47 48 PA21 PB10 RESET_N PB04 PB05 GND VDDCORE VDDIN PB14 PB13 PA01 13 12 11 10 9 8 7 6 5 4 3 2 1 PA02 PA05 PA00 PA06 PA22 PB03 PB02 PB00 PB12 PA03 PA08 PA09 GND 8 32142DS–06/2013 ATUC64/128/256L3/4U PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB22 PB21 PB09 PA04 VDDIO GND PA11 PA13 PA20 ATUC64/128/256L3U TQFP64/QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Figure 3-3. PA15 49 32 PA21 PA16 50 31 PB10 PA17 51 30 PA19 52 29 RESET_N PB04 PA18 53 28 PB05 PB23 54 27 PB24 55 26 GND VDDCORE PB11 56 PB15 57 25 24 PB16 58 23 PB17 59 22 PB27 PB14 PB13 PB18 60 21 PB26 PB25 61 20 PB01 PA10 62 19 PA12 63 18 PA07 PA01 VDDIO 64 17 PA02 VDDIN 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 GND VDDIO PB03 PB02 PB00 PB12 PA03 PB20 PB19 PA08 PA09 GND PA05 PA00 PA06 PA22 9 32142DS–06/2013 ATUC64/128/256L3/4U Peripheral Multiplexing on I/O lines 3.1.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing GPIO Function 48pin 64pin Pin Name G PI O Supply 11 15 PA00 0 14 18 PA01 13 17 4 Pad Type A B C VDDIO Normal I/O USART0TXD USART1RTS SPINPCS[2] 1 VDDIO Normal I/O USART0RXD USART1CTS SPINPCS[3] USART1CLK PWMAPWMA[1] PA02 2 VDDIO Highdrive I/O USART0RTS ADCIFBTRIGGER USART2TXD TC0-A0 6 PA03 3 VDDIO Normal I/O USART0CTS SPINPCS[1] USART2TXD 28 38 PA04 4 VDDIO Normal I/O SPI-MISO TWIMS0TWCK 12 16 PA05 5 VDDIO Normal I/O (TWI) SPI-MOSI 10 14 PA06 6 VDDIO Highdrive I/O, 5V tolerant 19 PA07 7 VDDIO G H SCIFGCLK[0] CATCSA[2] ACIFBACAP[0] TWIMS0TWALM CATCSA[1] PWMAPWMA[2] ACIFBACBP[0] USART0CLK CATCSA[3] TC0-B0 PWMAPWMA[3] ACIFBACBN[3] USART0CLK CATCSB[3] USART1RXD TC0-B1 PWMAPWMA[4] ACIFBACBP[1] TWIMS1TWCK USART1TXD TC0-A1 PWMAPWMA[5] ACIFBACBN[0] TWIMS0TWD CATCSB[7] SPI-SCK USART2TXD USART1CLK TC0-B0 PWMAPWMA[6] EICEXTINT[2] SCIFGCLK[1] CATCSB[1] Normal I/O (TWI) SPINPCS[0] USART2RXD TWIMS1TWALM TWIMS0TWCK PWMAPWMA[7] ACIFBACAN[0] USART1TXD SPINPCS[2] TC0-A2 ADCIFBADP[0] PWMAPWMA[8] SPINPCS[3] TC0-B2 ADCIFBADP[1] PWMAPWMA[9] SCIFGCLK[2] EICEXTINT[1] CATCSB[4] PWMAPWMA[10] ACIFBACAP[1] SCIFGCLK[2] CATCSA[5] 3 3 PA08 8 VDDIO Highdrive I/O 2 2 PA09 9 VDDIO Highdrive I/O USART1RXD 46 62 PA10 10 VDDIO Normal I/O TWIMS0TWD 27 35 PA11 11 VDDIN Normal I/O 47 63 PA12 12 VDDIO Normal I/O 26 34 PA13 13 VDDIN Normal I/O 36 48 PA14 14 VDDIO 37 49 PA15 15 38 50 PA16 16 D E F PWMAPWMA[0] TC0-A0 CATCSA[7] EICNMI (EXTINT[0]) CATCSB[2] CATCSA[4] PWMAPWMA[11] USART2CLK TC0-CLK1 CAT-SMP PWMAPWMA[12] ACIFBACAN[1] SCIFGCLK[3] CATCSB[5] GLOCOUT[0] GLOCIN[7] TC0-A0 SCIFGCLK[2] PWMAPWMA[13] CAT-SMP EICEXTINT[2] CATCSA[0] Normal I/O ADCIFBAD[0] TC0-CLK2 USART2RTS CAT-SMP PWMAPWMA[14] SCIFGCLK[4] CATCSA[6] VDDIO Normal I/O ADCIFBAD[1] TC0-CLK1 GLOCIN[6] PWMAPWMA[15] CATSYNC EICEXTINT[3] CATCSB[6] VDDIO Normal I/O ADCIFBAD[2] TC0-CLK0 GLOCIN[5] PWMAPWMA[16] ACIFBACREFN EICEXTINT[4] CATCSA[8] 10 32142DS–06/2013 ATUC64/128/256L3/4U Table 3-1. GPIO Controller Function Multiplexing 39 51 PA17 17 VDDIO Normal I/O (TWI) 41 53 PA18 18 VDDIO Normal I/O ADCIFBAD[4] 40 52 PA19 19 VDDIO Normal I/O ADCIFBAD[5] 25 33 PA20 20 VDDIN Normal I/O USART2TXD USART2RXD TWIMS1TWD PWMAPWMA[17] CAT-SMP CAT-DIS CATCSB[8] GLOCIN[4] PWMAPWMA[18] CATSYNC EICEXTINT[5] CATCSB[0] TC0-A2 TWIMS1TWALM PWMAPWMA[19] SCIFGCLK_IN[ 0] CAT-SYNC CATCSA[10] TC0-A1 GLOCIN[3] PWMAPWMA[20] SCIFRC32OUT TWIMS0TWD TC0-B1 ADCIFBTRIGGER PWMAPWMA[21] PWMAPWMAOD [21] TC0-A1 USART2CTS TC0-B1 24 32 PA21 21 VDDIN Normal I/O (TWI, 5V tolerant, SMBus) 9 13 PA22 22 VDDIO Normal I/O USART0CTS USART2CLK TC0-B2 CAT-SMP PWMAPWMA[22] ACIFBACBN[2] 6 8 PB00 32 VDDIO Normal I/O USART3TXD ADCIFBADP[0] SPINPCS[0] TC0-A1 PWMAPWMA[23] ACIFBACAP[2] 20 PB01 33 VDDIO Highdrive I/O USART3RXD ADCIFBADP[1] SPI-SCK TC0-B1 PWMAPWMA[24] 7 9 PB02 34 VDDIO Normal I/O USART3RTS USART3CLK SPI-MISO TC0-A2 PWMAPWMA[25] 8 10 PB03 35 VDDIO Normal I/O USART3CTS USART3CLK SPI-MOSI TC0-B2 VDDIN Normal I/O (TWI, 5V tolerant, SMBus) TC1-A0 USART1RTS USART1CLK TC1-B0 USART1CTS 21 29 PB04 36 20 28 PB05 37 VDDIN Normal I/O (TWI, 5V tolerant, SMBus) 30 42 PB06 38 VDDIO Normal I/O TC1-A1 CATCSA[12] SCIFGCLK[0] CATSMP CATCSB[10] TC1-A0 CATCSA[9] TC1-A1 CATCSB[9] ACIFBACAN[2] SCIFGCLK[1] CATCSB[11] PWMAPWMA[26] ACIFBACBP[2] TC1-A2 CATCSA[11] TWIMS0TWALM PWMAPWMA[27] PWMAPWMAOD [27] TWIMS1TWCK CATCSA[14] USART1CLK TWIMS0TWCK PWMAPWMA[28] PWMAPWMAOD [28] SCIFGCLK[3] CATCSB[14] USART3TXD ADCIFBAD[6] GLOCIN[2] PWMAPWMA[29] ACIFBACAN[3] EICNMI (EXTINT[0]) CATCSB[13] 31 43 PB07 39 VDDIO Normal I/O TC1-B1 USART3RXD ADCIFBAD[7] GLOCIN[1] PWMAPWMA[30] ACIFBACAP[3] EICEXTINT[1] CATCSA[13] 32 44 PB08 40 VDDIO Normal I/O TC1-A2 USART3RTS ADCIFBAD[8] GLOCIN[0] PWMAPWMA[31] CATSYNC EICEXTINT[2] CATCSB[12] 29 39 PB09 41 VDDIO Normal I/O TC1-B2 USART3CTS USART3CLK PWMAPWMA[32] ACIFBACBN[1] EICEXTINT[3] CATCSB[15] 23 31 PB10 42 VDDIN Normal I/O TC1-CLK0 USART1TXD USART3CLK GLOCOUT[1] PWMAPWMA[33] SCIFGCLK_IN[ 1] EICEXTINT[4] CATCSB[16] 44 56 PB11 43 VDDIO Normal I/O TC1-CLK1 USART1RXD ADCIFBTRIGGER PWMAPWMA[34] CATVDIVEN EICEXTINT[5] CATCSA[16] 5 7 PB12 44 VDDIO Normal I/O TC1-CLK2 CATSYNC PWMAPWMA[35] ACIFBACBP[3] SCIFGCLK[4] CATCSA[15] 15 22 PB13 45 VDDIN USB I/O USBC-DM USART3TXD TC1-A1 PWMAPWMA[7] ADCIFBADP[1] SCIFGCLK[5] CATCSB[2] 16 23 PB14 46 VDDIN USB I/O USBC-DP USART3RXD TC1-B1 PWMAPWMA[24] SCIFGCLK[5] CATCSB[9] TWIMS1TWALM 11 32142DS–06/2013 ATUC64/128/256L3/4U Table 3-1. 3.2 GPIO Controller Function Multiplexing 57 PB15 47 VDDIO Highdrive I/O ABDACBCLK IISCIMCK SPI-SCK PWMAPWMA[8] SCIFGCLK[3] CATCSB[4] 58 PB16 48 VDDIO Normal I/O ABDACBDAC[0] IISC-ISCK USART0TXD PWMAPWMA[9] SCIFGCLK[2] CATCSA[5] 59 PB17 49 VDDIO Normal I/O ABDACBDAC[1] IISC-IWS USART0RXD PWMAPWMA[10] CATCSB[5] 60 PB18 50 VDDIO Normal I/O ABDACBDACN[0] IISC-ISDI USART0RTS PWMAPWMA[12] CATCSA[0] 4 PB19 51 VDDIO Normal I/O ABDACBDACN[1] IISC-ISDO USART0CTS PWMAPWMA[20] 5 PB20 52 VDDIO Normal I/O TWIMS1TWD USART2RXD SPINPCS[1] TC0-A0 PWMAPWMA[21] 40 PB21 53 VDDIO Normal I/O TWIMS1TWCK USART2TXD SPINPCS[2] TC0-B0 41 PB22 54 VDDIO Normal I/O TWIMS1TWALM SPINPCS[3] 54 PB23 55 VDDIO Normal I/O SPI-MISO USART2RTS 55 PB24 56 VDDIO Normal I/O SPI-MOSI USART2CTS 61 PB25 57 VDDIO Normal I/O SPINPCS[0] 21 PB26 58 VDDIO Normal I/O SPI-SCK 24 PB27 59 VDDIN Normal I/O TC0-CLK2 EICEXTINT[1] CATCSA[12] USART1RTS USART1CLK CATCSA[14] PWMAPWMA[28] USART1CTS USART1CLK CATCSB[14] TC0-CLK0 PWMAPWMA[27] ADCIFBTRIGGER SCIFGCLK[0] CATCSA[8] USART2CLK TC0-A2 PWMAPWMA[0] CAT-SMP SCIFGCLK[6] CATCSA[4] USART2CLK TC0-B2 PWMAPWMA[1] ADCIFBADP[1] SCIFGCLK[7] CATCSA[2] USART1RXD TC0-A1 PWMAPWMA[2] SCIFGCLK_IN[ 2] SCIFGCLK[8] CATCSA[3] USART1TXD TC0-B1 PWMAPWMA[3] ADCIFBADP[0] SCIFGCLK[9] CATCSB[3] USART1RXD TC0-CLK1 PWMAPWMA[4] ADCIFBADP[1] EICNMI (EXTINT[0]) CATCSA[9] See Section 3.3 for a description of the various peripheral signals. Refer to ”Electrical Characteristics” on page 991 for a description of the electrical properties of the pin types used. 3.2.1 TWI, 5V Tolerant, and SMBUS Pins Some normal I/O pins offer TWI, 5V tolerance, and SMBUS features. These features are only available when either of the TWI functions or the PWMAOD function in the PWMA are selected for these pins. Refer to the ”Electrical Characteristics” on page 991 for a description of the electrical properties of the TWI, 5V tolerance, and SMBUS pins. 12 32142DS–06/2013 ATUC64/128/256L3/4U 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the same pin. Table 3-2. 3.2.3 Peripheral Functions Function Description GPIO Controller Function multiplexing GPIO and GPIO peripheral selection A to H Nexus OCD AUX port connections OCD trace system aWire DATAOUT aWire output in two-pin mode JTAG port connections JTAG debug port Oscillators OSC0, OSC32 JTAG Port Connections If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O Controller configuration. Table 3-3. 3.2.4 JTAG Pinout 48-pin 64-pin Pin name JTAG pin 11 15 PA00 TCK 14 18 PA01 TMS 13 17 PA02 TDO 4 6 PA03 TDI Nexus OCD AUX Port Connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the I/O Controller configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual. Table 3-4. Nexus OCD AUX Port Connections Pin AXS=1 AXS=0 EVTI_N PA05 PB08 MDO[5] PA10 PB00 MDO[4] PA18 PB04 MDO[3] PA17 PB05 MDO[2] PA16 PB03 MDO[1] PA15 PB02 MDO[0] PA14 PB09 13 32142DS–06/2013 ATUC64/128/256L3/4U Table 3-4. 3.2.5 Nexus OCD AUX Port Connections Pin AXS=1 AXS=0 EVTO_N PA04 PA04 MCKO PA06 PB01 MSEO[1] PA07 PB11 MSEO[0] PA11 PB12 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-5. 3.2.6 Oscillator Pinout 48-pin 64-pin Pin Name Oscillator Pin 3 3 PA08 XIN0 46 62 PA10 XIN32 26 34 PA13 XIN32_2 2 2 PA09 XOUT0 47 63 PA12 XOUT32 25 33 PA20 XOUT32_2 Other Functions The functions listed in Table 3-6 are not mapped to the normal GPIO functions. The aWire DATA pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be active after the aWire is enabled and the 2_PIN_MODE command has been sent. The WAKE_N pin is always enabled. Please refer to Section 6.1.4.2 on page 45 for constraints on the WAKE_N pin. Table 3-6. Other Functions 48-pin 64-pin Pin Name Function 27 35 PA11 WAKE_N 22 30 RESET_N aWire DATA 11 15 PA00 aWire DATAOUT 14 32142DS–06/2013 ATUC64/128/256L3/4U 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7. Signal Descriptions List Signal Name Function Type Active Level Comments Audio Bitstream DAC - ABDACB CLK D/A Clock out Output DAC1 - DAC0 D/A Bitstream out Output DACN1 - DACN0 D/A Inverted bitstream out Output Analog Comparator Interface - ACIFB ACAN3 - ACAN0 Negative inputs for comparators "A" Analog ACAP3 - ACAP0 Positive inputs for comparators "A" Analog ACBN3 - ACBN0 Negative inputs for comparators "B" Analog ACBP3 - ACBP0 Positive inputs for comparators "B" Analog ACREFN Common negative reference Analog ADC Interface - ADCIFB AD8 - AD0 Analog Signal Analog ADP1 - ADP0 Drive Pin for resistive touch screen Output TRIGGER External trigger Input aWire - AW DATA aWire data I/O DATAOUT aWire data output for 2-pin mode I/O Capacitive Touch Module - CAT CSA16 - CSA0 Capacitive Sense A I/O CSB16 - CSB0 Capacitive Sense B I/O DIS Discharge current control Analog SMP SMP signal Output SYNC Synchronize signal VDIVEN Voltage divider enable Input Output External Interrupt Controller - EIC NMI (EXTINT0) Non-Maskable Interrupt Input EXTINT5 - EXTINT1 External interrupt Input Glue Logic Controller - GLOC IN7 - IN0 Inputs to lookup tables OUT1 - OUT0 Outputs from lookup tables Input Output Inter-IC Sound (I2S) Controller - IISC 15 32142DS–06/2013 ATUC64/128/256L3/4U Table 3-7. Signal Descriptions List IMCK I2S Master Clock Output ISCK I2S Serial Clock I/O ISDI I2S Serial Data In ISDO I2S Serial Data Out IWS I2S Word Select Input Output I/O JTAG module - JTAG TCK Test Clock Input TDI Test Data In Input TDO Test Data Out TMS Test Mode Select Output Input Power Manager - PM RESET_N Reset Input Low Pulse Width Modulation Controller - PWMA PWMA35 - PWMA0 PWMA channel waveforms Output PWMAOD35 PWMAOD0 PWMA channel waveforms, open drain mode Output Not all channels support open drain mode System Control Interface - SCIF GCLK9 - GCLK0 Generic Clock Output Output GCLK_IN2 - GCLK_IN0 Generic Clock Input RC32OUT RC32K output at startup Output XIN0 Crystal 0 Input Analog/ Digital XIN32 Crystal 32 Input (primary location) Analog/ Digital XIN32_2 Crystal 32 Input (secondary location) Analog/ Digital XOUT0 Crystal 0 Output Analog XOUT32 Crystal 32 Output (primary location) Analog XOUT32_2 Crystal 32 Output (secondary location) Analog Input Serial Peripheral Interface - SPI MISO Master In Slave Out I/O MOSI Master Out Slave In I/O NPCS3 - NPCS0 SPI Peripheral Chip Select I/O SCK Clock I/O Low Timer/Counter - TC0, TC1 A0 Channel 0 Line A I/O A1 Channel 1 Line A I/O A2 Channel 2 Line A I/O 16 32142DS–06/2013 ATUC64/128/256L3/4U Table 3-7. Signal Descriptions List B0 Channel 0 Line B I/O B1 Channel 1 Line B I/O B2 Channel 2 Line B I/O CLK0 Channel 0 External Clock Input Input CLK1 Channel 1 External Clock Input Input CLK2 Channel 2 External Clock Input Input Two-wire Interface - TWIMS0, TWIMS1 TWALM SMBus SMBALERT I/O TWCK Two-wire Serial Clock I/O TWD Two-wire Serial Data I/O Low Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK Clock CTS Clear To Send RTS Request To Send RXD Receive Data Input TXD Transmit Data Output Note: I/O Input Low Output Low 1. ADCIFB: AD3 does not exist. Table 3-8. Signal Name Signal Description List, Continued Function Type Active Level Comments Power VDDCORE Core Power Supply / Voltage Regulator Output Power Input/Output 1.62V to 1.98V VDDIO I/O Power Supply Power Input 1.62V to 3.6V. VDDIO should always be equal to or lower than VDDIN. VDDANA Analog Power Supply Power Input 1.62V to 1.98V ADVREFP Analog Reference Voltage Power Input 1.62V to 1.98V VDDIN Voltage Regulator Input Power Input 1.62V to 3.6V(1) GNDANA Analog Ground Ground GND Ground Ground Auxiliary Port - AUX MCKO Trace Data Output Clock Output MDO5 - MDO0 Trace Data Output Output 17 32142DS–06/2013 ATUC64/128/256L3/4U Table 3-8. Signal Description List, Continued Signal Name Function MSEO1 - MSEO0 Trace Frame Control EVTI_N Event In EVTO_N Event Out Type Active Level Comments Output Input Low Output Low General Purpose I/O pin PA22 - PA00 Parallel I/O Controller I/O Port 0 I/O PB27 - PB00 Parallel I/O Controller I/O Port 1 I/O Note: 1. See Section 6. on page 40 3.4 I/O Line Considerations 3.4.1 JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up enabled during reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled. Please refer to Section 3.2.3 on page 13 for the JTAG port connections. 3.4.2 PA00 Note that PA00 is multiplexed with TCK. PA00 GPIO function must only be used as output in the application. 3.4.3 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIN. As the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debugging, it must not be driven by external circuitry. 3.4.4 TWI Pins PA21/PB04/PB05 When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. Selected pins are also SMBus compliant (refer to Section on page 10). As required by the SMBus specification, these pins provide no leakage path to ground when the ATUC64/128/256L3/4U is powered down. This allows other devices on the SMBus to continue communicating even though the ATUC64/128/256L3/4U is not powered. After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the GPIO Module Configuration chapter for details. 18 32142DS–06/2013 ATUC64/128/256L3/4U 3.4.5 TWI Pins PA05/PA07/PA17 When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the GPIO Module Configuration chapter for details. 3.4.6 GPIO Pins All the I/O lines integrate a pull-up resistor Programming of this pull-up resistor is performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as inputs with pull-up resistors disabled, except PA00 which has the pull-up resistor enabled. PA20 selects SCIF-RC32OUT (GPIO Function F) as default enabled after reset. 3.4.7 High-drive Pins The six pins PA02, PA06, PA08, PA09, PB01, and PB15 have high-drive output capabilities. Refer to Section 34. on page 991 for electrical characteristics. 3.4.8 USB Pins PB13/PB14 When these pins are used for USB, the pins are behaving according to the USB specification. When used as GPIO pins or used for other peripherals, the pins have the same behaviour as other normal I/O pins, but the characteristics are different. Refer to Section 34. on page 991 for electrical characteristics. To be able to use the USB I/O the VDDIN power supply must be 3.3 V nominal. 3.4.9 RC32OUT Pin 3.4.9.1 Clock output at startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by the system to start other devices or to clock a switching regulator to rise the power supply voltage up to an acceptable value. The clock will be available on PA20, but will be disabled if one of the following conditions are true: • PA20 is configured to use a GPIO function other than F (SCIF-RC32OUT) • PA20 is configured as a General Purpose Input/Output (GPIO) • The bit FRC32 in the Power Manager PPCR register is written to zero (refer to the Power Manager chapter) The maximum amplitude of the clock signal will be defined by VDDIN. Once the RC32K output on PA20 is disabled it can never be enabled again. 3.4.9.2 XOUT32_2 function PA20 selects RC32OUT as default enabled after reset. This function is not automatically disabled when the user enables the XOUT32_2 function on PA20. This disturbs the oscillator and may result in the wrong frequency. To avoid this, RC32OUT must be disabled when XOUT32_2 is enabled. 19 32142DS–06/2013 ATUC64/128/256L3/4U 3.4.10 ADC Input Pins These pins are regular I/O pins powered from the VDDIO. However, when these pins are used for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins are not used for ADC inputs, the pins may be driven to the full I/O voltage range. 20 32142DS–06/2013 ATUC64/128/256L3/4U 4. Mechanical Characteristics 4.1 4.1.1 Thermal Considerations Thermal Data Table 4-1 summarizes the thermal resistance data depending on the package. Table 4-1. 4.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ JA Junction-to-ambient thermal resistance Still Air TQFP48 54.4 JC Junction-to-case thermal resistance TQFP48 15.7 JA Junction-to-ambient thermal resistance QFN48 26.0 JC Junction-to-case thermal resistance QFN48 1.6 JA Junction-to-ambient thermal resistance TLLGA48 25.4 JC Junction-to-case thermal resistance TLLGA48 12.7 JA Junction-to-ambient thermal resistance TQFP64 52.9 JC Junction-to-case thermal resistance TQFP64 15.5 JA Junction-to-ambient thermal resistance QFN64 22.9 JC Junction-to-case thermal resistance QFN64 1.6 Still Air Still Air Still Air Still Air Unit C/W C/W C/W C/W C/W Junction Temperature The average chip-junction temperature, TJ, in °C can be obtained from the following: 1. T J = T A + P D JA 2. T J = T A + P D HEATSINK + JC where: • JA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 4-1. • JC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 4-1. • HEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet. • PD = device power consumption (W) estimated from data provided in Section 34.4 on page 992. • TA = ambient temperature (°C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C. 21 32142DS–06/2013 ATUC64/128/256L3/4U 4.2 Package Drawings Figure 4-1. TQFP-48 Package Drawing Table 4-2. Device and Package Maximum Weight 140 Table 4-3. mg Package Characteristics Moisture Sensitivity Level Table 4-4. MSL3 Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification E3 22 32142DS–06/2013 ATUC64/128/256L3/4U Figure 4-2. Note: QFN-48 Package Drawing The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 4-5. Device and Package Maximum Weight 140 Table 4-6. mg Package Characteristics Moisture Sensitivity Level Table 4-7. MSL3 Package Reference JEDEC Drawing Reference M0-220 JESD97 Classification E3 23 32142DS–06/2013 ATUC64/128/256L3/4U Figure 4-3. TLLGA-48 Package Drawing Table 4-8. Device and Package Maximum Weight 39.3 Table 4-9. mg Package Characteristics Moisture Sensitivity Level Table 4-10. MSL3 Package Reference JEDEC Drawing Reference N/A JESD97 Classification E4 24 32142DS–06/2013 ATUC64/128/256L3/4U Figure 4-4. TQFP-64 Package Drawing Table 4-11. Device and Package Maximum Weight 300 Table 4-12. mg Package Characteristics Moisture Sensitivity Level Table 4-13. MSL3 Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification E3 25 32142DS–06/2013 ATUC64/128/256L3/4U Figure 4-5. Note: QFN-64 Package Drawing The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 4-14. Device and Package Maximum Weight 200 Table 4-15. mg Package Characteristics Moisture Sensitivity Level Table 4-16. MSL3 Package Reference JEDEC Drawing Reference M0-220 JESD97 Classification E3 26 32142DS–06/2013 ATUC64/128/256L3/4U 4.3 Soldering Profile Table 4-17 gives the recommended soldering profile from J-STD-20. Table 4-17. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/s max Preheat Temperature 175°C ±25°C 150-200°C Time Maintained Above 217°C 60-150 s Time within 5C of Actual Peak Temperature 30 s Peak Temperature Range 260°C Ramp-down Rate 6°C/s max Time 25C to Peak Temperature 8 minutes max A maximum of three reflow passes is allowed per component. 27 32142DS–06/2013 ATUC64/128/256L3/4U 5. Ordering Information Table 5-1. Device Ordering Information Ordering Code Carrier Type ATUC256L3U-AUTES ES ATUC256L3U-AUT Tray ATUC256L3U-AUR Tape & Reel Package Package Type Temperature Operating Range N/A TQFP 64 Industrial (-40C to 85C) ATUC256L3U JESD97 Classification E3 ATUC256L3U-Z3UTES ES ATUC256L3U-Z3UT Tray ATUC256L3U-Z3UR Tape & Reel N/A QFN 64 Industrial (-40C to 85C) ATUC128L3U-AUT Tray ATUC128L3U-AUR Tape & Reel ATUC128L3U-Z3UT Tray ATUC128L3U-Z3UR Tape & Reel TQFP 64 ATUC128L3U JESD97 Classification E3 Industrial (-40C to 85C) JESD97 Classification E3 Industrial (-40C to 85C) QFN 64 ATUC64L3U-AUT Tray ATUC64L3U-AUR Tape & Reel ATUC64L3U-Z3UT Tray ATUC64L3U-Z3UR Tape & Reel TQFP 64 ATUC64L3U QFN 64 28 32142DS–06/2013 ATUC64/128/256L3/4U Table 5-1. Device Ordering Information Ordering Code Carrier Type ATUC256L4U-AUTES ES ATUC256L4U-AUT Tray ATUC256L4U-AUR Tape & Reel Package Package Type Temperature Operating Range N/A TQFP 48 Industrial (-40C to 85C) JESD97 Classification E3 ATUC256L4U ATUC256L4U-ZAUTES ES ATUC256L4U-ZAUT Tray ATUC256L4U-ZAUR Tape & Reel N/A QFN 48 Industrial (-40C to 85C) ATUC256L4U-D3HES ES ATUC256L4U-D3HT Tray ATUC256L4U-D3HR Tape & Reel ATUC128L4U-AUT Tray ATUC128L4U-AUR Tape & Reel ATUC128L4U-ZAUT Tray ATUC128L4U-ZAUR Tape & Reel ATUC128L4U-D3HT Tray ATUC128L4U-D3HR Tape & Reel N/A TLLGA 48 JESD97 Classification E4 TQFP 48 JESD97 Classification E3 ATUC128L4U QFN 48 TLLGA 48 ATUC64L4U-AUT Tray ATUC64L4U-AUR Tape & Reel ATUC64L4U-ZAUT Tray ATUC64L4U-ZAUR Tape & Reel ATUC64L4U-D3HT Tray ATUC64L4U-D3HR Tape & Reel JESD97 Classification E4 Industrial (-40C to 85C) TQFP 48 JESD97 Classification E3 ATUC64L4U QFN 48 TLLGA 48 JESD97 Classification E4 29 32142DS–06/2013 ATUC64/128/256L3/4U 6. Errata 6.1 6.1.1 Rev. C SCIF 1. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it: - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as one - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. 2. PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero. 3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any location in the SCIF memory range. Fix/Workaround None. 6.1.2 SPI 1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 2. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 3. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 30 32142DS–06/2013 ATUC64/128/256L3/4U 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 6. SPI RDR.PCS is not correct The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not correctly indicate the value on the NPCS pins at the end of a transfer. Fix/Workaround Do not use the PCS field of the SPI RDR. 6.1.3 TWI 1. SMBALERT bit may be set after reset The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after system reset. Fix/Workaround After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer. 2. Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. 6.1.4 TC 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 6.1.5 CAT 1. CAT QMatrix sense capacitors discharged prematurely At the end of a QMatrix burst charging sequence that uses different burst count values for different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph31 32142DS–06/2013 ATUC64/128/256L3/4U eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency. This results in premature loss of charge from the sense capacitors and thus increased variability of the acquired count values. Fix/Workaround Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register. 2. Autonomous CAT acquisition must be longer than AST source clock period When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST source clock is larger than one CAT acquisition. One AST clock period after the AST trigger, the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely, ruining the result. Fix/Workaround Always ensure that the ATCFG1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the AST source clock. 6.1.6 aWire 1. aWire MEMORY_SPEED_REQUEST command does not return correct CV The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to the formula in the aWire Debug Interface chapter. Fix/Workaround Issue a dummy read to address 0x100000000 before issuing the MEMORY_SPEED_REQUEST command and use this formula instead: 7f aw f sab = ---------------CV – 3 6.1.7 Flash 1. Corrupted data in flash may happen after flash page write operations After a flash page write operation from an external in situ programmer, reading (data read or code fetch) in flash may fail. This may lead to an exception or to others errors derived from this corrupted read access. Fix/Workaround Before any flash page write operation, each write in the page buffer must preceded by a write in the page buffer with 0xFFFF_FFFF content at any address in the page. 6.2 6.2.1 Rev. B SCIF 1. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it: - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as one 32 32142DS–06/2013 ATUC64/128/256L3/4U - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. 2. PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero. 3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any location in the SCIF memory range. Fix/Workaround None. 6.2.2 WDT 1. WDT Control Register does not have synchronization feedback When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN), Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchronizer is started to propagate the values to the WDT clcok domain. This synchronization takes a finite amount of time, but only the status of the synchronization of the EN bit is reflected back to the user. Writing to the synchronized fields during synchronization can lead to undefined behavior. Fix/Workaround -When writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the WDT peripheral bus clock and the selected WDT clock source. -When doing writes that changes the EN bit, the EN bit can be read back until it reflects the written value. 6.2.3 SPI 1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 2. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 3. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 33 32142DS–06/2013 ATUC64/128/256L3/4U 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 6. SPI RDR.PCS is not correct The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not correctly indicate the value on the NPCS pins at the end of a transfer. Fix/Workaround Do not use the PCS field of the SPI RDR. 6.2.4 TWI 1. TWIS may not wake the device from sleep mode If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condition, the CPU may not wake upon a TWIS address match. The request is NACKed. Fix/Workaround When using the TWI address match to wake the device from sleep, do not switch to sleep modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus events. 2. SMBALERT bit may be set after reset The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after system reset. Fix/Workaround After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer. 3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. 6.2.5 PWMA 1. The SR.READY bit cannot be cleared by writing to SCR.READY The Ready bit in the Status Register will not be cleared when writing a one to the corresponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is set. Fix/Workaround 34 32142DS–06/2013 ATUC64/128/256L3/4U Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Status Register before enabling the interrupt. 6.2.6 TC 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 6.2.7 CAT 1. CAT QMatrix sense capacitors discharged prematurely At the end of a QMatrix burst charging sequence that uses different burst count values for different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the peripheral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency. This results in premature loss of charge from the sense capacitors and thus increased variability of the acquired count values. Fix/Workaround Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register. 2. Autonomous CAT acquisition must be longer than AST source clock period When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST source clock is larger than one CAT acquisition. One AST clock period after the AST trigger, the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely, ruining the result. Fix/Workaround Always ensure that the ATCFG1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the AST source clock. 3. CAT consumes unnecessary power when disabled or when autonomous touch not used A CAT prescaler controlled by the ATCFG0.DIV field will be active even when the CAT module is disabled or when the autonomous touch feature is not used, thereby causing unnecessary power consumption. Fix/Workaround If the CAT module is not used, disable the CLK_CAT clock in the PM module. If the CAT module is used but the autonomous touch feature is not used, the power consumption of the CAT module may be reduced by writing 0xFFFF to the ATCFG0.DIV field. 6.2.8 aWire 1. aWire MEMORY_SPEED_REQUEST command does not return correct CV The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to the formula in the aWire Debug Interface chapter. Fix/Workaround 35 32142DS–06/2013 ATUC64/128/256L3/4U Issue a dummy read to address 0x100000000 before MEMORY_SPEED_REQUEST command and use this formula instead: issuing the 7f aw f sab = ---------------CV – 3 6.2.9 Flash 1. Corrupted data in flash may happen after flash page write operations After a flash page write operation from an external in situ programmer, reading (data read or code fetch) in flash may fail. This may lead to an exception or to others errors derived from this corrupted read access. Fix/Workaround Before any flash page write operation, each write in the page buffer must preceded by a write in the page buffer with 0xFFFF_FFFF content at any address in the page. 6.3 6.3.1 Rev. A Device 1. JTAGID is wrong The JTAGID reads 0x021DF03F for all devices. Fix/Workaround None. 6.3.2 FLASHCDW 1. General-purpose fuse programming does not work The general-purpose fuses cannot be programmed and are stuck at 1. Please refer to the Fuse Settings chapter in the FLASHCDW for more information about what functions are affected. Fix/Workaround None. 2. Set Security Bit command does not work The Set Security Bit (SSB) command of the FLASHCDW does not work. The device cannot be locked from external JTAG, aWire, or other debug accesses. Fix/Workaround None. 3. Flash programming time is longer than specified 36 32142DS–06/2013 ATUC64/128/256L3/4U The flash programming time is now: Table 6-1. Flash Characteristics Symbol Parameter TFPP Page programming time TFPE Page erase time TFFP Fuse programming time TFEA Full chip erase time (EA) TFCE JTAG chip erase time (CHIP_ERASE) Conditions Min Typ Max Unit 7.5 7.5 fCLK_HSB= 50MHz 1 ms 9 fCLK_HSB= 115kHz 250 Fix/Workaround None. 4. Power Manager 5. Clock Failure Detector (CFD) can be issued while turning off the CFD While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will change the main clock source to RCSYS. Fix/Workaround Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch back to original main clock source. Solution 2: Only turn off the CFD while running the main clock on RCSYS. 6. Sleepwalking in idle and frozen sleep mode will mask all other PB clocks If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walking, all PB clocks will be masked except the PB clock to the sleepwalking module. Fix/Workaround Mask all clock requests in the PM.PPCR register before going into idle or frozen mode. 2. Unused PB clocks are running Three unused PBA clocks are enabled by default and will cause increased active power consumption. Fix/Workaround Disable the clocks by writing zeroes to bits [27:25] in the PBA clock mask register. 6.3.3 SCIF 1. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it: - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as one - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. 2. PLL lock might not clear after disable 37 32142DS–06/2013 ATUC64/128/256L3/4U Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator may not go back to zero after the PLL oscillator has been disabled. This can cause the propagation of clock signals with the wrong frequency to parts of the system that use the PLL clock. Fix/Workaround PLL must be turned off before entering STOP, DEEPSTOP or STATIC sleep modes. If PLL has been turned off, a delay of 30us must be observed after the PLL has been enabled again before the SCIF.PLL0LOCK bit can be used as a valid indication that the PLL is locked. 3. PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero. 4. RCSYS is not calibrated The RCSYS is not calibrated and will run faster than 115.2kHz. Frequencies around 150kHz can be expected. Fix/Workaround If a known clock source is available the RCSYS can be runtime calibrated by using the frequency meter (FREQM) and tuning the RCSYS by writing to the RCCR register in SCIF. 5. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any location in the SCIF memory range. Fix/Workaround None. 6.3.4 WDT 1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will issue a Watchdog reset If the WDT counter is cleared in the second half of the timeout period, the WDT will immediately issue a Watchdog reset. Fix/Workaround Use twice as long timeout period as needed and clear the WDT counter within the first half of the timeout period. If the WDT counter is cleared after the first half of the timeout period, you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time before the reset will be twice as long as needed. 2. WDT Control Register does not have synchronization feedback When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN), Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchronizer is started to propagate the values to the WDT clcok domain. This synchronization takes a finite amount of time, but only the status of the synchronization of the EN bit is reflected back to the user. Writing to the synchronized fields during synchronization can lead to undefined behavior. Fix/Workaround -When writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the WDT peripheral bus clock and the selected WDT clock source. -When doing writes that changes the EN bit, the EN bit can be read back until it reflects the written value. 38 32142DS–06/2013 ATUC64/128/256L3/4U 6.3.5 GPIO 1. Clearing Interrupt flags can mask other interrupts When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening in the same clock cycle will not be registered. Fix/Workaround Read the PVR register of the port before and after clearing the interrupt to see if any pin change has happened while clearing the interrupt. If any change occurred in the PVR between the reads, they must be treated as an interrupt. 6.3.6 SPI 1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 2. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 3. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 6. SPI RDR.PCS is not correct The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not correctly indicate the value on the NPCS pins at the end of a transfer. Fix/Workaround Do not use the PCS field of the SPI RDR. 39 32142DS–06/2013 ATUC64/128/256L3/4U 6.3.7 TWI 1. TWIS may not wake the device from sleep mode If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condition, the CPU may not wake upon a TWIS address match. The request is NACKed. Fix/Workaround When using the TWI address match to wake the device from sleep, do not switch to sleep modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus events. 2. SMBALERT bit may be set after reset The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after system reset. Fix/Workaround After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer. 3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. 4. TWIS stretch on Address match error When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD at the same time. This can cause a TWI timing violation. Fix/Workaround None. 5. TWIM TWALM polarity is wrong The TWALM signal in the TWIM is active high instead of active low. Fix/Workaround Use an external inverter to invert the signal going into the TWIM. When using both TWIM and TWIS on the same pins, the TWALM cannot be used. 6.3.8 PWMA 1. The SR.READY bit cannot be cleared by writing to SCR.READY The Ready bit in the Status Register will not be cleared when writing a one to the corresponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is set. Fix/Workaround Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Status Register before enabling the interrupt. 6.3.9 TC 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. 40 32142DS–06/2013 ATUC64/128/256L3/4U Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 6.3.10 ADCIFB 1. ADCIFB DMA transfer does not work with divided PBA clock DMA requests from the ADCIFB will not be performed when the PBA clock is slower than the HSB clock. Fix/Workaround Do not use divided PBA clock when the PDCA transfers from the ADCIFB. 6.3.11 CAT 1. CAT QMatrix sense capacitors discharged prematurely At the end of a QMatrix burst charging sequence that uses different burst count values for different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the peripheral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency. This results in premature loss of charge from the sense capacitors and thus increased variability of the acquired count values. Fix/Workaround Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register. 2. Autonomous CAT acquisition must be longer than AST source clock period When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST source clock is larger than one CAT acquisition. One AST clock period after the AST trigger, the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely, ruining the result. Fix/Workaround Always ensure that the ATCFG1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the AST source clock. 3. CAT consumes unnecessary power when disabled or when autonomous touch not used A CAT prescaler controlled by the ATCFG0.DIV field will be active even when the CAT module is disabled or when the autonomous touch feature is not used, thereby causing unnecessary power consumption. Fix/Workaround If the CAT module is not used, disable the CLK_CAT clock in the PM module. If the CAT module is used but the autonomous touch feature is not used, the power consumption of the CAT module may be reduced by writing 0xFFFF to the ATCFG0.DIV field. 4. CAT module does not terminate QTouch burst on detect The CAT module does not terminate a QTouch burst when the detection voltage is reached on the sense capacitor. This can cause the sense capacitor to be charged more than necessary. Depending on the dielectric absorption characteristics of the capacitor, this can lead to unstable measurements. Fix/Workaround Use the minimum possible value for the MAX field in the ATCFG1, TG0CFG1, and TG1CFG1 registers. 41 32142DS–06/2013 ATUC64/128/256L3/4U 6.3.12 aWire 1. aWire MEMORY_SPEED_REQUEST command does not return correct CV The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to the formula in the aWire Debug Interface chapter. Fix/Workaround Issue a dummy read to address 0x100000000 before issuing the MEMORY_SPEED_REQUEST command and use this formula instead: 7f aw f sab = ---------------CV – 3 6.3.13 Flash 1. Corrupted data in flash may happen after flash page write operations After a flash page write operation from an external in situ programmer, reading (data read or code fetch) in flash may fail. This may lead to an exception or to others errors derived from this corrupted read access. Fix/Workaround Before any flash page write operation, each write in the page buffer must preceded by a write in the page buffer with 0xFFFF_FFFF content at any address in the page. 6.3.14 I/O Pins 1. PA05 is not 3.3V tolerant. PA05 should be grounded on the PCB and left unused if VDDIO is above 1.8V. Fix/Workaround None. 2. No pull-up on pins that are not bonded PB13 to PB27 are not bonded on UC3L0256/128, but has no pull-up and can cause current consumption on VDDIO/VDDIN if left undriven. Fix/Workaround Enable pull-ups on PB13 to PB27 by writing 0x0FFFE000 to the PUERS1 register in the GPIO. 3. PA17 has low ESD tolerance PA17 only tolerates 500V ESD pulses (Human Body Model). Fix/Workaround Care must be taken during manufacturing and PCB design. 42 32142DS–06/2013 ATUC64/128/256L3/4U 7. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 7.1 7.2 7.3 Rev. D – 06/2013 1. Updated the datasheet with a new ATmel blue logo and the last page. 2. Added Flash errata. Rev. C – 01/2012 1. Description: DFLL frequency is 20 to 150MHz, not 40 to 150MHz. 2. Block Diagram: GCLK_IN is input, not output. CAT SMP corrected from I/O to output. SPI NPCS corrected from output to I/O. 3, Package and Pinout: EXTINT0 in Signal Descriptions table is NMI. 4, Supply and Startup Considerations: In 1.8V single supply mode figure, the input voltage is 1.62-1.98V, not 1.98-3.6V. “On system start-up, the DFLL is disabled” is replaced by “On system start-up, all high-speed clocks are disabled”. 5, ADCIFB: PRND signal removed from block diagram. 6, Electrical Charateristics: Added 64-pin package information to I/O Pin Characteristics tables and Digital Clock Characteristics table. 7, Mechanical Characteristics: QFN48 Package Drawing updated. Note that the package drawing for QFN48 is correct in datasheet rev A, but wrong in rev B. Added notes to package drawings. 8. Summary: Removed Programming and Debugging chapter, added Processor and Architecture chapter. Rev. B – 12/2011 1. 7.4 JTAG Data Registers subchapter added in the Programming and Debugging chapter, containing JTAG IDs. Rev. A – 12/2011 1. Initial revision. 43 32142DS–06/2013 ATUC64/128/256L3/4U Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 2.1 Block Diagram ...................................................................................................5 2.2 Configuration Summary .....................................................................................6 Package and Pinout ................................................................................. 7 3.1 Package .............................................................................................................7 3.2 See Section 3.3 for a description of the various peripheral signals. ................12 3.3 Signal Descriptions ..........................................................................................15 3.4 I/O Line Considerations ...................................................................................18 Mechanical Characteristics ................................................................... 21 4.1 Thermal Considerations ..................................................................................21 4.2 Package Drawings ...........................................................................................22 4.3 Soldering Profile ..............................................................................................27 5 Ordering Information ............................................................................. 28 6 Errata ....................................................................................................... 30 7 6.1 Rev. C ..............................................................................................................30 6.2 Rev. B ..............................................................................................................32 6.3 Rev. A ..............................................................................................................36 Datasheet Revision History .................................................................. 43 7.1 Rev. D – 06/2013 .............................................................................................43 7.2 Rev. C – 01/2012 .............................................................................................43 7.3 Rev. B – 12/2011 .............................................................................................43 7.4 Rev. A – 12/2011 .............................................................................................43 Table of Contents....................................................................................... i i 32142DS–06/2013 Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.com Tel: (+852) 2245-6100 Fax: (+49) 89-3194621 Fax: (+81) (3) 6417-0370 Fax: (+852) 2722-1369 © 2013 Atmel Corporation. All rights reserved. / Rev.: 32142DS–AVR32–06/2013 Atmel ®, logo and combinations thereof, AVR ®, picoPower®, QTouch ®, AKS ® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.