Features • Single 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible – Supports SPI Modes 0 and 3 • 70 MHz Maximum Clock Frequency • Flexible, Uniform Erase Architecture • • • • • • • • • • – 4-Kbyte Blocks – 32-Kbyte Blocks – 64-Kbyte Blocks – Full Chip Erase Individual Sector Protection with Global Protect/Unprotect Feature – Sixty-Four 64-Kbyte Physical Sectors Hardware Controlled Locking of Protected Sectors Flexible Programming – Byte/Page Program (1 to 256 Bytes) Automatic Checking and Reporting of Erase/Program Failures JEDEC Standard Manufacturer and Device ID Read Methodology Low Power Dissipation – 7 mA Active Read Current (Typical) – 15 µA Deep Power-Down Current (Typical) Endurance: 100,000 Program/Erase Cycles Data Retention: 20 Years Complies with Full Industrial Temperature Range Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (200-mil wide) – 16-lead SOIC (300-mil wide) 1. Description 32-megabit 2.7-volt Minimum SPI Serial Flash Memory AT25DF321 For New Designs Use AT25DF321A The AT25DF321 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF321, with its erase granularity as small as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The physical sectoring and the erase block sizes of the AT25DF321 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. 3669B–DFLASH–6/09 The AT25DF321 also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. In addition to individual sector protection capabilities, the AT25DF321 incorporates Global Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming. Specifically designed for use in 3-volt systems, the AT25DF321 supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. 2 AT25DF321 3669B–DFLASH–6/09 AT25DF321 2. Pin Descriptions and Pinouts Table 2-1. Symbol Pin Descriptions Name and Function Asserted State Type Low Input CS CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. SCK SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. Input SI SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. Input SO SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. WP WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to “Protection Commands and Features” on page 12 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. Low Input HOLD HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to “Hold” on page 27 for additional details on the Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible. Low Input Output VCC DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. Power GND GROUND: The ground reference for the power supply. GND should be connected to the system ground. Power 3 3669B–DFLASH–6/09 Figure 2-1. CS SO WP GND 8-SOIC Top View 1 2 3 4 8 7 6 5 Figure 2-2. VCC HOLD SCK SI HOLD VCC NC NC NC NC CS SO 16-SOIC Top View 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SCK SI NC NC NC NC GND WP 3. Block Diagram CONTROL AND PROTECTION LOGIC CS SI SO WP HOLD SRAM DATA BUFFER INTERFACE CONTROL AND LOGIC Y-DECODER ADDRESS LATCH SCK I/O BUFFERS AND LATCHES X-DECODER Y-GATING FLASH MEMORY ARRAY 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF321 can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations. The size of the physical sectors is optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the breakdown of each physical sector. 4 AT25DF321 3669B–DFLASH–6/09 AT25DF321 Memory Architecture Diagram Block Erase Detail 64KB 32KB Block Erase Block Erase (D8h Command) (52h Command) 32KB 64KB (Sector 63) 64KB 32KB 32KB 64KB (Sector 62) 64KB ••• ••• ••• 32KB 32KB 64KB (Sector 0) 64KB 32KB 4KB Block Erase (20h Command) 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB Block Address Range 3FFFFFh 3FEFFFh 3FDFFFh 3FCFFFh 3FBFFFh 3FAFFFh 3F9FFFh 3F8FFFh 3F7FFFh 3F6FFFh 3F5FFFh 3F4FFFh 3F3FFFh 3F2FFFh 3F1FFFh 3F0FFFh 3EFFFFh 3EEFFFh 3EDFFFh 3ECFFFh 3EBFFFh 3EAFFFh 3E9FFFh 3E8FFFh 3E7FFFh 3E6FFFh 3E5FFFh 3E4FFFh 3E3FFFh 3E2FFFh 3E1FFFh 3E0FFFh – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 3FF000h 3FE000h 3FD000h 3FC000h 3FB000h 3FA000h 3F9000h 3F8000h 3F7000h 3F6000h 3F5000h 3F4000h 3F3000h 3F2000h 3F1000h 3F0000h 3EF000h 3EE000h 3ED000h 3EC000h 3EB000h 3EA000h 3E9000h 3E8000h 3E7000h 3E6000h 3E5000h 3E4000h 3E3000h 3E2000h 3E1000h 3E0000h 00FFFFh 00EFFFh 00DFFFh 00CFFFh 00BFFFh 00AFFFh 009FFFh 008FFFh 007FFFh 006FFFh 005FFFh 004FFFh 003FFFh 002FFFh 001FFFh 000FFFh – – – – – – – – – – – – – – – – 00F000h 00E000h 00D000h 00C000h 00B000h 00A000h 009000h 008000h 007000h 006000h 005000h 004000h 003000h 002000h 001000h 000000h ••• Internal Sectoring for Sector Protection Function Page Program Detail 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 1-256 Byte Page Program (02h Command) 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes Page Address Range 3FFFFFh 3FFEFFh 3FFDFFh 3FFCFFh 3FFBFFh 3FFAFFh 3FF9FFh 3FF8FFh 3FF7FFh 3FF6FFh 3FF5FFh 3FF4FFh 3FF3FFh 3FF2FFh 3FF1FFh 3FF0FFh 3FEFFFh 3FEEFFh 3FEDFFh 3FECFFh 3FEBFFh 3FEAFFh 3FE9FFh 3FE8FFh – – – – – – – – – – – – – – – – – – – – – – – – 3FFF00h 3FFE00h 3FFD00h 3FFC00h 3FFB00h 3FFA00h 3FF900h 3FF800h 3FF700h 3FF600h 3FF500h 3FF400h 3FF300h 3FF200h 3FF100h 3FF000h 3FEF00h 3FEE00h 3FED00h 3FEC00h 3FEB00h 3FEA00h 3FE900h 3FE800h 0017FFh 0016FFh 0015FFh 0014FFh 0013FFh 0012FFh 0011FFh 0010FFh 000FFFh 000EFFh 000DFFh 000CFFh 000BFFh 000AFFh 0009FFh 0008FFh 0007FFh 0006FFh 0005FFh 0004FFh 0003FFh 0002FFh 0001FFh 0000FFh – – – – – – – – – – – – – – – – – – – – – – – – 001700h 001600h 001500h 001400h 001300h 001200h 001100h 001000h 000F00h 000E00h 000D00h 000C00h 000B00h 000A00h 000900h 000800h 000700h 000600h 000500h 000400h 000300h 000200h 000100h 000000h ••• Figure 4-1. 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 5 3669B–DFLASH–6/09 5. Device Operation The AT25DF321 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25DF321 via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF321 supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. Figure 5-1. SPI Mode 0 and 3 CS SCK SI MSB SO LSB MSB LSB 6. Commands and Addressing A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with the most significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25DF321 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0. Since the upper address limit of the AT25DF321 memory array is 3FFFFFh, address bits A23-A22 are always ignored by the device. 6 AT25DF321 3669B–DFLASH–6/09 AT25DF321 Table 6-1. Command Listing Command Opcode Address Bytes Dummy Bytes Data Bytes Read Commands Read Array 0Bh 0000 1011 3 1 1+ Read Array (Low Frequency) 03h 0000 0011 3 0 1+ Block Erase (4-KBytes) 20h 0010 0000 3 0 0 Block Erase (32-KBytes) 52h 0101 0010 3 0 0 Block Erase (64-KBytes) D8h 1101 1000 3 0 0 60h 0110 0000 0 0 0 C7h 1100 0111 0 0 0 02h 0000 0010 3 0 1+ Write Enable 06h 0000 0110 0 0 0 Write Disable 04h 0000 0100 0 0 0 Protect Sector 36h 0011 0110 3 0 0 Unprotect Sector 39h 0011 1001 3 0 0 Program and Erase Commands Chip Erase Byte/Page Program (1 to 256 Bytes) Protection Commands Global Protect/Unprotect Read Sector Protection Registers Use Write Status Register command 3Ch 0011 1100 3 0 1+ Read Status Register 05h 0000 0101 0 0 1+ Write Status Register 01h 0000 0001 0 0 1 Read Manufacturer and Device ID 9Fh 1001 1111 0 0 1 to 4 Deep Power-Down B9h 1011 1001 0 0 0 Resume from Deep Power-Down ABh 1010 1011 0 0 0 Status Register Commands Miscellaneous Commands 7 3669B–DFLASH–6/09 7. Read Commands 7.1 Read Array The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the SCK signal once the initial starting address has been specified. The device incorporates an internal address counter that automatically increments on every clock cycle. Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the device. The 0Bh opcode can be used at any SCK frequency up to the maximum specified by fSCK. The 03h opcode can be used for lower frequency read operations up to the maximum specified by fRDLF. To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. If the 0Bh opcode is used, then one don’t care byte must also be clocked in after the three address bytes. After the three address bytes (and the one don’t care byte if using opcode 0Bh) have been clocked in, additional clock cycles will result in serial data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array. Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. Read Array – 0Bh Opcode CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SCK OPCODE SI 0 0 0 0 1 ADDRESS BITS A23-A0 0 1 1 MSB A A A A A A A DON'T CARE A A MSB X X X X X X X X MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D D D D MSB Figure 7-2. D D D D MSB Read Array – 03h Opcode CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A23-A0 0 MSB 1 1 A A A A A A A A A MSB DATA BYTE 1 SO HIGH-IMPEDANCE D MSB 8 D D D D D D D D D MSB AT25DF321 3669B–DFLASH–6/09 AT25DF321 8. Program and Erase Commands 8.1 Byte/Page Program The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations. An erased memory location is one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable command must have been previously issued to the device (see Write Enable command description) to set the Write Enable Latch (WEL) bit of the Status Register to a logical “1” state. To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not all 0), then special circumstances regarding which memory locations will be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) will be unaffected and will not change. In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting address specified by A23-A0 and the number of complete data bytes sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be altered. The programming of the data bytes is internally self-timed and should take place in a time of tPP. The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. In addition, if the address specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector” on page 13), then the Byte/Page Program command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, or because the memory location to be programmed is protected. While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tPP time to determine if the data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register. 9 3669B–DFLASH–6/09 Figure 8-1. Byte Program CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A23-A0 0 1 0 MSB A A A A A A A A D MSB D D D D D D D MSB HIGH-IMPEDANCE SO Figure 8-2. A DATA IN Page Program CS 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A23-A0 0 MSB SO 8.2 1 0 A MSB A A A A A DATA IN BYTE 1 D MSB D D D D D D DATA IN BYTE n D D D D D D D D D MSB HIGH-IMPEDANCE Block Erase A block of 4K-, 32K-, or 64K-bytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4K-byte erase, an opcode of 52h is used for a 32K-byte erase, and an opcode of D8h is used for a 64K-byte erase. Before a Block Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state. To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the 4K-, 32K-, or 64K-byte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally self-timed and should take place in a time of tBLKE. Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. Therefore, for a 4K-byte erase, address bits A11-A0 will be ignored by the device and their values can be either a logical “1” or “0”. For a 32K-byte erase, address bits A14-A0 will be ignored, and for a 64K-byte erase, address bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. 10 AT25DF321 3669B–DFLASH–6/09 AT25DF321 If the address specified by A23-A0 points to a memory location within a sector that is in the protected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete address being sent or because a memory location within the region to be erased is protected. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent erasing algorithm that can detect when a byte location fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in the Status Register. Figure 8-3. Block Erase CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE SI C C C C C C MSB SO 8.3 ADDRESS BITS A23-A0 C C A A A A A A A A A A A A MSB HIGH-IMPEDANCE Chip Erase The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state. Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a time of tCHPE. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if any sector of the memory array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if a sector is in the protected state. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Regis11 3669B–DFLASH–6/09 ter be polled rather than waiting the tCHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent erasing algorithm that can detect when a byte location fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in the Status Register. Figure 8-4. Chip Erase CS 0 1 2 3 4 5 6 7 SCK OPCODE SI C C C C C C C C MSB SO HIGH-IMPEDANCE 9. Protection Commands and Features 9.1 Write Enable The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state. The WEL bit must be set before a program, erase, Protect Sector, Unprotect Sector, or Write Status Register command can be executed. This makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the issuance of one of these commands, then the command will not be executed. To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. Write Enable CS 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 0 0 0 0 1 1 0 MSB SO 12 HIGH-IMPEDANCE AT25DF321 3669B–DFLASH–6/09 AT25DF321 9.2 Write Disable The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical “0” state. With the WEL bit reset, all program, erase, Protect Sector, Unprotect Sector, and Write Status Register commands will not be executed. The Write Disable command is also used to exit the Sequential Program Mode. Other conditions can also cause the WEL bit to be reset; for more details, refer to the WEL bit section of the Status Register description on page 21. To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-2. Write Disable CS 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 0 0 0 0 1 0 0 MSB SO 9.3 HIGH-IMPEDANCE Protect Sector Every physical sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector. Upon device power-up or after a device reset, each Sector Protection Register will default to the logical “1” state indicating that all sectors are protected and cannot be programmed or erased. Issuing the Protect Sector command to a particular sector address will set the corresponding Sector Protection Register to the logical “1” state. The following table outlines the two states of the Sector Protection Registers. Table 9-1. Value Sector Protection Register Values Sector Protection Status 0 Sector is unprotected and can be programmed and erased. 1 Sector is protected and cannot be programmed or erased. This is the default state. Before the Protect Sector command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the Protect Sector command, the CS pin must first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designating any address within the sector to be locked. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the physical sector addressed by A2313 3669B–DFLASH–6/09 A0 will be set to the logical “1” state, and the sector itself will then be protected from program and erase operations. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state. The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0”. As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status Register (please refer to “Status Register Commands” on page 20 for more details). If the Sector Protection Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-3. Protect Sector CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE SI 0 0 1 1 0 ADDRESS BITS A23-A0 1 MSB SO 9.4 1 0 A A A A A A A A A A A A MSB HIGH-IMPEDANCE Unprotect Sector Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector Protection Register to the logical “0” state (see Table 9-1 on page 13 for Sector Protection Register values). Every physical sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector. Before the Unprotect Sector command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the Unprotect Sector command, the CS pin must first be asserted and the opcode of 39h must be clocked into the device. After the opcode has been clocked in, the three address bytes designating any address within the sector to be unlocked must be clocked in. Any additional data clocked into the device after the address bytes will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the sector addressed by A23-A0 will be reset to the logical “0” state, and the sector itself will be unprotected. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state. The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0”. 14 AT25DF321 3669B–DFLASH–6/09 AT25DF321 As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status Register (please refer to “Status Register Commands” on page 20 for more details). If the Sector Protection Registers are locked, then any attempts to issue the Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-4. Unprotect Sector CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE SI 0 0 1 1 1 ADDRESS BITS A23-A0 0 MSB SO 9.5 0 1 A A A A A A A A A A A A MSB HIGH-IMPEDANCE Global Protect/Unprotect The Global Protect and Global Unprotect features can work in conjunction with the Protect Sector and Unprotect Sector functions. For example, a system can globally protect the entire memory array and then use the Unprotect Sector command to individually unprotect certain sectors and individually reprotect them later by using the Protect Sector command. Likewise, a system can globally unprotect the entire memory array and then individually protect certain sectors as needed. Performing a Global Protect or Global Unprotect is accomplished by writing a certain combination of data to the Status Register using the Write Status Register command (see “Write Status Register” section on page 22 for command execution details). The Write Status Register command is also used to modify the SPRL (Sector Protection Registers Locked) bit to control hardware and software locking. To perform a Global Protect, the appropriate WP pin and SPRL conditions must be met and the system must write a logical “1” to bits 5, 4, 3, and 2 of the Status Register. Conversely, to perform a Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits 5, 4, 3, and 2 of the Status Register. Table 9-2 details the conditions necessary for a Global Protect or Global Unprotect to be performed. 15 3669B–DFLASH–6/09 Table 9-2. WP State Valid SPRL and Global Protect/Unprotect Conditions Current SPRL Value New Write Status Register Data Bit 76543210 0x0000xx 0x0001xx 0x1110xx 0x1111xx 0 New SPRL Value Protection Operation Global Unprotect – all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect – all Sector Protection Registers set to 1 0 0 0 0 0 Global Unprotect – all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect – all Sector Protection Registers set to 1 1 1 1 1 1 0 1x0000xx 1x0001xx 1x1110xx 1x1111xx No change to the current protection level. All sectors currently protected will remain protected and all sectors currently unprotected will remain unprotected. 0 1 xxxxxxxx The Sector Protection Registers are hard-locked and cannot be changed when the WP pin is LOW and the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur. In addition, the SPRL bit cannot be changed (the WP pin must be HIGH in order to change SPRL back to a 0). 0x0000xx 0x0001xx Global Unprotect – all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect – all Sector Protection Registers set to 1 0 0 0 0 0 Global Unprotect – all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect – all Sector Protection Registers set to 1 1 1 1 1 1 No change to the current protection level. All sectors currently protected will remain protected, and all sectors currently unprotected will remain unprotected. 0 0 0 0 0 0x1110xx 0x1111xx 1 0 1x0000xx 1x0001xx 1x1110xx 1x1111xx 0x0000xx 0x0001xx 0x1110xx 0x1111xx 1 1 1x0000xx 1x0001xx 1x1110xx 1x1111xx The Sector Protection Registers are soft-locked and cannot be changed when the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur. However, the SPRL bit can be changed back to a 0 from a 1 since the WP pin is HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from a 1 to a 0. 1 1 1 1 1 Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection Registers are not locked), then writing a 00h to the Status Register will perform a Global Unprotect without changing the state of the SPRL bit. Similarly, writing a 7Fh to the Status Register will perform a Global Protect and keep the SPRL bit in the logical “0” state. The SPRL bit can, of course, be changed to a logical “1” by writing an FFh if software-locking or hardware-locking is desired along with the Global Protect. 16 AT25DF321 3669B–DFLASH–6/09 AT25DF321 If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the system can simply write a 0Fh to the Status Register to change the SPRL bit from a logical “1” to a logical “0” provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from a logical “0” to a logical “1” without affecting the current sector protection status (no changes will be made to the Sector Protection Registers). When writing to the Status Register, bits 5, 4, 3, and 2 will not actually be modified but will be decoded by the device for the purposes of the Global Protect and Global Unprotect functions. Only bit 7, the SPRL bit, will actually be modified. Therefore, when reading the Status Register, bits 5, 4, 3, and 2 will not reflect the values written to them but will instead indicate the status of the WP pin and the sector protection status. Please refer to the “Read Status Register” section and Table 10-1 on page 20 for details on the Status Register format and what values can be read for bits 5, 4, 3, and 2. 9.6 Read Sector Protection Registers The Sector Protection Registers can be read to determine the current software protection status of each sector. Reading the Sector Protection Registers, however, will not determine the status of the WP pin. To read the Sector Protection Register for a particular sector, the CS pin must first be asserted and the opcode of 3Ch must be clocked in. Once the opcode has been clocked in, three address bytes designating any address within the sector must be clocked in. After the last address byte has been clocked in, the device will begin outputting data on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denote the value of the appropriate Sector Protection Register Table 9-3. Read Sector Protection Register – Output Data Output Data Sector Protection Register Value 00h Sector Protection Register value is 0 (sector is unprotected). FFh Sector Protection Register value is 1 (sector is protected). Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are software protected (please refer to “Status Register Commands” on page 20 for more details). 17 3669B–DFLASH–6/09 Figure 9-5. Read Sector Protection Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 1 1 1 ADDRESS BITS A23-A0 1 MSB 0 0 A A A A A A A A A MSB DATA BYTE SO HIGH-IMPEDANCE D MSB 9.7 D D D D D D D D D MSB Protected States and the Write Protect (WP) Pin The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware locking to be active, two conditions must be met – the WP pin must be asserted and the SPRL bit must be in the logical “1” state. When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit itself is also locked. Therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be locked in the unprotected state. These states cannot be changed as long as hardware locking is active, so the Protect Sector, Unprotect Sector, and Write Status Register commands will be ignored. In order to modify the protection status of a sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be reset back to the logical “0” state using the Write Status Register command. When resetting the SPRL bit back to a logical “0”, it is not possible to perform a Global Protect or Global Unprotect at the same time since the Sector Protection Registers remain soft-locked until after the Write Status Register command has been executed. If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”, the only way to reset the bit back to the logical “0” state is to power-cycle or reset the device. This allows a system to power-up with all sectors software protected but not hardware locked. Therefore, sectors can be unprotected and protected as needed and then hardware locked at a later time by simply setting the SPRL bit in the Status Register. When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bit in the Status Register can still be set to a logical “1” to lock the Sector Protection Registers. This provides a software locking ability to prevent erroneous Protect Sector or Unprotect Sector commands from being processed. When changing the SPRL bit to a logical “1” from a logical “0”, it is also possible to perform a Global Protect or Global Unprotect at the same time by writing the appropriate values into bits 5, 4, 3, and 2 of the Status Register. 18 AT25DF321 3669B–DFLASH–6/09 AT25DF321 The tables below detail the various protection and locking states of the device. Table 9-4. Software Protection Register States WP Sector Protection Register n(1) Sector n(1) 0 Unprotected 1 Protected X (Don't Care) Note: 1. “n” represents a sector number Table 9-5. WP 0 0 1 1 Hardware and Software Locking SPRL Locking 0 1 Hardware Locked 0 1 Software Locked SPRL Change Allowed Sector Protection Registers Can be modified from 0 to 1 Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed. Locked Locked in current state. Protect and Unprotect Sector commands will be ignored. Global Protect and Unprotect cannot be performed. Can be modified from 0 to 1 Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed. Can be modified from 1 to 0 Locked in current state. Protect and Unprotect Sector commands will be ignored. Global Protect and Unprotect cannot be performed. 19 3669B–DFLASH–6/09 10. Status Register Commands 10.1 Read Status Register The Status Register can be read to determine the device’s ready/busy status, as well as the status of many other functions such as Hardware Locking and Software Protection. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the device. After the last bit of the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin during every subsequent clock cycle. After the last bit (bit 0) of the Status Register has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the CS pin remains asserted and the SCK pin is being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence will output new data. Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 10-1. Bit Status Register Format (1) 7 Name SPRL Sector Protection Registers Locked Type(2) RES Reserved for future use R 5 EPE Erase/Program Error R 3:2 1 0 Notes: WPP SWP WEL RDY/BSY Write Protect (WP) Pin Status Software Protection Status Write Enable Latch Status Ready/Busy Status 0 Sector Protection Registers are unlocked (default). 1 Sector Protection Registers are locked. 0 Reserved for future use. 0 Erase or program operation was successful. 1 Erase or program error detected. 0 WP is asserted. 1 WP is deasserted. 00 All sectors are software unprotected (all Sector Protection Registers are 0). 01 Some sectors are software protected. Read individual Sector Protection Registers to determine which sectors are protected. 10 Reserved for future use. 11 All sectors are software protected (all Sector Protection Registers are 1 – default). 0 Device is not write enabled (default). 1 Device is write enabled. 0 Device is ready. 1 Device is busy with an internal operation. R/W 6 4 Description R R R R 1. Only bit 7 of the Status Register will be modified when using the Write Status Register command. 2. R/W = Readable and writeable R = Readable only 20 AT25DF321 3669B–DFLASH–6/09 AT25DF321 10.1.1 SPRL Bit The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL bit is in the logical “1” state, all Sector Protection Registers are locked and cannot be modified with the Protect Sector and Unprotect Sector commands (the device will ignore these commands). In addition, the Global Protect and Global Unprotect features cannot be performed. Any sectors that are presently protected will remain protected, and any sectors that are presently unprotected will remain unprotected. When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked and can be modified (the Protect Sector and Unprotect Sector commands, as well as the Global Protect and Global Unprotect features, will be processed as normal). The SPRL bit defaults to the logical “0” state after a power-up or a device reset. The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then the SPRL bit may only be changed from a logical “0” (Sector Protection Registers are unlocked) to a logical “1” (Sector Protection Registers are locked). In order to reset the SPRL bit back to a logical “0” using the Write Status Register command, the WP pin will have to first be deasserted. The SPRL bit is the only bit of the Status Register that can be user modified via the Write Status Register command. 10.1.2 WPP Bit The WPP bit can be read to determine if the WP pin has been asserted or not. 10.1.3 EPE Bit The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the logical “1” state. The EPE bit will not be set if an erase or program operation aborts for any reason such as an attempt to erase or program a protected region or if the WEL bit is not set prior to an erase or program operation. The EPE bit will be updated after every erase and program operation. 10.1.4 SWP Bits The SWP bits provide feedback on the software protection status for the device. There are three possible combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using the Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Protection Registers can be read with the Read Sector Protection Registers command to determine which sectors are in fact protected. 10.1.5 WEL Bit The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a device power-up or reset. In addition, the WEL bit will be reset to the logical “0” state automatically under the following conditions: 21 3669B–DFLASH–6/09 • Write Disable operation completes successfully • Write Status Register operation completes successfully or aborts • Protect Sector operation completes successfully or aborts • Unprotect Sector operation completes successfully or aborts • Byte/Page Program operation completes successfully or aborts • Block Erase operation completes successfully or aborts • Chip Erase operation completes successfully or aborts If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register command must have been clocked into the device. 10.1.6 RDY/BSY Bit The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a logical “0”. Figure 10-1. Read Status Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCK OPCODE SI 0 0 0 0 0 1 0 1 MSB STATUS REGISTER DATA SO HIGH-IMPEDANCE D MSB 10.2 D D D D D D D STATUS REGISTER DATA D MSB D D D D D D D D D MSB Write Status Register The Write Status Register command is used to modify the SPRL bit of the Status Register and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Register command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the Write Status Register command, the CS pin must first be asserted and the opcode of 01h must be clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value, a don't care bit, four data bits to denote whether a Global Protect or Unprotect should be performed, and two additional don’t care bits (see Table 10-2). Any additional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the SPRL bit in the Status Register will be modified and the WEL bit in the Status Register will be reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before the Write Status Register command was executed (the prior state of the SPRL bit) will determine whether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “Global Protect/Unprotect” section on page 15 for more details. 22 AT25DF321 3669B–DFLASH–6/09 AT25DF321 The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the SPRL bit will not change, no potential Global Protect or Unprotect will be performed, and the WEL bit in the Status Register will be reset back to the logical “0” state. If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register command will be ignored, and the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 10-2. Write Status Register Format Bit 7 Bit 6 SPRL X Bit 5 Bit 4 Bit 3 Bit 2 Global Protect/Unprotect Bit 1 Bit 0 X X Figure 10-2. Write Status Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK OPCODE SI 0 0 0 0 0 STATUS REGISTER IN 0 MSB SO 0 1 D X D D D D X X MSB HIGH-IMPEDANCE 11. Other Commands and Functions 11.1 Read Manufacturer and Device ID Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the vendor specific Extended Device Information. To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length, which will be 00h indicating that no Extended Device Information follows. After the Extended Device Information String Length byte is output, the SO pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the SO pin and no data will be output. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional. 23 3669B–DFLASH–6/09 Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 11-1. Manufacturer and Device ID Information Byte No. Data Type Value 1 Manufacturer ID 1Fh 2 Device ID (Part 1) 47h 3 Device ID (Part 2) 00h 4 Extended Device Information String Length 00h Table 11-2. Manufacturer and Device ID Details Data Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 Hex Value Details JEDEC Assigned Code Manufacturer ID 0 0 0 1 1 1 Family Code 1 0 0 Sub Code 0 1 0 0001 1111 (1Fh for Atmel) 47h Family Code: Density Code: 010 (AT25/26DFxxx series) 00111 (32-Mbit) 00h Sub Code: Product Version: 000 (Standard series) 00000 (Initial version) Product Version Code Device ID (Part 2) 0 JEDEC Code: Density Code Device ID (Part 1) 0 1Fh 0 0 0 0 0 0 Figure 11-1. Read Manufacturer and Device ID CS 0 6 7 8 14 15 16 22 23 24 30 31 32 38 SCK OPCODE SI SO 9Fh HIGH-IMPEDANCE Note: Each transition 24 1Fh 47h 00h 00h MANUFACTURER ID DEVICE ID BYTE 1 DEVICE ID BYTE 2 EXTENDED DEVICE INFORMATION STRING LENGTH shown for SI and SO represents one byte (8 bits) AT25DF321 3669B–DFLASH–6/09 AT25DF321 11.2 Deep Power-Down During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place the device into an even lower power consumption state called the Deep Power-Down mode. When the device is in the Deep Power-Down mode, all commands including the Read Status Register command will be ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode of B9h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of tEDPD. The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a power-cycle or a device reset. The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. Figure 11-2. Deep Power-Down CS tEDPD 0 1 2 3 4 5 6 7 SCK OPCODE SI 1 0 1 1 1 0 0 1 MSB SO HIGH-IMPEDANCE Active Current ICC Standby Mode Current Deep Power-Down Mode Current 25 3669B–DFLASH–6/09 11.3 Resume from Deep Power-Down In order exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down command must be issued. The Resume from Deep Power-Down command is the only command that the device will recognize while in the Deep Power-Down mode. To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode of ABh must be clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep PowerDown mode within the maximum time of tRDPD and return to the standby mode. After the device has returned to the standby mode, normal command operations such as Read Array can be resumed. If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode. Figure 11-3. Resume from Deep Power-Down CS tRDPD 0 1 2 3 4 5 6 7 SCK OPCODE SI 1 0 1 0 1 0 1 1 MSB SO HIGH-IMPEDANCE Active Current ICC Deep Power-Down Mode Current 26 Standby Mode Current AT25DF321 3669B–DFLASH–6/09 AT25DF321 11.4 Hold The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until it is finished. The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won't be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are asserted. While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode. To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won't end until the beginning of the next SCK low pulse. If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 11-4. Hold Mode CS SCK HOLD Hold Hold Hold 27 3669B–DFLASH–6/09 12. Electrical Specifications 12.1 Absolute Maximum Ratings* Temperature Under Bias ............................... -55C to +125C *NOTICE: Storage Temperature..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground .....................................-0.6V to +4.1V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.5V 12.2 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC and AC Operating Range AT25DF321 Operating Temperature (Case) Ind. -40C to +85C VCC Power Supply 12.3 2.7V to 3.6V DC Characteristics Symbol Parameter Condition ISB Standby Current IDPD Deep Power-Down Current ICC1 Active Current, Read Operation Min Typ Max Units CS, WP, HOLD = VCC, all inputs at CMOS levels 25 35 µA CS, WP, HOLD = VCC, all inputs at CMOS levels 15 25 µA f = 70 MHz, IOUT = 0 mA, CS = VIL, VCC = Max 11 16 f = 66 MHz, IOUT = 0 mA, CS = VIL, VCC = Max 10 15 f = 50 MHz; IOUT = 0 mA, CS = VIL, VCC = Max 9 14 f = 33 MHz, IOUT = 0 mA, CS = VIL, VCC = Max 8 12 f = 20 MHz, IOUT = 0 mA, CS = VIL, VCC = Max 7 10 12 18 mA 14 20 mA mA ICC2 Active Current, Program Operation CS = VCC, VCC = Max ICC3 Active Current, Erase Operation CS ILI Input Leakage Current VIN = CMOS levels 1 µA ILO Output Leakage Current VOUT = CMOS levels 1 µA VIL Input Low Voltage 0.3 x VCC V VIH Input High Voltage VOL Output Low Voltage IOL = 1.6 mA, VCC = Min VOH Output High Voltage IOH = -100 µA 28 = VCC, VCC = Max 0.7 x VCC V 0.4 VCC - 0.2 V V AT25DF321 3669B–DFLASH–6/09 AT25DF321 12.4 AC Characteristics Symbol Parameter fSCK Max Units Serial Clock (SCK) Frequency 70 MHz fRDLF SCK Frequency for Read Array (Low Frequency – 03h opcode) 33 MHz tSCKH SCK High Time 6.8 ns tSCKL SCK Low Time 6.8 ns tSCKR(1) SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tSCKF(1) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tCSH Chip Select High Time 50 ns tCSLS Chip Select Low Setup Time (relative to SCK) 5 ns tCSLH Chip Select Low Hold Time (relative to SCK) 5 ns tCSHS Chip Select High Setup Time (relative to SCK) 5 ns tCSHH Chip Select High Hold Time (relative to SCK) 5 ns tDS Data In Setup Time 2 ns tDH Data In Hold Time 3 ns tDIS(1) Output Disable Time 6 ns tV(2) Output Valid Time 6 ns tOH Output Hold Time 0 ns tHLS HOLD Low Setup Time (relative to SCK) 5 ns tHLH HOLD Low Hold Time (relative to SCK) 5 ns tHH HOLD High Setup Time (relative to SCK) 5 ns tHHH HOLD High Hold Time (relative to SCK) 5 ns tHLQZ(1) HOLD Low to Output High-Z 6 tHHQX(1) HOLD High to Output Low-Z 6 tWPS(1)(3) Write Protect Setup Time 20 ns tWPH(1)(3) Write Protect Hold Time 100 ns (1) Min ns Sector Protect Time (from Chip Select High) 20 ns tSECUP(1) Sector Unprotect Time (from Chip Select High) 20 ns tEDPD(1) Chip Select High to Deep Power-Down 3 µs tRDPD(1) Chip Select High to Standby Mode 3 µs tSECP Notes: 1. Not 100% tested (value guaranteed by design and characterization). 2. 15 pF load at 70 MHz, 30 pF load at 66 MHz. 3. Only applicable as a constraint for the Write Status Register command when SPRL = 1. 29 3669B–DFLASH–6/09 12.5 Program and Erase Characteristics Symbol Parameter tPP Page Program Time (256 Bytes) tBP Byte Program Time tCHPE(1) Units 1.5 5.0 ms µs 50 200 32-Kbyte 350 600 64-Kbyte 600 950 36 56 sec 200 ns Max Units Write Status Register Time Notes: 1. Not 100% tested (value guaranteed by design and characterization). 12.6 Power-Up Conditions Symbol Parameter tVCSL Minimum VCC to Chip Select Low Time tPUW Power-up Device Delay Before Program or Erase Allowed VPOR Power-On Reset Voltage 12.7 Max 4-Kbyte Chip Erase Time (1) Typ 6 Block Erase Time tBLKE tWRSR Min Min 50 1.5 ms µs 10 ms 2.5 V Input Test Waveforms and Measurement Levels AC DRIVING LEVELS 2.4V 1.5V 0.45V AC MEASUREMENT LEVEL tR, tF < 2 ns (10% to 90%) 12.8 Output Test Load DEVICE UNDER TEST 30 pF 30 AT25DF321 3669B–DFLASH–6/09 AT25DF321 13. AC Waveforms Figure 13-1. Serial Input Timing tCSH CS tCSLH tSCKL tCSLS tSCKH tCSHH tCSHS SCK tDS SI SO tDH MSB LSB MSB HIGH-IMPEDANCE Figure 13-2. Serial Output Timing CS tSCKH tSCKL tDIS SCK SI tOH tV tV SO Figure 13-3. HOLD Timing – Serial Input CS SCK tHHH tHLS tHLH tHHS HOLD SI SO HIGH-IMPEDANCE 31 3669B–DFLASH–6/09 Figure 13-4. HOLD Timing – Serial Output CS SCK tHHH tHLS tHLH tHHS HOLD SI tHLQZ tHHQX SO Figure 13-5. WP Timing for Write Status Register Command When SPRL = 1 CS tWPH tWPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE SO 32 0 0 X MSB LSB OF WRITE STATUS REGISTER DATA BYTE MSB OF NEXT OPCODE HIGH-IMPEDANCE AT25DF321 3669B–DFLASH–6/09 AT25DF321 14. Ordering Information 14.1 Green Package Options (Pb/Halide-free/RoHS Compliant) fSCK (MHz) Ordering Code Package Operation Range 70 AT25DF321-SU 8S2 70 AT25DF321-S3U 16S Industrial (-40°C to +85°C) Package Type 8S2 8-lead, 0.209" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 16S 16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 33 3669B–DFLASH–6/09 15. Packaging Information 15.1 8S2 – EIAJ SOIC C 1 E E1 L N θ TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW NOTE 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 θ 0° 2 8° 1.27 BSC 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: [email protected] 34 MAX NOM A e Notes: 1. 2. 3. 4. MIN TITLE 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) GPC STN 4/15/08 DRAWING NO. REV. 8S2 F AT25DF321 3669B–DFLASH–6/09 AT25DF321 15.2 16S – SOIC 1 N L Top View C e COMMON DIMENSIONS (Unit of Measure = mm) b SYMBOL A1 A D MIN NOM MAX A 2.35 – 2.65 A1 0.10 – 0.30 b 0.31 – 0.51 D Side View NOTE 10.30 BSC 2 E 7.50 BSC 3 H 10.30 BSC L 0.40 e C Notes: End View E H E – 1.27 4 1.27 BSC 0.20 0.33 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AA for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. L is the length of the terminal for soldering to a substrate. 11/02/05 TITLE R 2325 Orchard Parkway San Jose, CA 95131 DRAWING NO. 16S, 16-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 16S REV. A 35 3669B–DFLASH–6/09 16. Revision History Revision Level – Release Date History A – July 2007 Initial release B – June 2009 Corrected errors in datasheet. - Changed Deep Power-Down Current typical value from 4 µa to 15 µa - Changed Deep Power-Down Current maximum value from 8 µa to 25 µa 36 AT25DF321 3669B–DFLASH–6/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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