8-bit AVR Microcontroller
ATmega8A
DATASHEET SUMMARY
Introduction
®
The Atmel ATmega8A is a low-power CMOS 8-bit microcontroller based on
®
the AVR enhanced RISC architecture. By executing powerful instructions in
a single clock cycle, the ATmega8A achieves throughputs close to 1MIPS
per MHz. This empowers system designer to optimize the device for power
consumption versus processing speed.
Features
•
•
•
•
•
High-performance, Low-power Atmel AVR 8-bit Microcontroller
Advanced RISC Architecture
– 130 Powerful Instructions - Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 8KBytes of In-System Self-programmable Flash program
memory
– 512Bytes EEPROM
– 1KByte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
Atmel QTouch® library support
– Capacitive touch buttons, sliders and wheels
– Atmel QTouch and QMatrix acquisition
– Up to 64 sense channels
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare
Mode
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–
–
–
–
–
–
•
•
•
•
•
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
Real Time Counter with Separate Oscillator
Three PWM Channels
8-channel ADC in TQFP and QFN/MLF package
• Eight Channels 10-bit Accuracy
6-channel ADC in PDIP package
• Six Channels 10-bit Accuracy
Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V
Speed Grades
– 0 - 16MHz
Power Consumption at 4MHz, 3V, 25°C
– Active: 3.6mA
– Idle Mode: 1.0mA
– Power-down Mode: 0.5μA
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Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description.................................................................................................................4
2. Configuration Summary............................................................................................. 5
3. Ordering Information..................................................................................................6
4. Block Diagram........................................................................................................... 7
5. Pin Configurations..................................................................................................... 8
5.1.
5.2.
Pin Descriptions..........................................................................................................................10
Accessing 16-bit Registers.........................................................................................................12
6. I/O Multiplexing........................................................................................................ 15
7. Resources................................................................................................................16
8. Data Retention.........................................................................................................17
9. About Code Examples............................................................................................. 18
10. Capacitive Touch Sensing....................................................................................... 19
11. Packaging Information............................................................................................. 20
11.1. 32A............................................................................................................................................. 20
11.2. 28P3........................................................................................................................................... 21
11.3. 32M1-A.......................................................................................................................................22
12. Errata.......................................................................................................................23
12.1. ATmega8A, rev. L....................................................................................................................... 23
13. Datasheet Revision History..................................................................................... 25
13.1. Rev.8159F – 07/2015................................................................................................................. 25
13.2. Rev.8159E – 02/2013................................................................................................................. 25
13.3.
13.4.
13.5.
13.6.
Rev.8159D – 02/11..................................................................................................................... 25
DRH_Rev.8159C – 07/09........................................................................................................... 25
Rev.8159B – 05/09..................................................................................................................... 25
Rev.8159A – 08/08..................................................................................................................... 25
1.
Description
The Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega8A provides the following features: 8K bytes of In-System Programmable Flash with ReadWhile- Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32
general purpose working registers, three flexible Timer/Counters with compare modes, internal and
external interrupts, a serial programmable USART, one byte oriented Two-wire Serial Interface, a 6channel ADC (eight channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable
Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving
modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, one SPI port, and
interrupt system to continue functioning. The Power-down mode saves the register contents but freezes
the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save
mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest
of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except
asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode,
the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low-power consumption.
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality
into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and
includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®)
technology for unambiguous detection of key events. The easy-to-use QTouch Composer allows you to
explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega8A is a powerful microcontroller that
provides a highly flexible and cost effective solution to many embedded control applications.
The device is supported with a full suite of program and system development tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kit.
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2.
Configuration Summary
Features
ATmega8A
Pin count
32
Flash (KB)
8
SRAM (KB)
1
EEPROM (Bytes)
512
General Purpose I/O pins
23
SPI
1
TWI (I2C)
1
USART
1
ADC
10-bit 15ksps
ADC channels
6 (8 in TQFP and QFN/MLF packages)
AC propagation delay
Typ 400ns
8-bit Timer/Counters
2
16-bit Timer/Counters
1
PWM channels
3
RC Oscillator
+/-3%
Operating voltage
2.7 - 5.5V
Max operating frequency
16MHz
Temperature range
-40°C to +105°C
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3.
Ordering Information
Speed (MHz)
16
Power Supply
2.7 - 5.5V
Ordering Code(2)
Package(1)
ATmega8A-AU
ATmega8A-AUR(3)
32A
32A
ATmega8A-PU
28P3
ATmega8A-MU
32M1-A
ATmega8A-MUR(3)
32M1-A
ATmega8A-AN
ATmega8A-ANR(3)
32A
32A
ATmega8A-MN
32M1-A
ATmega8A-MNR(3)
32M1-A
ATmega8A-PN
28P3
Operational Range
Industrial (-40oC to 85oC)
Extended (-40oC to 105oC)
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Tape and Reel
Package Type
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame
Package (QFN/MLF)
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4.
Block Diagram
Figure 4-1 Block Diagram
SRAM
CPU
FLASH
XTAL1/
TOSC1
XTAL2/
TOSC2
VCC
RESET
GND
Clock generation
8 MHz
Crystal Osc
1/2/4/8MHz
Calib RC
12MHz
External
RC Osc
32.768kHz
XOSC
External
clock
1MHz int
osc
Power
Supervision
POR/BOD &
RESET
ADC[7:0]
AREF
AIN0
AIN1
ADCMUX
Power
management
and clock
control
EEPROMIF
NVM
programming
Watchdog
Timer
Internal
Reference
ADC
D
A
T
A
B
U
S
SPI
MISO
MOSI
SCK
SS
I/O
PORTS
PB[7:0]
PC[6:0]
PD[7:0]
EXTINT
INT[1:0]
AC
(8-bit)
USART
TC 1
(16-bit)
SDA
SCL
PARPROG
Serial
Programming
TC 0
RxD
TxD
XCK
EEPROM
TWI
TC 2
(8-bit async)
T0
OC1A/B
T1
ICP1
OC2
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5.
Pin Configurations
Figure 5-1 PDIP
(RESET) PC6
1
28
PC5 (ADC5/SCL)
(RXD) PD0
2
27
PC4 (ADC4/SDA)
(TXD) PD1
3
26
PC3 (ADC3)
(INT0) PD2
4
25
PC2 (ADC2)
(INT1) PD3
5
24
PC1 (ADC1)
(XCK/T0) PD4
6
23
PC0 (ADC0)
VCC
7
22
GND
GND
8
21
AREF
(XTAL1/TOSC1) PB6
9
20
AVCC
(XTAL2/TOSC2) PB7
10
19
PB5 (SCK)
(T1) PD5
11
18
PB4 (MISO)
(AIN0) PD6
12
17
PB3 (MOSI/OC2)
(AIN1) PD7
13
16
PB2 (SS/OC1B)
(ICP1) PB0
14
15
PB1 (OC1A)
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PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
32
31
30
29
28
27
26
25
Figure 5-2 TQFP Top View
GND
5
20
AREF
VCC
6
19
ADC6
(XTAL1/TOSC1) PB6
7
18
AVCC
(XTAL2/TOSC2) PB7
8
17
PB5 (SCK)
16
GND
(MISO) PB4
21
15
4
(MOSI/OC2) PB3
VCC
14
ADC7
(SS/OC1B) PB2
22
13
3
(OC1A) PB1
GND
12
PC0 (ADC0)
(ICP1) PB0
23
11
2
(AIN1) PD7
(XCK/T0) PD4
10
PC1 (ADC1)
(AIN0) PD6
24
9
1
(T1) PD5
(INT1) PD3
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PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
32
31
30
29
28
27
26
25
Figure 5-3 MLF Top View
GND
3
22
ADC7
VCC
4
21
GND
GND
5
20
AREF
VCC
6
19
ADC6
(XTAL1/TOSC1) PB6
7
18
AVCC
(XTAL2/TOSC2) PB7
8
17
PB5 (SCK)
Pin Descriptions
5.1.1.
VCC
(MISO) PB4
(MOSI/OC2) PB3
(SS/OC1B) PB2
(OC1A) PB1
(ICP1) PB0
(AIN1) PD7
(AIN0) PD6
(T1) PD5
5.1.
16
PC0 (ADC0)
15
23
14
2
13
(XCK/T0) PD4
12
PC1 (ADC1)
11
24
10
1
9
(INT1) PD3
NOTE:
The large center pad underneath
the MLF packages is made of
metal and internally connected to
GND. It should be soldered or
glued to the PCB to ensure good
mechanical stability. If the center
pad is left unconneted, the
package might loosen from the
PCB.
Digital supply voltage.
5.1.2.
GND
Ground.
5.1.3.
Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
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Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator
amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator
amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1 input for
the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in Alternate Functions of Port B and System Clock
and Clock Options.
5.1.4.
Port C (PC5:PC0)
Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
5.1.5.
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics
of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer
than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse
length is given in Table 30-5. Shorter pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated in Alternate Functions of Port C.
5.1.6.
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8A as listed in Alternate
Functions of Port D.
5.1.7.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. The minimum pulse length is given in Table 30-5. Shorter pulses are not
guaranteed to generate a reset.
5.1.8.
AVCC
AVCC is the supply voltage pin for the A/D Converter, Port C (3:0), and ADC (7:6). It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter. Note that Port C (5:4) use digital supply voltage, VCC.
5.1.9.
AREF
AREF is the analog reference pin for the A/D Converter.
5.1.10.
ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are
powered from the analog supply and serve as 10-bit ADC channels.
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5.2.
Accessing 16-bit Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit
data bus. A 16-bit register must be byte accessed using two read or write operations. The 16-bit timer has
a single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporary
register is shared between all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the
16-bit read or write operation. When the Low byte of a 16-bit register is written by the CPU, the High byte
stored in the temporary register, and the Low byte written are both copied into the 16-bit register in the
same clock cycle. When the Low byte of a 16-bit register is read by the CPU, the High byte of the 16-bit
register is copied into the temporary register in the same clock cycle as the Low byte is read.
Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16-bit
registers does not involve using the temporary register.
To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte
must be read before the High byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts
updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and
ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access.
Assembly Code Example(1)
:.
; Set TCNT1 to 0x01FF
ldi
r17,0x01
ldi
r16,0xFF
out
TCNT1H,r17
out
TCNT1L,r16
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
:.
C Code Example(1)
unsigned int i;
:.
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
:.
Note: 1. See About Code Examples.
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs
between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary
register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access
outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update
the temporary register, the main code must disable the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading
any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
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Asesmbly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note: 1. See About Code Examples.
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing
any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out
TCNT1H,r17
out
TCNT1L,r16
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
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}
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
Note: 1. See About Code Examples.
The assembly code example requires that the r17:r16 Register pair contains the value to be written to
TCNT1.
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6.
I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions. This table describes the peripheral signals multiplexed to the
PORT I/O pins.
Table 6-1 PORT Function Multiplexing
PAD
Pin #
PD[4]
EXTINT
PCINT
AC
Custom
OSC
TC1(16bit)
TC2(8-bit)
14
PCINT20
ACO
-
-
O1CA
-
PB[6]
1
PCINT06
-
-
EXTCLK
-
-
PD[5]
2
PCINT21
AINP1
-
-
CLK1
PD[6]
3
PCINT22
AINP0
-
-
ICP1
PD[7]
4
PCINT23
AINN0
-
-
PB[2]
5
PCINT02
-
CLO0
CLKOUT
PB[3]
6
PCINT03
-
-
-
PB[4]
7
PCINT04
-
-
-
PB[5]
8
PCINT05
-
CLO1
-
PC[4]
9
PCINT12
AINN1
-
PC[5]
10
PCINT13
AINN2
-
PC[6]/
RESET
13
PCINT14
-
VCC
11
GND
12
INT0
USART
SPI
Misc
-
-
-
-
SII
-
-
-
SDO
-
TC2-OCB
-
-
SDI
TC1-OCB
-
-
SS
TC2-OCA
TXD
MOSI
-
-
RXD
MISO
-
-
XCK
SCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HVRST/d
W
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7.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download
on http://www.atmel.com/avr.
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8.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.
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9.
About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device.
These code examples assume that the part specific header file is included before compilation. Be aware
that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is
compiler dependent. Please confirm with the C compiler documentation for more details.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
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10.
Capacitive Touch Sensing
The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most
®
Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix
acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the
AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,
and then calling the touch sensing API’s to retrieve the channel information and determine the touch
sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel
QTouch Library User Guide - also available for download from the Atmel website.
Atmel ATmega8A [DATASHEET]
Atmel-8159FS-8-bit AVR Microcontroller_Datasheet_Summary-09/2015
19
11.
Packaging Information
11.1.
32A
PIN 1 IDENTIFIER
PIN 1
e
B
E1
E
D1
D
C
0°~7°
L
A1
A2
A
COMMON DIMENSIONS
(Unit of measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
8.75
9.00
9.25
D1
6.90
7.00
7.10
E
8.75
9.00
9.25
E1
6.90
7.00
7.10
–
0.45
–
0.20
–
0.75
B
0.30
C
0.09
L
0.45
e
NOTE
Note 2
Note 2
0.80 TYP
2010-10-20
TITLE
32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness,
0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
DRAWING NO.
REV.
32A
C
Atmel ATmega8A [DATASHEET]
Atmel-8159FS-8-bit AVR Microcontroller_Datasheet_Summary-09/2015
20
11.2.
28P3
D
PIN
1
E1
A
SEATING PLANE
L
B2
B1
A1
B
(4 PLACES)
0º ~ 15º
REF
e
E
C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
eB
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").
MIN
NOM
MAX
A
–
–
4.5724
A1
0.508
–
–
D
34.544
–
34.798
E
7.620
–
8.255
E1
7.112
–
7.493
B
0.381
–
0.533
B1
1.143
–
1.397
B2
0.762
–
1.143
L
3.175
–
3.429
C
0.203
–
0.356
eB
–
–
10.160
e
NOTE
Note 1
Note 1
2.540 TYP
09/28/01
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
REV.
28P3
B
Atmel ATmega8A [DATASHEET]
Atmel-8159FS-8-bit AVR Microcontroller_Datasheet_Summary-09/2015
21
11.3.
32M1-A
D
D1
1
2
3
0
Pin 1 ID
E1
SIDE VIEW
E
TOP VIEW
A3
A2
A1
A
K
0.08 C
P
D2
1
2
3
Pin #1 Notch
(0.20 R)
NOM
MAX
0.80
0.90
1.00
A1
–
0.02
0.05
A2
–
0.65
1.00
A3
E2
K
b
MIN
A
SYMBOL
P
e
COMMON DIMENSIONS
(Unit of Measure = mm)
L
BOTTOM VIEW
0.20 REF
b
0.18
0.23
0.30
D
4.90
5.00
5.10
D1
4.70
4.75
4.80
D2
2.95
3.10
3.25
E
4.90
5.00
5.10
E1
4.70
4.75
4.80
E2
2.95
3.10
3.25
e
Note : JEDEC Standard MO-220, Fig
. 2 (Anvil Singulation), VHHD-2 .
NOTE
0.50 BSC
L
0.30
0.40
0.50
P
–
–
0
–
–
0.60
o
12
K
0.20
–
–
03/14/2014
32M1-A , 32-pad, 5 x 5 x 1.0mm Bod y, Lead Pitch 0.50mm ,
3.10mm Exposed P ad, Micro Lead Frame P a ckage (MLF)
32M1-A
Atmel ATmega8A [DATASHEET]
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F
22
12.
Errata
The revision letter in this section refers to the revision of the ATmega8A device.
12.1.
ATmega8A, rev. L
•
•
•
•
•
1.
First Analog Comparator conversion may be delayed
Interrupts may be lost when writing the timer registers in the asynchronous timer
Signature may be Erased in Serial Programming Mode
CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32kHz Oscillator is
Used to Clock the Asynchronous Timer/Counter2
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request
First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take
longer than expected on some devices.
Problem Fix / Workaround:
2.
When the device has been powered or reset, disable then enable theAnalog Comparator before the
first conversion.
Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the
asynchronous Timer/Counter register (TCNTx) is 0x00.
Problem Fix / Workaround:
3.
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00
before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter
Register (TCNTx), or asynchronous Output Compare Register (OCRx).
Signature may be Erased in Serial Programming Mode
If the signature bytes are read before a chiperase command is completed, the signature may be
erased causing the device ID and calibration bytes to disappear. This is critical, especially, if the
part is running on internal RC oscillator.
Problem Fix / Workaround:
4.
Ensure that the chiperase command has exceeded before applying the next command.
CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32kHz Oscillator is
Used to Clock the Asynchronous Timer/Counter2
When the internal RC Oscillator is used as the main clock source, it is possible to run the Timer/
Counter2 asynchronously by connecting a 32kHz Oscillator between XTAL1/TOSC1 and XTAL2/
TOSC2. But when the internal RC Oscillator is selected as the main clock source, the CKOPT Fuse
does not control the internal capacitors on XTAL1/TOSC1 and XTAL2/TOSC2. As long as there are
no capacitors connected to XTAL1/TOSC1 and XTAL2/TOSC2, safe operation of the Oscillator is
not guaranteed.
Problem Fix / Workaround:
Use external capacitors in the range of 20 - 36 pF on XTAL1/TOSC1 and XTAL2/TOSC2. This will
be fixed in ATmega8A Rev. G where the CKOPT Fuse will control internal capacitors also when
internal RC Oscillator is selected as main clock source. For ATmega8A Rev. G, CKOPT = 0
(programmed) will enable the internal capacitors on XTAL1 and XTAL2. Customers who want
Atmel ATmega8A [DATASHEET]
Atmel-8159FS-8-bit AVR Microcontroller_Datasheet_Summary-09/2015
23
5.
compatibility between Rev. G and older revisions, must ensure that CKOPT is unprogrammed
(CKOPT = 1).
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register
triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround:
Always use OUT or SBI to set EERE in EECR.
Atmel ATmega8A [DATASHEET]
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24
13.
Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring
revision in this section refers to the document revision.
13.1.
Rev.8159F – 07/2015
1.
13.2.
Rev.8159E – 02/2013
1.
2.
3.
4.
5.
13.3.
Updated Errata.
Rev.8159B – 05/09
1.
2.
3.
4.
5.
13.6.
Updated the datasheet according to the Atmel new Brand Style Guide.
Updated Performing Page Erase by SPM by adding an extra note.
Updated Ordering Information to include Tape & Reel.
DRH_Rev.8159C – 07/09
1.
13.5.
Applied the Atmel new page layout for datasheets including new logo and last page.
Removed the reference to the debuggers and In-Circuit Emulators.
Added Capacitive touch sensing.
Added Electrical Characteristics – TA = -40°C to 105°C.
Added Typical Characteristics – TA = -40°C to 105°C.
Rev.8159D – 02/11
1.
2.
3.
13.4.
New workflow used for the publication.
Updated System and Reset Characteristics with new BODLEVEL values
Updated ADC Characteristics with new VINT values.
Updated Typical Characteristics – TA = -40°C to 85°C view.
Updated Errata. ATmega8A, rev L.
Created a new Table Of Contents.
Rev.8159A – 08/08
1.
2.
Initial revision (Based on the ATmega8/L datasheet 2486T-AVR-05/08)
Changes done compared to ATmega8/L datasheet 2486T-AVR-05/08:
– All Electrical Characteristics are moved to Electrical Characteristics – TA = -40°C to 85°C.
– Updated DC Characteristics with new VOL Max (0.9V and 0.6V) and typical value for ICC.
– Added Speed Grades.
– Added a new sub section System and Reset Characteristics.
– Updated System and Reset Characteristics with new VBOT BODLEVEL = 0 (3.6V, 4.0V and
4.2V).
Atmel ATmega8A [DATASHEET]
Atmel-8159FS-8-bit AVR Microcontroller_Datasheet_Summary-09/2015
25
–
–
–
Register descriptions are moved to sub section at the end of each chapter.
New graphics in Typical Characteristics – TA = -40°C to 85°C.
New Ordering Information.
Atmel ATmega8A [DATASHEET]
Atmel-8159FS-8-bit AVR Microcontroller_Datasheet_Summary-09/2015
26
Atmel Corporation
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2015 Atmel Corporation. / Rev.: Atmel-8159FS-8-bit AVR Microcontroller_Datasheet_Summary-09/2015
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