SAM C20 - Preliminary

SMART ARM-Based Microcontrollers
SAM C20E / SAM C20G /SAM C20J
DATASHEET PRELIMINARY
Introduction
®
™
The Atmel | SMART SAM C20 is a series of microcontrollers optimized for
industrial automation, appliances and other 5V applications using the 32-bit
®
®
ARM Cortex -M0+ processor, ranging from 32- to 64-pins with up to 256KB
Flash and 32KB of SRAM and operate at a maximum frequency of 48MHz
®
and reach 2.46 CoreMark /MHz. The SAM C20 devices are designed for
simple and intuitive migration with identical peripheral modules, hex
compatible code, identical linear address map and pin compatible migration
paths between all devices in the product series. All devices include
intelligent and flexible peripherals, Atmel Event System for inter-peripheral
signaling, and support for capacitive touch button, slider and wheel user
interfaces.
SAM C20 devices are pin compatible to the SAM D family of general
purpose microcontrollers.
Features
•
•
•
Processor
– ARM Cortex-M0+ CPU running at up to 48MHz
• Single-cycle hardware multiplier
• Micro Trace Buffer
• Memory Protection Unit (MPU)
Memories
– 32/64/128/256KB in-system self-programmable Flash
– 1/2/4/8KB independent self-programmable Flash for EEPROM
emulation
– 4/8/16/32KB SRAM Main Memory
System
– Power-on reset (POR) and brown-out detection (BOD)
– Internal and external clock options with 48MHz to 96MHz
Fractional Digital Phase Locked Loop (FDPLL96M)
– External Interrupt Controller (EIC)
– 16 external interrupts
– One non-maskable interrupt
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•
– Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
Low Power
– Idle, standby, and off sleep modes
– SleepWalking peripherals
Peripherals
– Hardware Divide and Square Root Accelerator (DIVAS)
– 6-channel Direct Memory Access Controller (DMAC)
– 6-channel Event System
–
–
–
–
–
–
–
–
–
–
–
•
•
•
Up to five 16-bit Timer/Counters (TC), configurable as either:
• One 16-bit TC with compare/capture channels
• One 8-bit TC with compare/capture channels
• One 32-bit TC with compare/capture channels, by using two TCs
Two 24-bit Timer/Counters and one 16-bit Timer/Counter for Control (TCC), with extended
functions:
• Up to four compare channels with optional complementary output
• Generation of synchronized pulse width modulation (PWM) pattern across port pins
• Deterministic fault protection, fast decay and configurable dead-time between
complementary output
• Dithering that increase resolution with up to 5 bit and reduce quantization error
Frequency Meter
32-bit Real Time Counter (RTC) with clock/calendar function
Watchdog Timer (WDT)
CRC-32 generator
Up to four Serial Communication Interfaces (SERCOM), each configurable to operate as
either:
• USART with full-duplex and single-wire half-duplex configuration
• I2C up to 3.4MHz
• SPI
• LIN master/slave
• RS-485
One Configurable Custom Logic (CCL)
One 12-bit, 1Msps Analog-to-Digital Converter (ADC) with up to 12 channels
• Differential and single-ended input
• Automatic offset and gain error compensation
• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
Two Analog Comparators (AC) with window compare function
Peripheral Touch Controller (PTC)
• 256-Channel capacitive touch and proximity sensing
I/O
– Up to 52 programmable I/O pins
Drop in compatible with SAM D20 and SAM D21
Packages
– 64-pin TQFP, QFN
– 48-pin TQFP, QFN
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•
– 32-pin TQFP, QFN
Operating Voltage
– 2.7V – 5.5V
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Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description...............................................................................................................13
2. Configuration Summary........................................................................................... 14
3. Ordering Information................................................................................................16
3.1.
3.2.
3.3.
3.4.
SAM C20E..................................................................................................................................16
SAM C20G................................................................................................................................. 17
SAM C20J.................................................................................................................................. 18
Device Identification................................................................................................................... 19
4. Block Diagram......................................................................................................... 21
5. Pinout.......................................................................................................................23
5.1.
5.2.
5.3.
SAM C20E..................................................................................................................................23
SAM C20G................................................................................................................................. 24
SAM C20J.................................................................................................................................. 25
6. Signal Descriptions List........................................................................................... 26
7. I/O Multiplexing and Considerations........................................................................ 28
7.1.
7.2.
Multiplexed Signals.....................................................................................................................28
Other Functions..........................................................................................................................29
8. Power Supply and Start-Up Considerations............................................................ 32
8.1.
8.2.
8.3.
Power Domain Overview............................................................................................................32
Power Supply Considerations.................................................................................................... 32
Power-Up....................................................................................................................................34
8.4.
Power-On Reset and Brown-Out Detector................................................................................. 35
9. Product Mapping......................................................................................................36
10. Memories.................................................................................................................37
10.1.
10.2.
10.3.
10.4.
10.5.
Embedded Memories................................................................................................................. 37
Physical Memory Map................................................................................................................ 37
NVM User Row Mapping............................................................................................................38
NVM Software Calibration Area Mapping...................................................................................39
Serial Number.............................................................................................................................40
11. Processor and Architecture..................................................................................... 41
11.1. Cortex M0+ Processor................................................................................................................41
11.2. Nested Vector Interrupt Controller..............................................................................................43
11.3. Micro Trace Buffer...................................................................................................................... 44
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11.4. High-Speed Bus System............................................................................................................ 45
12. PAC - Peripheral Access Controller.........................................................................48
12.1.
12.2.
12.3.
12.4.
12.5.
12.6.
12.7.
Overview.....................................................................................................................................48
Features..................................................................................................................................... 48
Block Diagram............................................................................................................................ 48
Product Dependencies............................................................................................................... 48
Functional Description................................................................................................................49
Register Summary......................................................................................................................53
Register Description................................................................................................................... 54
13. Peripherals Configuration Summary........................................................................69
14. DSU - Device Service Unit...................................................................................... 71
14.1. Overview.....................................................................................................................................71
14.2. Features..................................................................................................................................... 71
14.3. Block Diagram............................................................................................................................ 72
14.4. Signal Description.......................................................................................................................72
14.5. Product Dependencies............................................................................................................... 72
14.6. Debug Operation........................................................................................................................ 73
14.7. Chip Erase..................................................................................................................................75
14.8. Programming..............................................................................................................................76
14.9. Intellectual Property Protection...................................................................................................76
14.10. Device Identification................................................................................................................... 78
14.11. Functional Description................................................................................................................79
14.12. Register Summary..................................................................................................................... 84
14.13. Register Description...................................................................................................................86
15. DIVAS – Divide and Square Root Accelerator....................................................... 110
15.1.
15.2.
15.3.
15.4.
15.5.
Overview...................................................................................................................................110
Features....................................................................................................................................110
Block Diagram.......................................................................................................................... 110
Signal Description.....................................................................................................................110
Product Dependencies............................................................................................................. 110
15.6. Functional Description.............................................................................................................. 111
15.7. Register Summary.................................................................................................................... 114
15.8. Register Description................................................................................................................. 114
16. Clock System.........................................................................................................122
16.1.
16.2.
16.3.
16.4.
16.5.
16.6.
16.7.
Clock Distribution......................................................................................................................122
Synchronous and Asynchronous Clocks..................................................................................123
Register Synchronization..........................................................................................................123
Enabling a Peripheral............................................................................................................... 125
On-demand, Clock Requests................................................................................................... 125
Power Consumption vs. Speed................................................................................................ 126
Clocks after Reset.................................................................................................................... 126
17. GCLK - Generic Clock Controller.......................................................................... 127
17.1. Overview...................................................................................................................................127
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17.2. Features................................................................................................................................... 127
17.3.
17.4.
17.5.
17.6.
17.7.
17.8.
Block Diagram.......................................................................................................................... 127
Signal Description.....................................................................................................................128
Product Dependencies............................................................................................................. 128
Functional Description..............................................................................................................129
Register Summary....................................................................................................................135
Register Description................................................................................................................. 139
18. MCLK – Main Clock...............................................................................................149
18.1.
18.2.
18.3.
18.4.
18.5.
18.6.
18.7.
18.8.
Overview...................................................................................................................................149
Features................................................................................................................................... 149
Block Diagram.......................................................................................................................... 149
Signal Description.....................................................................................................................149
Product Dependencies............................................................................................................. 149
Functional Description..............................................................................................................151
Register Summary....................................................................................................................156
Register Description................................................................................................................. 156
19. RSTC – Reset Controller.......................................................................................172
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
19.8.
Overview...................................................................................................................................172
Features................................................................................................................................... 172
Block Diagram.......................................................................................................................... 172
Signal Description.....................................................................................................................172
Product Dependencies............................................................................................................. 172
Functional Description..............................................................................................................173
Register Summary....................................................................................................................175
Register Description................................................................................................................. 175
20. PM – Power Manager............................................................................................177
20.1.
20.2.
20.3.
20.4.
20.5.
20.6.
20.7.
20.8.
Overview...................................................................................................................................177
Features................................................................................................................................... 177
Block Diagram.......................................................................................................................... 177
Signal Description.....................................................................................................................177
Product Dependencies............................................................................................................. 177
Functional Description..............................................................................................................178
Register Summary....................................................................................................................182
Register Description................................................................................................................. 182
21. OSCCTRL – Oscillators Controller........................................................................ 185
21.1.
21.2.
21.3.
21.4.
21.5.
21.6.
21.7.
21.8.
Overview...................................................................................................................................185
Features................................................................................................................................... 185
Block Diagram.......................................................................................................................... 186
Signal Description.....................................................................................................................186
Product Dependencies............................................................................................................. 186
Functional Description..............................................................................................................187
Register Summary....................................................................................................................196
Register Description................................................................................................................. 197
22. OSC32KCTRL – 32KHz Oscillators Controller......................................................225
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22.1. Overview...................................................................................................................................225
22.2.
22.3.
22.4.
22.5.
22.6.
22.7.
22.8.
Features................................................................................................................................... 225
Block Diagram.......................................................................................................................... 226
Signal Description.....................................................................................................................226
Product Dependencies............................................................................................................. 226
Functional Description..............................................................................................................228
Register Summary....................................................................................................................234
Register Description................................................................................................................. 234
23. SUPC – Supply Controller..................................................................................... 251
23.1.
23.2.
23.3.
23.4.
23.5.
23.6.
23.7.
23.8.
Overview...................................................................................................................................251
Features................................................................................................................................... 251
Block Diagram.......................................................................................................................... 252
Signal Description.....................................................................................................................252
Product Dependencies............................................................................................................. 252
Functional Description..............................................................................................................253
Register Summary....................................................................................................................258
Register Description................................................................................................................. 258
24. WDT – Watchdog Timer........................................................................................ 272
24.1.
24.2.
24.3.
24.4.
24.5.
24.6.
24.7.
24.8.
Overview...................................................................................................................................272
Features................................................................................................................................... 272
Block Diagram.......................................................................................................................... 273
Signal Description.....................................................................................................................273
Product Dependencies............................................................................................................. 273
Functional Description..............................................................................................................274
Register Summary....................................................................................................................280
Register Description................................................................................................................. 280
25. RTC – Real-Time Counter..................................................................................... 292
25.1. Overview...................................................................................................................................292
25.2. Features................................................................................................................................... 292
25.3. Block Diagram.......................................................................................................................... 292
25.4. Signal Description.....................................................................................................................293
25.5. Product Dependencies............................................................................................................. 293
25.6. Functional Description..............................................................................................................295
25.7. Register Summary - COUNT32................................................................................................300
25.8. Register Description - COUNT32............................................................................................. 301
25.9. Register Summary - COUNT16................................................................................................314
25.10. Register Description - COUNT16.............................................................................................315
25.11. Register Summary - CLOCK.................................................................................................... 329
25.12. Register Description - CLOCK................................................................................................. 330
26. DMAC – Direct Memory Access Controller........................................................... 346
26.1.
26.2.
26.3.
26.4.
26.5.
Overview...................................................................................................................................346
Features................................................................................................................................... 346
Block Diagram.......................................................................................................................... 347
Signal Description.....................................................................................................................347
Product Dependencies............................................................................................................. 347
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26.6. Functional Description..............................................................................................................349
26.7. Register Summary....................................................................................................................370
26.8. Register Description................................................................................................................. 371
26.9. Register Summary - SRAM...................................................................................................... 403
26.10. Register Description - SRAM................................................................................................... 403
27. EIC – External Interrupt Controller.........................................................................411
27.1.
27.2.
27.3.
27.4.
27.5.
27.6.
27.7.
27.8.
Overview...................................................................................................................................411
Features....................................................................................................................................411
Block Diagram.......................................................................................................................... 411
Signal Description.....................................................................................................................412
Product Dependencies............................................................................................................. 412
Functional Description..............................................................................................................413
Register Summary....................................................................................................................418
Register Description................................................................................................................. 419
28. NVMCTRL – Non-Volatile Memory Controller....................................................... 430
28.1.
28.2.
28.3.
28.4.
28.5.
28.6.
28.7.
28.8.
Overview...................................................................................................................................430
Features................................................................................................................................... 430
Block Diagram.......................................................................................................................... 430
Signal Description.....................................................................................................................431
Product Dependencies............................................................................................................. 431
Functional Description..............................................................................................................432
Register Summary....................................................................................................................439
Register Description................................................................................................................. 440
29. PORT - I/O Pin Controller...................................................................................... 455
29.1.
29.2.
29.3.
29.4.
29.5.
29.6.
29.7.
29.8.
Overview...................................................................................................................................455
Features................................................................................................................................... 455
Block Diagram.......................................................................................................................... 456
Signal Description.....................................................................................................................456
Product Dependencies............................................................................................................. 456
Functional Description..............................................................................................................459
Register Summary....................................................................................................................465
Register Description................................................................................................................. 467
30. EVSYS – Event System........................................................................................ 487
30.1.
30.2.
30.3.
30.4.
30.5.
30.6.
30.7.
30.8.
Overview...................................................................................................................................487
Features................................................................................................................................... 487
Block Diagram.......................................................................................................................... 487
Signal Description.....................................................................................................................488
Product Dependencies............................................................................................................. 488
Functional Description..............................................................................................................489
Register Summary....................................................................................................................493
Register Description................................................................................................................. 494
31. SERCOM – Serial Communication Interface.........................................................510
31.1. Overview...................................................................................................................................510
31.2. Features................................................................................................................................... 510
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31.3. Block Diagram.......................................................................................................................... 510
31.4. Signal Description.....................................................................................................................511
31.5. Product Dependencies............................................................................................................. 511
31.6. Functional Description..............................................................................................................512
32. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver
and Transmitter......................................................................................................518
32.1.
32.2.
32.3.
32.4.
32.5.
32.6.
32.7.
32.8.
Overview...................................................................................................................................518
USART Features...................................................................................................................... 518
Block Diagram.......................................................................................................................... 519
Signal Description.....................................................................................................................519
Product Dependencies............................................................................................................. 519
Functional Description..............................................................................................................521
Register Summary....................................................................................................................533
Register Description................................................................................................................. 533
33. SERCOM SPI – SERCOM Serial Peripheral Interface..........................................558
33.1.
33.2.
33.3.
33.4.
33.5.
33.6.
33.7.
33.8.
Overview...................................................................................................................................558
Features................................................................................................................................... 558
Block Diagram.......................................................................................................................... 559
Signal Description.....................................................................................................................559
Product Dependencies............................................................................................................. 559
Functional Description..............................................................................................................561
Register Summary....................................................................................................................570
Register Description................................................................................................................. 571
34. SERCOM I2C – SERCOM Inter-Integrated Circuit................................................ 591
34.1.
34.2.
34.3.
34.4.
34.5.
34.6.
Overview...................................................................................................................................591
Features................................................................................................................................... 591
Block Diagram.......................................................................................................................... 592
Signal Description.....................................................................................................................592
Product Dependencies............................................................................................................. 592
Functional Description..............................................................................................................594
34.7. Register Summary - I2C Slave.................................................................................................613
34.8. Register Description - I2C Slave...............................................................................................613
34.9. Register Summary - I2C Master...............................................................................................633
34.10. Register Description - I2C Master.............................................................................................634
35. TC – Timer/Counter............................................................................................... 656
35.1.
35.2.
35.3.
35.4.
35.5.
35.6.
35.7.
35.8.
Overview...................................................................................................................................656
Features................................................................................................................................... 656
Block Diagram.......................................................................................................................... 657
Signal Description.....................................................................................................................657
Product Dependencies............................................................................................................. 658
Functional Description..............................................................................................................659
Register Summary....................................................................................................................674
Register Description................................................................................................................. 678
36. TCC – Timer/Counter for Control Applications...................................................... 708
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36.1. Overview...................................................................................................................................708
36.2.
36.3.
36.4.
36.5.
36.6.
36.7.
36.8.
Features................................................................................................................................... 708
Block Diagram.......................................................................................................................... 709
Signal Description.....................................................................................................................709
Product Dependencies............................................................................................................. 709
Functional Description.............................................................................................................. 711
Register Summary....................................................................................................................744
Register Description................................................................................................................. 746
37. CCL – Configurable Custom Logic........................................................................ 791
37.1.
37.2.
37.3.
37.4.
37.5.
37.6.
37.7.
37.8.
Overview...................................................................................................................................791
Features................................................................................................................................... 791
Block Diagram.......................................................................................................................... 792
Signal Description.....................................................................................................................792
Product Dependencies............................................................................................................. 792
Functional Description..............................................................................................................793
Register Summary....................................................................................................................804
Register Description................................................................................................................. 804
38. ADC – Analog-to-Digital Converter........................................................................809
38.1.
38.2.
38.3.
38.4.
38.5.
38.6.
38.7.
38.8.
Overview...................................................................................................................................809
Features................................................................................................................................... 809
Block Diagram.......................................................................................................................... 810
Signal Description.....................................................................................................................810
Product Dependencies............................................................................................................. 810
Functional Description..............................................................................................................812
Register Summary....................................................................................................................822
Register Description................................................................................................................. 823
39. AC – Analog Comparators.....................................................................................851
39.1.
39.2.
39.3.
39.4.
39.5.
39.6.
39.7.
39.8.
Overview...................................................................................................................................851
Features................................................................................................................................... 851
Block Diagram.......................................................................................................................... 852
Signal Description.....................................................................................................................852
Product Dependencies............................................................................................................. 852
Functional Description..............................................................................................................854
Register Summary....................................................................................................................863
Register Description................................................................................................................. 863
40. PTC - Peripheral Touch Controller.........................................................................881
40.1.
40.2.
40.3.
40.4.
40.5.
40.6.
Overview...................................................................................................................................881
Features................................................................................................................................... 881
Block Diagram.......................................................................................................................... 882
Signal Description.....................................................................................................................883
Product Dependencies............................................................................................................. 883
Functional Description..............................................................................................................884
41. FREQM – Frequency Meter.................................................................................. 886
41.1. Overview...................................................................................................................................886
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41.2. Features................................................................................................................................... 886
41.3.
41.4.
41.5.
41.6.
41.7.
41.8.
Block Diagram.......................................................................................................................... 886
Signal Description.....................................................................................................................886
Product Dependencies............................................................................................................. 886
Functional Description..............................................................................................................887
Register Summary....................................................................................................................890
Register Description................................................................................................................. 890
42. Electrical Characteristics 85°C.............................................................................. 900
42.1. Disclaimer.................................................................................................................................900
42.2. Absolute Maximum Ratings......................................................................................................900
42.3. General Operating Ratings.......................................................................................................900
42.4. Supply Characteristics..............................................................................................................901
42.5. Maximum Clock Frequencies................................................................................................... 902
42.6. Power Consumption................................................................................................................. 903
42.7. Wake-Up Time..........................................................................................................................904
42.8. I/O Pin Characteristics..............................................................................................................905
42.9. Analog Characteristics..............................................................................................................906
42.10. NVM Characteristics................................................................................................................ 917
42.11. Oscillator Characteristics..........................................................................................................918
42.12. Timing Characteristics..............................................................................................................926
43. Electrical Characteristics 105°C............................................................................ 929
43.1.
43.2.
43.3.
43.4.
43.5.
Disclaimer.................................................................................................................................929
General Operating Ratings.......................................................................................................929
Power Consumption................................................................................................................. 930
Analog Characteristics..............................................................................................................931
Oscillator Characteristics..........................................................................................................933
44. Packaging Information...........................................................................................935
44.1. Thermal Considerations........................................................................................................... 935
44.2. Package Drawings....................................................................................................................936
44.3. Soldering Profile....................................................................................................................... 944
45. Schematic Checklist.............................................................................................. 945
45.1.
45.2.
45.3.
45.4.
45.5.
45.6.
45.7.
45.8.
Introduction...............................................................................................................................945
Operation in Noisy Environment...............................................................................................945
Power Supply........................................................................................................................... 945
External Analog Reference Connections................................................................................. 947
External Reset Circuit...............................................................................................................948
Unused or Unconnected Pins...................................................................................................950
Clocks and Crystal Oscillators..................................................................................................950
Programming and Debug Ports................................................................................................953
46. Errata.....................................................................................................................957
46.1.
46.2.
46.3.
46.4.
Die Revision A..........................................................................................................................957
Die Revision B..........................................................................................................................957
Die Revision C..........................................................................................................................964
Die Revision D..........................................................................................................................966
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47. Revision History.....................................................................................................969
47.1.
47.2.
47.3.
47.4.
47.5.
47.6.
47.7.
47.8.
Rev H - 05/2016....................................................................................................................... 969
Rev G - 04/2015....................................................................................................................... 969
Rev F - 02/2015........................................................................................................................971
Rev E - 12/2015........................................................................................................................972
Rev D - 09/2015....................................................................................................................... 973
Rev C - 09/2015....................................................................................................................... 973
Rev B - 06/2015........................................................................................................................973
Rev A - 04/2015........................................................................................................................973
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1.
Description
The Atmel SAM C20 devices provide the following features: In-system programmable Flash, six-channel
direct memory access (DMA) controller, six-channel Event System, programmable interrupt controller, up
to 52 programmable I/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC)
and three Timer/Counters for Control (TCC), where each TC can be configured to perform frequency and
waveform generation, accurate program execution timing or input capture with time and frequency
measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded
to form a 32-bit TC, and three timer/counters have extended functions optimized for motor, lighting and
other control applications. Two TCC can operate in 24-bit mode, and the third TCC can operate in 16- bit
mode. The series provide up to four Serial Communication Modules (SERCOM) that each can be
configured to act as an USART, UART, SPI, I2C up to 3.4MHz, SMBus, PMBus, RS-485 and LIN master/
slave; two 12-bit, 1Msps ADCs with up to 12-channels each (20 unique channels total), two analog
comparators with window mode, Peripheral Touch Controller supporting up to 256 buttons, sliders, wheels
and proximity sensing; programmable Watchdog Timer, brown-out detector and power-on reset and twopin Serial Wire Debug (SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a
source for the system clock. Different clock domains can be independently configured to run at different
frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus
maintaining a high CPU frequency while reducing power consumption.
The SAM C20 devices have three software-selectable sleep modes, idle, standby and off. In idle mode
the CPU is stopped while all other functions can be kept running. In standby all clocks and functions are
stopped expect those selected to continue running. In this mode all RAMs and logic contents are
retained. The device supports SleepWalking. This feature allows the peripheral to wake up from sleep
based on predefined conditions, and thus allows some internal operation like DMA transfer and/or the
CPU to wake up only when needed, e.g. when a threshold is crossed or a result is ready. The Event
System supports synchronous and asynchronous events, allowing peripherals to receive, react to and
send events even in standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface. The same
interface can be used for non-intrusive on-chip debug of application code. A boot loader running in the
device can use any communication interface to download and upgrade the application program in the
Flash memory.
The Atmel SAM C20 devices are supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation
kits.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
13
2.
Configuration Summary
SAM C20J
SAM C20G
SAM C20E
Pins
64
48
32
General Purpose I/O-pins (GPIOs)
52
38
26
256/128/64/32KB
256/128/64/32KB
256/128/64/32KB
8/4/2/1KB
8/4/2/1KB
8/4/2/1KB
32/16/8/4KB
32/16/8/4KB
32/16/8/4KB
Timer Counter (TC) instances
5
5
5
Waveform output channels per TC
instance
2
2
2
Timer Counter for Control (TCC)
instances
3
3
3
8/4/2
8/4/2
6/4/2
DMA channels
6
6
6
Configurable Custom Logic (CCL) (LUTs)
4
4
4
Serial Communication Interface
(SERCOM) instances
4
4
4
Analog-to-Digital Converter (ADC)
channels
12
12
10
Analog Comparators (AC)
2
2
2
Real-Time Counter (RTC)
Yes
Yes
Yes
1
1
1
Flash
Flash RWW section
System SRAM
Waveform output channels per TCC
RTC alarms
RTC compare values
One 32-bit value or One 32-bit value or One 32-bit value or
two 16-bit values
two 16-bit values
two 16-bit values
External Interrupt lines
16
16
16
Peripheral Touch Controller (PTC)
32
22
16
256 (16x16)
121 (11x11)
64 (8x8)
Number of self-capacitance channels (Ylines)
Peripheral Touch Controller (PTC)
Number of mutual-capacitance channels
(X x Y lines)
Maximum CPU frequency
Packages
48MHz
QFN
QFN
QFN
TQFP
TQFP
TQFP
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
14
SAM C20J
Oscillators
SAM C20G
SAM C20E
32.768kHz crystal oscillator (XOSC32K)
0.4-32MHz crystal oscillator (XOSC)
32.768kHz internal oscillator (OSC32K)
32KHz ultra-low-power internal oscillator (OSCULP32K)
48MHz high-accuracy internal oscillator (OSC48M)
96MHz Fractional Digital Phased Locked Loop (FDPLL96M)
Event System channels
6
6
6
SW Debug Interface
Yes
Yes
Yes
Watchdog Timer (WDT)
Yes
Yes
Yes
Related Links
I/O Multiplexing and Considerations on page 28
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
15
3.
Ordering Information
SAMC 20 E 15 A - M U T
Product Family
Package Carrier
SAMC = 5V Microcontroller
No character = Tray (Default)
T = Tape and Reel
Product Series
20 = Cortex M0 + CPU, DMA
Package Grade
Pin Count
U = -40 - 85 C Matte Sn Plating
N = -40 - 105 C Matte Sn Plating
O
O
E = 32 Pins
G = 48 Pins
J = 64 Pins
Package Type
Flash Memory Density
A = TQFP
M = QFN
18 = 256KB
17 = 128KB
16 = 64KB
15 = 32KB
Device Variant
A = Default Variant
3.1.
SAM C20E
Table 3-1. SAM C20E15A Ordering Codes
Ordering Code
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20E15A-AUT
32K
4K
TQFP32
Tape & Reel
85°C
ATSAM C20E15A-ANT
32K
4K
TQFP32
Tape & Reel
105°C
ATSAM C20E15A-MUT
32K
4K
QFN32
Tape & Reel
85°C
ATSAM C20E15A-MNT
32K
4K
QFN32
Tape & Reel
105°C
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20E16A-AUT
64K
8K
TQFP32
Tape & Reel
85°C
ATSAM C20E16A-ANT
64K
8K
TQFP32
Tape & Reel
105°C
ATSAM C20E16A-MUT
64K
8K
QFN32
Tape & Reel
85°C
ATSAM C20E16A-MNT
64K
8K
QFN32
Tape & Reel
105°C
Table 3-2. SAM C20E16A Ordering Codes
Ordering Code
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
16
Table 3-3. SAM C20E17A Ordering Codes
Ordering Code
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20E17A-AUT
128K
16K
TQFP32
Tape & Reel
85°C
ATSAM C20E17A-ANT
128K
16K
TQFP32
Tape & Reel
105°C
ATSAM C20E17A-MUT
128K
16K
QFN32
Tape & Reel
85°C
ATSAM C20E17A-MNT
128K
16K
QFN32
Tape & Reel
105°C
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20E18A-AUT
256K
32K
TQFP32
Tape & Reel
85°C
ATSAM C20E18A-ANT
256K
32K
TQFP32
Tape & Reel
105°C
ATSAM C20E18A-MUT
256K
32K
QFN32
Tape & Reel
85°C
ATSAM C20E18A-MNT
256K
32K
QFN32
Tape & Reel
105°C
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20G15A-AUT
32K
4K
TQFP48
Tape & Reel
85°C
ATSAM C20G15A-ANT
32K
4K
TQFP48
Tape & Reel
105°C
ATSAM C20G15A-MUT
32K
4K
QFN48
Tape & Reel
85°C
ATSAM C20G15A-MNT
32K
4K
QFN48
Tape & Reel
105°C
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20G16A-AUT
64K
8K
TQFP48
Tape & Reel
85°C
ATSAM C20G16A-ANT
64K
8K
TQFP48
Tape & Reel
105°C
ATSAM C20G16A-MUT
64K
8K
QFN48
Tape & Reel
85°C
ATSAM C20G16A-MNT
64K
8K
QFN48
Tape & Reel
105°C
Table 3-4. SAM C20E18A Ordering Codes
Ordering Code
3.2.
SAM C20G
Table 3-5. SAM C20G15A Ordering Codes
Ordering Code
Table 3-6. SAM C20G16A Ordering Codes
Ordering Code
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
17
Table 3-7. SAM C20G17A Ordering Codes
Ordering Code
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20G17A-AUT
128K
16K
TQFP48
Tape & Reel
85°C
ATSAM C20G17A-ANT
128K
16K
TQFP48
Tape & Reel
105°C
ATSAM C20G17A-MUT
128K
16K
QFN48
Tape & Reel
85°C
ATSAM C20G17A-MNT
128K
16K
QFN48
Tape & Reel
105°C
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20G18A-AUT
256K
32K
TQFP48
Tape & Reel
85°C
ATSAM C20G18A-ANT
256K
32K
TQFP48
Tape & Reel
105°C
ATSAM C20G18A-MUT
256K
32K
QFN48
Tape & Reel
85°C
ATSAM C20G18A-MNT
256K
32K
QFN48
Tape & Reel
105°C
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20J15A-AUT
32K
4K
TQFP64
Tape & Reel
85°C
ATSAM C20J15A-ANT
32K
4K
TQFP64
Tape & Reel
105°C
ATSAM C20J15A-MUT
32K
4K
QFN64
Tape & Reel
85°C
ATSAM C20J15A-MNT
32K
4K
QFN64
Tape & Reel
105°C
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20J16A-AUT
64K
8K
TQFP64
Tape & Reel
85°C
ATSAM C20J16A-ANT
64K
8K
TQFP64
Tape & Reel
105°C
ATSAM C20J16A-MUT
64K
8K
QFN64
Tape & Reel
85°C
ATSAM C20J16A-MNT
64K
8K
QFN64
Tape & Reel
105°C
Table 3-8. SAM C20G18A Ordering Codes
Ordering Code
3.3.
SAM C20J
Table 3-9. SAM C20J15A Ordering Codes
Ordering Code
Table 3-10. SAM C20J16A Ordering Codes
Ordering Code
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
18
Table 3-11. SAM C20J17A Ordering Codes
Ordering Code
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20J17A-AUT
128K
16K
TQFP64
Tape & Reel
85°C
ATSAM C20J17A-ANT
128K
16K
TQFP64
Tape & Reel
105°C
ATSAM C20J17A-MUT
128K
16K
QFN64
Tape & Reel
85°C
ATSAM C20J17A-MNT
128K
16K
QFN64
Tape & Reel
105°C
FLASH
(bytes)
SRAM
(bytes)
Package
Carrier Type
Temp
ATSAM C20J18A-AUT
256K
32K
TQFP64
Tape & Reel
85°C
ATSAM C20J18A-ANT
256K
32K
TQFP64
Tape & Reel
105°C
ATSAM C20J18A-MUT
256K
32K
QFN64
Tape & Reel
85°C
ATSAM C20J18A-MNT
256K
32K
QFN64
Tape & Reel
105°C
Table 3-12. SAM C20J18A Ordering Codes
Ordering Code
3.4.
Device Identification
The DSU - Device Service Unit peripheral provides the Device Selection bits in the Device Identification
register (DID.DEVSEL) in order to identify the device by software. The SAM C20 variants have a reset
value of DID=0x1101drxx, with the LSB identifying the die number ('d'), the die revision ('r') and the device
selection ('xx').
Table 3-13. SAM C20 Device Identification Values
DEVSEL (DID[7:0])
Device
0x00
SAM C20J18A
0x01
SAM C20J17A
0x02
SAM C20J16A
0x03
SAM C20J15A
0x04
Reserved
0x05
SAM C20G18A
0x06
SAM C20G17A
0x07
SAM C20G16A
0x08
SAM C20G15A
0x09
Reserved
0x0A
SAM C20E18A
0x0B
SAM C20E17A
0x0C
SAM C20E16A
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
19
DEVSEL (DID[7:0])
Device
0x0D
SAM C20E15A
0x0E-0xFF
Reserved
Note: The device variant (last letter of the ordering number) is independent of the die revision
(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks
evolution of the die.
Related Links
DSU - Device Service Unit on page 71
DID on page 95
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
20
Block Diagram
SWCLK
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
SERIAL
WIRE
SWDIO
MICRO
TRACE BUFFER
IOBUS
DEVICE
SERVICE
UNIT
M
DivideAccellerator
S
AHB-APB
BRIDGE B
256/128/64/32KB
8KB RWW
NVM
32/16/8/4KB
RAM
NVM
CONTROLLER
Cache
SRAM
CONTROLLER
M
M
S
S
S
M
HIGH SPEED
BUS MATRIX
S
PERIPHERAL
ACCESS CONTROLLER
DMA
S
AHB-APB
BRIDGE A
AHB-APB
BRIDGE C
MAIN CLOCKS
CONTROLLER
PORT
DMA
4x6SERCOM
x SERCOM
OSCILLATORS CONTROLLER
PAD0
PAD1
PAD2
PAD3
OSC48M
DMA
XOSC
GCLK_IO[7..0]
GENERIC CLOCK
CONTROLLER
WATCHDOG
TIMER
EXTINT[15..0]
NMI
5 x TIMER / COUNTER
8 x Timer Counter
FDPLL96M
EXTERNAL INTERRUPT
CONTROLLER
DMA
TIMER / COUNTER
FOR CONTROL
OSC32K CONTROLLER
XOSC32K
OSCULP32K
WO0
WO1
WOn
AIN[19..0]
DMA
12-CHANNEL
12-bit ADC 1MSPS
POWER
MANAGER
XIN32
XOUT32
WO0
WO1
PORT
XIN
XOUT
EVENT SYSTEM
4.
2 ANALOG
COMPARATORS
VREFA
VREFB
AIN[7..0]
OSC32K
SUPPLY CONTROLLER
BOD55
VREF
PERIPHERAL
TOUCH
CONTROLLER
X[15..0]
Y[15..0]
VREG
RESETN
RESET
CONTROLLER
REAL TIME
COUNTER
FREQUENCY
METER
Note: Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
21
1.
2.
Some products have different number of SERCOM instances, Timer/Counter instances, PTC
signals and ADC signals.
The three TCC instances have different configurations, including the number of Waveform Output
(WO) lines.
Related Links
TCC Configurations on page 31
Multiplexed Signals on page 28
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
22
Pinout
5.1.
SAM C20E
32
31
30
29
28
27
26
25
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESETN
PA27
5.
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
VDDANA
GND
PA08
PA09
PA10
PA11
PA14
PA15
9
10
11
12
13
14
15
16
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
23
48
47
46
45
44
43
42
41
40
39
38
37
PB03
PB02
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESETN
PA27
PB23
PB22
SAM C20G
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
13
14
15
16
17
18
19
20
21
22
23
24
PA00
PA01
PA02
PA03
GNDANA
VDDANA
PB08
PB09
PA04
PA05
PA06
PA07
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PA12
PA13
PA14
PA15
5.2.
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB03
PB02
PB01
PB00
PB31
PB30
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESETN
PA27
PB23
PB22
SAM C20J
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
PA19
PA18
PA17
PA16
VDDIO
GND
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PA00
PA01
PA02
PA03
PB04
PB05
GNDANA
VDDANA
PB06
PB07
PB08
PB09
PA04
PA05
PA06
PA07
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PB12
PB13
PB14
PB15
PA12
PA13
PA14
PA15
5.3.
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
25
6.
Signal Descriptions List
The following table gives details on signal names classified by peripheral.
Table 6-1. Signal Descriptions List
Signal Name
Function
Type
AIN[7:0]
AC Analog Inputs
Analog
CMP[2:0]
AC Comparator Outputs
Digital
AIN[19:0]
ADC Analog Inputs
Analog
VREFA
ADC Voltage External Reference A
Analog
EXTINT[15:0]
External Interrupts inputs
Digital
NMI
External Non-Maskable Interrupt input
Digital
Generic Clock (source clock inputs or generic clock generator
output)
Digital
IN[11:0]
Logic Inputs
Digital
OUT[3:0]
Logic Outputs
Digital
Reset input
Digital
SERCOM Inputs/Outputs Pads
Digital
XIN
Crystal or external clock Input
Analog/Digital
XOUT
Crystal Output
Analog
XIN32
32KHz Crystal or external clock Input
Analog/Digital
XOUT32
32KHz Crystal Output
Analog
Waveform Outputs
Digital
Waveform Outputs
Digital
X[15:0]
PTC Input
Analog
Y[15:0]
PTC Input
Analog
Parallel I/O Controller I/O Port A
Digital
Active Level
Analog Comparators - AC
Analog Digital Converter - ADCx
External Interrupt Controller - EIC
Generic Clock Generator - GCLK
GCLK_IO[7:0]
Custom Control Logic - CCL
Power Manager - PM
RESETN
Low
Serial Communication Interface - SERCOMx
PAD[3:0]
Oscillators Control - OSCCTRL
32KHz Oscillators Control - OSC32KCTRL
Timer Counter - TCx
WO[1:0]
Timer Counter - TCCx
WO[1:0]
Peripheral Touch Controller - PTC
General Purpose I/O - PORT
PA25 - PA00
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
26
Signal Name
Function
Type
PA28 - PA27
Parallel I/O Controller I/O Port A
Digital
PA31 - PA30
Parallel I/O Controller I/O Port A
Digital
PB17 - PB00
Parallel I/O Controller I/O Port B
Digital
PB23 - PB22
Parallel I/O Controller I/O Port B
Digital
PB31 - PB30
Parallel I/O Controller I/O Port B
Digital
Active Level
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
27
7.
I/O Multiplexing and Considerations
7.1.
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions A, B, C, D, E, F, G; H or I. To enable a peripheral function on a
pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A
to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing
register (PMUXn.PMUXE/O) in the PORT.
Table 7-1. PORT Function Multiplexing
Pin
I/O Pin
Supply
C
D
E
F
G
H
I
SERCOM-ALT
TC(4)/TCC
TCC
COM
AC/GCLK
CCL
EXTINT[0]
SERCOM1/
PAD[0]
TCC2/WO[0]
CMP[2]
VDDANA
EXTINT[1]
SERCOM1/
PAD[1]
TCC2/WO[1]
CMP[3]
PA02
VDDANA
EXTINT[2]
PA03
VDDANA
EXTINT[3]
5
PB04
VDDANA
EXTINT[4]
6
PB05
VDDANA
EXTINT[5]
AIN[6]
Y[11]
9
PB06
VDDANA
EXTINT[6]
AIN[7]
Y[12]
CCL2/
IN[6]
10
PB07
VDDANA
EXTINT[7]
Y[13]
CCL2/
IN[7]
7
11
PB08
VDDANA
EXTINT[8]
AIN[2]
Y[14]
TC0/WO[0]
CCL2/
IN[8]
8
12
PB09
VDDANA
EXTINT[9]
AIN[3]
Y[15]
TC0WO[1]
CCL2/
OUT[2]
9
13
PA04
VDDANA
EXTINT[4]
SAM C20G
SAM C20J
1
1
1
PA00
VDDANA
2
2
2
PA01
3
3
3
4
4
4
5
B(1)(2)
SERCOM(1)(2)
SAM C20E
A
EIC
REF
ADC/VREFA
ADC0
AC
AIN[0]
AIN[4]
AIN[1]
AIN[5]
PTC
Y[0]
Y[1]
Y[10]
AIN[4]
AIN[0]
Y[2]
SERCOM0/
PAD[0]
TCC0/WO[0]
CCL0/
IN[0]
VREFB
6
10
14
PA05
VDDANA
EXTINT[5]
AIN[5]
AIN[1]
Y[3]
SERCOM0/
PAD[1]
TCC0/WO[1]
CCL0/
IN[1]
7
11
15
PA06
VDDANA
EXTINT[6]
AIN[6]
AIN[2]
Y[4]
SERCOM0/
PAD[2]
TCC1/WO[0]
CCL0/
IN[2]
8
12
16
PA07
VDDANA
EXTINT[7]
AIN[7]
AIN[3]
Y[5]
SERCOM0/
PAD[3]
TCC1/WO[1]
CCL0/
OUT[0]
11
13
17
PA08
VDDIO
NMI
AIN[8]
X[0]/Y[16]
SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TCC0/WO[0]
TCC1/
WO[2]
CCL1/
IN[3]
12
14
18
PA09
VDDIO
EXTINT[9]
AIN[9]
X[1]/Y[17]
SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TCC0/WO[1]
TCC1/
WO[3]
CCL1/
IN[4]
13
15
19
PA10
VDDIO
EXTINT[10]
AIN[10]
X[2]/Y[18]
SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TCC1/WO[0]
TCC0/
WO[2]
GCLK_IO[4]
CCL1/
IN[5]
14
16
20
PA11
VDDIO
EXTINT[11]
AIN[11]
X[3]/Y[19]
SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TCC1/WO[1]
TCC0/
WO[3]
GCLK_IO[5]
CCL1/
OUT[1]
19
23
PB10
VDDIO
EXTINT[10]
TC1/WO[0]
TCC0/
WO[4]
GCLK_IO[4]
CCL1/
IN[5]
20
24
PB11
VDDIO
EXTINT[11]
TC1/WO[1]
TCC0/
WO[5]
GCLK_IO[5]
CCL1/
OUT[1]
25
PB12
VDDIO
EXTINT[12]
X[12]/Y[28]
TC0/WO[0]
TCC0/
WO[6]
GCLK_IO[6]
26
PB13
VDDIO
EXTINT[13]
X[13]/Y[29]
TC0/WO[1]
TCC0/
WO[7]
GCLK_IO[7]
27
PB14
VDDIO
EXTINT[14]
X[14]/Y[30]
TC1/WO[0]
GCLK_IO[0]
CCL3/
IN[9]
28
PB15
VDDIO
EXTINT[15]
X[15]/Y[31]
TC1/WO[1]
GCLK_IO[1]
CCL3/
IN[10]
21
29
PA12
VDDIO
EXTINT[12]
SERCOM2/
PAD[0]
TCC2/WO[0]
TCC0/
WO[6]
AC/CMP[0]
22
30
PA13
VDDIO
EXTINT[13]
SERCOM2/
PAD[1]
TCC2/WO[1]
TCC0/
WO[7]
AC/CMP[1]
15
23
31
PA14
VDDIO
EXTINT[14]
SERCOM2/
PAD[2]
TC4/WO[0]
TCC0/
WO[4]
GCLK_IO[0]
16
24
32
PA15
VDDIO
EXTINT[15]
SERCOM2/
PAD[3]
TC4/WO[1]
TCC0/
WO[5]
GCLK_IO[1]
17
25
35
PA16
VDDIO
EXTINT[0]
TCC2/WO[0]
TCC0/
WO[6]
GCLK_IO[2]
X[4]/Y[20]
SERCOM1/
PAD[0]
SERCOM3/
PAD[0]
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
CCL0/
IN[0]
28
Pin
I/O Pin
Supply
B(1)(2)
C
D
E
F
G
H
I
PTC
SERCOM(1)(2)
SERCOM-ALT
TC(4)/TCC
TCC
COM
AC/GCLK
CCL
EXTINT[1]
X[5]/Y[21]
SERCOM1/
PAD[1]
SERCOM3/
PAD[1]
TCC2/WO[1]
TCC0/
WO[7]
GCLK_IO[3]
CCL0/
IN[1]
VDDIO
EXTINT[2]
X[6]/Y[22]
SERCOM1/
PAD[2]
SERCOM3/
PAD[2]
TC4/WO[0]
TCC0/
WO[2]
AC/CMP[0]
CCL0/
IN[2]
PA19
VDDIO
EXTINT[3]
X[7]/Y[23]
SERCOM1/
PAD[3]
SERCOM3/
PAD[3]
TC4/WO[1]
TCC0/
WO[3]
AC/CMP[1]
CCL0/
OUT[0]
39
PB16
VDDIO
EXTINT[0]
TC2/WO[0]
TCC0/
WO[4]
GCLK_IO[2]
CCL3/
IN[11]
40
PB17
VDDIO
EXTINT[1]
TC2/WO[1]
TCC0/
WO[5]
GCLK_IO[3]
CCL3/
OUT[3]
29
41
PA20
VDDIO
EXTINT[4]
X[8]/Y[24]
SERCOM3/
PAD[2]
TC3/WO[0]
TCC0/
WO[6]
GCLK_IO[4]
30
42
PA21
VDDIO
EXTINT[5]
X[9]/Y[25]
SERCOM3/
PAD[3]
TC3/WO[1]
TCC0/
WO[7]
GCLK_IO[5]
21
31
43
PA22
VDDIO
EXTINT[6]
X[10]/Y[26]
SERCOM3/
PAD[0]
TC0/WO[0]
TCC0/
WO[4]
GCLK_IO[6]
CCL2/
IN[6]
22
32
44
PA23
VDDIO
EXTINT[7]
X[11]/Y[27]
SERCOM3/
PAD[1]
TC0/WO[1]
TCC0/
WO[5]
GCLK_IO[7]
CCL2/
IN[7]
23
33
45
PA24
VDDIO
EXTINT[12]
SERCOM3/
PAD[2]
TC1/WO[0]
TCC1/
WO[2]
AC/CMP[2]
CCL2/
IN[8]
24
34
46
PA25
VDDIO
EXTINT[13]
SERCOM3/
PAD[3]
TC1/WO[1]
TCC1/
WO[3]
AC/CMP[3]
CCL2/
OUT[2]
37
49
PB22
VDDIN
EXTINT[6]
TC3/WO[0]
GCLK_IO[0]
CCL0/
IN[0]
38
50
PB23
VDDIN
EXTINT[7]
TC3/WO[1]
GCLK_IO[1]
CCL0/
OUT[0]
25
39
51
PA27
VDDIN
EXTINT[15]
27
41
53
PA28
VDDIN
EXTINT[8]
31
45
57
PA30
VDDIN
EXTINT[10]
SERCOM1/
PAD[2]
TCC1/WO[0]
CORTEX_M0P/
SWCLK
32
46
58
PA31
VDDIN
EXTINT[11]
SERCOM1/
PAD[3]
TCC1/WO[1]
CORTEX_M0P/
SWDIO
59
PB30
VDDIN
EXTINT[14]
TCC0/WO[0]
TCC1/
WO[2]
AC/CMP[2]
60
PB31
VDDIN
EXTINT[15]
TCC0/WO[1]
TCC1/
WO[3]
AC/CMP[3]
61
PB00
VDDANA
EXTINT[0]
Y[6]
TC3/WO[0]
CCL0/
IN[1]
62
PB01
VDDANA
EXTINT[1]
Y[7]
TC3/WO[1]
CCL0/
IN[2]
47
63
PB02
VDDANA
EXTINT[2]
Y[8]
TC2/WO[0]
CCL0/
OUT[0]
48
64
PB03
VDDANA
EXTINT[3]
Y[9]
TC2/WO[1]
SAM C20E
SAM C20G
SAM C20J
18
26
36
PA17
VDDIO
19
27
37
PA18
20
28
38
1.
2.
3.
A
EIC
REF
ADC0
AC
BRK
GCLK_IO[0]
GCLK_IO[0]
GCLK_IO[0]
CCL1/
IN[3]
CCL1/
OUT[1]
All analog pin functions are on peripheral function B. Peripheral function B must be selected to
disable the digital control of the pin.
Only some pins can be used in SERCOM I2C mode. Refer to SERCOM I2C Pins.
TC2 and TC3 not supported on the SAM C20E/G.
Related Links
SERCOM I2C Pins on page 30
7.2.
Other Functions
7.2.1.
Oscillator Pinout
The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by
registers in the Oscillators Controller (OSCCTRL) and in the 32K Oscillators Controller (OSC32KCTRL).
Table 7-2. Oscillator Pinout
Oscillator
Supply
Signal
I/O pin
XOSC
VDDIO
XIN
PA14
XOUT
PA15
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
29
7.2.2.
Oscillator
Supply
Signal
I/O pin
XOSC32K
VDDANA
XIN32
PA00
XOUT32
PA01
Serial Wire Debug Interface Pinout
Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging
detection will automatically switch the SWDIO port to the SWDIO function.
Table 7-3. Serial Wire Debug Interface Pinout
7.2.3.
Signal
Supply
I/O pin
SWCLK
VDDIN
PA30
SWDIO
VDDIN
PA31
SERCOM I2C Pins
Table 7-4. SERCOM Pins Supporting I2C
7.2.4.
Device
Pins Supporting I2C Hs mode
SAM C20E
PA08, PA09, PA10, PA11, PA16, PA17, PA22, PA23
SAM C20G
PA08, PA09, PA10, PA11, PA12, PA13, PA16, PA17, PA22, PA23, PB10, PB11
SAM C20J
PA08, PA09, PA10, PA11, PA12, PA13, PA16, PA17, PA22, PA23, PB10, PB11,
PB12, PB13, PB16, PB17, PB30, PB31
GPIO Clusters
Table 7-5. GPIO Clusters
Package Cluster GPIO
Supplies Pin connected to the cluster
64 pins
1
PB31 PB30 PA31 PA30 PA28 PA27
VDDIN (56)
GND (54)
2
PB23 PB22
VDDIO (48)
GND (54+47)
3
PA25 PA24 PA23 PA22 PA21 PA20 PB17
PB16 PA19 PA18 PA17 PA16
VDDIO (48+34)
GND (47+33)
4
PA15 PA14 PA13 PA12 PB15 PB14 PB13 VDDIO (34+21)
PB12 PB11 PB10
GND (33+22)
5
PA11 PA10 PA08 PA09
GND (22)
6
PA07 PA06 PA05 PA04 PB09 PB08 PB07 VDDANA (8)
PB06 PB05 PB04 PA03 PA02 PA01 PA00
PB03 PB02 PB01 PB00
VDDIO (21)
GNDANA (7)
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
30
Package Cluster GPIO
Supplies Pin connected to the cluster
48 pins
32 pins
7.2.5.
1
PA31 PA30 PA28 PA27
VDDIN (44)
GND (42)
2
PB23 PB22
VDDIO (36)
GND (42+35)
3
PA25 PA24 PA23 PA22 PA21 PA20 PA19
PA18 PA17 PA16 PA15 PA14 PA13 PA12
PB11 PB10
VDDIO (36+17)
GND (35+18)
4
PA11 PA10 PA08 PA09
VDDIO (17)
GND (18)
5
PA07 PA06 PA05 PA04 PB09 PB08 PA03
PA02 PA01 PA00 PB03 PB02
VDDANA (6)
GNDANA (5)
1
PA31 PA30 PA28 PA27
VDDIN (30)
GND (28)
2
PA25 PA24 PA23 PA22 PA19 PA18 PA17
PA16 PA15 PA14 PA11 PA10 PA08 PA09
VDDIO (9)
GND (28+10)
3
PA07 PA06 PA05 PA04 PA03 PA02 PA01
PA00
VDDANA (9)
GND (28+10)
TCC Configurations
The SAM C20 has three instances of the Timer/Counter for Control applications (TCC) peripheral, ,
TCC[2:0]. The following table lists the features for each TCC instance.
Table 7-6. TCC Configuration Summary
TCC#
Channels
(CC_NUM)
Waveform
Output
(WO_NUM)
Counter
size
Fault
Dithering
Output
matrix
Dead Time
Insertion
(DTI)
SWAP
Pattern
generation
0
4
8
24-bit
Yes
Yes
Yes
Yes
Yes
Yes
1
2
4
24-bit
Yes
Yes
2
2
2
16-bit
Yes
Yes
Note: The number of CC registers (CC_NUM) for each TCC corresponds to the number of compare/
capture channels, so that a TCC can have more Waveform Outputs (WO_NUM) than CC registers.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
31
VDDIO
PA[31:27]
PB[31:22]
GND
VDDIN
Power Domain Overview
VDDCORE
8.1.
GNDANA
Power Supply and Start-Up Considerations
VDDANA
8.
ADC
PA[7:2]
PB[9:0]
Voltage
Regulator
AC
PTC
POR
BOD50
OSCULP32K
OSC32K
PA[1:0]
Digital Logic
(CPU, PD1
Peripherals)
Digital Logic
SERCOM[4:0],
TCC[2:0]
DPLL
TC[3:0], DAC,
I2S,
AES,
TRNG
LOW POWER
NVM
PAC,
DMAC
RAM
XOSC32K
POR
XOSC
PB[17:10]
PA[25:8]
HIGHPOWER
SPEED
LOW
RAM
Power Supply Considerations
8.2.1.
Power Supplies
The SAM C20 has several different power supply pins:
•
TOSC
BODCORE
8.2.
•
•
•
OSC48M
VDDIO: Powers I/O lines and XOSC. Voltage is 2.70V to 5.50V.
VDDIN: Powers I/O lines and the OSC48M, TOSC and internal regulator. Voltage is 2.70V to 5.50V.
VDDANA: Powers I/O lines and the ADC, AC, PTC, OSCULP32K, OSC32K and XOSC32K.
Voltage is 2.70V to 5.50V.
VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, and
FDPLL96M. Voltage is 1.2V typical.
The same voltage must be applied to both VDDIN and VDDANA. This common voltage is referred to as
VDD in the datasheet. VDDIO must always be less than or equal to VDDIN.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
32
The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is
GNDANA.
For decoupling recommendations for the different power supplies, refer to the schematic checklist.
8.2.2.
Voltage Regulator
The SAM C20 voltage regulator has two different modes:
•
•
8.2.3.
Normal mode: This is the default mode when CPU and peripherals are running
Low Power (LP) mode: This is the default mode used when the chip is in standby mode.
Typical Powering Schematics
The SAM C20 uses a single supply from 2.70V to 5.50V or dual supply mode where VDDIO is supplied
separately from VDDIN.
The following figures show the recommended power supply connections.
Figure 8-1. Power Supply Connection for single supply mode only
Main Supply
(2.70V - 5.50V)
VDDIO
VDDANA
VDDIN
VDDCORE
GND
GNDANA
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
33
Power Supply Connection for dual supply mode
IO Supply
(2.70V - 5.50V)
Main Supply
(2.70V - 5.50V)
8.2.4.
Power-Up Sequence
8.2.4.1.
Minimum Rise Rate
The integrated power-on reset (POR) circuitry monitoring the VDDIN power supply requires a minimum
rise rate.
8.2.4.2.
Maximum Rise Rate
The rise rate of the power supply must not exceed the values described in Electrical Characteristics.
8.3.
Power-Up
This section summarizes the power-up sequence of the SAM C20. The behavior after power-up is
controlled by the Power Manager.
8.3.1.
Starting of Clocks
After power-up, the device is set to its initial state and kept in reset, until the power has stabilized
throughout the device. Once the power has stabilized, the device will use a 4MHz clock. This clock is
derived from the 48MHz Internal Oscillator (OSC48M), which is configured to provide a 4MHz clock and
used as a clock source for generic clock generator 0. Generic clock generator 0 is the main clock for the
Power Manager (PM).
Some synchronous system clocks are active, allowing software execution.
Refer to the “Clock Mask Register” in the Power Manager for the list of default peripheral clocks running.
Synchronous system clocks that are running are by default not divided and receive a 4MHz clock through
generic clock generator 0. Other generic clocks are disabled.
8.3.2.
I/O Pins
After power-up, the I/O pins are tri-stated.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
34
8.3.3.
Fetching of Initial Instructions
After reset has been released, the CPU starts fetching PC and SP values from the reset address, which is
0x00000000. This address points to the first executable address in the internal flash. The code read from
the internal flash is free to configure the clock system and clock sources. Refer to the ARM Architecture
Reference Manual for more information on CPU startup (http://www.arm.com).
8.4.
Power-On Reset and Brown-Out Detector
The SAM C20 embeds three features to monitor, warn and/or reset the device:
•
•
•
POR: Power-on reset on VDDIN and VDDIO
BODVDD: Brown-out detector on VDDIN
BODCORE: Voltage Regulator Internal Brown-out detector on VDDCORE. The Voltage Regulator
Internal BOD is calibrated in production and its calibration configuration is stored in the NVM User
Row. This configuration should not be changed if the user row is written to assure the correct
behavior of the BODCORE.
8.4.1.
Power-On Reset on VDDIN
POR monitors VDDIN. It is always activated and monitors voltage at startup and also during all the sleep
modes. If VDDIN goes below the threshold voltage, the entire chip is reset.
8.4.2.
Power-On Reset on VDDIO
POR monitors VDDIO. It is always activated and monitors voltage at startup and also during all the sleep
modes. If VDDIO goes below the threshold voltage, all IOs supplied by VDDIO are reset.
8.4.3.
Brown-Out Detector on VDDIN
BODVDD monitors VDDIN.
8.4.4.
Brown-Out Detector on VDDCORE
Once the device has started up, BODCORE monitors the internal VDDCORE.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
35
9.
Product Mapping
Figure 9-1. SAM C20 Product Mapping
Global Memory Space
0x00000000
Code
0x00000000
Internal Flash
Code
0x20000000
Reserved
SRAM
Undefined
0x40000000
SRAM
Internal SRAM
0x20008000
0x48000200
Reserved
0x60000000
0x40000000
0x60000400
Reserved
0x40000C00
0x40001000
0x40001400
0x40001800
0x40001C00
0x40002000
PM
0x40003000
0x40003400
0x40FFFFFF
AHB-APB
Bridge B
0x42002400
0x42002000
0x42002800
0x43000000
RSTC
OSCCTRL
OSC32KCTRL
SUPC
GCLK
WDT
EIC
FREQM
Reserved
0x42002C00
0x42003000
Reserved
0x48000000
0x42003400
0x42003800
AHB
DIVAS
MCLK
RTC
0x40002C00
0x42001C00
AHB-APB
Bridge C
PAC
0x40002400
0x40002800
AHB-APB
Bridge A
0x42000000
AHB-APB Bridge A
0x40000800
0x42001800
0x41000000
0xFFFFFFFF
0x40000400
0x42001000
0x42001400
AHB-APB
IOBUS
0x42000800
0x42000C00
0x20000000
Peripherals
0x42000000
0x42000400
0x1FFFFFFF
0x22008000
0x40000000
AHB-APB Bridge C
0x00400000
0x42003C00
0x480001FF
0x42004000
AHB-APB Bridge B
0x41000000
0x41002000
0x41004000
0x41006000
0x41008000
0x41009000
0x42004400
PORT
0x42004800
DSU
0x42004C00
NVMCTRL
0x42005000
DMAC
0x42005400
MTB
0x42005800
Reserved
0x42005C00
0x41FFFFFF
EVSYS
SERCOM0
SERCOM1
SERCOM2
SERCOM3
Reserved
Reserved
Reserved
Reserved
TCC0
Reserved
Reserved
TC0
TC1
TC2
TC3
TC4
ADC0
Reserved
Reserved
AC
Reserved
PTC
CCL
0x42006000
0x42FFFFFF
Reserved
Reserved
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
36
10.
Memories
10.1.
Embedded Memories
•
•
10.2.
Internal high-speed flash with Read-While-Write capability on section of the array
Internal high-speed RAM, single-cycle access at full speed
Physical Memory Map
The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they
are never remapped in any way, even during boot. The 32-bit physical address space is mapped as
follow:
Table 10-1. SAM C20 Physical Memory Map(1)
Memory
Start address
Size
Size
Size
Size
SAM C20x18 SAM C20x17 SAM C20x16 SAM C20x15
Embedded Flash
0x00000000
256Kbytes
128Kbytes
64Kbytes
32Kbytes
Embedded RWW section
0x00400000
8Kbytes
4Kbytes
2Kbytes
1Kbytes
Embedded high-speed
SRAM
0x20000000
32Kbytes
16Kbytes
8Kbytes
4Kbytes
AHB-APB Bridge A
0x40000000
64Kbytes
64Kbytes
64Kbytes
64Kbytes
AHB-APB Bridge B
0x41000000
64Kbytes
64Kbytes
64Kbytes
64Kbytes
AHB-APB Bridge C
0x42000000
64Kbytes
64Kbytes
64Kbytes
64Kbytes
AHB DIVAS
0x48000000
64Kbytes
64Kbytes
64Kbytes
64Kbytes
IOBUS
0x60000000
64Kbytes
64Kbytes
64Kbytes
64Kbytes
Note: 1. x = G, J or E.
Table 10-2. Flash Memory Parameters(1)
Device
Flash size (FLASH_PM)
Number of pages (FLASH_P)
Page size (FLASH_W)
SAM C20x18
256Kbytes
4096
64 bytes
SAM C20x17
128Kbytes
2046
64 bytes
SAM C20x16
64Kbytes
1024
64 bytes
SAM C20x15
32Kbytes
512
64 bytes
Flash size (FLASH_PM)
Number of pages (FLASH_P)
Page size (FLASH_W)
SAM C20x18
8Kbytes
128
64 bytes
SAM C20x17
4Kbytes
64
64 bytes
Note: 1. x = G, J or E .
Table 10-3. RWW Section Parameters(1)
Device
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
37
Device
Flash size (FLASH_PM)
Number of pages (FLASH_P)
Page size (FLASH_W)
SAM C20x16
2Kbytes
32
64 bytes
SAM C20x15
1Kbytes
16
64 bytes
Note: 1. x = G, J or E .
10.3.
NVM User Row Mapping
The NVM User Row contains calibration data that are automatically read at device power on.
The NVM User Row can be read at address 0x804000.
To write the NVM User Row, refer to the NVMCTRL - Non-Volatile Memory Controller.
Note that when writing to the user row the values do not get loaded by the other modules on the device
until a device reset occurs.
Table 10-4. NVM User Row Mapping
Bit Position Name
Usage
Production
setting
Related Peripheral
Register
2:0
BOOTPROT
Used to select one of eight
different bootloader sizes.
7
NVMCTRL
3
Reserved
-
1
-
6:4
EEPROM
Used to select one of eight
different EEPROM sizes.
7
NVMCTRL
7
Reserved
-
1
-
13:8
BODVDD Level
BODVDD Threshold Level at
power on.
8
SUPC.BODVDD
14
BODVDD Disable BODVDD Disable at power on.
0
SUPC.BODVDD
16:15
BODVDD Action
BODVDD Action at power on.
1
SUPC.BODVDD
25:17
Reserved
Voltage Regulator Internal
BOD (BODCORE)
configuration. These bits are
written in production and must
not be changed.
0xA8
26
WDT Enable
WDT Enable at power on.
0
WDT.CTRLA
27
WDT Always-On
WDT Always-On at power on.
0
WDT.CTRLA
31:28
WDT Period
WDT Period at power on.
0xB
WDT.CONFIG
35:32
WDT Window
WDT Window mode time-out at
power on.
0xB
WDT.CONFIG
39:36
WDT
EWOFFSET
WDT Early Warning Interrupt
Time Offset at power on.
0xB
WDT.EWCTRL
-
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Bit Position Name
Usage
Production
setting
40
WDT WEN
WDT Timer Window Mode
Enable at power on.
0
WDT.CTRLA
41
BODVDD
Hysteresis
BODVDD Hysteresis
configuration at power on.
0
SUPC.BODVDD
42
Reserved
Voltage Regulator Internal
BOD (BODCORE)
configuration. These bits are
written in production and must
not be changed.
0
-
47:43
Reserved
-
0x1F
-
63:48
LOCK
NVM Region Lock Bits.
0xFFFF
Related Peripheral
Register
NVMCTRL
Related Links
NVMCTRL – Non-Volatile Memory Controller on page 430
CTRLA on page 281
CONFIG on page 283
EWCTRL on page 285
BODVDD on page 266
10.4.
NVM Software Calibration Area Mapping
The NVM Software Calibration Area contains calibration data that are measured and written during
production test. These calibration values should be read by the application software and written back to
the corresponding register.
The NVM Software Calibration Area can be read at address 0x806020.
The NVM Software Calibration Area can not be written.
Table 10-5. NVM Software Calibration Area Mapping
Bit Position Name
Description
2:0
ADC0 LINEARITY ADC0 Linearity Calibration. Should be written to the CALIB register.
5:3
ADC0 BIASCAL
11:6
Reserved
18:12
OSC32K CAL
OSC32K Calibration. Should be written to OSC32K register.
40:19
CAL48M 5V
OSC48M Calibration: VDD range 3.6V to 5.5V. Should be written to
the CAL48M register.
62:41
CAL48M 3V3
OSC48M Calibration: VDD range 2.7V to 3.6V. Should be written to
the CAL48M register.
63
Reserved
ADC0 Bias Calibration. Should be written to the CALIB register.
Related Links
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CAL48M on page 224
10.5.
Serial Number
Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained
at the following addresses:
Word 0: 0x0080A00C
Word 1: 0x0080A040
Word 2: 0x0080A044
Word 3: 0x0080A048
The uniqueness of the serial number is guaranteed only when using all 128 bits.
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11.
Processor and Architecture
11.1.
Cortex M0+ Processor
®
™
The Atmel SAM C20 implements the ARM Cortex -M0+ processor, based on the ARMv6 Architecture
®
and Thumb -2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the CortexM0 core, and upward compatible to Cortex-M3 and M4 cores. The implemented ARM Cortex-M0+ is
revision r0p1. For more information refer to http://www.arm.com.
11.1.1.
Cortex M0+ Configuration
Table 11-1. Cortex M0+ Configuration
Features
Cortex-M0+ options
SAM C20 configuration
Interrupts
External interrupts 0-32
32
Data endianness
Little-endian or big-endian
Little-endian
SysTick timer
Present or absent
Present
Number of watchpoint comparators
0, 1, 2
2
Number of breakpoint comparators
0, 1, 2, 3, 4
4
Halting debug support
Present or absent
Present
Multiplier
Fast or small
Fast (single cycle)
Single-cycle I/O port
Present or absent
Present
Wake-up interrupt controller
Supported or not supported
Not supported
Vector Table Offset Register
Present or absent
Present
Unprivileged/Privileged support
Present or absent
Present
Memory Protection Unit
Not present or 8-region
8-region
Reset all registers
Present or absent
Absent
Instruction fetch width
16-bit only or mostly 32-bit
32-bit
The ARM Cortex-M0+ core has two bus interfaces:
•
•
11.1.2.
Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all
system memory, which includes flash and RAM.
Single 32-bit I/O port bus interfacing to the PORT and DIVAS with 1-cycle loads and stores.
Cortex-M0+ Peripherals
•
•
System Control Space (SCS)
– The processor provides debug through registers in the SCS. Refer to the Cortex-M0+
Technical Reference Manual for details (http://www.arm.com).
Nested Vectored Interrupt Controller (NVIC)
– External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts.
Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core
are closely coupled, providing low latency interrupt processing and efficient processing of late
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•
•
•
•
11.1.3.
arriving interrupts. Refer to Nested Vector Interrupt Controller and the Cortex-M0+ Technical
Reference Manual for details (http://www.arm.com).
System Timer (SysTick)
– The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both
the processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details
(http://www.arm.com).
System Control Block (SCB)
– The System Control Block provides system implementation information, and system control.
This includes configuration, control, and reporting of the system exceptions. Refer to the
Cortex-M0+ Devices Generic User Guide for details (http://www.arm.com).
Micro Trace Buffer (MTB)
– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the CortexM0+ processor. Refer to section Micro Trace Buffer and the CoreSight MTB-M0+ Technical
Reference Manual for details (http://www.arm.com).
Memory Protection Unit (MPU)
– The Memory Protection Unit divides the memory map into a number of regions, and defines
the location, size, access permissions and memory attributes of each region. Refer to the
Cortex-M0+ Devices Generic User Guide for details (http://www.arm.com)
Cortex-M0+ Address Map
Table 11-2. Cortex-M0+ Address Map
Address
Peripheral
0xE000E000
System Control Space (SCS)
0xE000E010
System Timer (SysTick)
0xE000E100
Nested Vectored Interrupt Controller (NVIC)
0xE000ED00
System Control Block (SCB)
0x41008000
Micro Trace Buffer (MTB)
Related Links
Product Mapping on page 36
11.1.4.
I/O Interface
11.1.4.1. Overview
Because accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently,
the Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables single
cycle I/O accesses to be sustained for as long as needed.
Related Links
CPU Local Bus on page 458
11.1.4.2. Description
Direct access to PORT registers and DIVAS registers.
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11.2.
Nested Vector Interrupt Controller
11.2.1.
Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM C20 supports 32 interrupt lines with four
different priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (http://
www.arm.com).
11.2.2.
Interrupt Line Mapping
Each of the interrupt lines is connected to one peripheral instance, as shown in the table below. Each
peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear
(INTFLAG) register.
The interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be
individually enabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set
(INTENSET) register, and disabled by writing a one to the corresponding bit in the peripheral’s Interrupt
Enable Clear (INTENCLR) register.
An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding
interrupt is enabled.
The interrupt requests for one peripheral are ORed together on system level, generating one interrupt
request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the
NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/
CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for
each interrupt.
Table 11-3. Interrupt Line Mapping
Peripheral Source
EIC NMI – External Interrupt Controller
PM – Power Manager
MCLK - Main Clock
NVIC Line
NMI
0
OSCCTRL - Oscillators Controller
OSC32KCTRL - 32kHz Oscillators Controller
SUPC - Supply Controller
PAC - Protection Access Controller
WDT – Watchdog Timer
1
RTC – Real Time Clock
2
EIC – External Interrupt Controller
3
FREQM – Frequency Meter
4
Reserved
5
NVMCTRL – Non-Volatile Memory Controller
6
DMAC - Direct Memory Access Controller
7
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Peripheral Source
NVIC Line
EVSYS – Event System
8
SERCOM0 – Serial Communication Controller 0
9
SERCOM1 – Serial Communication Controller 1
10
SERCOM2 – Serial Communication Controller 2
11
SERCOM3 – Serial Communication Controller 3
12
Reserved
13
Reserved
14
Reserved
15
Reserved
16
TCC0 – Timer Counter for Control 0
17
TCC1 – Timer Counter for Control 1
18
TCC2 – Timer Counter for Control 2
19
TC0 – Timer Counter 0
20
TC1 – Timer Counter 2
21
TC2 – Timer Counter 2
22
Reserved
23
Reserved
24
ADC0 – Analog-to-Digital Converter 0
25
Reserved
26
AC – Analog Comparator
27
Reserved
28
Reserved
29
PTC – Peripheral Touch Controller
30
Reserved
31
11.3.
Micro Trace Buffer
11.3.1.
Features
•
•
•
•
Program flow tracing for the Cortex-M0+ processor
MTB SRAM can be used for both trace and general purpose storage by the processor
The position and size of the trace buffer in SRAM is configurable by software
CoreSight compliant
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11.3.2.
Overview
When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over
the execution trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+.
This information is stored as trace packets in the SRAM by the MTB. An off-chip debugger can extract the
trace information using the Debug Access Port to read the trace information from the SRAM. The
debugger can then reconstruct the program flow from this information.
The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the
SRAM. The MTB ensures that trace write accesses have priority over processor accesses.
The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the
processor PC value changes non-sequentially. A non-sequential PC change can occur during branch
instructions or during exception entry. See the CoreSight MTB-M0+ Technical Reference Manual for more
details on the MTB execution trace packet format.
Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various
ways to set the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical
Reference Manual for more details on the Trace start and stop and for a detailed description of the MTB’s
MASTER register. The MTB can be programmed to stop tracing automatically when the memory fills to a
specified watermark level or to start or stop tracing by writing directly to the MASTER.EN bit. If the
watermark mechanism is not being used and the trace buffer overflows, then the buffer wraps around
overwriting previous trace packets.
The base address of the MTB registers is 0x41008000; this address is also written in the CoreSight ROM
Table. The offset of each register from the base address is fixed and as defined by the CoreSight MTBM0+ Technical Reference Manual. The MTB has 4 programmable registers to control the behavior of the
trace features:
•
•
•
•
POSITION: Contains the trace write pointer and the wrap bit,
MASTER: Contains the main trace enable bit and other trace control fields,
FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,
BASE: Indicates where the SRAM is located in the processor memory map. This register is
provided to enable auto discovery of the MTB SRAM location, by a debug agent.
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
11.4.
High-Speed Bus System
11.4.1.
Features
High-Speed Bus Matrix has the following features:
•
•
•
•
Symmetric crossbar bus switch implementation
Allows concurrent accesses from different masters to different slaves
32-bit data bus
Operation at a 1-to-1 clock frequency with the bus masters
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Configuration
Figure 11-1. Master-Slave Relation High-Speed Bus Matrix
High-Speed Bus SLAVES
Multi-Slave
MASTERS
CM0+
0
DSU
DSU
1
DSUData
DMAC
2
DMAC Fetch
DMAC Data
DSU
CM0+
DIVAS
7
DMAC WB
AHB-APB Bridge C
5
Reserved
AHB-APB Bridge B
4
Reserved
AHB-APB Bridge A
3
MTB
Internal Flash
FlexRAM
0
MASTER ID
Priviledged
FlexRAM-access
MASTERS
11.4.2.
9
8
7
5-6
3-4
6
2
2
1
1
0
SLAVE ID
FlexRAM PORT ID
MTB
DMAC WB
DMAC Fetch
Table 11-4. Bus Matrix Masters
Bus Matrix Masters
Master ID
CM0+ - Cortex M0+ Processor
0
DSU - Device Service Unit
1
DMAC - Direct Memory Access Controller / Data Access
2
Table 11-5. Bus Matrix Slaves
Bus Matrix Slaves
Slave ID
Internal Flash Memory
0
SRAM Port 4 - CM0+ Access
1
SRAM Port 6 - DSU Access
2
AHB-APB Bridge A
3
AHB-APB Bridge B
4
AHB-APB Bridge C
5
SRAM Port 5 - DMAC Data Access
6
DIVAS - Divide Accelerator
7
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Table 11-6. SRAM Port Connections
SRAM Port Connection
11.4.3.
Port ID
Connection Type
CM0+ - Cortex M0+ Processor
0
Bus Matrix
DSU - Device Service Unit
1
Bus Matrix
DMAC - Direct Memory Access Controller - Data Access
2
Bus Matrix
DMAC - Direct Memory Access Controller - Fetch Access 0
3
Direct
DMAC - Direct Memory Access Controller - Fetch Access 1
4
Direct
DMAC - Direct Memory Access Controller - Write-Back Access 0
5
Direct
DMAC - Direct Memory Access Controller - Write-Back Access 1
6
Direct
Reserved
7
Direct
Reserved
8
Direct
MTB - Micro Trace Buffer
9
Direct
SRAM Quality of Service
To ensure that masters with latency requirements get sufficient priority when accessing RAM, the different
masters can be configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any
access to the RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit
values for the QoS level configuration is shown in below.
Table 11-7. Quality of Service Level Configuration
Value
Name
0x0
DISABLE
0x1
LOW
0x2
MEDIUM
0x3
HIGH
Description
Background (no sensitive operation)
Sensitive Bandwidth
Sensitive Latency
Critical Latency
If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be minimum latency of
one cycle for the RAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master
and second, a static priority given by Table 11-6 SRAM Port Connections. The lowest port ID has the
highest static priority.
The MTB has fixed QoS level HIGH (0x3) and the DSU has fixed QoS level LOW (0x1).
The CPU QoS level can be written/read at address 0x41007110, bits [1:0]. Its reset value is 0x0.
Refer to different master QOSCTRL registers for configuring QoS for the other masters (DMAC).
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12.
PAC - Peripheral Access Controller
12.1.
Overview
The Peripheral Access Controller provides an interface for the locking and unlocking of peripheral
registers within the device. It reports all violations that could happen when accessing a peripheral: write
protected access, illegal access, enable protected access, access when clock synchronization or
software reset is on-going. These errors are reported in a unique interrupt flag for a peripheral. The PAC
module also reports errors occurring at the slave bus level, when an access to a non-existing address is
detected.
12.2.
Features
•
12.3.
Manages write protection access and reports access errors for the peripheral modules or bridges
Block Diagram
Figure 12-1. PAC Block Diagram
PAC
IRQ
Slave ERROR
SLAVEs
INTFLAG
APB
Peripheral ERROR
PERIPHERAL m
BUSn
WRITE CONTROL
PAC CONTROL
PERIPHERAL 0
Peripheral ERROR
PERIPHERAL m
BUS0
WRITE CONTROL
12.4.
PERIPHERAL 0
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
12.4.1.
IO Lines
Not applicable.
12.4.2.
Power Management
The PAC can continue to operate in any sleep mode where the selected source clock is running. The PAC
interrupts can be used to wake up the device from sleep modes. The events can trigger other operations
in the system without exiting sleep modes.
Related Links
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
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PM – Power Manager on page 177
12.4.3.
Clocks
The PAC bus clock (CLK_PAC_APB) can be enabled and disabled in the Main Clock module. The default
state of CLK_PAC_APB can be found in the related links.
Related Links
MCLK – Main Clock on page 149
Peripheral Clock Masking on page 152
12.4.4.
DMA
Not applicable.
12.4.5.
Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the PAC interrupt requires the
Interrupt Controller to be configured first.
Table 12-1. Interrupt Lines
Instances
NVIC Line
PAC
PACERR
Related Links
Nested Vector Interrupt Controller on page 43
12.4.6.
Events
The events are connected to the Event System, which may need configuration.
Related Links
EVSYS – Event System on page 487
12.4.7.
Debug Operation
When the CPU is halted in debug mode, write protection of all peripherals is disabled and the PAC
continues normal operation.
12.4.8.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except the following registers:
•
•
Write Control (WRCTRL) register
AHB Slave Bus Interrupt Flag Status and Clear (INTFLAGAHB) register
•
Peripheral Interrupt Flag Status and Clear n (INTFLAG A/B/C...) registers
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
12.5.
Functional Description
12.5.1.
Principle of Operation
The Peripheral Access Control module allows the user to set a write protection on peripheral modules
and generate an interrupt in case of a peripheral access violation. The peripheral’s protection can be set,
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cleared or locked for user convenience. A set of Interrupt Flag and Status registers informs the user on
the status of the violation in the peripherals. In addition, slaves bus errors can be also reported in the
cases where reserved area is accessed by the application.
12.5.2.
Basic Operation
12.5.2.1. Initialization
After reset, the PAC is enabled.
12.5.2.2. Enabling and Resetting
The PAC is always enabled after reset.
Only a hardware reset will reset the PAC module.
12.5.2.3. Operations
The PAC module allows the user to set, clear or lock the write protection status of all peripherals on all
Peripheral Bridges.
If a peripheral register violation occurs, the Peripheral Interrupt Flag n registers (INTFLAGn) are updated
to inform the user on the status of the violation in the peripherals connected to the Peripheral Bridge n (n
= A,B,C ...). The corresponding Peripheral Write Control Status n register (STATUSn) gives the state of
the write protection for all peripherals connected to the corresponding Peripheral Bridge n. Refer to the
Peripheral Access Errors for details.
The PAC module reports also the errors occurring at slave bus level when an access to reserved area is
detected. AHB Slave Bus Interrupt Flag register (INTFLAGAHB) informs the user on the status of the
violation in the corresponding slave. Refer to the AHB Slave Bus Errors for details.
12.5.2.4. Peripheral Access Errors
The following events will generate a Peripheral Access Error:
•
•
•
Protected write: To avoid unexpected writes to a peripheral's registers, each peripheral can be write
protected. Only the registers denoted as “PAC Write-Protection” in the module’s datasheet can be
protected. If a peripheral is not write protected, write data accesses are performed normally. If a
peripheral is write protected and if a write access is attempted, data will not be written and
peripheral returns an access error. The corresponding interrupt flag bit in the INTFLAGn register will
be set.
Illegal access: Access to an unimplemented register within the module.
Synchronized write error: For write-synchronized registers an error will be reported if the register is
written while a synchronization is ongoing.
When any of the INTFLAGn registers bit are set, an interrupt will be requested if the PAC interrupt enable
bit is set.
12.5.2.5. Write Access Protection Management
Peripheral access control can be enabled or disabled by writing to the WRCTRL register.
The data written to the WRCTRL register is composed of two fields; WRCTRL.PERID and WRCTRL.KEY.
The WRCTRL.PERID is an unique identifier corresponding to a peripheral. The WRCTRL.KEY is a key
value that defines the operation to be done on the control access bit. These operations can be “clear
protection”, “set protection” and “set and lock protection bit”.
The “clear protection” operation will remove the write access protection for the peripheral selected by
WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral.
The “set protection” operation will set the write access protection for the peripheral selected by
WRCTRL.PERID. Write accesses are not allowed for the registers with write protection property in this
peripheral.
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The “set and lock protection” operation will permanently set the write access protection for the peripheral
selected by WRCTRL.PERID. The write access protection will only be cleared by a hardware reset.
The peripheral access control status can be read from the corresponding STATUSn register.
12.5.2.6. Write Access Protection Management Errors
Only word-wise writes to the WRCTRL register will effectively change the access protection. Other type of
accesses will have no effect and will cause a PAC write access error. This error is reported in the
INTFLAGn.PAC bit corresponding to the PAC module.
PAC also offers an additional safety feature for correct program execution with an interrupt generated on
double write clear protection or double write set protection. If a peripheral is write protected and a
subsequent set protection operation is detected then the PAC returns an error, and similarly for a double
clear protection operation. In addition, an error is generated when writing a “set and lock” protection to a
write-protected peripheral or when a write access is done to a locked set protection.
This can be used to ensure that the application follows the intended program flow by always following a
write protect with an unprotect and conversely. However in applications where a write protected
peripheral is used in several contexts, e.g. interrupt, care should be taken so that either the interrupt can
not happen while the main application or other interrupt levels manipulates the write protection status or
when the interrupt handler needs to unprotect the peripheral based on the current protection status by
reading the STATUS register.
The errors generated while accessing the PAC module registers (eg. key error, double protect error...) will
set the INTFLAGn.PAC flag.
12.5.2.7. AHB Slave Bus Errors
The PAC module reports errors occurring at the Slave bus level. These errors are generated when an
access is performed at an address where no slave (bridge or peripheral) is mapped. These errors are
reported in the INTFLAGAHB register.
12.5.2.8. Generating Events
The PAC module can also generate an event when any of the Interrupt Flag registers bit are set. To
enable the PAC event generation, the control bit EVCTRL.ERREO must be set.
12.5.3.
DMA Operation
Not applicable.
12.5.4.
Interrupts
The PAC has the following interrupt source:
•
Error (ERR): Indicates that a peripheral access violation occurred in one of the peripherals
controlled by the PAC module, or a bridge error occurred in one of the bridges reported by the PAC
– This interrupt is a synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAGAHB and INTFLAGn) registers is set when the interrupt condition occurs. Each
interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set
(INTENSET) register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear
(INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the
corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared,
the interrupt is disabled, or the PAC is reset. All interrupt requests from the peripheral are ORed together
on system level to generate one combined interrupt request to the NVIC. The user must read the
INTFLAGAHB and INTFLAGn registers to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
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Related Links
Nested Vector Interrupt Controller on page 43
Sleep Mode Controller on page 179
12.5.5.
Events
The PAC can generate the following output event:
•
Error (ERR): Generated when one of the interrupt flag registers bits is set
Writing a one to an Event Output bit in the Event Control Register (EVCTRL.ERREO) enables the
corresponding output event. Writing a zero to this bit disables the corresponding output event.
12.5.6.
Sleep Mode Operation
In Sleep mode, the PAC is kept enabled if an available master (CPU, DMA) is running. The PAC will
continue to catch access errors from module and generate interrupts or events.
12.5.7.
Synchronization
Not applicable.
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12.6.
Offset
Register Summary
Name
0x00
0x01
0x02
WRCTRL
0x03
0x04
Bit Pos.
7:0
PERID[7:0]
15:8
PERID[15:8]
23:16
KEY[7:0]
31:24
EVCTRL
7:0
ERREO
0x05
...
Reserved
0x07
0x08
INTENCLR
7:0
ERR
0x09
INTENSET
7:0
ERR
0x0A
...
Reserved
0x0F
0x10
7:0
0x11
15:8
0x12
INTFLAGAHB
31:24
0x14
7:0
INTFLAGA
23:16
0x17
31:24
0x18
7:0
0x19
15:8
INTFLAGB
0x1B
GCLK
SUPC
HPB0
HPB1
HSRAMDSU HSRAMCM0P
FLASH
OSC32KCTR
L
OSCCTRL
RSTC
MCLK
PM
PAC
FREQM
EIC
RTC
WDT
MTB
DMAC
NVMCTRL
DSU
PORT
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
TC0
TCC2
TCC1
TCC0
23:16
31:24
0x1C
7:0
0x1D
15:8
TC3
TC2
23:16
CCL
PTC
GCLK
SUPC
0x1E
HPB2
15:8
0x16
0x1A
LPRAMDMAC
23:16
0x13
0x15
DIVAS
INTFLAGC
0x1F
TC1
AC
ADC0
TC4
31:24
0x20
...
Reserved
0x33
0x34
0x35
7:0
STATUSA
23:16
0x37
31:24
0x38
7:0
0x39
15:8
0x3B
STATUSB
L
OSCCTRL
15:8
0x36
0x3A
OSC32KCTR
MTB
RSTC
MCLK
PM
PAC
FREQM
EIC
RTC
WDT
DMAC
NVMCTRL
DSU
PORT
23:16
31:24
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Offset
Name
Bit Pos.
0x3C
7:0
0x3D
15:8
TC3
TC2
23:16
CCL
PTC
0x3E
0x3F
12.7.
STATUSC
TC1
SERCOM3
SERCOM2
SERCOM1
SERCOM0
TC0
TCC2
TCC1
TCC0
AC
ADC0
EVSYS
TC4
31:24
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to the related links.
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12.7.1.
Write Control
Name: WRCTRL
Offset: 0x0
Reset: 0x00000000
Property: –
Bit
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
Access
Reset
Bit
KEY[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PERID[15:8]
Access
PERID[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 23:16 – KEY[7:0]: Peripheral Access Control Key
These bits define the peripheral access control key:
Value
Name
Description
0x0
OFF
No action
0x1
CLEAR
Clear the peripheral write control
0x2
SET
Set the peripheral write control
0x3
LOCK
Set and lock until the next hardware reset the peripheral write control
Bits 15:0 – PERID[15:0]: Peripheral Identifier
The PERID represents the peripheral whose control is changed using the WRCTRL.KEY. The Peripheral
Identifier is calculated following formula:
����� = 32* BridgeNumber + N
Where BridgeNumber represents the Peripheral Bridge Number (0 for Peripheral Bridge A, 1 for
Peripheral Bridge B, etc). N represents the peripheral index from the respective Bridge Number:
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Table 12-2. PERID Values
Periph. Bridge Name
BridgeNumber
PERID Values
A
0
0+N
B
1
32+N
C
2
64+N
D
3
96+N
E
4
128+N
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12.7.2.
Event Control
Name: EVCTRL
Offset: 0x04
Reset: 0x00
Property: Bit
7
6
5
4
3
2
1
0
ERREO
Access
R/W
Reset
0
Bit 0 – ERREO: Peripheral Access Error Event Output
This bit indicates if the Peripheral Access Error Event Output is enabled or not. When enabled, an event
will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:
Value
Description
0
Peripheral Access Error Event Output is disabled.
1
Peripheral Access Error Event Output is enabled.
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12.7.3.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
ERR
Access
R/W
Reset
0
Bit 0 – ERR: Peripheral Access Error Interrupt Enable
This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be
generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Peripheral Access Error interrupt Enable bit and disables the
corresponding interrupt request.
Value
Description
0
Peripheral Access Error interrupt is disabled.
1
Peripheral Access Error interrupt is enabled.
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12.7.4.
Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENCLR).
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
ERR
Access
R/W
Reset
0
Bit 0 – ERR: Peripheral Access Error Interrupt Enable
This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be
generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Peripheral Access Error interrupt Enable bit and enables the
corresponding interrupt request.
Value
Description
0
Peripheral Access Error interrupt is disabled.
1
Peripheral Access Error interrupt is enabled.
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12.7.5.
AHB Slave Bus Interrupt Flag Status and Clear
This flag is cleared by writing a '1' to the flag.
This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if
INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Name: INTFLAGAHB
Offset: 0x10
Reset: 0x000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIVAS
LPRAMDMAC
HPB2
HPB0
HPB1
HSRAMDSU
HSRAMCM0P
FLASH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 7 – DIVAS: Interrupt Flag for SLAVE DIVAS
Bit 6 – LPRAMDMAC: Interrupt Flag for SLAVE LPRAMDMAC
Bit 5 – HPB2: Interrupt Flag for SLAVE HPB2
Bit 4 – HPB0: Interrupt Flag for SLAVE HPB0
Bit 3 – HPB1: Interrupt Flag for SLAVE HPB1
Bit 2 – HSRAMDSU: Interrupt Flag for SLAVE HSRAMDSU
Bit 1 – HSRAMCM0P: Interrupt Flag for SLAVE HSRAMCM0P
Bit 0 – FLASH: Interrupt Flag for SLAVE FLASH
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12.7.6.
Peripheral Interrupt Flag Status and Clear A
This flag is cleared by writing a one to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the
respective INTFLAGA bit, and will generate an interrupt request if INTENCLR/SET.ERR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding INTFLAGA interrupt flag.
Name: INTFLAGA
Offset: 0x14
Reset: 0x000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
FREQM
EIC
RTC
WDT
R/W
R/W
R/W
R/W
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
5
4
3
2
1
0
GCLK
SUPC
OSC32KCTRL
OSCCTRL
RSTC
MCLK
PM
PAC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 11 – FREQM: Interrupt Flag for FREQM
Bit 10 – EIC: Interrupt Flag for EIC
Bit 9 – RTC: Interrupt Flag for RTC
Bit 8 – WDT: Interrupt Flag for WDT
Bit 7 – GCLK: Interrupt Flag for GCLK
Bit 6 – SUPC: Interrupt Flag for SUPC
Bit 5 – OSC32KCTRL: Interrupt Flag for OSC32KCTRL
Bit 4 – OSCCTRL: Interrupt Flag for OSCCTRL
Bit 3 – RSTC: Interrupt Flag for RSTC
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Bit 2 – MCLK: Interrupt Flag for MCLK
Bit 1 – PM: Interrupt Flag for PM
Bit 0 – PAC: Interrupt Flag for PAC
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12.7.7.
Peripheral Interrupt Flag Status and Clear B
This flag is cleared by writing a '1' to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the
respective INTFLAGB bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding INTFLAGB interrupt flag.
Name: INTFLAGB
Offset: 0x18
Reset: 0x000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MTB
DMAC
NVMCTRL
DSU
PORT
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – MTB: Interrupt Flag for MTB
Bit 3 – DMAC: Interrupt Flag for DMAC
Bit 2 – NVMCTRL: Interrupt Flag for NVMCTRL
Bit 1 – DSU: Interrupt Flag for DSU
Bit 0 – PORT: Interrupt Flag for PORT
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12.7.8.
Peripheral Interrupt Flag Status and Clear C
This flag is cleared by writing a one to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the
respective INTFLAGC bit, and will generate an interrupt request if INTENCLR/SET.ERR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding INTFLAGC interrupt flag.
Name: INTFLAGC
Offset: 0x1C
Reset: 0x000000
Property: –
Bit
31
30
29
21
28
27
26
20
19
18
25
24
Access
Reset
Bit
Access
Reset
Bit
Access
23
22
17
16
CCL
PTC
AC
ADC0
TC4
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
8
15
14
13
12
11
10
9
TC3
TC2
TC1
TC0
TCC2
TCC1
TCC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Access
Reset
Bit 23 – CCL: Interrupt Flag for CCL
Bit 22 – PTC: Interrupt Flag for PTC
Bit 20 – AC: Interrupt Flag for AC
Bit 17 – ADC0: Interrupt Flag for ADC
Bit 0 – EVSYS: Interrupt Flag for EVSYS
Bits 12, 13, 14, 15, 16 – TCn: Interrupt Flag for TCn [n = 4..0]
Bits 9, 10, 11 – TCCn: Interrupt Flag for TCCn [n = 2..0]
Bits 1, 2, 3, 4 – SERCOMn: Interrupt Flag for SERCOMn [n = 3..0]
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12.7.9.
Peripheral Write Protection Status A
Writing to this register has no effect.
Reading STATUS register returns peripheral write protection status:
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
Name: STATUSA
Offset: 0x34
Reset: 0x000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
Bit
FREQM
EIC
RTC
WDT
Access
R
R
R
R
Reset
0
0
0
0
Bit
7
6
5
4
3
2
1
0
GCLK
SUPC
OSC32KCTRL
OSCCTRL
RSTC
MCLK
PM
PAC
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit 11 – FREQM: Peripheral FREQM Write Protection Status
Bit 10 – EIC: Peripheral EIC Write Protection Status
Bit 9 – RTC: Peripheral RTC Write Protection Status
Bit 8 – WDT: Peripheral WDT Write Protection Status
Bit 7 – GCLK: Peripheral GCLK Write Protection Status
Bit 6 – SUPC: Peripheral SUPC Write Protection Status
Bit 5 – OSC32KCTRL: Peripheral OSC32KCTRL Write Protection Status
Bit 4 – OSCCTRL: Peripheral OSCCTRL Write Protection Status
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Bit 3 – RSTC: Peripheral RSTC Write Protection Status
Bit 2 – MCLK: Peripheral MCLK Write Protection Status
Bit 1 – PM: Peripheral PM Write Protection Status
Bit 0 – PAC: Peripheral PAC Write Protection Status
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12.7.10. Peripheral Write Protection Status B
Writing to this register has no effect.
Reading STATUS register returns peripheral write protection status:
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
Name: STATUSB
Offset: 0x38
Reset: 0x000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
4
3
2
1
0
MTB
DMAC
NVMCTRL
DSU
PORT
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 4 – MTB: Peripheral MTB Write Protection Status
Bit 3 – DMAC: Peripheral DMAC Write Protection Status
Bit 2 – NVMCTRL: Peripheral NVMCTRL Write Protection Status
Bit 1 – DSU: Peripheral DSU Write Protection Status
Bit 0 – PORT: Peripheral PORt Write Protection Status
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12.7.11. Peripheral Write Protection Status C
Writing to this register has no effect.
Reading STATUS register returns peripheral write protection status:
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
Name: STATUSC
Offset: 0x3C
Reset: 0x000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CCL
PTC
AC
ADC0
TC4
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
15
14
8
Access
Reset
Bit
Access
13
12
11
10
9
TC3
TC2
TC1
TC0
TCC2
TCC1
TCC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit
7
6
5
Access
4
3
2
1
0
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 23 – CCL: Peripheral CCL Write Protection Status
Bit 22 – PTC: Peripheral PTC Write Protection Status
Bit 20 – AC: Peripheral AC Write Protection Status
Bit 17 – ADC0: Peripheral ADC0 Write Protection Status
Bit 0 – EVSYS: Peripheral EVSYS Write Protection Status
Bits 12, 13, 14, 15, 16 – TCn: Peripheral TCn Write Protection Status [n = 4..0]
Bits 9, 10, 11 – TCCn: Peripheral TCCn [n = 2..0] Write Protection Status TCCn [n = 2..0]
Bits 1, 2, 3, 4 – SERCOMn: Peripheral SERCOMn Write Protection Status [n = 3..0]
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13.
Peripherals Configuration Summary
Table 13-1. Peripherals Configuration Summary SAM C20 J, G, E
Peripheral
Name
Base Address IRQ
Line
AHB Clock
APB Clock
Index Enabled Index Enabled
at Reset
at Reset
10
Y
Events
Index
Index Prot at
Reset
User
Generator
DMA
Index
Sleep
Walking
0x40000000
PAC
0x44000000
0
0
Y
0
N
PM
0x40000400
0
1
Y
1
N
MCLK
0x40000800
0
2
Y
2
N
Y
RSTC
0x40000C00
3
Y
3
N
N/A
OSCCTRL
0x40001000
0
4
Y
4
N
0: XOSC_FAIL
OSC32KCTRL
0x40001400
0
5
Y
5
N
1: XOSC32K_FAIL
SUPC
0x40001800
0
6
Y
6
N
N/A
GCLK
0x40001C00
7
Y
7
N
N/A
WDT
0x40002000
1
8
Y
8
N
RTC
0x40002400
2
9
Y
9
N
2: CMP0/ALARM0
3: CMP1
4: OVF
5-12: PER0-7
Y
EIC
0x40002800
3,
NMI
10
Y
2
10
N
13-28: EXTINT0-15
Y
FREQM
0x40002C00
4
11
Y
3: Measure
4: Reference
11
N
AHB-APB
Bridge B
0x41000000
PORT
0x41000000
DSU
0x41002000
NVMCTRL
0x41004000
DMAC
0x41006000
MTB
0x41008000
AHB-APB
Bridge C
0x42000000
EVSYS
0x42000000
8
0
N
6-17: one per
CHANNEL
0
N
SERCOM0
0x42000400
9
1
N
19: CORE
18: SLOW
1
N
2: RX
3: TX
Y
SERCOM1
0x42000800
10
2
N
20: CORE
18: SLOW
2
N
4: RX
5: TX
Y
SERCOM2
0x42000C00
11
3
N
21: CORE
18: SLOW
3
N
6: RX
7: TX
Y
SERCOM3
0x42001000
12
4
N
22: CORE
18: SLOW
4
N
8: RX
9: TX
Y
TCC0
0x42002400
17
9
N
28
9
N
16: OVF
17-20:
MC0-3
Y
21: OVF
22-23:
MC0-1
Y
0x42002800
Y
PAC
AHB-APB
Bridge A
TCC1
0
Generic
Clock
N/A
0: FDPLL96M
clk source
1: FDPLL96M
32kHz
85 : ACCERR
N/A
Y
N/A
Y
0
Y
0
N
3
Y
1
Y
1
Y
6
5
Y
2
Y
2
N
7
7
Y
3
N
5-8: CH0-3
N
44: START
45: STOP
18
Y
Y
1
2
N/A
N/A
39
1-4 : EV0-3
Y
N/A
Y
30-33: CH0-3
Y
N/A
Y
N/A
10
N
28
10
N
Y
9-10: EV0-1
11-14:
MC0-3
15-16:
EV0-1
17-18:
MC0-1
34: OVF
35: TRG
36: CNT
37-40: MC0-3
41: OVF
42: TRG
43: CNT
44-45: MC0-1
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Peripheral
Name
Base Address IRQ
Line
AHB Clock
APB Clock
Index Enabled Index Enabled
at Reset
at Reset
TCC2
0x42002C00
19
11
N
Generic
Clock
PAC
Index
Index Prot at
Reset
29
11
Events
N
DMA
User
Generator
Index
Sleep
Walking
19-20:
EV0-1
21-22:
MC0-1
46: OVF
47: TRG
24: OVF
25-26:
MC0-1
Y
48: CNT
49-50: MC0-1
TC0
0x42003000
20
12
N
30
12
N
23: EVU
51: OVF
52-53: MC0-1
27: OVF
28-29:
MC0-1
Y
TC1
0x42003400
21
13
N
30
13
N
24: EVU
54: OVF
55-56: MC0-1
30: OVF
21-32:
MC0-1
Y
TC2
0x42003800
22
14
N
31
14
N
25: EVU
57: OVF
58-59: MC0-1
33: OVF
23-35:
MC0-1
Y
TC3
0x42003C00
23
15
N
31
15
N
26: EVU
60: OVF
61-62: MC0-1
36: OVF
37-38:
MC0-1
Y
TC4
0x42004000
24
16
N
32
16
N
27: EVU
63: OVF
64-65: MC0-1
39: OVF
40-41:
MC0-1
Y
ADC0
0x42004400
25
17
N
33
17
N
28: START
29: SYNC
66: RESRDY
67: WINMON
42:
RESRDY
Y
AC
0x42005000
27
20
N
34
20
N
34-37:
SOC0-3
72-75: COMP0-3
76-77: WIN0-1
PTC
0x42005800
30
22
N
37
22
N
39:
STCONV
79: EOC
80: WCOMP
CCL
0x42005C00
23
N
38
23
N
40-43 :
LUTIN0-3
781-84:
LUTOUT0-3
DIVAS
0x48000000
Y
EOC: 46
WCOMP: 47
SEQ: 48
12
Y
Y
N/A
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14.
DSU - Device Service Unit
14.1.
Overview
The Device Service Unit (DSU) provides a means to detect debugger probes. This enables the ARM
Debug Access Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also
provides system-level services to debug adapters in an ARM debug system. It implements a CoreSight
Debug ROM that provides device identification as well as identification of other debug components within
the system. Hence, it complies with the ARM Peripheral Identification specification. The DSU also
provides system services to applications that need memory testing, as required for IEC60730 Class B
compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as it is
connected on the High-Speed Bus Matrix. For security reasons, some of the DSU features will be limited
or unavailable when the device is protected by the NVMCTRL security bit.
Related Links
NVMCTRL – Non-Volatile Memory Controller on page 430
Security Bit on page 438
14.2.
Features
•
•
•
•
•
•
•
•
CPU reset extension
Debugger probe detection (Cold- and Hot-Plugging)
Chip-Erase command and status
32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
®
™
ARM CoreSight compliant device identification
Two debug communications channels
Debug access port security filter
Onboard memory built-in self-test (MBIST)
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14.3.
Block Diagram
Figure 14-1. DSU Block Diagram
DSU
RESET
SWCLK
debugger_present
DEBUGGER PROBE
INTERFACE
cpu_reset_extension
CPU
DAP
AHB-AP
DAP SECURITY FILTER
NVMCTRL
DBG
CORESIGHT ROM
PORT
S
M
CRC-32
SWDIO
MBIST
M
HIGH-SPEED
BUS MATRIX
CHIP ERASE
14.4.
Signal Description
The DSU uses three signals to function.
Signal Name
Type
Description
RESET
Digital Input
External reset
SWCLK
Digital Input
SW clock
SWDIO
Digital I/O
SW bidirectional data pin
Related Links
I/O Multiplexing and Considerations on page 28
14.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
14.5.1.
IO Lines
The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and to
stretch the CPU reset phase. For more information, refer to Debugger Probe Detection. The Hot-Plugging
feature depends on the PORT configuration. If the SWCLK pin function is changed in the PORT or if the
PORT_MUX is disabled, the Hot-Plugging feature is disabled until a power-reset or an external reset.
14.5.2.
Power Management
The DSU will continue to operate in any sleep mode where the selected source clock is running.
Related Links
PM – Power Manager on page 177
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14.5.3.
Clocks
The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Main
Clock Controller.
Related Links
PM – Power Manager on page 177
MCLK – Main Clock on page 149
Peripheral Clock Masking on page 152
14.5.4.
DMA
Not applicable.
14.5.5.
Interrupts
Not applicable.
14.5.6.
Events
Not applicable.
14.5.7.
Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except the following:
•
•
Debug Communication Channel 0 register (DCC0)
Debug Communication Channel 1 register (DCC1)
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection
does not apply for accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
14.5.8.
Analog Connections
Not applicable.
14.6.
Debug Operation
14.6.1.
Principle of Operation
The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the
ARM processor debug resources:
•
CPU reset extension
•
Debugger probe detection
For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture
Specification.
14.6.2.
CPU Reset Extension
“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset
is released. This ensures that the CPU is not executing code at startup while a debugger connects to the
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system. It is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally
pulled up to avoid false detection of a debugger if SWCLK is left unconnected. When the CPU is held in
the reset extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is
set. To release the CPU, write a '1' to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to zero.
Writing a '0' to STATUSA.CRSTEXT has no effect. For security reasons, it is not possible to release the
CPU reset extension when the device is protected by the NVMCTRL security bit. Trying to do so sets the
Protection Error bit (PERR) of the Status A register (STATUSA.PERR).
Figure 14-2. Typical CPU Reset Extension Set and Clear Timing Diagram
SWCLK
RESET
DSU CRSTEXT
Clear
CPU reset
extension
CPU_STATE
reset
running
Related Links
NVMCTRL – Non-Volatile Memory Controller on page 430
Security Bit on page 438
14.6.3.
Debugger Probe Detection
14.6.3.1. Cold Plugging
Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when
the CPU reset extension is requested, as described above.
14.6.3.2. Hot Plugging
Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not
possible under reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is
active when a SWCLK falling edge is detected. The SWCLK pad is multiplexed with other functions and
the user must ensure that its default function is assigned to the debug system. If the SWCLK function is
changed, the Hot-Plugging feature is disabled until a power-reset or external reset occurs. Availability of
the Hot-Plugging feature can be read from the Hot-Plugging Enable bit of the Status B register
(STATUSB.HPE).
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Figure 14-3. Hot-Plugging Detection Timing Diagram
SWCLK
RESET
CPU_STATE
reset
running
Hot-Plugging
The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected.
Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For
security reasons, Hot-Plugging is not available when the device is protected by the NVMCTRL security
bit.
This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be
done until POR is released. If the device is protected, Cold-Plugging is the only way to detect a debugger
probe, and so the external reset timing must be longer than the POR timing. If external reset is
deasserted before POR release, the user must retry the procedure above until it gets connected to the
device.
Related Links
NVMCTRL – Non-Volatile Memory Controller on page 430
Security Bit on page 438
14.7.
Chip Erase
Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL
security bit (refer to Security Bit) . Therefore, all volatile memories and the Flash memory (including the
EEPROM emulation area) will be erased. The Flash auxiliary rows, including the user row, will not be
erased.
When the device is protected, the debugger must reset the device in order to be detected. This ensures
that internal registers are reset after the protected state is removed. The Chip-Erase operation is
triggered by writing a '1' to the Chip-Erase bit in the Control register (CTRL.CE). This command will be
discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once issued, the module
clears volatile memories prior to erasing the Flash array. To ensure that the Chip-Erase operation is
completed, check the Done bit of the Status A register (STATUSA.DONE).
The Chip-Erase operation depends on clocks and power management features that can be altered by the
CPU. For that reason, it is recommended to issue a Chip- Erase after a Cold-Plugging procedure to
ensure that the device is in a known and safe state.
The recommended sequence is as follows:
1. Issue the Cold-Plugging procedure (refer to Cold Plugging). The device then:
1.1.
Detects the debugger probe.
1.2.
Holds the CPU in reset.
2. Issue the Chip-Erase command by writing a '1' to CTRL.CE. The device then:
2.1.
Clears the system volatile memories.
2.2.
Erases the whole Flash array (including the EEPROM emulation area, not including
auxiliary rows).
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3.
4.
14.8.
2.3.
Erases the lock row, removing the NVMCTRL security bit protection.
Check for completion by polling STATUSA.DONE (read as one when completed).
Reset the device to let the NVMCTRL update fuses.
Programming
Programming the Flash or RAM memories is only possible when the device is not protected by the
NVMCTRL security bit. The programming procedure is as follows:
1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR
state until the input supply is above the POR threshold. The system continues to be held in this
static state until the internally regulated supplies have reached a safe operating state.
2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and
any Bus Clocks that do not have clock gate control). Internal resets are maintained due to the
external reset.
3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger ColdPlugging procedure.
4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives
a clock.
5. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system
is released.
6. A Chip-Erase is issued to ensure that the Flash is fully erased prior to programming.
7. Programming is available through the AHB-AP.
8. After the operation is completed, the chip can be restarted either by asserting RESET, toggling
power, or writing a '1' to the Status A register CPU Reset Phase Extension bit
(STATUSA.CRSTEXT). Make sure that the SWCLK pin is high when releasing RESET to prevent
extending the CPU reset.
Related Links
Electrical Characteristics 85°C on page 900
NVMCTRL – Non-Volatile Memory Controller on page 430
Security Bit on page 438
14.9.
Intellectual Property Protection
Intellectual property protection consists of restricting access to internal memories from external tools
when the device is protected, and this is accomplished by setting the NVMCTRL security bit. This
protected state can be removed by issuing a Chip-Erase (refer to Chip Erase). When the device is
protected, read/write accesses using the AHB-AP are limited to the DSU address range and DSU
commands are restricted. When issuing a Chip-Erase, sensitive information is erased from volatile
memory and Flash.
The DSU implements a security filter that monitors the AHB transactions generated by the ARM AHB-AP
inside the DAP. If the device is protected, then AHB-AP read/write accesses outside the DSU external
address range are discarded, causing an error response that sets the ARM AHB-AP sticky error bits
(refer to the ARM Debug Interface v5 Architecture Specification on http://www.arm.com).
The DSU is intended to be accessed either:
•
Internally from the CPU, without any limitation, even when the device is protected
•
Externally from a debug adapter, with some restrictions when the device is protected
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For security reasons, DSU features have limitations when used from a debug adapter. To differentiate
external accesses from internal ones, the first 0x100 bytes of the DSU register map have been replicated
at offset 0x100:
•
The first 0x100 bytes form the internal address range
•
The next 0x100 bytes form the external address range
When the device is protected, the DAP can only issue MEM-AP accesses in the DSU address range
limited to the 0x100- 0x2000 offset range.
The DSU operating registers are located in the 0x00-0xFF area and remapped in 0x100-0x1FF to
differentiate accesses coming from a debugger and the CPU. If the device is protected and an access is
issued in the region 0x100-0x1FF, it is subject to security restrictions. For more information, refer to the
Table 14-1 Feature Availability Under Protection.
Figure 14-4. APB Memory Mapping
0x0000
DSU operating
registers
Internal address range
(cannot be accessed from debug tools when the device is
protected by the NVMCTRL security bit)
0x00FC
0x0100
Replicated
DSU operating
registers
0x01FD
Empty
External address range
(can be accessed from debug tools with some restrictions)
0x1000
DSU CoreSight
ROM
0x1FFC
Some features not activated by APB transactions are not available when the device is protected:
Table 14-1. Feature Availability Under Protection
Features
Availability when the device is protected
CPU Reset Extension
Yes
Clear CPU Reset Extension
No
Debugger Cold-Plugging
Yes
Debugger Hot-Plugging
No
Related Links
NVMCTRL – Non-Volatile Memory Controller on page 430
Security Bit on page 438
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14.10. Device Identification
Device identification relies on the ARM CoreSight component identification scheme, which allows the chip
to be identified as an Atmel device implementing a DSU. The DSU contains identification registers to
differentiate the device.
14.10.1. CoreSight Identification
A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip
identification method. Its address is provided in the MEM-AP BASE register inside the ARM Debug
Access Port. The CoreSight ROM implements a 64-bit conceptual ID composed as follows from the PID0
to PID7 CoreSight ROM Table registers:
Figure 14-5. Conceptual 64-bit Peripheral ID
Table 14-2. Conceptual 64-Bit Peripheral ID Bit Descriptions
Field
Size Description
Location
JEP-106 CC code 4
Atmel continuation code: 0x0
PID4
JEP-106 ID code
7
Atmel device ID: 0x1F
PID1+PID2
4KB count
4
Indicates that the CoreSight component is a ROM: 0x0
PID4
RevAnd
4
Not used; read as 0
PID3
CUSMOD
4
Not used; read as 0
PID3
PARTNUM
12
Contains 0xCD0 to indicate that DSU is present
PID0+PID1
REVISION
4
DSU revision (starts at 0x0 and increments by 1 at both major
and minor revisions). Identifies DSU identification method
variants. If 0x0, this indicates that device identification can be
completed by reading the Device Identification register (DID)
PID3
For more information, refer to the ARM Debug Interface Version 5 Architecture Specification.
14.10.2. Chip Identification Method
The DSU DID register identifies the device by implementing the following information:
•
•
•
•
Processor identification
Product family identification
Product series identification
Device select
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14.11. Functional Description
14.11.1. Principle of Operation
The DSU provides memory services such as CRC32 or MBIST that require almost the same interface.
Hence, the Address, Length and Data registers (ADDR, LENGTH, DATA) are shared. These shared
registers must be configured first; then a command can be issued by writing the Control register. When a
command is ongoing, other commands are discarded until the current operation is completed. Hence, the
user must wait for the STATUSA.DONE bit to be set prior to issuing another one.
14.11.2. Basic Operation
14.11.2.1. Initialization
The module is enabled by enabling its clocks. For more details, refer to Clocks. The DSU registers can be
PAC write-protected.
Related Links
PAC - Peripheral Access Controller on page 48
14.11.2.2. Operation From a Debug Adapter
Debug adapters should access the DSU registers in the external address range 0x100 – 0x2000. If the
device is protected by the NVMCTRL security bit, accessing the first 0x100 bytes causes the system to
return an error. Refer to Intellectual Property Protection.
Related Links
NVMCTRL – Non-Volatile Memory Controller on page 430
Security Bit on page 438
14.11.2.3. Operation From the CPU
There are no restrictions when accessing DSU registers from the CPU. However, the user should access
DSU registers in the internal address range (0x0 – 0x100) to avoid external security restrictions. Refer to
Intellectual Property Protection.
14.11.3. 32-bit Cyclic Redundancy Check CRC32
The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory
area (including Flash and AHB RAM).
When the CRC32 command is issued from:
•
The internal range, the CRC32 can be operated at any memory location
•
The external range, the CRC32 operation is restricted; DATA, ADDR, and LENGTH values are
forced (see below)
Table 14-3. AMOD Bit Descriptions when Operating CRC32
AMOD[1:0] Short name External range restrictions
0
ARRAY
CRC32 is restricted to the full Flash array area (EEPROM emulation area not
included) DATA forced to 0xFFFFFFFF before calculation (no seed)
1
EEPROM
CRC32 of the whole EEPROM emulation area DATA forced to 0xFFFFFFFF
before calculation (no seed)
2-3
Reserved
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The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial
0xEDB88320 (reversed representation).
14.11.3.1. Starting CRC32 Calculation
CRC32 calculation for a memory range is started after writing the start address into the Address register
(ADDR) and the size of the memory range into the Length register (LENGTH). Both must be wordaligned.
The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value
will usually be 0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if
generating a common CRC32 of separate memory blocks.
Once completed, the calculated CRC32 value can be read out of the Data register. The read value must
be complemented to match standard CRC32 implementations or kept non-inverted if used as starting
point for subsequent CRC32 calculations.
If the device is in protected state by the NVMCTRL security bit, it is only possible to calculate the CRC32
of the whole flash array when operated from the external address space. In most cases, this area will be
the entire onboard non-volatile memory. The Address, Length and Data registers will be forced to
predefined values once the CRC32 operation is started, and values written by the user are ignored. This
allows the user to verify the contents of a protected device.
The actual test is started by writing a '1' in the 32-bit Cyclic Redundancy Check bit of the Control register
(CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing '1' to
CTRL.SWRST).
Related Links
NVMCTRL – Non-Volatile Memory Controller on page 430
Security Bit on page 438
14.11.3.2. Interpreting the Results
The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set.
Then the Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus
error occurred.
14.11.4. Debug Communication Channels
The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated
handshake logic, accessible by both CPU and debugger even if the device is protected by the NVMCTRL
security bit. The registers can be used to exchange data between the CPU and the debugger, during run
time as well as in debug mode. This enables the user to build a custom debug protocol using only these
registers.
The DCC0 and DCC1 registers are accessible when the protected state is active. When the device is
protected, however, it is not possible to connect a debugger while the CPU is running
(STATUSA.CRSTEXT is not writable and the CPU is held under Reset).
Two Debug Communication Channel status bits in the Status B registers (STATUS.DCCDx) indicate
whether a new value has been written in DCC0 or DCC1. These bits, DCC0D and DCC1D, are located in
the STATUSB registers. They are automatically set on write and cleared on read.
Note: The DCC0 and DCC1 registers are shared with the on-board memory testing logic (MBIST).
Accordingly, DCC0 and DCC1 must not be used while performing MBIST operations.
Related Links
NVMCTRL – Non-Volatile Memory Controller on page 430
Security Bit on page 438
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14.11.5. Testing of On-Board Memories MBIST
The DSU implements a feature for automatic testing of memory also known as MBIST (memory built-in
self test). This is primarily intended for production test of on-board memories. MBIST cannot be operated
from the external address range when the device is protected by the NVMCTRL security bit. If an MBIST
command is issued when the device is protected, a protection error is reported in the Protection Error bit
in the Status A register (STATUSA.PERR).
1.
Algorithm
The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able
to detect a wide range of memory defects, while still keeping a linear run time. The algorithm is:
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
Write entire memory to '0', in any order.
Bit for bit read '0', write '1', in descending order.
Bit for bit read '1', write '0', read '0', write '1', in ascending order.
Bit for bit read '1', write '0', in ascending order.
Bit for bit read '0', write '1', read '1', write '0', in ascending order.
Read '0' from entire memory, in ascending order.
The specific implementation used has a run time which depends on the CPU clock frequency and
the number of bytes tested in the RAM. The detected faults are:
2.
– Address decoder faults
– Stuck-at faults
– Transition faults
– Coupling faults
– Linked Coupling faults
Starting MBIST
To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit field,
and the size of the memory into the Length register.
For best test coverage, an entire physical memory block should be tested at once. It is possible to
test only a subset of a memory, but the test coverage will then be somewhat lower.
3.
The actual test is started by writing a '1' to CTRL.MBIST. A running MBIST operation can be
canceled by writing a '1' to CTRL.SWRST.
Interpreting the Results
The tester should monitor the STATUSA register. When the operation is completed,
STATUSA.DONE is set. There are two different modes:
–
4.
ADDR.AMOD=0: exit-on-error (default)
In this mode, the algorithm terminates either when a fault is detected or on successful
completion. In both cases, STATUSA.DONE is set. If an error was detected, STATUSA.FAIL
will be set. User then can read the DATA and ADDR registers to locate the fault.
– ADDR.AMOD=1: pause-on-error
In this mode, the MBIST algorithm is paused when an error is detected. In such a situation,
only STATUSA.FAIL is asserted. The state machine waits for user to clear STATUSA.FAIL by
writing a '1' in STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and
ADDR registers to locate the fault.
Locating Faults
If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first
detected error. The position of the failing bit can be found by reading the following registers:
–
ADDR: Address of the word containing the failing bit
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–
DATA: contains data to identify which bit failed, and during which phase of the test it failed.
The DATA register will in this case contains the following bit groups:
Figure 14-6. DATA bits Description When MBIST Operation Returns an Error
Bit
31
30
29
28
27
26
25
24
Bit
23
22
21
20
19
18
17
16
Bit
15
14
13
12
11
10
9
8
phase
Bit
7
6
5
3
4
2
1
0
bit_index
•
•
bit_index: contains the bit number of the failing bit
phase: indicates which phase of the test failed and the cause of the error, as listed in the following
table.
Table 14-4. MBIST Operation Phases
Phase
Test actions
0
Write all bits to zero. This phase cannot fail.
1
Read '0', write '1', increment address
2
Read '1', write '0'
3
Read '0', write '1', decrement address
4
Read '1', write '0', decrement address
5
Read '0', write '1'
6
Read '1', write '0', decrement address
7
Read all zeros. bit_index is not used
Table 14-5. AMOD Bit Descriptions for MBIST
AMOD[1:0]
Description
0x0
Exit on Error
0x1
Pause on Error
0x2, 0x3
Reserved
Related Links
NVMCTRL – Non-Volatile Memory Controller on page 430
Security Bit on page 438
Product Mapping on page 36
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14.11.6. System Services Availability when Accessed Externally
External access: Access performed in the DSU address offset 0x200-0x1FFF range.
Internal access: Access performed in the DSU address offset 0x0-0x100 range.
Table 14-6. Available Features when Operated From The External Address Range and Device is Protected
Features
Availability From The External Address Range
and Device is Protected
Chip-Erase command and status
Yes
CRC32
Yes, only full array or full EEPROM
CoreSight Compliant Device identification
Yes
Debug communication channels
Yes
Testing of onboard memories (MBIST)
No
STATUSA.CRSTEXT clearing
No (STATUSA.PERR is set when attempting to do
so)
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83
14.12. Register Summary
Offset
Name
Bit Pos.
0x00
CTRL
7:0
CE
0x01
STATUSA
7:0
PERR
FAIL
0x02
STATUSB
7:0
HPE
DCCD1
0x03
Reserved
MBIST
0x04
7:0
0x05
15:8
ADDR[13:6]
23:16
ADDR[21:14]
0x06
ADDR
0x07
31:24
0x08
7:0
0x09
0x0A
LENGTH
15:8
LENGTH[13:6]
23:16
LENGTH[21:14]
LENGTH[29:22]
DATA[7:0]
0x0D
15:8
DATA[15:8]
23:16
DATA[23:16]
0x0F
31:24
DATA[31:24]
0x10
7:0
DATA[7:0]
DCC0
15:8
DATA[15:8]
23:16
DATA[23:16]
DATA[31:24]
0x13
31:24
0x14
7:0
DATA[7:0]
0x15
15:8
DATA[15:8]
0x16
DCC1
23:16
DATA[23:16]
0x17
31:24
DATA[31:24]
0x18
7:0
DEVSEL[7:0]
0x19
0x1A
DID
0x1B
15:8
23:16
31:24
DONE
PROT
ADDR[29:22]
7:0
0x11
CRSTEXT
DBGPRES
LENGTH[5:0]
31:24
0x12
BERR
DCCD0
AMOD[1:0]
0x0B
DATA
SWRST
ADDR[5:0]
0x0C
0x0E
CRC
DIE[3:0]
REVISION[3:0]
FAMILY[0:0]
SERIES[5:0]
PROCESSOR[3:0]
FAMILY[4:1]
0x1C
...
Reserved
0x0FFF
0x1000
7:0
0x1001
15:8
0x1002
ENTRY0
23:16
ADDOFF[11:4]
0x1003
31:24
ADDOFF[19:12]
0x1004
7:0
0x1005
0x1006
ENTRY1
0x1007
15:8
ADDOFF[11:4]
31:24
ADDOFF[19:12]
7:0
END[7:0]
0x1009
15:8
END[15:8]
23:16
END[23:16]
31:24
END[31:24]
0x100B
END
EPRES
FMT
EPRES
ADDOFF[3:0]
23:16
0x1008
0x100A
FMT
ADDOFF[3:0]
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Offset
Name
Bit Pos.
0x100C
...
Reserved
0x1FCB
0x1FCC
7:0
0x1FCD
15:8
0x1FCE
MEMTYPE
0x1FCF
23:16
31:24
0x1FD0
7:0
0x1FD1
15:8
0x1FD2
SMEMP
PID4
0x1FD3
FKBC[3:0]
JEPCC[3:0]
23:16
31:24
0x1FD4
...
Reserved
0x1FDF
0x1FE0
0x1FE1
0x1FE2
7:0
PID0
0x1FE3
15:8
23:16
31:24
0x1FE4
7:0
0x1FE5
15:8
0x1FE6
PID1
31:24
0x1FE8
7:0
0x1FE9
PID2
0x1FEB
7:0
PID3
31:24
0x1FF0
7:0
CID0
0x1FF3
7:0
CID1
31:24
0x1FF8
7:0
CID2
0x1FFB
CCLASS[3:0]
PREAMBLE[3:0]
23:16
0x1FF7
PREAMBLEB2[7:0]
15:8
23:16
31:24
0x1FFC
7:0
0x1FFD
15:8
0x1FFF
PREAMBLEB0[7:0]
31:24
15:8
0x1FFE
CUSMOD[3:0]
15:8
0x1FF5
0x1FF9
REVAND[3:0]
23:16
0x1FF4
0x1FFA
JEPIDCH[2:0]
23:16
0x1FEF
0x1FF6
JEPU
31:24
15:8
0x1FF2
REVISION[3:0]
15:8
0x1FED
0x1FF1
PARTNBH[3:0]
23:16
0x1FEC
0x1FEE
JEPIDCL[3:0]
23:16
0x1FE7
0x1FEA
PARTNBL[7:0]
CID3
PREAMBLEB3[7:0]
23:16
31:24
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14.13. Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
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14.13.1. Control
Name: CTRL
Offset: 0x0000
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
1
0
CE
MBIST
2
CRC
SWRST
Access
W
W
W
W
Reset
0
0
0
0
Bit 4 – CE: Chip Erase
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the Chip-Erase operation.
Bit 3 – MBIST: Memory Built-In Self-Test
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the memory BIST algorithm.
Bit 1 – CRC: 32-bit Cyclic Redundancy Check
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the cyclic redundancy check algorithm.
Bit 0 – SWRST: Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the module.
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14.13.2. Status A
Name: STATUSA
Offset: 0x0001
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
Access
4
3
2
1
0
PERR
FAIL
BERR
CRSTEXT
DONE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Reset
Bit 4 – PERR: Protection Error
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Protection Error bit.
This bit is set when a command that is not allowed in protected state is issued.
Bit 3 – FAIL: Failure
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Failure bit.
This bit is set when a DSU operation failure is detected.
Bit 2 – BERR: Bus Error
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Bus Error bit.
This bit is set when a bus error is detected.
Bit 1 – CRSTEXT: CPU Reset Phase Extension
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the CPU Reset Phase Extension bit.
This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase.
Bit 0 – DONE: Done
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Done bit.
This bit is set when a DSU operation is completed.
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14.13.3. Status B
Name: STATUSB
Offset: 0x0002
Reset: 0x1X
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
HPE
DCCD1
DCCD0
DBGPRES
PROT
Access
R
R
R
R
R
Reset
1
0
0
x
x
Bit 4 – HPE: Hot-Plugging Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when Hot-Plugging is enabled.
This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed.
Only a power-reset or a external reset can set it again.
Bit 1 – DBGPRES: Debugger Present
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when a debugger probe is detected.
This bit is never cleared.
Bit 0 – PROT: Protected
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set at power-up when the device is protected.
This bit is never cleared.
Bits 3,2 – DCCDx: Debug Communication Channel x Dirty [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when DCCx is written.
This bit is cleared when DCCx is read.
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14.13.4. Address
Name: ADDR
Offset: 0x0004
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
ADDR[29:22]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
ADDR[21:14]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
ADDR[13:6]
Access
ADDR[5:0]
Access
Reset
0
AMOD[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:2 – ADDR[29:0]: Address
Initial word start address needed for memory operations.
Bits 1:0 – AMOD[1:0]: Address Mode
The functionality of these bits is dependent on the operation mode.
Bit description when operating CRC32: refer to 32-bit Cyclic Redundancy Check CRC32
Bit description when testing onboard memories (MBIST): refer to Testing of On-Board Memories MBIST
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14.13.5. Length
Name: LENGTH
Offset: 0x0008
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
LENGTH[29:22]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
LENGTH[21:14]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
LENGTH[13:6]
Access
LENGTH[5:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 31:2 – LENGTH[29:0]: Length
Length in words needed for memory operations.
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14.13.6. Data
Name: DATA
Offset: 0x000C
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
DATA[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DATA[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DATA[15:8]
Access
DATA[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – DATA[31:0]: Data
Memory operation initial value or result value.
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14.13.7. Debug Communication Channel 0
Name: DCC0
Offset: 0x0010
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
DATA[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DATA[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DATA[15:8]
Access
DATA[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – DATA[31:0]: Data
Data register.
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14.13.8. Debug Communication Channel 1
Name: DCC1
Offset: 0x0014
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
DATA[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DATA[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DATA[15:8]
Access
DATA[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – DATA[31:0]: Data
Data register.
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94
14.13.9. Device Identification
The information in this register is related to the Ordering Information.
Name: DID
Offset: 0x0018
Reset: see related links
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
PROCESSOR[3:0]
25
24
FAMILY[4:1]
Access
R
R
R
R
R
R
R
R
Reset
p
p
p
p
f
f
f
f
Bit
23
22
21
20
19
18
17
16
FAMILY[0:0]
SERIES[5:0]
Access
R
R
R
R
R
R
R
Reset
f
s
s
s
s
s
s
13
12
11
10
9
8
Bit
15
14
DIE[3:0]
REVISION[3:0]
Access
R
R
R
R
R
R
R
R
Reset
d
d
d
d
r
r
r
r
Bit
7
6
5
4
3
2
1
0
DEVSEL[7:0]
Access
R
R
R
R
R
R
R
R
Reset
x
x
x
x
x
x
x
x
Bits 31:28 – PROCESSOR[3:0]: Processor
The value of this field defines the processor used on the device.
Bits 27:23 – FAMILY[4:0]: Product Family
The value of this field corresponds to the Product Family part of the ordering code.
Bits 21:16 – SERIES[5:0]: Product Series
The value of this field corresponds to the Product Series part of the ordering code.
Bits 15:12 – DIE[3:0]: Die Number
Identifies the die family.
Bits 11:8 – REVISION[3:0]: Revision Number
Identifies the die revision number. 0x0=rev.A, 0x1=rev.B etc.
Note: The device variant (last letter of the ordering number) is independent of the die revision
(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks
evolution of the die.
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Bits 7:0 – DEVSEL[7:0]: Device Selection
This bit field identifies a device within a product family and product series. Refer to the Ordering
Information for device configurations and corresponding values for Flash memory density, pin count and
device variant.
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14.13.10. CoreSight ROM Table Entry 0
Name: ENTRY0
Offset: 0x1000
Reset: 0xXXXXX00X
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
ADDOFF[19:12]
Access
R
R
R
R
R
R
R
R
Reset
x
x
x
x
x
x
x
x
23
22
21
20
19
18
17
16
Bit
ADDOFF[11:4]
Access
R
R
R
R
R
R
R
R
Reset
x
x
x
x
x
x
x
x
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
Reset
x
x
x
x
Bit
7
6
5
4
3
2
ADDOFF[3:0]
1
0
FMT
EPRES
Access
R
R
Reset
1
x
Bits 31:12 – ADDOFF[19:0]: Address Offset
The base address of the component, relative to the base address of this ROM table.
Bit 1 – FMT: Format
Always reads as '1', indicating a 32-bit ROM table.
Bit 0 – EPRES: Entry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at power-up if the device is not protected indicating that the entry is not present.
This bit is cleared at power-up if the device is not protected indicating that the entry is present.
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14.13.11. CoreSight ROM Table Entry 1
Name: ENTRY1
Offset: 0x1004
Reset: 0xXXXXX00X
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
ADDOFF[19:12]
Access
R
R
R
R
R
R
R
R
Reset
x
x
x
x
x
x
x
x
23
22
21
20
19
18
17
16
Bit
ADDOFF[11:4]
Access
R
R
R
R
R
R
R
R
Reset
x
x
x
x
x
x
x
x
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
Reset
x
x
x
x
Bit
7
6
5
4
3
2
ADDOFF[3:0]
1
0
FMT
EPRES
Access
R
R
Reset
1
x
Bits 31:12 – ADDOFF[19:0]: Address Offset
The base address of the component, relative to the base address of this ROM table.
Bit 1 – FMT: Format
Always read as '1', indicating a 32-bit ROM table.
Bit 0 – EPRES: Entry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at power-up if the device is not protected indicating that the entry is not present.
This bit is cleared at power-up if the device is not protected indicating that the entry is present.
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14.13.12. CoreSight ROM Table End
Name: END
Offset: 0x1008
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
END[31:24]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
END[23:16]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
END[15:8]
END[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – END[31:0]: End Marker
Indicates the end of the CoreSight ROM table entries.
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14.13.13. CoreSight ROM Table Memory Type
Name: MEMTYPE
Offset: 0x1FCC
Reset: 0x0000000X
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
SMEMP
Access
R
Reset
x
Bit 0 – SMEMP: System Memory Present
This bit indicates whether system memory is present on the bus that connects to the ROM table.
This bit is set at power-up if the device is not protected, indicating that the system memory is accessible
from a debug adapter.
This bit is cleared at power-up if the device is protected, indicating that the system memory is not
accessible from a debug adapter.
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14.13.14. Peripheral Identification 4
Name: PID4
Offset: 0x1FD0
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
FKBC[3:0]
JEPCC[3:0]
Bits 7:4 – FKBC[3:0]: 4KB Count
These bits will always return zero when read, indicating that this debug component occupies one 4KB
block.
Bits 3:0 – JEPCC[3:0]: JEP-106 Continuation Code
These bits will always return zero when read, indicating an Atmel device.
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14.13.15. Peripheral Identification 0
Name: PID0
Offset: 0x1FE0
Reset: 0x000000D0
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
1
1
0
1
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PARTNBL[7:0]
Bits 7:0 – PARTNBL[7:0]: Part Number Low
These bits will always return 0xD0 when read, indicating that this device implements a DSU module
instance.
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14.13.16. Peripheral Identification 1
Name: PID1
Offset: 0x1FE4
Reset: 0x000000FC
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
JEPIDCL[3:0]
PARTNBH[3:0]
Bits 7:4 – JEPIDCL[3:0]: Low part of the JEP-106 Identity Code
These bits will always return 0xF when read, indicating a Atmel device (Atmel JEP-106 identity code is
0x1F).
Bits 3:0 – PARTNBH[3:0]: Part Number High
These bits will always return 0xC when read, indicating that this device implements a DSU module
instance.
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14.13.17. Peripheral Identification 2
Name: PID2
Offset: 0x1FE8
Reset: 0x00000009
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
1
0
0
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
REVISION[3:0]
JEPU
JEPIDCH[2:0]
Bits 7:4 – REVISION[3:0]: Revision Number
Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions.
Bit 3 – JEPU: JEP-106 Identity Code is used
This bit will always return one when read, indicating that JEP-106 code is used.
Bits 2:0 – JEPIDCH[2:0]: JEP-106 Identity Code High
These bits will always return 0x1 when read, indicating an Atmel device (Atmel JEP-106 identity code is
0x1F).
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14.13.18. Peripheral Identification 3
Name: PID3
Offset: 0x1FEC
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
REVAND[3:0]
CUSMOD[3:0]
Bits 7:4 – REVAND[3:0]: Revision Number
These bits will always return 0x0 when read.
Bits 3:0 – CUSMOD[3:0]: ARM CUSMOD
These bits will always return 0x0 when read.
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14.13.19. Component Identification 0
Name: CID0
Offset: 0x1FF0
Reset: 0x0000000D
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
1
1
0
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PREAMBLEB0[7:0]
Bits 7:0 – PREAMBLEB0[7:0]: Preamble Byte 0
These bits will always return 0xD when read.
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14.13.20. Component Identification 1
Name: CID1
Offset: 0x1FF4
Reset: 0x00000010
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
1
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
CCLASS[3:0]
PREAMBLE[3:0]
Bits 7:4 – CCLASS[3:0]: Component Class
These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table
(refer to the ARM Debug Interface v5 Architecture Specification at http://www.arm.com).
Bits 3:0 – PREAMBLE[3:0]: Preamble
These bits will always return 0x0 when read.
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14.13.21. Component Identification 2
Name: CID2
Offset: 0x1FF8
Reset: 0x00000005
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
1
0
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PREAMBLEB2[7:0]
Bits 7:0 – PREAMBLEB2[7:0]: Preamble Byte 2
These bits will always return 0x05 when read.
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14.13.22. Component Identification 3
Name: CID3
Offset: 0x1FFC
Reset: 0x000000B1
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
1
0
1
1
0
0
0
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PREAMBLEB3[7:0]
Bits 7:0 – PREAMBLEB3[7:0]: Preamble Byte 3
These bits will always return 0xB1 when read.
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15.
DIVAS – Divide and Square Root Accelerator
15.1.
Overview
The Divide and Square Root Accelerator (DIVAS) is a programmable 32-bit signed or unsigned hardware
divider and a 32-bit unsigned square root hardware engine. The DIVAS is connected to the high-speed
bus matrix and may also be accessed using the low-latency CPU local bus (IOBUS; ARM® single-cycle
I/O port). The DIVAS takes dividend and divisor values and returns the quotient and remainder when it is
used as divider. The DIVAS takes unsigned input value and returns its square root and remainder when it
is used as square root function.
15.2.
Features
•
•
•
•
•
•
•
•
•
15.3.
Division accelerator for Cortex-M0+ systems
32-bit signed or unsigned integer division
32-bit unsigned square root
32-bit division in 2-16 cycles
Programmable leading zero optimization
Result includes quotient and remainder
Result includes square root and remainder
Busy and Divide-by-zero
status
D
Automatic start of operation when divisor or square root input is loaded
Block Diagram
Figure 15-1. DIVAS Block Diagram
IVAS
DEVIDE ENGINE
DIVIDEND
DIVISOR
AHB
CTRLA
QUOTIENT
REMAINDER
15.4.
IOBUS
INTERFACE
Signal Description
Not applicable
15.5.
Product Dependencies
In order to use this peripherial, other parts of the system must be configured correctly, as described
below.
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15.5.1.
I/O Lines
Not applicable
15.5.2.
Power Management
The DIVAS will not operate in any sleep mode .
15.5.3.
Clocks
The DIVAS bus clock (CLK_DIVAS_AHB) can be enabled and disabled in the power manager, and the
default state of CLK_DIVAS_AHB can be found in the Peripheral Clock Masking section in the Power
Manager chapter.
15.5.4.
DMA
Not applicable
15.5.5.
Interrupts
Not applicable
15.5.6.
Events
Not applicable
15.5.7.
Debug Operation
Not applicable
15.5.8.
Register Access Protection
Certain registers cannot be modified while DIVAS is busy. The following registers are write-protected
while busy:
•
•
•
•
Control A (CTRLA)
Dividend (DIVIDEND)
Divisor (DIVISOR)
Square Root Input (SQRNUM)
Accessing these registers while protected will result in an error.
15.5.9.
Analog Connections
Not applicable
15.5.10. CPU Local Bus
The CPU local bus (IOBUS) is an interface that connects the CPU directly to the DIVAS. It is a singlecycle bus interface, and does not support wait states. It supports byte, half word and word sizes. This bus
is generally used for low latency. All registers can be read and written using this bus.
Since the IOBUS cannot wait for DIVAS to complete operation, the Quotient and Remainder registers
must be only be read via the IOBUS while the Busy bit in the Status register (STATUS.BUSY) is zero to
prevent incorrect data from being read.
15.6.
Functional Description
15.6.1.
Principle of Operation
The Divide and Square Root Accelerator (DIVAS) supports signed or unsigned hardware division of 32-bit
values and unsigned square root of 32-bit value. It is accessible from the CPU via both the AHB bus and
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IOBUS. When the dividend and divide registers are programmed, the division starts and the result will be
stored in the Result and Remainder registers. The Busy and Divide-by-zero status can be read from
STATUS register.
When the square root input register (SQRNUM) is programmed, the square root function starts and the
result will be stored in the Result and Remainder registers. The Busy status can be read from STATUS
register.
15.6.2.
Basic Operation
15.6.2.1. Initialization
The DIVAS configuration cannot be modified while a divide operation is ongoing. The following bits must
be written prior to starting a division:
•
•
Sign selection bit in Control A register (CTRLA.SIGNED)
Leading zero mode bit in Control A register (CTRLA.DLZ)
15.6.2.2. Performing Division
First write the dividend to DIVIDEND register. Writing the divisor to DIVISOR register starts the division
and sets the busy bit in the Status register (STATUS.BUSY). When the division has completed, the
STATUS.BUSY bit is cleared and the result will be stored in RESULT and REMAINDER registers.
The RESULT and REMAINDER registers can be read directly via the high-speed bus without checking
first STATUS.BUSY. Wait states will be inserted on the high-speed bus until the operation is complete.
The IOBUS does not support wait states. For accesses via the IOBUS, the STATUS.BUSY bit must be
polled before reading the result from the RESULTand REMAINDER registers.
15.6.2.3. Operand Size
Divide
The DIVAS can perform 32-bit signed and unsigned division and the operation follows the equation as
below.
������ 31: 0 = �������� 31: 0 /������� 31: 0
��������� 31: 0 = �������� 31: 0 % ������� 31: 0
DIVAS completes 32-bit division in 2-16 cycles.
Square Root
The DIVAS can perform 32-bit unsigned division and the operation follows the equation as below.
��������� 31: 0 =
������ 31: 0
��������� 31: 0 = ������ 31: 0 − ������ 31: 0
15.6.2.4. Signed Division
2
When CTRLA.SIGNED is one, both the input and the result will be in 2’s complement format. The results
of signed division are such that the remainder and dividend have the same sign and the quotient is
negative if the dividend and divisor have opposite signs. 16-bit results are sign extended to 32-bits. Note
that when the maximum negative number is divided by the minimum negative number, the resulting
quotient overflows the signed integer range and will return the maximum negative number with no
indication of the overflow. This occurs for 0x80000000 / 0xFFFFFFFF in 32-bit operation and 0x8000 /
0xFFFF in 16-bit operation.
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15.6.2.5. Divide By Zero
A divide by zero fault occurs if the DIVISOR is programmed to zero. QUOTIENT will be zero and the
REMAINDER is equal to DIVIDEND. Divide by zero sets the Divide-by-zero bit in the Status register
(STATUS.DBZ) to one. STATUS.DBZ must be cleared by writing a one to it.
15.6.2.6. Leading Zero Optimization
Leading zero optimization can reduce the time it takes to complete a division by skipping leading zeros in
the DIVIDEND (or leading ones in signed mode). Leading zero optimization is enabled by default and can
be disabled by the Disable Leading Zero bit in the Control A register (CTRLA.DLZ). When CTRLA.DLZ is
zero, 16-bit division completes in 2-8 cycles and 32-bit division completes in 2-16 cycles, depending on
the dividend value. If deterministic timing is required, setting CTRLA.DLZ to one forces 16-bit division to
always take 8 cycles and 32-bit division to always take 16 cycles.
15.6.2.7. Unsigned Square Root
When the square root input register (SQRNUM) is programmed, the square root function starts and the
result will be stored in the Result and Remainder registers. The Busy status can be read from STATUS
register.
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15.7.
Register Summary
Offset
Name
Bit Pos.
0x00
CTRLA
7:0
DLZ
SIGNED
7:0
DBZ
BUSY
0x01
...
Reserved
0x03
0x04
STATUS
0x05
...
Reserved
0x07
0x08
7:0
DIVIDEND[7:0]
0x09
15:8
DIVIDEND[15:8]
0x0A
DIVIDEND
23:16
DIVIDEND[23:16]
0x0B
31:24
DIVIDEND[31:24]
0x0C
7:0
DIVISOR[7:0]
0x0D
15:8
DIVISOR[15:8]
23:16
DIVISOR[23:16]
0x0F
31:24
DIVISOR[31:24]
0x10
7:0
RESULT[7:0]
0x11
15:8
RESULT[15:8]
0x0E
0x12
DIVISOR
RESULT
23:16
RESULT[23:16]
0x13
31:24
RESULT[31:24]
0x14
7:0
REMAINDER[7:0]
0x15
15:8
REMAINDER[15:8]
23:16
REMAINDER[23:16]
0x17
31:24
REMAINDER[31:24]
0x18
7:0
SQRNUM[7:0]
0x19
15:8
SQRNUM[15:8]
23:16
SQRNUM[23:16]
31:24
SQRNUM[31:24]
0x16
0x1A
0x1B
15.8.
REMAINDER
SQRNUM
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
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15.8.1.
Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: Bit
7
6
5
4
3
2
Access
Reset
1
0
DLZ
SIGNED
R/W
R/W
0
0
Bit 1 – DLZ: Disable Leading Zero Optimization
Value
Description
0
Enable leading zero optimization; 32-bit division takes 2-16 cycles.
1
Disable leading zero optimization; 32-bit division takes 16 cycles.
Bit 0 – SIGNED: Signed Division Enable
Value
Description
0
Unsigned division.
1
Signed division.
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15.8.2.
Status
Name: STATUS
Offset: 0x04
Reset: 0x00
Property: Bit
7
6
5
4
3
2
Access
Reset
1
0
DBZ
BUSY
R/W
R/W
0
0
Bit 1 – DBZ: Disable-By-Zero
Writing a zero to this bit has no effect.
Writing a one to this bit clears DBZ to zero.
Value
Description
0
A divide-by-zero fault has not occurred
1
A divide-by-zero fault has occurred
Bit 0 – BUSY: DIVAS Accelerator Busy
This bit is set when a value is written to the DIVISOR or SQRNUM registers.
This bit is cleared when either division or square root function completes and results are ready in the
RESULT and REMAINDER registers.
Value
Description
0
DIVAS is idle
1
DIVAS is busy with an ongoing division
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15.8.3.
Dividend
Name: DIVIDEND
Offset: 0x08
Reset: 0x0000
Property: Bit
31
30
29
28
27
26
25
24
DIVIDEND[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIVIDEND[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DIVIDEND[15:8]
Access
DIVIDEND[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – DIVIDEND[31:0]: Dividend Value
Holds the 32-bit dividend for the divide operation. If the Signed bit in Control A register (CTRLA.SIGNED)
is zero, DIVIDEND is unsigned. If CTRLA.SIGNED = 1, DIVIDEND is signed two’s complement. Refer to
Performing Division, Operand Size and Signed Division.
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15.8.4.
Divisor
Name: DIVISOR
Offset: 0x0C
Reset: 0x0000
Property: Bit
31
30
29
28
27
26
25
24
DIVISOR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIVISOR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DIVISOR[15:8]
Access
DIVISOR[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – DIVISOR[31:0]: Divisor Value
Holds the 32-bit divisor for the divide operation. If the Signed bit in Control A register (CTRLA.SIGNED) is
zero, DIVISOR is unsigned. If CTRLA.SIGNED = 1, DIVISOR is signed two’s complement. Writing the
DIVISOR register will start the divide function. Refer to Performing Division, Operand Size and Signed
Division.
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15.8.5.
Result
Name: RESULT
Offset: 0x10
Reset: 0x0000
Property: Bit
31
30
29
28
27
26
25
24
RESULT[31:24]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RESULT[23:16]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RESULT[15:8]
RESULT[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – RESULT[31:0]: Result of Operation
Holds the 32-bit result of the last performed operation. For a divide operation this is the quotient. If the
Signed bit in Control A register (CTRLA.SIGNED) is zero, the quotient is unsigned. If CTRLA.SIGNED =
1, the quotient is signed two’s complement. For a square root operation this is the square root. Refer to
Performing Division, Operand Size and Signed Division.
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15.8.6.
Remainder
Name: REMAINDER
Offset: 0x14
Reset: 0x0000
Property: Bit
31
30
29
28
27
26
25
24
REMAINDER[31:24]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
REMAINDER[23:16]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
REMAINDER[15:8]
REMAINDER[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – REMAINDER[31:0]: Remainder of Operation
Holds the 32-bit remainder of the last performed operation. For a divide operation this is the division
remainder. If the Signed bit in Control A register (CTRLA.SIGNED) is zero, the quotient is unsigned. If
CTRLA.SIGNED = 1, the quotient is signed two’s complement. For a square root operation this is the
square root remainder. Refer to Performing Division, Operand Size and Signed Division.
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15.8.7.
Square Root Input
Name: SQRNUM
Offset: 0x18
Reset: 0x0000
Property: Bit
31
30
29
28
27
26
25
24
SQRNUM[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
SQRNUM[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SQRNUM[15:8]
Access
SQRNUM[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – SQRNUM[31:0]: Square Root Input
Holds the 32-bit unsigned input for the square root operation. Writing the SQRNUM register will start the
square root function. Refer to Unsigned Square Root.
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16.
Clock System
This chapter only aims to summarize the clock distribution and terminology in the SAM C20 device. It will
not explain every detail of its configuration. For in-depth documentation, see the referenced module
chapters.
Clock Distribution
Figure 16-1. Clock distribution
MCLK
GCLK_MAIN
GCLK
XOSC
Syncronous Clock
Controller
GCLK Generator 0
Peripheral Channel 0
GCLK Generator 1
Peripheral Channel 1
(FDPLL96M Reference)
GCLK_DPLL
GCLK Generator x
Peripheral Channel 2
(FDPLL96M Reference)
GCLK_DPLL_32K
OSC48M
GCLK_DPLL
GCLK_DPLL_32K
FDPLL96M
OSCK32CTRL
OSC32K
Peripheral Channel 3
32kHz
XOSC32K
32kHz
1kHz
OSCULP32K
Peripheral 0
Generic
Clocks
1kHz
Peripheral Channel y
32kHz
Peripheral z
1kHz
AHB/APB System Clocks
16.1.
RTC
CLK_RTC_OSC
CLK_WDT_OSC
CLK_ULP32K
WDT
EIC
The clock system on the SAM C20 consists of:
•
•
•
Clock sources, controlled by OSCCTRL and OSC32KCTRL
– A Clock source is the base clock signal used in the system. Example clock sources are the
internal 48MHz oscillator (OSC48M), External crystal oscillator (XOSC) and the Digital phase
locked loop (FDPLL96M).
Generic Clock Controller (GCLK) which controls the clock distribution system, made up of:
– Generic Clock generators: A programmable prescaler, that can use any of the system clock
sources as its source clock. The Generic Clock Generator 0, also called GCLK_MAIN, is the
clock feeding the Power Manager used to generate synchronous clocks.
– Generic Clocks: Typically the clock input of a peripheral on the system. The generic clocks,
through the Generic Clock Multiplexer, can use any of the Generic Clock generators as its
clock source. Multiple instances of a peripheral will typically have a separate generic clock for
each instance.
Main Clock controller (MCLK)
– The MCLK controls synchronous clocks on the system. This includes the CPU, bus clocks
(APB, AHB) as well as the synchronous (to the CPU) user interfaces of the peripherals. It
contains clock masks that can turn on/off the user interface of a peripheral as well as
prescalers for the CPU and bus clocks.
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The figure below shows an example where SERCOM0 is clocked by the OSC48M. The OSC48M is
enabled, the Generic Clock Generator 1 uses the OSCLL48M as its clock source, and the generic clock
19, also called GCLK_SERCOM0_CORE, that is connected to SERCOM0 uses generator 1 as its source.
The SERCOM0 interface, clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask
register in the MCLK.
Figure 16-2. Example of SERCOM clock
MCLK
Syncronous Clock
Controller
OSCCTRL
OSC48
16.2.
CLK_SERCOM0_APB
GCLK
Generic Clock
Generator 1
Peripheral
Channel 19
GCLK_SERCOM0_CORE
SERCOM 0
Synchronous and Asynchronous Clocks
As the CPU and the peripherals can be clocked from different clock sources, possibly with widely different
clock speeds, some peripheral accesses by the CPU needs to be synchronized between the different
clock domains. In these cases the peripheral includes a SYNCBUSY status register that can be used to
check if a sync operation is in progress. As the nature of the synchronization might vary between different
peripherals, detailed description for each peripheral can be found in the sub-chapter “synchronization” for
each peripheral where this is necessary.
In the datasheet references to synchronous clocks are referring to the CPU and bus clocks, while
asynchronous clocks are clock generated by generic clocks.
16.3.
Register Synchronization
16.3.1.
Overview
All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and
clocked using a corresponding synchronous clock, and one core clock, which is clocked using a generic
clock. Access between these clock domains must be synchronized. As this mechanism is implemented in
hardware the synchronization process takes place even if the different clocks domains are clocked from
the same source and on the same frequency. All registers in the bus interface are accessible without
synchronization. All core registers in the generic clock domain must be synchronized when written. Some
core registers must be synchronized when read. Registers that need synchronization has this denoted in
each individual register description.
16.3.2.
General Write-Synchronization
Inside the same module, each core register, denoted by the Write-Synchronized property, use its own
synchronization mechanism so that writing to different core registers can be done without waiting for the
end of synchronization of previous core register access.
However a second write access to the same core register, while synchronization is on going, is discarded
and an error is reported through the PAC. To write again to the same core register in the same module,
user must wait for the end of synchronization.
For each core register, that can be written, a synchronization status bit is associated
Example:
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REGA, REGB are 8-bit core registers. REGC is 16-bit core register.
Offset
Register
0x00
REGA
0x01
REGB
0x02
REGC
0x03
Since synchronization is per register, user can write REGA (8-bit access) then immediately write REGB
(8-bit access) without error.
User can write REGC (16-bit access) without affecting REGA or REGB. But if user writes REGC in two
consecutive 8-bit accesses, second write will be discarded and generate an error.
When user makes a 32-bit access to offset 0x00, all registers are written but REGA, REGB, REGC can
be updated at a different time because of independent write synchronization
16.3.3.
General Read-Synchronization
Before any read of a core register, the user must check that the related bit in SYNCBUSY register is
cleared.
Read access to core register is always immediate but the return value is reliable only if a synchronization
of this core register is not going.
16.3.4.
Completion of Synchronization
The user can either poll SYNCBUSY register or use the Synchronization Ready interrupt (if available) to
check when the synchronization is complete.
16.3.5.
Enable Write-Synchronization
Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and
set SYNCBUSY.ENABLE. CTRL.ENABLE will read its new value immediately after being written. The
Synchronisation Ready interrupt (if available) cannot be used for Enable write-synchronization.
16.3.6.
Software Reset Write-Synchronization
Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization
and set SYNCBUSY.SWRST. When writing a one to the CTRL.SWRST bit it will immediately read as one.
CTRL.SWRST and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset.
Writing a zero to the CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available)
cannot be used for Software Reset write-synchronization.
16.3.7.
Synchronization Delay
The synchronization will delay the write or read access duration by a delay D, given by the equation:
5 ⋅ �GCLK + 2 ⋅ �APB < � < 6 ⋅ �GCLK + 3 ⋅ �APB
Where �GCLK is the period of the generic clock and �APB is the period of the peripheral bus clock. A
normal peripheral bus register access duration is 2 ⋅ �APB.
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16.4.
Enabling a Peripheral
To enable a peripheral clocked by a generic clock, the following parts of the system needs to be
configured:
•
•
•
•
16.5.
A running clock source.
A clock from the Generic Clock Generator must be configured to use one of the running clock
sources, and the generator must be enabled.
The generic clock, through the Generic Clock Multiplexer, that connects to the peripheral needs to
be configured with a running clock from the Generic Clock Generator, and the generic clock must
be enabled.
The user interface of the peripheral needs to be unmasked in the PM. If this is not done the
peripheral registers will read as all 0’s and any writes to the peripheral will be discarded.
On-demand, Clock Requests
Figure 16-3. Clock request routing
Clock request
OSC48
Generic Clock
Generator
ENABLE
GENEN
RUNSTDBY
RUNSTDBY
Clock request
Generic Clock
Periph. Channel
CLKEN
Clock request
Peripheral
ENABLE
RUNSTDBY
ONDEMAND
All the clock sources in the system can be run in an on-demand mode, where the clock source is in a
stopped state when no peripherals are requesting the clock source. Clock requests propagate from the
peripheral, via the GCLK, to the clock source. If one or more peripheral is using a clock source, the clock
source will be started/kept running. As soon as the clock source is no longer needed and no peripheral
have an active request the clock source will be stopped until requested again. For the clock request to
reach the clock source, the peripheral, the generic clock and the clock from the Generic Clock Generator
in-between must be enabled. The time taken from a clock request being asserted to the clock source
being ready is dependent on the clock source startup time, clock source frequency as well as the divider
used in the Generic Clock Generator. The total startup time from a clock request to the clock is available
for the peripheral is:
Delay_start_max = Clock source startup time + 2 * clock source periods + 2 * divided clock
source periods
Delay_start_min = Clock source startup time + 1 * clock source period + 1 * divided clock
source periodDelay_start_min = Clock source startup time + 1 * clock source period + 1 *
divided clock source period
The delay for shutting down the clock source when there is no longer an active request is:
Delay_stop_min = 1 * divided clock source period + 1 * clock source period
Delay_stop_max = 2 * divided clock source periods + 2 * clock source periods
The On-Demand principle can be disabled individually for each clock source by clearing the ONDEMAND
bit located in each clock source controller. The clock is always running whatever is the clock request. This
has the effect to remove the clock source startup time at the cost of the power consumption.
In standby mode, the clock request mechanism is still working if the modules are configured to run in
standby mode (RUNSTDBY bit).
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16.6.
Power Consumption vs. Speed
Due to the nature of the asynchronous clocking of the peripherals there are some considerations that
needs to be taken if either targeting a low-power or a fast-acting system. If clocking a peripheral with a
very low clock, the active power consumption of the peripheral will be lower. At the same time the
synchronization to the synchronous (CPU) clock domain is dependent on the peripheral clock speed, and
will be longer with a slower peripheral clock; giving lower response time and more time waiting for the
synchronization to complete.
16.7.
Clocks after Reset
On any reset the synchronous clocks start to their initial state:
•
•
•
OSC48M is enabled and divided by 12
GCLK_MAIN uses OSC48M as source
CPU and BUS clocks are undivided
On a power reset the GCLK starts to their initial state:
•
•
All generic clock generators disabled except:
– The generator 0 (GCLK_MAIN) using OSC48M as source, with no division
All generic clocks disabled
On a user reset the GCLK starts to their initial state, except for:
•
Generic clocks that are write-locked (WRTLOCK is written to one prior to reset)
On any reset the clock sources are reset to their initial state except the 32KHz clock sources which are
reset only by a power reset.
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17.
GCLK - Generic Clock Controller
17.1.
Overview
Depending on the application, peripherals may require specific clock frequencies to operate correctly. The
Generic Clock controller GCLK provides nine Generic Clock Generators [8:0] that can provide a wide
range of clock frequencies.
Generators can be set to use different external and internal oscillators as source. The clock of each
Generator can be divided. The outputs from the Generators are used as sources for the Peripheral
Channels, which provide the Generic Clock (GCLK_PERIPH) to the peripheral modules, as shown in
Figure 17-2 Generic Clock Controller Block Diagram. The number of Peripheral Clocks depends on how
many peripherals the device has.
Note: The Generator 0 is always the direct source of the GCLK_MAIN signal.
17.2.
Features
•
•
17.3.
Provides a device-defined, configurable number of Peripheral Channel clocks
Wide frequency range
Block Diagram
The generation of Peripheral Clock signals (GCLK_PERIPH) and the Main Clock (GCLK_MAIN) can be
seen in Device Clocking Diagram.
Figure 17-1. Device Clocking Diagram
GENERIC CLOCK CONTROLLER
OSCCTRL
Generic Clock Generator
XOSC
DPLL96M
Peripheral Channel
OSC48M
GCLK_PERIPH
OSC32CTRL
XOSC32K
Clock
Divider &
Masker
Clock
Gate
PERIPHERAL
OSCULP32K
OSC32K
GCLK_MAIN
MCLK
The GCLK block diagram is shown below:
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Figure 17-2. Generic Clock Controller Block Diagram
Clock Generator 0
Clock Sources
GCLK_MAIN
GCLKGEN[0]
Clock
Divider &
Masker
GCLK_IO[0]
(I/O input)
Peripheral Channel 0
Clock
Gate
Generic Clock Generator 1
Peripheral Channel 1
Clock
Divider &
Masker
GCLK_IO[1]
(I/O input)
GCLK_IO[0]
(I/O output)
GCLK_PERIPH[0]
GCLK_IO[1]
(I/O output)
GCLKGEN[1]
Clock
Gate
GCLK_PERIPH[1]
Generic Clock Generator n
GCLK_IO[n]
(I/O input)
Clock
Divider &
Masker
GCLK_IO[n]
(I/O output)
GCLKGEN[n]
Peripheral Channel m
Clock
Gate
GCLK_PERIPH[m]
GCLKGEN[n:0]
17.4.
Signal Description
Table 17-1. GCLK Signal Description
Signal Name
Type
Description
GCLK_IO[7:0]
Digital I/O
Clock source for Generators
when input
Generic Clock signal when output
Note: One signal can be mapped on several pins.
Related Links
I/O Multiplexing and Considerations on page 28
17.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
17.5.1.
I/O Lines
Using the GCLK I/O lines requires the I/O pins to be configured.
Related Links
PORT - I/O Pin Controller on page 455
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17.5.2.
Power Management
The GCLK can operate in all sleep modes, if required.
Related Links
PM – Power Manager on page 177
17.5.3.
Clocks
The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Main Clock Controller.
Related Links
Peripheral Clock Masking on page 152
OSC32KCTRL – 32KHz Oscillators Controller on page 225
17.5.4.
DMA
Not applicable.
17.5.5.
Interrupts
Not applicable.
17.5.6.
Events
Not applicable.
17.5.7.
Debug Operation
When the CPU is halted in debug mode the GCLK continues normal operation. If the GCLK is configured
in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
17.5.8.
Register Access Protection
All registers with write-access can be optionally write-protected by the Peripheral Access Controller
(PAC).
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection
does not apply for accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
17.5.9.
Analog Connections
Not applicable.
17.6.
Functional Description
17.6.1.
Principle of Operation
The GCLK module is comprised of nine Generic Clock Generators (Generators) sourcing up to 64
Peripheral Channels and the Main Clock signal GCLK_MAIN.
A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the
Generator. A generator output is used by one or more Peripheral Channels to provide a peripheral
generic clock signal (GCLK_PERIPH) to the peripherals.
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17.6.2.
Basic Operation
17.6.2.1. Initialization
Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock
must be configured as outlined by the following steps:
1. The Generator must be enabled (GENCTRLn.GENEN=1) and the division factor must be set
(GENTRLn.DIVSEL and GENCTRLn.DIV) by performing a single 32-bit write to the Generator
Control register (GENCTRLn).
2. The Generic Clock for a peripheral must be configured by writing to the respective Peripheral
Channel Control register (PCHCTRLm). The Generator used as the source for the Peripheral Clock
must be written to the GEN bit field in the Peripheral Channel Control register (PCHCTRLm.GEN).
Note: Each Generator n is configured by one dedicated register GENCTRLn.
Note: Each Peripheral Channel m is configured by one dedicated register PCHCTRLm.
17.6.2.2. Enabling, Disabling, and Resetting
The GCLK module has no enable/disable bit to enable or disable the whole module.
The GCLK is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST) to 1. All
registers in the GCLK will be reset to their initial state, except for Peripheral Channels and associated
Generators that have their Write Lock bit set to 1 (PCHCTRLm.WRTLOCK). For further details, refer to
Configuration Lock.
17.6.2.3. Generic Clock Generator
Each Generator (GCLK_GEN) can be set to run from one of nine different clock sources except
GCLK_GEN[1], which can be set to run from one of eight sources. GCLK_GEN[1] is the only Generator
that can be selected as source to others Generators.
Each generator GCLK_GEN[x] can be connected to one specific pin (GCLK_IO[y]). The GCLK_IO[y] can
be set to act as source to GCLK_GEN[x] or to output the clock signal generated by GCLK_GEN[x].
The selected source can be divided. Each Generator can be enabled or disabled independently.
Each GCLK_GEN clock signal can then be used as clock source for Peripheral Channels. Each
Generator output is allocated to one or several Peripherals.
GCLK_GEN[0] is used as GCLK_MAIN for the synchronous clock controller inside the Main Clock
Controller. Refer to the Main Clock Controller description for details on the synchronous clock generation.
Figure 17-3. Generic Clock Generator
Related Links
MCLK – Main Clock on page 149
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17.6.2.4. Enabling a Generator
A Generator is enabled by writing a '1' to the Generator Enable bit in the Generator Control register
(GENCTRLn.GENEN=1).
17.6.2.5. Disabling a Generator
A Generator is disabled by writing a '0' to GENCTRLn.GENEN. When GENCTRLn.GENEN=0, the
GCLK_GEN[n] clock is disabled and gated.
17.6.2.6. Selecting a Clock Source for the Generator
Each Generator can individually select a clock source by setting the Source Select bit group in the
Generator Control register (GENCTRLn.SRC).
Changing from one clock source, for example A, to another clock source, B, can be done on the fly: If
clock source B is not ready, the Generator will continue using clock source A. As soon as source B is
ready, the Generator will switch to it. During the switching operation, the Generator maintains clock
requests to both clock sources A and B, and will release source A as soon as the switch is done. The
according bit in SYNCBUSY register (SYNCBUSY.GENCTRLn) will remain '1' until the switch operation is
completed.
The available clock sources are device dependent (usually the oscillators, RC oscillators, DPLL, and
DFLL). Only Generator 1 can be used as a common source for all other generators.
17.6.2.7. Changing the Clock Frequency
The selected source for a Generator can be divided by writing a division value in the Division Factor bit
field of the Generator Control register (GENCTRLn.DIV). How the actual division factor is calculated is
depending on the Divide Selection bit (GENCTRLn.DIVSEL).
If GENCTRLn.DIVSEL=0 and GENCTRLn.DIV is either 0 or 1, the output clock will be undivided.
Note: The number of DIV bits for each Generator is device dependent.
17.6.2.8. Duty Cycle
When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Setting the Improve
Duty Cycle bit of the Generator Control register (GENCTRLn.IDC) will result in a 50/50 duty cycle.
17.6.2.9. External Clock
The output clock (GCLK_GEN) of each Generator can be sent to I/O pins (GCLK_IO).
If the Output Enable bit in the Generator Control register is set (GENCTRLn.OE = 1) and the generator is
enabled (GENCTRLn.GENEN=1), the Generator requests its clock source and the GCLK_GEN clock is
output to an I/O pin.
If GENCTRLn.OE is 0, the according I/O pin is set to an Output Off Value, which is selected by
GENCTRLn.OOV: If GENCTRLn.OOV is '0', the output clock will be low when turned off. If this bit is '1',
the output clock will be high when turned off.
In Standby mode, if the clock is output (GENCTRLn.OE=1), the clock on the I/O pin is frozen to the OOV
value if the Run In Standby bit of the Generic Control register (GENCTRLn.RUNSTDBY) is zero.
Note: With GENCTRLn.OE=1 and RUNSTDBY=0, entering the Standby mode can take longer due to a
clock source dependent delay between turning off Power Domain 1 and 2. The maximum delay can be
equal to the clock source period multiplied by the division factor.
If GENCTRLn.RUNSTDBY is '1', the GCLKGEN clock is kept running and output to the I/O pin.
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17.6.3.
Peripheral Clock
Figure 17-4. Peripheral Clock
17.6.3.1. Enabling a Peripheral Clock
Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and
selected as source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral
Channel Control register (PCHCTRL.GEN). Any available Generator can be selected as clock source for
each Peripheral Channel.
When a Generator has been selected, the peripheral clock is enabled by setting the Channel Enable bit in
the Peripheral Channel Control register, PCHCTRLm.CHEN = 1. The PCHCTRLm.CHEN bit must be
synchronized to the generic clock domain. PCHCTRLm.CHEN will continue to read as its previous state
until the synchronization is complete.
17.6.3.2. Disabling a Peripheral Clock
A Peripheral Clock is disabled by writing PCHCTRLm.CHEN=0. The PCHCTRLm.CHEN bit must be
synchronized to the Generic Clock domain. PCHCTRLm.CHEN will stay in its previous state until the
synchronization is complete. The Peripheral Clock is gated when disabled.
Related Links
PCHCTRLmn on page 146
17.6.3.3. Selecting the Clock Source for a Peripheral
When changing a peripheral clock source by writing to PCHCTRLm.GEN, the peripheral clock must be
disabled before re-enabling it with the new clock source setting. This prevents glitches during the
transition:
1. Disable the Peripheral Channel by writing PCHCTRLm.CHEN=0
2. Assert that PCHCTRLm.CHEN reads '0'
3. Change the source of the Peripheral Channel by writing PCHCTRLm.GEN
4. Re-enable the Peripheral Channel by writing PCHCTRLm.CHEN=1
Related Links
PCHCTRLmn on page 146
17.6.3.4. Configuration Lock
The peripheral clock configuration can be locked for further write accesses by setting the Write Lock bit in
the Peripheral Channel Control register PCHCTRLm.WRTLOCK=1). All writing to the PCHCTRLm
register will be ignored. It can only be unlocked by a Power Reset.
The Generator source of a locked Peripheral Channel will be locked, too: The corresponding GENCTRLn
register is locked, and can be unlocked only by a Power Reset.
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There is one exception concerning the Generator 0. As it is used as GCLK_MAIN, it cannot be locked. It
is reset by any Reset and will start up in a known configuration. The software reset (CTRLA.SWRST) can
not unlock the registers.
In case of an external Reset, the Generator source will be disabled. Even if the WRTLOCK bit is written to
'1' the peripheral channels are disabled (PCHCTRLm.CHEN set to '0') until the Generator source is
enabled again. Then, the PCHCTRLm.CHEN are set to '1' again.
Related Links
CTRLA on page 141
PCHCTRLmn on page 146
17.6.4.
Additional Features
17.6.4.1. Peripheral Clock Enable after Reset
The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a
Reset. That means that the configuration of the Generators and Peripheral Channels after Reset is
device-dependent.
Refer to GENCTRLn.SRC for details on GENCTRLn reset.
Refer to PCHCTRLm.SRC for details on PCHCTRLm reset.
17.6.5.
Sleep Mode Operation
17.6.5.1. SleepWalking
The GCLK module supports the SleepWalking feature.
If the system is in a sleep mode where the Generic Clocks are stopped, a peripheral that needs its clock
in order to execute a process must request it from the Generic Clock Controller.
The Generic Clock Controller receives this request, determines which Generic Clock Generator is
involved and which clock source needs to be awakened. It then wakes up the respective clock source,
enables the Generator and Peripheral Channel stages successively, and delivers the clock to the
peripheral.
The RUNSTDBY bit in the Generator Control register controls clock output to pin during standby sleep
mode. If the bit is cleared, the Generator output is not available on pin. When set, the GCLK can
continuously output the generator output to GCLK_IO. Refer to External Clock for details.
Related Links
PM – Power Manager on page 177
17.6.5.2. Minimize Power Consumption in Standby
The following table identifies when a Clock Generator is off in Standby Mode, minimizing the power
consumption:
Table 17-2. Clock Generator n Activity in Standby Mode
Request for Clock n
present
GENCTRLn.RUNSTDB
Y
GENCTRLn.OE
Clock Generator n
yes
-
-
active
no
1
1
active
no
1
0
OFF
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Request for Clock n
present
GENCTRLn.RUNSTDB
Y
GENCTRLn.OE
Clock Generator n
no
0
1
OFF
no
0
0
OFF
17.6.5.3. Entering Standby Mode
There may occur a delay when the device is put into Standby, until the power is turned off. This delay is
caused by running Clock Generators: if the Run in Standby bit in the Generator Control register
(GENCTRLn.RUNSTDBY) is '0', GCLK must verify that the clock is turned of properly. The duration of this
verification is frequency-dependent.
Related Links
PM – Power Manager on page 177
17.6.6.
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN).
When changing this bit, the bit value must be read-back to ensure the synchronization is complete and to
assert glitch free internal operation. Note that changing the bit value under ongoing synchronization will
not generate an error.
The following registers are synchronized when written:
•
•
Generic Clock Generator Control register (GENCTRLn)
Control A register (CTRLA)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
Related Links
CTRLA on page 141
Register Synchronization on page 123
PCHCTRLmn on page 146
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17.7.
Register Summary
Offset
Name
Bit Pos.
0x00
CTRLA
7:0
SWRST
0x01
...
Reserved
0x03
0x04
7:0
0x05
15:8
0x06
SYNCBUSY
0x07
GENCTRL5
GENCTRL4
GENCTRL3
GENCTRL2
GENCTRL1
GENCTRL0
GENCTRL8
SWRST
GENCTRL7
GENCTRL6
IDC
GENEN
IDC
GENEN
IDC
GENEN
IDC
GENEN
IDC
GENEN
IDC
GENEN
IDC
GENEN
IDC
GENEN
23:16
31:24
0x08
...
Reserved
0x1F
0x20
7:0
0x21
15:8
0x22
GENCTRLn0
0x23
DIV[7:0]
DIV[15:8]
7:0
15:8
7:0
0x29
15:8
0x2B
OE
DIV[7:0]
DIV[15:8]
7:0
15:8
GENCTRLn3
DIVSEL
31:24
0x2D
DIVSEL
OE
DIV[7:0]
0x2F
31:24
DIV[15:8]
0x30
7:0
0x31
15:8
0x32
0x33
DIV[7:0]
7:0
GENCTRLn5
7:0
0x39
15:8
0x3B
DIV[7:0]
7:0
0x3F
OE
DIV[15:8]
15:8
GENCTRLn7
DIVSEL
31:24
0x3D
OOV
SRC[4:0]
RUNSTDBY
23:16
0x3C
0x3E
OE
DIV[15:8]
31:24
0x3A
DIVSEL
DIV[7:0]
0x37
OOV
SRC[4:0]
RUNSTDBY
23:16
0x38
GENCTRLn6
OE
DIV[15:8]
15:8
0x36
DIVSEL
31:24
0x35
OOV
SRC[4:0]
RUNSTDBY
23:16
0x34
OOV
SRC[4:0]
RUNSTDBY
23:16
GENCTRLn4
OOV
SRC[4:0]
RUNSTDBY
23:16
0x2C
0x2E
OE
DIV[15:8]
31:24
0x2A
DIVSEL
DIV[7:0]
0x27
OOV
SRC[4:0]
RUNSTDBY
23:16
0x28
GENCTRLn2
OE
31:24
0x25
GENCTRLn1
DIVSEL
23:16
0x24
0x26
SRC[4:0]
RUNSTDBY
OOV
SRC[4:0]
RUNSTDBY
DIVSEL
OE
23:16
DIV[7:0]
31:24
DIV[15:8]
OOV
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Offset
Name
Bit Pos.
0x40
7:0
0x41
15:8
0x42
GENCTRLn8
0x43
SRC[4:0]
RUNSTDBY
DIVSEL
OE
23:16
DIV[7:0]
31:24
DIV[15:8]
OOV
IDC
GENEN
0x44
...
Reserved
0x7F
0x80
7:0
0x81
15:8
0x82
PCHCTRLm0
0x83
7:0
15:8
PCHCTRLm1
0x87
7:0
15:8
PCHCTRLm2
0x8B
7:0
15:8
PCHCTRLm3
0x8F
7:0
15:8
PCHCTRLm4
0x93
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
31:24
7:0
0x95
15:8
PCHCTRLm5
0x97
23:16
31:24
0x98
7:0
0x99
15:8
PCHCTRLm6
0x9B
23:16
31:24
0x9C
7:0
0x9D
15:8
PCHCTRLm7
0x9F
23:16
31:24
0xA0
7:0
0xA1
15:8
PCHCTRLm8
0xA3
23:16
31:24
0xA4
7:0
0xA5
15:8
0xA7
WRTLOCK
23:16
0x94
0xA6
GEN[3:0]
31:24
0x91
0xA2
CHEN
23:16
0x90
0x9E
WRTLOCK
31:24
0x8D
0x9A
GEN[3:0]
23:16
0x8C
0x96
CHEN
31:24
0x89
0x92
WRTLOCK
23:16
0x88
0x8E
GEN[3:0]
31:24
0x85
0x8A
CHEN
23:16
0x84
0x86
WRTLOCK
PCHCTRLm9
23:16
31:24
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Offset
Name
Bit Pos.
0xA8
7:0
0xA9
15:8
0xAA
PCHCTRLm10
0xAB
31:24
7:0
0xAE
PCHCTRLm11
0xAF
7:0
PCHCTRLm12
31:24
0xB4
7:0
PCHCTRLm13
0xB7
7:0
PCHCTRLm14
0xBB
31:24
7:0
PCHCTRLm15
0xBF
7:0
PCHCTRLm16
31:24
0xC4
7:0
PCHCTRLm17
0xC7
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
15:8
31:24
7:0
0xC9
15:8
PCHCTRLm18
23:16
0xCB
31:24
0xCC
7:0
PCHCTRLm19
0xCF
15:8
23:16
31:24
0xD0
7:0
0xD1
15:8
0xD3
GEN[3:0]
23:16
0xC8
0xD2
CHEN
23:16
0xC3
0xCE
WRTLOCK
31:24
15:8
0xCD
GEN[3:0]
15:8
0xC1
0xCA
CHEN
23:16
0xC0
0xC6
WRTLOCK
23:16
0xBC
0xC5
GEN[3:0]
31:24
15:8
0xC2
CHEN
15:8
0xB9
0xBE
WRTLOCK
23:16
0xB8
0xBD
GEN[3:0]
23:16
0xB3
0xBA
CHEN
31:24
15:8
0xB6
WRTLOCK
15:8
0xB1
0xB5
GEN[3:0]
23:16
0xB0
0xB2
CHEN
23:16
0xAC
0xAD
WRTLOCK
PCHCTRLm20
23:16
31:24
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Offset
Name
Bit Pos.
0xD4
7:0
0xD5
15:8
0xD6
PCHCTRLm21
31:24
0xD8
7:0
0xD9
PCHCTRLm22
0xDB
7:0
PCHCTRLm23
31:24
0xE0
7:0
PCHCTRLm24
0xE3
7:0
PCHCTRLm25
31:24
0xE8
7:0
PCHCTRLm26
0xEB
7:0
PCHCTRLm27
31:24
0xF0
7:0
PCHCTRLm28
0xF3
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
15:8
31:24
7:0
0xF5
15:8
PCHCTRLm29
23:16
0xF7
31:24
0xF8
7:0
PCHCTRLm30
0xFB
15:8
23:16
31:24
0xFC
7:0
0xFD
15:8
0xFF
GEN[3:0]
23:16
0xF4
0xFE
CHEN
23:16
0xEF
0xF9
WRTLOCK
31:24
15:8
0xFA
GEN[3:0]
15:8
0xED
0xF6
CHEN
23:16
0xEC
0xF2
WRTLOCK
23:16
0xE7
0xF1
GEN[3:0]
31:24
15:8
0xEE
CHEN
15:8
0xE5
0xE9
WRTLOCK
23:16
0xE4
0xEA
GEN[3:0]
23:16
0xDF
0xE6
CHEN
31:24
15:8
0xE2
WRTLOCK
15:8
0xDD
0xE1
GEN[3:0]
23:16
0xDC
0xDE
CHEN
23:16
0xD7
0xDA
WRTLOCK
PCHCTRLm31
23:16
31:24
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Offset
Name
Bit Pos.
0x0100
7:0
0x0101
15:8
0x0102
PCHCTRLm32
31:24
0x0104
7:0
0x0106
PCHCTRLm33
0x0107
7:0
PCHCTRLm34
0x010B
31:24
7:0
PCHCTRLm35
0x010F
7:0
PCHCTRLm36
31:24
0x0114
7:0
PCHCTRLm37
0x0117
7:0
PCHCTRLm38
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
WRTLOCK
CHEN
GEN[3:0]
23:16
0x011B
31:24
0x011C
7:0
PCHCTRLm39
0x011F
15:8
23:16
31:24
0x0120
7:0
0x0121
15:8
17.8.
WRTLOCK
31:24
15:8
0x0123
GEN[3:0]
15:8
0x0119
0x0122
CHEN
23:16
0x0118
0x011E
WRTLOCK
23:16
0x0113
0x011D
GEN[3:0]
31:24
15:8
0x011A
CHEN
15:8
0x0111
0x0116
WRTLOCK
23:16
0x0110
0x0115
GEN[3:0]
23:16
0x010C
0x0112
CHEN
31:24
15:8
0x010E
WRTLOCK
15:8
0x0109
0x010D
GEN[3:0]
23:16
0x0108
0x010A
CHEN
23:16
0x0103
0x0105
WRTLOCK
PCHCTRLm40
23:16
31:24
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
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Some registers are synchronized when read and/or written. Synchronization is denoted by the "WriteSynchronized" or the "Read-Synchronized" property in each individual register description. For details,
refer to Synchronization.
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17.8.1.
Control A
Name: CTRLA
Offset: 0x0
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
SWRST
Access
R/W
Reset
0
Bit 0 – SWRST: Software Reset
Writing a zero to this bit has no effect.
Setting this bit to 1 will reset all registers in the GCLK to their initial state after a Power Reset, except for
generic clocks and associated Generators that have their WRTLOCK bit in PCHCTRLm set to 1.
Refer to GENCTRL Reset Value for details on GENCTRL register reset.
Refer to PCHCTRL Reset Value for details on PCHCTRL register reset.
Due to synchronization, there is a waiting period between setting CTRLA.SWRST and a completed
Reset. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value
Description
0
There is no Reset operation ongoing.
1
A Reset operation is ongoing.
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17.8.2.
Synchronization Busy
Name: SYNCBUSY
Offset: 0x04
Reset: 0x00000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
Bit
GENCTRL8
GENCTRL7
GENCTRL6
Access
R
R
R
Reset
0
0
0
1
0
Bit
7
6
5
4
3
2
GENCTRL5
GENCTRL4
GENCTRL3
GENCTRL2
GENCTRL1
GENCTRL0
SWRST
Access
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
Bit 0 – SWRST: SWRST Synchronization Busy
This bit is cleared when the synchronization of the CTRLA.SWRST register bit between clock domains is
complete.
This bit is set when the synchronization of the CTRLA.SWRST register bit between clock domains is
started.
Bits 2,3,4,5,6,7,8,9,10 – GENCTRLx: Generator Control x Synchronization Busy
This bit is cleared when the synchronization of the Generator Control n register (GENCTRLn) between
clock domains is complete, or when clock switching operation is complete.
This bit is set when the synchronization of the Generator Control n register (GENCTRLn) between clock
domains is started.
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17.8.3.
Generator Control
GENCTRLn controls the settings of Generic Generator n (n=0..8).
Name: GENCTRLn
Offset: 0x20 + n*0x04 [n=0..8]
Reset: 0x00000106 for Generator n=0, else 0x00000000
Property: PAC Write-Protection, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
DIV[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
DIV[7:0]
Access
13
12
11
10
9
8
RUNSTDBY
DIVSEL
OE
OOV
IDC
GENEN
5
4
3
2
1
0
Access
Reset
Bit
7
6
SRC[4:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bits 31:16 – DIV[15:0]: Division Factor
These bits represent a division value for the corresponding Generator. The actual division factor is
dependent on the state of DIVSEL. The number of relevant DIV bits for each Generator can be seen in
this table. Written bits outside of the specified range will be ignored.
Table 17-3. Division Factor Bits
Generic Clock Generator
Division Factor Bits
Generator 0
8 division factor bits - DIV[7:0]
Generator 1
16 division factor bits - DIV[15:0]
Generator 2
5 division factor bits - DIV[4:0]
Generator 3 - 8
8 division factor bits - DIV[7:0]
Bit 13 – RUNSTDBY: Run in Standby
This bit is used to keep the Generator running in Standby as long as it is configured to output to a
dedicated GCLK_IO pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be
running if a peripheral requires the clock.
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Value
Description
0
The Generator is stopped in Standby and the GCLK_IO pin state (one or zero) will be
dependent on the setting in GENCTRL.OOV.
1
The Generator is kept running and output to its dedicated GCLK_IO pin during Standby
mode.
Bit 12 – DIVSEL: Divide Selection
This bit determines how the division factor of the clock source of the Generator will be calculated from
DIV. If the clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be
either 0 or 1.
Value
Description
0
The Generator clock frequency equals the clock source frequency divided by
GENCTRLn.DIV.
1
The Generator clock frequency equals the clock source frequency divided by
2^(GENCTRLn.DIV+1).
Bit 11 – OE: Output Enable
This bit is used to output the Generator clock output to the corresponding pin (GCLK_IO), as long as
GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field.
Value
Description
0
No Generator clock signal on pin GCLK_IO.
1
The Generator clock signal is output on the corresponding GCLK_IO, unless GCLK_IO is
selected as a generator source in the GENCTRLn.SRC bit field.
Bit 10 – OOV: Output Off Value
This bit is used to control the clock output value on pin (GCLK_IO) when the Generator is turned off or the
OE bit is zero, as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit
field.
Value
Description
0
The GCLK_IO will be LOW when generator is turned off or when the OE bit is zero.
1
The GCLK_IO will be HIGH when generator is turned off or when the OE bit is zero.
Bit 9 – IDC: Improve Duty Cycle
This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors.
Value
Description
0
Generator output clock duty cycle is not balanced to 50/50 for odd division factors.
1
Generator output clock duty cycle is 50/50.
Bit 8 – GENEN: Generator Enable
This bit is used to enable and disable the Generator.
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Value
Description
0
Generator is disabled.
1
Generator is enabled.
Bits 4:0 – SRC[4:0]: Generator Clock Source Selection
These bits select the Generator clock source, as shown in this table.
Table 17-4. Generator Clock Source Selection
Value
Name
Description
0x00
XOSC
XOSC oscillator output
0x01
GCLK_IN
Generator input pad (GCLK_IO)
0x02
GCLK_GEN1
Generic clock generator 1 output
0x03
OSCULP32K
OSCULP32K oscillator output
0x04
OSC32K
OSC32K oscillator output
0x05
XOSC32K
XOSC32K oscillator output
0x06
OSC48M
OSC48M oscillator output
0x07
DPLL96M
DPLL96M output
0x08-0x1F
Reserved
Reserved for future use
A Power Reset will reset all GENCTRLn registers. the Reset values of the GENCTRLn registers are
shown in table below.
Table 17-5. GENCTRLn Reset Value after a Power Reset
GCLK Generator
Reset Value after a Power Reset
0
0x00000106
others
0x00000000
A User Reset will reset the associated GENCTRL register unless the Generator is the source of a locked
Peripheral Channel (PCHCTRLm.WRTLOCK=1). The reset values of the GENCTRL register are as
shown in the table below.
Table 17-6. GENCTRLn Reset Value after a User Reset
GCLK Generator Reset Value after a User Reset
0
0x00000106
others
No change if the generator is used by a Peripheral Channel m with
PCHCTRLm.WRTLOCK=1
else 0x00000000
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17.8.4.
Peripheral Channel Control
PCHTRLm controls the settings of Peripheral Channel number m (m=0..40).
Name: PCHCTRLmn
Offset: 0x80 + n*0x04 [n=0..40]
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
WRTLOCK
CHEN
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
GEN[3:0]
Bit 7 – WRTLOCK: Write Lock
After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of
the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can
only be unlocked by a Power Reset.
Note that Generator 0 cannot be locked.
Value
Description
0
The Peripheral Channel register and the associated Generator register are not locked
1
The Peripheral Channel register and the associated Generator register are locked
Bit 6 – CHEN: Channel Enable
This bit is used to enable and disable a Peripheral Channel.
Value
Description
0
The Peripheral Channel is disabled
1
The Peripheral Channel is enabled
Bits 3:0 – GEN[3:0]: Generator Selection
This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table
below:
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Table 17-7. Generator Selection
Value
Description
0x0
Generic Clock Generator 0
0x1
Generic Clock Generator 1
0x2
Generic Clock Generator 2
0x3
Generic Clock Generator 3
0x4
Generic Clock Generator 4
0x5
Generic Clock Generator 5
0x6
Generic Clock Generator 6
0x7
Generic Clock Generator 7
0x8
Generic Clock Generator 8
0x9 - 0xF
Reserved
Table 17-8. Reset Value after a User Reset or a Power Reset
Reset
PCHCTRLm.GEN
PCHCTRLm.CHEN
PCHCTRLm.WRTLOCK
Power Reset 0x0
0x0
0x0
User Reset
If WRTLOCK = 0
: 0x0
If WRTLOCK = 0
: 0x0
No change
If WRTLOCK = 1: no change
If WRTLOCK = 1: no change
A Power Reset will reset all the PCHCTRLm registers.
A User Reset will reset a PCHCTRL if WRTLOCK=0, or else, the content of that PCHCTRL remains
unchanged.
PCHCTRL register Reset values are shown in the table PCHCTRLm Mapping.
Table 17-9. PCHCTRLm Mapping
index(m) Name
Description
0
GCLK_DPLL
FDPLL96M input clock source for reference
1
GCLK_DPLL_32K
FDPLL96M 32kHz clock for FDPLL96M internal clock
timer
2
GCLK_EIC
EIC
3
GCLK_FREQM_MSR
FREQM Measure
4
GCLK_FREQM_REF
FREQM Reference
5
-
Reserved
6
GCLK_EVSYS_CHANNEL_0
EVSYS_CHANNEL_0
7
GCLK_EVSYS_CHANNEL_1
EVSYS_CHANNEL_1
8
GCLK_EVSYS_CHANNEL_2
EVSYS_CHANNEL_2
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index(m) Name
Description
9
GCLK_EVSYS_CHANNEL_3
EVSYS_CHANNEL_3
10
GCLK_EVSYS_CHANNEL_4
EVSYS_CHANNEL_4
11
GCLK_EVSYS_CHANNEL_5
EVSYS_CHANNEL_5
12 - 17
-
Reserved
18
GCLK_SERCOM[0,1,2,3]_SLOW SERCOM[0,1,2,3]_SLOW
19
GCLK_SERCOM0_CORE
SERCOM0_CORE
20
GCLK_SERCOM1_CORE
SERCOM1_CORE
21
GCLK_SERCOM2_CORE
SERCOM2_CORE
22
GCLK_SERCOM3_CORE
SERCOM3_CORE
23
-
Reserved
24
-
Reserved
25
-
Reserved
26
-
Reserved
27
-
Reserved
28
GCLK_TCC0, GCLK_TCC1
TCC0,TCC1
29
GCLK_TCC2
TCC2
30
GCLK_TC0, GCLK_TC1
TC0,TC1
31
GCLK_TC2, GCLK_TC3
TC2,TC3
32
GCLK_TC4
TC4
33
GCLK_ADC0
ADC0
34
-
Reserved
35
-
Reserved
36
-
Reserved
37
GCLK_PTC
PTC
38
GCLK_CCL
CCL
39
-
Reserved
40
GCLK_AC
AC
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18.
MCLK – Main Clock
18.1.
Overview
The Main Clock (MCLK) controls the synchronous clock generation of the device.
Using a clock provided by the Generic Clock Module (GCLK_MAIN), the Main Clock Controller provides
synchronous system clocks to the CPU and the modules connected to the AHBx and the APBx bus. The
synchronous system clocks are divided into a number of clock domains. Each clock domain can run at
different frequencies, enabling the user to save power by running peripherals at a relatively low clock
frequency, while maintaining high CPU performance or vice versa. In addition, the clock can be masked
for individual modules, enabling the user to minimize power consumption.
18.2.
18.3.
Features
•
Generates CPU, AHB, and APB system clocks
– Clock source and division factor from GCLK
– Clock prescaler with 1x to 128x division
•
•
Safe run-time clock switching from GCLK
Module-level clock gating through maskable peripheral clocks
Block Diagram
Figure 18-1. MCLK Block Diagram
CLK_APBx
GCLK
GCLK_MAIN
MAIN
CLOCK CONTROLLER
CLK_AHBx
PERIPHERALS
CLK_CPU
CPU
18.4.
Signal Description
Not applicable.
18.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
18.5.1.
I/O Lines
Not applicable.
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18.5.2.
Power Management
The MCLK will operate in all sleep modes if a synchronous clock is required in these modes.
Related Links
PM – Power Manager on page 177
18.5.3.
Clocks
The MCLK bus clock (CLK_MCLK_APB) can be enabled and disabled in the Main Clock module, and the
default state of CLK_MCLK_APB can be found in the Peripheral Clock Masking section. If this clock is
disabled, it can only be re-enabled by a reset.
The Generic Clock GCLK_MAIN is required to generate the Main Clocks. GCLK_MAIN is configured in
the Generic Clock Controller, and can be re-configured by the user if needed.
Related Links
GCLK - Generic Clock Controller on page 127
Peripheral Clock Masking on page 152
18.5.3.1. Main Clock
The main clock GCLK_MAIN is the common source for the synchronous clocks. This is fed into the
common 8-bit prescaler that is used to generate synchronous clocks to the CPU, AHBx, and APBx
modules.
18.5.3.2. CPU Clock
The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing
instructions.
18.5.3.3. APBx and AHBx Clock
The APBx clocks (CLK_APBx) and the AHBx clocks (CLK_AHBx) are the root clock source used by
modules requiring a clock on the APBx and the AHBx bus. These clocks are always synchronous to the
CPU clock, but can be divided by a prescaler, and can run even when the CPU clock is turned off in sleep
mode. A clock gater is inserted after the common APB clock to gate any APBx clock of a module on
APBx bus, as well as the AHBx clock.
18.5.3.4. Clock Domains
The device has these synchronous clock domains:
•
CPU synchronous clock domain (CPU Clock Domain). Frequency is fCPU.
See also the related links for the clock domain partitioning.
Related Links
Peripheral Clock Masking on page 152
18.5.4.
DMA
Not applicable.
18.5.5.
Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the MCLK interrupt requires the
Interrupt Controller to be configured first.
18.5.6.
Events
Not applicable.
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18.5.7.
Debug Operation
When the CPU is halted in debug mode, the MCLK continues normal operation. In sleep mode, the clocks
generated from the MCLK are kept running to allow the debugger accessing any module. As a
consequence, power measurements are incorrect in debug mode.
18.5.8.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except the following registers:
•
Interrupt Flag register (INTFLAG)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
18.5.9.
Analog Connections
Not applicable.
18.6.
Functional Description
18.6.1.
Principle of Operation
The GCLK_MAIN clock signal from the GCLK module is the source for the main clock, which in turn is the
common root for the synchronous clocks for the CPU, APBx, and AHBx modules. The GCLK_MAIN is
divided by an 8-bit prescaler. Each of the derived clocks can run from any divided or undivided main
clock, ensuring synchronous clock sources for each clock domain. The clock domain (CPU) can be
changed on the fly to respond to variable load in the application. The clocks for each module in a clock
domain can be masked individually to avoid power consumption in inactive modules. Depending on the
sleep mode, some clock domains can be turned off.
18.6.2.
Basic Operation
18.6.2.1. Initialization
After a Reset, the default clock source of the GCLK_MAIN clock is started and calibrated before the CPU
starts running. The GCLK_MAIN clock is selected as the main clock without any prescaler division.
By default, only the necessary clocks are enabled.
Related Links
Peripheral Clock Masking on page 152
18.6.2.2. Enabling, Disabling, and Resetting
The MCLK module is always enabled and cannot be reset.
18.6.2.3. Selecting the Main Clock Source
Refer to the Generic Clock Controller description for details on how to configure the clock source of the
GCLK_MAIN clock.
Related Links
GCLK - Generic Clock Controller on page 127
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18.6.2.4. Selecting the Synchronous Clock Division Ratio
The main clock GCLK_MAIN feeds an 8-bit prescaler, which can be used to generate the synchronous
clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a
prescaler division for the CPU clock domain by writing the Division (DIV) bits in the CPU Clock Division
register CPUDIV, resulting in a CPU clock domain frequency determined by this equation:
���� =
�����
������
If the application attempts to write forbidden values in CPUDIV register, registers are written but these
bad values are not used and a violation is reported to the PAC module.
Division bits (DIV) can be written without halting or disabling peripheral modules. Writing DIV bits allows a
new clock setting to be written to all synchronous clocks belonging to the corresponding clock domain at
the same time.
Figure 18-2. Synchronous Clock Selection and Prescaler
Sleep Controller
Sleep mode
MASK
Clock
gate
CLK_APB_HS
Clock
gate
CLK_AHB_HS
Clock
gate
CLK_CPU
Clock
gate
clk_apb_ipn
clk_apb_ip1
clk_apb_ip0
gate
Clock
gate
Clock
Clock
gate
clk_ahb_ipn
clk_ahb_ip1
clk_ahb_ip0
MASK
GCLKMAIN
GCLK
Prescaler
CPU
Clock Domain: fCPU
PERIPHERALS
CPU
CPUDIV
18.6.2.5. Clock Ready Flag
There is a slight delay between writing to CPUDIV until the new clock settings become effective.
During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register
(INTFLAG.CKRDY) will return zero when read. If CKRDY in the INTENSET register is set to '1', the Clock
Ready interrupt will be triggered when the new clock setting is effective. The clock settings (CLKCFG)
must not be re-written while INTFLAG. CKRDY reads '0'. The system may become unstable or hang, and
a violation is reported to the PAC module.
Related Links
PAC - Peripheral Access Controller on page 48
18.6.2.6. Peripheral Clock Masking
It is possible to disable/enable the AHB or APB clock for a peripheral by writing the corresponding bit in
the Clock Mask registers (APBxMASK) to '0'/'1'. The default state of the peripheral clocks is shown here.
Table 18-1. Peripheral Clock Default State
CPU Clock Domain
Peripheral Clock
Default State
CLK_AC_APB
Disabled
CLK_ADC0_APB
Disabled
CLK_BRIDGE_A_AHB
Enabled
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CPU Clock Domain
Peripheral Clock
Default State
CLK_BRIDGE_B_AHB
Enabled
CLK_BRIDGE_C_AHB
Enabled
CLK_CCL_APB
Disabled
CLK_DIVAS_AHB
Enabled
CLK_DMAC_AHB
Enabled
CLK_DMAC_APB
Enabled
CLK_DSU_AHB
Enabled
CLK_DSU_APB
Enabled
CLK_EIC_APB
Enabled
CLK_EVSYS_APB
Disabled
CLK_FREQM_APB
Enabled
CLK_GCLK_AHB
Enabled
CLK_HAMATRIX_APB
Disabled
CLK_MCLK_APB
Enabled
CLK_MTB_APB
Enabled
CLK_NVMCTRL_AHB
Enabled
CLK_NVMCTRL_APB
Enabled
CLK_OSCCTRL_APB
Enabled
CLK_OSC32CTRL_APB
Enabled
CLK_PAC_AHB
Enabled
CLK_PAC_APB
Enabled
CLK_PM_APB
Enabled
CLK_PORT_APB
Enabled
CLK_PTC_APB
Disabled
CLK_RSTC_APB
Enabled
CLK_RTC_APB
Enabled
CLK_SERCOM0_APB
Disabled
CLK_SERCOM1_AHB
Disabled
CLK_SERCOM2_APB
Disabled
CLK_SERCOM3_APB
Disabled
CLK_SUPC_APB
Enabled
CLK_TCC0_APB
Disabled
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CPU Clock Domain
Peripheral Clock
Default State
CLK_TCC1_APB
Disabled
CLK_TCC2_APB
Disabled
CLK_TC0_APB
Disabled
CLK_TC1_APB
Disabled
CLK_TC2_APB
Disabled
CLK_TC3_APB
Disabled
CLK_TC4_APB
Disabled
CLK_WDT_APB
Enabled
When the APB clock is not provided to a module, its registers cannot be read or written. The module can
be re-enabled later by writing the corresponding mask bit to '1'.
A module may be connected to several clock domains (for instance, AHB and APB), in which case it will
have several mask bits.
Note that clocks should only be switched off if it is certain that the module will not be used: Switching off
the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the
Flash Memory. Switching off the clock to the MCLK module (which contains the mask registers) or the
corresponding APBx bridge, will make it impossible to write the mask registers again. In this case, they
can only be re-enabled by a system reset.
18.6.3.
DMA Operation
Not applicable.
18.6.4.
Interrupts
The peripheral has the following interrupt sources:
•
Clock Ready (CKRDY): indicates that CPU clocks are ready. This interrupt is a synchronous wakeup source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be enabled
individually by writing a '1' to the corresponding enabling bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a '1' to the corresponding clearing bit in the Interrupt Enable Clear
(INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the
peripheral is reset. An interrupt flag is cleared by writing a '1' to the corresponding bit in the INTFLAG
register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt
request line for all the interrupt sources.If the peripheral has one common interrupt request line for all the
interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is
present.
Related Links
Overview on page 43
Sleep Mode Controller on page 179
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PM – Power Manager on page 177
18.6.5.
Events
Not applicable.
18.6.6.
Sleep Mode Operation
In IDLE sleep mode, the MCLK is still running on the selected main clock.
In STANDBY sleep mode, the MCLK is frozen if no synchronous clock is required.
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18.7.
Register Summary
Offset
Name
Bit Pos.
0x00
CTRLA
7:0
0x01
INTENCLR
7:0
CKRDY
0x02
INTENSET
7:0
CKRDY
0x03
INTFLAG
7:0
CKRDY
0x04
Reserved
0x05
CPUDIV
7:0
CPUDIV[7:0]
0x06
...
Reserved
0x0F
0x10
0x11
7:0
AHBMASK
23:16
0x13
31:24
0x14
7:0
APBAMASK
23:16
0x17
31:24
0x18
7:0
0x19
15:8
APBBMASK
0x1B
S
GCLK
SUPC
APBC
APBB
APBA
DIVAS
Reserved
PAC
OSCCTRL
RSTC
MCLK
PM
PAC
FREQM
EIC
RTC
WDT
NVMCTRL
DSU
PORT
EVSYS
31:24
7:0
15:8
TC3
TC2
23:16
CCL
PTC
18.8.
L
DSU
23:16
0x1D
0x1F
OSC32KCTR
HMATRIXHS
HMATRIXHS
0x1C
0x1E
NVMCTRL
15:8
0x16
0x1A
HMCRAMCH
15:8
0x12
0x15
DMAC
APBCMASK
TC1
SERCOM3
SERCOM2
SERCOM1
SERCOM0
TC0
TCC2
TCC1
TCC0
AC
ADC0
TC4
31:24
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers can be write-protected optionally by the Peripheral Access Controller (PAC). This is
denoted by the property "PAC Write-Protection" in each individual register description. Refer to the
Register Access Protection for details.
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18.8.1.
Control A
All bits in this register are reserved.
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
Access
Reset
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18.8.2.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
CKRDY
Access
R/W
Reset
0
Bit 0 – CKRDY: Clock Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt
request.
Value
Description
0
The Clock Ready interrupt is disabled.
1
The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock
Ready Interrupt Flag is set.
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18.8.3.
Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x02
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
CKRDY
Access
R/W
Reset
0
Bit 0 – CKRDY: Clock Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt.
Value
Description
0
The Clock Ready interrupt is disabled.
1
The Clock Ready interrupt is enabled.
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18.8.4.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x03
Reset: 0x01
Property: –
Bit
7
6
5
4
3
2
1
0
CKRDY
Access
R/W
Reset
1
Bit 0 – CKRDY: Clock Ready
This flag is cleared by writing a '1' to the flag.
This flag is set when the synchronous CPU, APBx, and AHBx clocks have frequencies as indicated in the
CLKCFG registers and will generate an interrupt if INTENCLR/SET.CKRDY is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Clock Ready interrupt flag.
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18.8.5.
CPU Clock Division
Name: CPUDIV
Offset: 0x05
Reset: 0x01
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
CPUDIV[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
Reset
Bits 7:0 – CPUDIV[7:0]: CPU Clock Division Factor
These bits define the division ratio of the main clock prescaler related to the CPU clock domain.
Frequencies must never exceed the specified maximum frequency for each clock domain.
Value
Name
Description
0x01
DIV1
Divide by 1
0x02
DIV2
Divide by 2
0x04
DIV4
Divide by 4
0x08
DIV8
Divide by 8
0x10
DIV16
Divide by 16
0x20
DIV32
Divide by 32
0x40
DIV64
Divide by 64
0x80
DIV128
Divide by 128
others
-
Reserved
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18.8.6.
AHB Mask
Name: AHBMASK
Offset: 0x10
Reset: 0x000001CFF
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
DIVAS
Reserved
PAC
R/W
R
R/W
1
1
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
5
4
3
2
1
0
DMAC
HMCRAMCHS
NVMCTRL
HMATRIXHS
DSU
APBC
APBB
APBA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Bit 12 – DIVAS: DIVAS AHB Clock Enable
Value
Description
0
The AHB clock for the DIVAS is stopped.
1
The AHB clock for the DIVAS is enabled.
Bit 11 – Reserved
Bit 10 – PAC: PAC AHB Clock Enable
Value
Description
0
The AHB clock for the PAC is stopped.
1
The AHB clock for the PAC is enabled.
Bit 7 – DMAC: DMAC AHB Clock Enable
Value
Description
0
The AHB clock for the DMAC is stopped.
1
The AHB clock for the DMAC is enabled.
Bit 6 – HMCRAMCHS: HMCRAMCHS AHB Clock Enable
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Value
Description
0
The AHB clock for the HMCRAMCHS is stopped.
1
The AHB clock for the HMCRAMCHS is enabled.
Bit 5 – NVMCTRL: NVMCTRL AHB Clock Enable
Value
Description
0
The AHB clock for the NVMCTRL is stopped.
1
The AHB clock for the NVMCTRL is enabled.
Bit 4 – HMATRIXHS: HMATRIXHS AHB Clock Enable
Value
Description
0
The AHB clock for the HMATRIXHS is stopped.
1
The AHB clock for the HMATRIXHS is enabled.
Bit 3 – DSU: DSU AHB Clock Enable
Value
Description
0
The AHB clock for the DSU is stopped.
1
The AHB clock for the DSU is enabled.
Bit 2 – APBC: APBC AHB Clock Enable
Value
Description
0
The AHB clock for the APBC is stopped.
1
The AHB clock for the APBC is enabled
Bit 1 – APBB: APBB AHB Clock Enable
Value
Description
0
The AHB clock for the APBB is stopped.
1
The AHB clock for the APBB is enabled.
Bit 0 – APBA: APBA AHB Clock Enable
Value
Description
0
The AHB clock for the APBA is stopped.
1
The AHB clock for the APBA is enabled.
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18.8.7.
APBA Mask
Name: APBAMASK
Offset: 0x14
Reset: 0x00000FFF
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
FREQM
EIC
RTC
WDT
R/W
R/W
R/W
R/W
1
1
1
1
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
5
4
3
2
GCLK
SUPC
OSC32KCTRL
OSCCTRL
RSTC
MCLK
PM
PAC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Bit 11 – FREQM: FREQM APBA Clock Enable
Value
Description
0
The APBA clock for the FREQM is stopped.
1
The APBA clock for the FREQM is enabled.
Bit 10 – EIC: EIC APBA Clock Enable
Value
Description
0
The APBA clock for the EIC is stopped.
1
The APBA clock for the EIC is enabled.
Bit 9 – RTC: RTC APBA Clock Enable
Value
Description
0
The APBA clock for the RTC is stopped.
1
The APBA clock for the RTC is enabled.
Bit 8 – WDT: WDT APBA Clock Enable
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Value
Description
0
The APBA clock for the WDT is stopped.
1
The APBA clock for the WDT is enabled.
Bit 7 – GCLK: GCLK APBA Clock Enable
Value
Description
0
The APBA clock for the GCLK is stopped.
1
The APBA clock for the GCLK is enabled.
Bit 6 – SUPC: SUPC APBA Clock Enable
Value
Description
0
The APBA clock for the SUPC is stopped.
1
The APBA clock for the SUPC is enabled.
Bit 5 – OSC32KCTRL: OSC32KCTRL APBA Clock Enable
Value
Description
0
The APBA clock for the OSC32KCTRL is stopped.
1
The APBA clock for the OSC32KCTRL is enabled.
Bit 4 – OSCCTRL: OSCCTRL APBA Clock Enable
Value
Description
0
The APBA clock for the OSCCTRL is stopped.
1
The APBA clock for the OSCCTRL is enabled.
Bit 3 – RSTC: RSTC APBA Clock Enable
Value
Description
0
The APBA clock for the RSTC is stopped.
1
The APBA clock for the RSTC is enabled.
Bit 2 – MCLK: MCLK APBA Clock Enable
Value
Description
0
The APBA clock for the MCLK is stopped.
1
The APBA clock for the MCLK is enabled.
Bit 1 – PM: PM APBA Clock Enable
Value
Description
0
The APBA clock for the PM is stopped.
1
The APBA clock for the PM is enabled.
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Bit 0 – PAC: PAC APBA Clock Enable
Value
Description
0
The APBA clock for the PAC is stopped.
1
The APBA clock for the PAC is enabled.
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18.8.8.
APBB Mask
Name: APBBMASK
Offset: 0x18
Reset: 0x00000007
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HMATRIXHS
NVMCTRL
DSU
PORT
R/W
R/W
R/W
R/W
0
1
1
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 5 – HMATRIXHS: HMATRIXHS APBB Clock Enable
Value
Description
0
The APBB clock for the HMATRIXHS is stopped
1
The APBB clock for the HMATRIXHS is enabled
Bit 2 – NVMCTRL: NVMCTRL APBB Clock Enable
Value
Description
0
The APBB clock for the NVMCTRL is stopped
1
The APBB clock for the NVMCTRL is enabled
Bit 1 – DSU: DSU APBB Clock Enable
Value
Description
0
The APBB clock for the DSU is stopped
1
The APBB clock for the DSU is enabled
Bit 0 – PORT: PORT APBB Clock Enable
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Value
Description
0
The APBB clock for the PORT is stopped.
1
The APBB clock for the PORT is enabled.
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18.8.9.
APBC Mask
Name: APBCMASK
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
21
28
27
26
20
19
18
25
24
Access
Reset
Bit
Access
23
22
17
16
CCL
PTC
AC
ADC0
TC4
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
15
14
8
13
12
11
10
9
TC3
TC2
TC1
TC0
TCC2
TCC1
TCC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit
7
6
5
Access
Access
4
3
2
1
0
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Reset
Bit 23 – CCL: CCL APBC Clock Enable
Value
Description
0
The APBC clock for the CCL is stopped.
1
The APBC clock for the CCL is enabled.
Bit 22 – PTC: PTC APBC Mask Clock Enable
Value
Description
0
The APBC clock for the PTC is stopped.
1
The APBC clock for the PTC is enabled.
Bit 20 – AC: AC APBC Clock Enable
Value
Description
0
The APBC clock for the AC is stopped.
1
The APBC clock for the AC is enabled.
Bit 17 – ADC0: ADC0 APBC Clock Enable
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Value
Description
0
The APBC clock for the ADC0 is stopped.
1
The APBC clock for the ADC0 is enabled.
Bit 16 – TC4: TC4 APBC Mask Clock Enable
Bit 15 – TC3: TC3 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC3 is stopped.
1
The APBC clock for the TC3 is enabled.
Bit 14 – TC2: TC2 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC2 is stopped.
1
The APBC clock for the TC2 is enabled.
Bit 13 – TC1: TC1 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC1 is stopped.
1
The APBC clock for the TC1 is enabled.
Bit 12 – TC0: TC0 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC0 is stopped.
1
The APBC clock for the TC0 is enabled.
Bit 11 – TCC2: TCC2 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TCC2 is stopped.
1
The APBC clock for the TCC2 is enabled.
Bit 10 – TCC1: TCC1 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TCC1 is stopped.
1
The APBC clock for the TCC1 is enabled.
Bit 9 – TCC0: TCC0 APBC Mask Clock Enable
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Value
Description
0
The APBC clock for the TCC0 is stopped.
1
The APBC clock for the TCC0 is enabled.
Bit 4 – SERCOM3: SERCOM3 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM3 is stopped.
1
The APBC clock for the SERCOM3 is enabled.
Bit 3 – SERCOM2: SERCOM2 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM2 is stopped.
1
The APBC clock for the SERCOM2 is enabled.
Bit 2 – SERCOM1: SERCOM1 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM1 is stopped.
1
The APBC clock for the SERCOM1 is enabled.
Bit 1 – SERCOM0: SERCOM0 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM0 is stopped.
1
The APBC clock for the SERCOM0 is enabled.
Bit 0 – EVSYS: EVSYS APBC Clock Enable
Value
Description
0
The APBC clock for the EVSYS is stopped.
1
The APBC clock for the EVSYS is enabled.
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19.
RSTC – Reset Controller
19.1.
Overview
The Reset Controller (RSTC) manages the reset of the microcontroller. It issues a microcontroller reset,
sets the device to its initial state and allows the reset source to be identified by software.
19.2.
Features
•
•
•
19.3.
Reset the microcontroller and set it to an initial state according to the reset source
Reset cause register for reading the reset source from the application code
Multiple reset sources
– Power supply reset sources: POR, BODCORE, BODVDD
– User reset sources: External reset (RESET), Watchdog reset, and System Reset Request
Block Diagram
Figure 19-1. Reset System
RESET SOURCES
RESET CONTROLLER
BODCORE
BODVDD
RTC
32kHz clock sources
WDT with ALWAYSON
GCLK with WRTLOCK
POR
Debug Logic
RESET
WDT
Other Modules
CPU
RCAUSE
19.4.
Signal Description
Signal Name
Type
Description
RESET
Digital input
External reset
One signal can be mapped on several pins.
Related Links
I/O Multiplexing and Considerations on page 28
19.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
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19.5.1.
I/O Lines
Not applicable.
19.5.2.
Power Management
The Reset Controller module is always on.
19.5.3.
Clocks
The RSTC bus clock (CLK_RSTC_APB) can be enabled and disabled in the Main Clock Controller.
Related Links
MCLK – Main Clock on page 149
Peripheral Clock Masking on page 152
19.5.4.
DMA
Not applicable.
19.5.5.
Interrupts
Not applicable.
19.5.6.
Events
Not applicable.
19.5.7.
Debug Operation
When the CPU is halted in debug mode, the RSTC continues normal operation.
19.5.8.
Register Access Protection
All registers with write-access can be optionally write-protected by the Peripheral Access Controller
(PAC).
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection
does not apply for accesses through an external debugger.
19.5.9.
Analog Connections
Not applicable.
19.6.
Functional Description
19.6.1.
Principle of Operation
The Reset Controller collects the various Reset sources and generates Reset for the device.
19.6.2.
Basic Operation
19.6.2.1. Initialization
After a power-on Reset, the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the
POR source.
19.6.2.2. Enabling, Disabling, and Resetting
The RSTC module is always enabled.
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19.6.2.3. Reset Causes and Effects
The latest Reset cause is available in RCAUSE register, and can be read during the application boot
sequence in order to determine proper action.
These are the groups of Reset sources:
•
•
Power supply Reset: Resets caused by an electrical issue. It covers POR and BODs Resets
User Reset: Resets caused by the application. It covers external Resets, system Reset requests
and watchdog Resets
The following table lists the parts of the device that are reset, depending on the Reset type.
The external Reset is generated when pulling the RESET pin low.
The POR, BODCORE, and BODVDD Reset sources are generated by their corresponding module in the
Supply Controller Interface (SUPC).
The WDT Reset is generated by the Watchdog Timer.
The System Reset Request is a Reset generated by the CPU when asserting the SYSRESETREQ bit
®
™
located in the Reset Control register of the CPU (for details refer to the ARM Cortex Technical
Reference Manual on http://www.arm.com).
Related Links
SUPC – Supply Controller on page 251
19.6.3.
Additional Features
Not applicable.
19.6.4.
DMA Operation
Not applicable.
19.6.5.
Interrupts
Not applicable.
19.6.6.
Events
Not applicable.
19.6.7.
Sleep Mode Operation
The RSTC module is active in all sleep modes.
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19.7.
Register Summary
Offset
Name
Bit Pos.
0x00
RCAUSE
7:0
0x01
Reserved
0x02
BKUPEXIT
19.8.
7:0
SYST
WDT
EXT
BODVDD
BODCORE
BBPS
RTC
POR
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
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19.8.1.
Reset Cause
When a Reset occurs, the bit corresponding to the Reset source is set to '1' and all other bits are written
to '0'.
Name: RCAUSE
Offset: 0x00
Reset: Latest Reset Source
Property: –
Bit
7
6
5
4
3
2
1
0
SYST
WDT
EXT
BODVDD
BODCORE
POR
Access
R
R
R
R
R
R
Reset
x
x
x
x
x
x
Bit 6 – SYST: System Reset Request
This bit is set if a System Reset Request has occurred. Refer to the Cortex processor documentation for
more details.
Bit 5 – WDT: Watchdog Reset
This bit is set if a Watchdog Timer Reset has occurred.
Bit 4 – EXT: External Reset
This bit is set if an external Reset has occurred.
Bit 2 – BODVDD: Brown Out VDD Detector Reset
This bit is set if a BODVDD Reset has occurred.
Bit 1 – BODCORE: Brown Out CORE Detector Reset
This bit is set if a BODCORE Reset has occurred.
Bit 0 – POR: Power On Reset
This bit is set if a POR has occurred.
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20.
PM – Power Manager
20.1.
Overview
The Power Manager (PM) controls the sleep modes of the device.
Various sleep modes are provided in order to fit power consumption requirements. This enables the PM
to stop unused modules in order to save power. In active mode, the CPU is executing application code.
When the device enters a sleep mode, program execution is stopped and some modules and clock
domains are automatically switched off by the PM according to the sleep mode. The application code
decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset
sources can restore the device from a sleep mode to active mode.
20.2.
Features
•
20.3.
Power management control
– Sleep modes: Idle, Standby
Block Diagram
Figure 20-1. PM Block Diagram
POWER MANAGER
MAIN CLOCK
CONTROLLER
SLEEP MODE
CONTROLLER
SUPPLY
CONTROLLER
SLEEPCFG
POWER DOMAIN
CONTROLLER
STDBYCFG
20.4.
Signal Description
Not applicable.
20.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
20.5.1.
I/O Lines
Not applicable.
20.5.2.
Clocks
The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Main Clock module. If this clock is
disabled, it can only be re-enabled by a system reset.
20.5.3.
DMA
Not applicable.
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20.5.4.
Interrupts
The interrupt request line is connected to the interrupt controller. Using the PM interrupt requires the
interrupt controller to be configured first.
20.5.5.
Events
Not applicable.
20.5.6.
Debug Operation
When the CPU is halted in debug mode, the PM continues normal operation. If standby sleep mode is
requested by the system while in debug mode, the power domains are not turned off. As a consequence,
power measurements while in debug mode are not relevant.
Hot plugging in standby mode is supported.
20.5.7.
Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual
register description.
Write-protection does not apply to accesses through an external debugger.
20.5.8.
Analog Connections
Not applicable.
20.6.
Functional Description
20.6.1.
Terminology
The following is a list of terms used to describe the Power Managemement features of this
microcontroller.
20.6.1.1. Sleep Modes
The device can be set in a sleep mode. In sleep mode, the CPU is stopped and the peripherals are either
active or idle, according to the sleep mode depth:
•
•
20.6.2.
Idle sleep mode: The CPU is stopped. Synchronous clocks are stopped except when requested.
The logic is retained.
Standby sleep mode: The CPU is stopped as well as the peripherals.
Principle of Operation
In active mode, all clock domains and power domains are active, allowing software execution and
peripheral operation. The PM Sleep Mode Controller allows to save power by choosing between different
sleep modes depending on application requirements, see Sleep Mode Controller.
The PM Power Domain Controller allows to reduce the power consumption in standby mode even further.
20.6.3.
Basic Operation
20.6.3.1. Initialization
After a power-on reset, the PM is enabled, the device is in ACTIVE mode.
20.6.3.2. Enabling, Disabling and Resetting
The PM is always enabled and can not be reset.
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20.6.3.3. Sleep Mode Controller
A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the
Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the sleep mode.
Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG
register due to bridges. Software must ensure that the SLEEPCFG register reads the desired value
before issuing a WFI instruction.
Table 20-1. Sleep Mode Entry and Exit Table
Mode
Mode Entry
Wake-Up Sources
IDLE
SLEEPCFG.SLEEPMODE = IDLE
Synchronous (2) (APB, AHB),
asynchronous (1)
STANDBY
SLEEPCFG.SLEEPMODE = STANDBY
Synchronous(3), Asynchronous
Note: 1. Asynchronous: interrupt generated on generic clock, external clock, or external event.
2. Synchronous: interrupt generated on the APB clock.
3. Synchronous interrupt only for peripherals configured to run in standby.
Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt
section.
The sleep modes (idle, standby) and their effect on the clocks activity, the regulator and the NVM state
are described in the table and the sections below.
Table 20-2. Sleep Mode Overview
CPU
clock
AHB
clock
APB clock
Stop
Stop(2)
STANDBY Stop
Stop(2)
Mode
IDLE
Main
clock
GCLK
clocks
Stop(2)
Run
Stop(2)
Stop
Oscillators
ONDEMAND = 0
ONDEMAND =
1
Run(1)
Run
Run if
requested
Stop(2)
Run if requested Run if
or RUNSTDBY=1 requested
Regulator
RAM
Main
Normal
LPVREG(3)
Low power(4)
Note: 1. Running if requested by peripheral.
2. Running during SleepWalking.
3. Regulator state is programmable by using STDBYCFG.VREGSMOD bits.
4. RAM state is programmable by using STDBYCFG.BBIASHS bit.
IDLE Mode
The IDLE mode allows power optimization with the fastest wake-up time.
The CPU is stopped. To further reduce power consumption, the user can disable the clocking of modules
and clock sources by configuring the SLEEPCFG bit group to IDLE. The peripheral will be halted
regardless of the bit settings of the mask registers in the MCLK (MCLK.AHBMASK, MCLK.APBxMASK).
•
Entering IDLE mode: The IDLE mode is entered by executing the WFI instruction. Additionally, if the
SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is set, the IDLE mode will
also be entered when the CPU exits the lowest priority ISR. This mechanism can be useful for
applications that only require the processor to run when an interrupt occurs. Before entering the
IDLE mode, the user must configure the Sleep Configuration register.
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•
Exiting IDLE mode: The processor wakes the system up when it detects any non-masked interrupt
with sufficient priority to cause exception entry. The system goes back to the ACTIVE mode. The
CPU and affected modules are restarted.
Regulator operates in normal mode.
STANDBY Mode
The STANDBY mode is the lowest power configuration while keeping the state of the logic and the
content of the RAM.
In this mode, all clocks are stopped except those which are kept running if requested by a running
peripheral or have the ONDEMAND bit written to "0". For example, the RTC can operate in STANDBY
mode. In this case, its GCLK clock source will also be enabled.
All features that don’t require CPU intervention are supported in STANDBY mode. Here are examples:
•
•
•
•
•
•
Autonomous peripherals features.
Features relying on Event System allowing autonomous communication between peripherals.
Features relying on on-demand clock.
DMA transfers.
Entering STANDBY mode: This mode is entered by executing the WFI instruction with the
SLEEPCFG register written to STANDBY. The SLEEPONEXIT feature is also available as in IDLE
mode.
Exiting STANDBY mode: Any peripheral able to generate an asynchronous interrupt can wake up
the system. For example, a peripheral running on a GCLK clock can trigger an interrupt. When the
enabled asynchronous wake-up event occurs and the system is woken up, the device will either
execute the interrupt service routine or continue the normal program execution according to the
Priority Mask Register (PRIMASK) configuration of the CPU.
Depending on the configuration of these modules, the current consumption of the device in STANDBY
mode can be slightly different.
The regulator operates in low-power mode (LP VREG) by default and can switch automatically to the
main regulator if a task required by a peripheral requires more power. It returns automatically in the low
power mode as soon as the task is completed.
20.6.4.
Advanced Features
20.6.4.1. RAM Automatic Low Power Mode
The RAM is by default put in low power mode (back-biased) if the device is in standby sleep mode.
This behavior can be changed by configuring the Back Bias bit in the Standby Configuration register
(STDBYCFG.BBIASHS), refer to the table below for details.
Note: In standby sleep mode, the RAM is put in low-power mode by default. This means that the RAM is
back-biased, and the DMAC cannot access it. The DMAC can only access the RAM when it is not back
biased (PM.STDBYCFG.BBIASxx=0x0).
Table 20-3. RAM Back-Biasing Mode
STBYCDFG.BBIASHS
RAM
0x0 No Back Biasing
RAM is not back-biased if the device is in standby sleep mode.
0x1 Standby Back Biasing mode
RAM is back-biased if the device is in standby sleep mode.
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20.6.4.2. Regulator Automatic Low Power Mode
In standby mode, the PM selects either the main or the low power voltage regulator to supply the
VDDCORE. By default the low power voltage regulator is used.
If a sleepwalking task is working on either asynchronous clocks (generic clocks) or synchronous clock
(APB/AHB clocks), the main voltage regulator is used. This behavior can be changed by writing the
Voltage Regulator Standby Mode bits in the Standby Configuration register (STDBYCFG.VREGSMOD).
Refer to the following table for details.
Table 20-4. Regulator State in Sleep Mode
Sleep
Mode
STDBYCFG.
VREGSMOD
SleepWalking
Regulator state for VDDCORE
Active
-
-
main voltage regulator
Idle
-
-
main voltage regulator
Standby
0x0: AUTO
NO
low power regulator
YES
main voltage regulator
0x1: PERFORMANCE
-
main voltage regulator
0x2: LP
-
low power regulator
20.6.5.
DMA Operation
Not applicable.
20.6.6.
Interrupts
Not applicable.
20.6.7.
Events
Not applicable.
20.6.8.
Sleep Mode Operation
The Power Manager is always active.
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20.7.
Register Summary
Offset
Name
Bit Pos.
0x01
SLEEPCFG
7:0
SLEEPMODE[2:0]
0x02
...
Reserved
0x07
0x08
0x09
20.8.
STDBYCFG
7:0
VREGSMOD[1:0]
15:8
BBIASHS
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
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20.8.1.
Sleep Configuration
Name: SLEEPCFG
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
SLEEPMODE[2:0]
Access
Reset
R/W
R/W
R/W
0
0
0
Bits 2:0 – SLEEPMODE[2:0]: Sleep Mode
Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG
register due to bridges. Software has to make sure the SLEEPCFG register reads the wanted value
before issuing Wait For Interrupt (WFI) instruction.
Value
Name
Definition
0x0
Reserved
Reserved
0x1
Reserved
Reserved
0x2
IDLE
CPU, AHBx and APBx clocks are OFF
0x3
Reserved
Reserved
0x4
STANDBY
ALL clocks are OFF, unless requested by sleepwalking peripheral
0x5 - 0x7
Reserved
Reserved
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20.8.2.
Standby Configuration
Name: STDBYCFG
Offset: 0x08
Reset: 0x0400
Property: PAC Write-Protection
Bit
15
14
13
12
11
10
9
8
1
0
BBIASHS
Access
R/W
Reset
1
Bit
7
6
5
4
3
2
VREGSMOD[1:0]
Access
Reset
R/W
R/W
0
0
Bit 10 – BBIASHS: Back Bias for HMCRAMCHS
Refer to RAM Automatic Low Power Mode for details.
Value
Description
0
No Back Biasing Mode
1
Standby Back Biasing Mode
Bits 7:6 – VREGSMOD[1:0]: VREG Switching Mode
Refer to for Regulator Automatic Low Power Mode details.
Value
Name
Description
0x0
AUTO
Automatic Mode
0x1
PERFORMANCE
Performance oriented
0x2
LP
Low Power consumption oriented
0x9
Reserved
Reserved
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21.
OSCCTRL – Oscillators Controller
21.1.
Overview
The Oscillators Controller (OSCCTRL) provides a user interface to the XOSC, OSC48M, and FDPLL96M.
Through the interface registers, it is possible to enable, disable, calibrate, and monitor the OSCCTRL
sub-peripherals.
All sub-peripheral statuses are collected in the Status register (STATUS). They can additionally trigger
interrupts upon status changes via the INTENSET, INTENCLR, and INTFLAG registers.
Related Links
INTENCLR on page 198
INTENSET on page 201
INTFLAG on page 204
STATUS on page 206
21.2.
Features
•
•
•
0.4-32MHz Crystal Oscillator (XOSC)
– Tunable gain control
– Programmable start-up time
– Crystal or external input clock on XIN I/O
– Clock failure detection with safe clock switch
– Clock failure event output
48MHz Internal Oscillator (OSC48M)
– Fast start-up
– Programmable start-up time
– 4-bit linear divider available
Fractional Digital Phase Locked Loop (FDPLL96M)
– 48MHz to 96MHz output frequency
– 32kHz to 2MHz reference clock
– A selection of sources for the reference clock
– Adjustable proportional integral controller
– Fractional part used to achieve 1/16th of reference clock step
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21.3.
Block Diagram
Figure 21-1. OSCCTRL Block Diagram
XOUT
XIN
OSCCTRL
CFD
XOSC
OSCILLATORS
CONTROL
CFD Event
CLK_XOSC
OSC48M
CLK_OSC48M
DPLL96M
CLK_DPLL
STATUS
register
INTERRUPTS
GENERATOR
21.4.
Interrupts
Signal Description
Signal
Description
Type
XIN
Multipurpose Crystal Oscillator or external clock generator input
Analog input
XOUT
Multipurpose Crystal Oscillator output
Analog output
The I/O lines are automatically selected when XOSC is enabled.
21.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
21.5.1.
I/O Lines
I/O lines are configured by OSCCTRL when XOSC is enabled, and need no user configuration.
21.5.2.
Power Management
The OSCCTRL can continue to operate in any sleep mode where the selected source clock is running.
The OSCCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger
other operations in the system without exiting sleep modes.
Related Links
PM – Power Manager on page 177
21.5.3.
Clocks
The OSCCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock
Controller (GCLK). The available clock sources are: XOSC, OSC48M, and FDPLL96M.
The OSCCTRL bus clock (CLK_OSCCTRL_APB) can be enabled and disabled in the Main Clock module
(MCLK).
The OSC48M control logic uses the oscillator output, which is also asynchronous to the user interface
clock (CLK_OSCCTRL_APB). Due to this asynchronicity, writes to certain registers will require
synchronization between the clock domains. Refer to Synchronization for further details.
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Related Links
MCLK – Main Clock on page 149
Peripheral Clock Masking on page 152
21.5.4.
DMA
Not applicable.
21.5.5.
Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the OSCCTRL interrupts requires
the interrupt controller to be configured first.
Related Links
Nested Vector Interrupt Controller on page 43
INTFLAG on page 204
Sleep Mode Controller on page 179
21.5.6.
Events
The events of this peripheral are connected to the Event System.
Related Links
EVSYS – Event System on page 487
21.5.7.
Debug Operation
When the CPU is halted in debug mode the OSCCTRL continues normal operation. If the OSCCTRL is
configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar,
improper operation or data loss may result during debugging.
21.5.8.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except the following registers:
•
Interrupt Flag Status and Clear register (INTFLAG)
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection
does not apply for accesses through an external debugger.
21.5.9.
Analog Connections
The 0.4-32MHz crystal must be connected between the XIN and XOUT pins, along with any required load
capacitors.
21.6.
Functional Description
21.6.1.
Principle of Operation
XOSC, OSC48M, and FDPLL96M are configured via OSCCTRL control registers. Through this interface,
the sub-peripherals are enabled, disabled, or have their calibration values updated.
The Status register gathers different status signals coming from the sub-peripherals controlled by the
OSCCTRL. The status signals can be used to generate system interrupts, and in some cases wake up
the system from standby mode, provided the corresponding interrupt is enabled.
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21.6.2.
External Multipurpose Crystal Oscillator (XOSC) Operation
The XOSC can operate in two different modes:
•
•
External clock, with an external clock signal connected to the XIN pin
Crystal oscillator, with an external 0.4-32MHz crystal
The XOSC can be used as a clock source for generic clock generators. This is configured by the Generic
Clock Controller.
At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins
or by other peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO
usage. When in crystal oscillator mode, the XIN and XOUT pins are controlled by the OSCCTRL, and
GPIO functions are overridden on both pins. When in external clock mode, only the XIN pin will be
overridden and controlled by the OSCCTRL, while the XOUT pin can still be used as a GPIO pin.
The XOSC is enabled by writing a '1' to the Enable bit in the External Multipurpose Crystal Oscillator
Control register (XOSCCTRL.ENABLE).
To enable XOSC as an external crystal oscillator, the XTAL Enable bit (XOSCCTRL.XTALEN) must
written to '1'. If XOSCCTRL.XTALEN is zero, the external clock input on XIN will be enabled.
When in crystal oscillator mode (XOSCCTRL.XTALEN=1), the External Multipurpose Crystal Oscillator
Gain (XOSCCTRL.GAIN) must be set to match the external crystal oscillator frequency. If the External
Multipurpose Crystal Oscillator Automatic Amplitude Gain Control (XOSCCTRL.AMPGC) is '1', the
oscillator amplitude will be automatically adjusted, and in most cases result in a lower power
consumption.
The XOSC will behave differently in different sleep modes, based on the settings of
XOSCCTRL.RUNSTDBY, XOSCCTRL.ONDEMAND, and XOSCCTRL.ENABLE. If
XOSCCTRL.ENABLE=0, the XOSC will be always stopped. For XOSCCTRL.ENABLE=1, this table is
valid:
Table 21-1. XOSC Sleep Behavior
CPU Mode
XOSCCTRL.RUNST
DBY
XOSCCTRL.ONDEM Sleep Behavior
AND
Active or Idle
-
0
Always run
Active or Idle
-
1
Run if requested by peripheral
Standby
1
0
Always run
Standby
1
1
Run if requested by peripheral
Standby
0
-
Run if requested by peripheral
After a hard reset, or when waking up from a sleep mode where the XOSC was disabled, the XOSC will
need a certain amount of time to stabilize on the correct frequency. This start-up time can be configured
by changing the Oscillator Start-Up Time bit group (XOSCCTRL.STARTUP) in the External Multipurpose
Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that
no unstable clock propagates to the digital logic.
The External Multipurpose Crystal Oscillator Ready bit in the Status register (STATUS.XOSCRDY) is set
once the external clock or crystal oscillator is stable and ready to be used as a clock source. An interrupt
is generated on a zero-to-one transition on STATUS.XOSCRDY if the External Multipurpose Crystal
Oscillator Ready bit in the Interrupt Enable Set register (INTENSET.XOSCRDY) is set.
Related Links
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GCLK - Generic Clock Controller on page 127
21.6.3.
Clock Failure Detection Operation
The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator signal
provided by the external oscillator (XOSC). The CFD detects failing operation of the XOSC clock with
reduced latency, and allows to switch to a safe clock source in case of clock failure. The user can also
switch from the safe clock back to XOSC in case of recovery. The safe clock is derived from the OSC48M
oscillator with a configurable prescaler. This allows to configure the safe clock in order to fulfill the
operative conditions of the microcontroller.
In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to
run by a peripheral. See the Sleep Behavior table above when this is the case.
The user interface registers allow to enable, disable, and configure the CFD. The Status register provides
status flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event
when a failure is detected.
Clock Failure Detection
The CFD is reset only at power-on (POR). The CFD does not monitor the XOSC clock when the oscillator
is disabled (XOSCCTRL.ENABLE=0).
Before starting CFD operation, the user must start and enable the safe clock source (OSC48M oscillator).
CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register
(XOCCTRL.CFDEN). After starting or restarting the XOSC, the CFD does not detect failure until the startup time has elapsed. The start-up time is configured by the Oscillator Start-Up Time in the External
Multipurpose Crystal Oscillator Control register (XOSCCTRL.STARTUP). Once the XOSC Start-Up Time
is elapsed, the XOSC clock is constantly monitored.
During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the XOSC.
There must be at least one rising and one falling XOSC clock edge during 4 safe clock periods to meet
non-failure conditions. If no or insufficient activity is detected, the failure status is asserted: The Clock
Failure Detector status bit in the Status register (STATUS.CLKFAIL) and the Clock Failure Detector
interrupt flag bit in the Interrupt Flag register (INTFLAG.CLKFAIL) are set. If the CLKFAIL bit in the
Interrupt Enable Set register (INTENSET.CLKFAIL) is set, an interrupt is generated as well. If the Event
Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an output event is generated,
too.
After a clock failure was issued the monitoring of the XOSC clock is continued, and the Clock Failure
Detector status bit in the Status register (STATUS.CLKFAIL) reflects the current XOSC activity.
Clock Switch
When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an
active clock during the XOSC clock failure. The safe clock source is the OSC48M oscillator clock. The
safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock frequency
does not exceed the operating conditions selected by the application. When the XOSC clock is switched
to the safe clock, the Clock Switch bit in the Status register (STATUS.CLKSW) is set.
When the CFD has switched to the safe clock, the XOSC is not disabled. If desired, the application must
take the necessary actions to disable the oscillator. The application must also take the necessary actions
to configure the system clocks to continue normal operations.
In the case the application can recover the XOSC, the application can switch back to the XOSC clock by
writing a '1' to Switch Back Enable bit in the Clock Failure Control register (XOSCCTRL.SWBACK). Once
the XOSC clock is switched back, the Switch Back bit (XOSCCTRL.SWBACK) is cleared by hardware.
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Prescaler
The CFD has an internal configurable prescaler to generate the safe clock from the OSC48M oscillator.
The prescaler size allows to scale down the OSC48M oscillator so the safe clock frequency is not higher
than the XOSC clock frequency monitored by the CFD. The division factor is 2^P, with P being the value
of the CFD Prescaler bits in the CFD Prescaler Register (CFDPRESC.CFDPRESC).
Example
For an external crystal oscillator at 0.4MHz and the OSC48M frequency at 16MHz, the
CFDPRESC.CFDPRESC value should be set scale down by more than factor 16/0.4=80,
e.g. to 128, for a safe clock of adequate frequency.
Event
If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock
failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock
failure will not be output on the Event Output.
Sleep Mode
The CFD is halted depending on configuration of the XOSC and the peripheral clock request. For further
details, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device
from sleep modes.
21.6.4.
48MHz Internal Oscillator (OSC48M) Operation
The OSC48M is an internal oscillator operating in open-loop mode and generating 48MHz frequency. The
OSC48M frequency is selected by writing to the Division Factor field in the OSC48MDIV register
(OSC48MDIV.DIV). OSC48M is enabled by writing '1' to the Oscillator Enable bit in the OSC48M Control
register (OSC48MCTRL.ENABLE), and disabled by writing a '0' to this bit. Frequency selection must be
done when OSC48M is disabled.
After enabling OSC48M, the OSC48M clock is output as soon as the oscillator is ready
(STATUS.OSC48MRDY=1). User must ensure that the OSC48M is fully disabled before enabling it by
reading STATUS.OSC48MRDY=0.
After reset, OSC48M is enabled and serves as the default clock source at 4MHz.
OSC48M will behave differently in different sleep modes based on the settings of
OSC48MCTRL.RUNSTDBY, OSC48MCTRL.ONDEMAND, and OSC48MCTRL.ENABLE. If
OSC48MCTRL.ENABLE=0, the OSC48M will be always stopped. For OSC48MCTRL.ENABLE=1, this
table is valid:
Table 21-2. OSC48M Sleep Behavior
CPU Mode
OSC48MCTRL.RUN
STDBY
OSC48MCTRL.OND Sleep Behavior
EMAND
Active or Idle
-
0
Always run
Active or Idle
-
1
Run if requested by peripheral
Standby
1
0
Always run
Standby
1
1
Run if requested by peripheral
Standby
0
-
Run if requested by peripheral
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After a hard reset, or when waking up from a sleep mode where the OSC48M was disabled, the OSC48M
will need a certain amount of time to stabilize on the correct frequency. This start-up time can be
configured by changing the Oscillator Start-Up Delay bit group (OSC48MSTUP.STARTUP) in the
OSC48M Startup register. During the start-up time, the oscillator output is masked to ensure that no
unstable clock propagates to the digital logic. The OSC48M Ready bit in the Status register
(STATUS.OSC48MRDY) is set when the oscillator is stable and ready to be used as a clock source. An
interrupt is generated on a zero-to-one transition on STATUS.OSC48MRDY if the OSC48M Ready bit in
the Interrupt Enable Set register (INTENSET.OSC48MRDY) is set.
Faster start-up times are achievable by selecting shorter delays. However, the oscillator frequency may
not stabilize within tolerances when short delays are used. If a fast start-up time is desired at the expense
of initial accuracy, the division factor should be set to two or higher (OSC48MDIV.DIV > 0).
The OSC48M is used as a clock source for the generic clock generators.
Related Links
GCLK - Generic Clock Controller on page 127
21.6.5.
Digital Phase Locked Loop (DPLL) Operation
The task of the DPLL is to maintain coherence between the input (reference) signal and the respective
output frequency, CLK_DPLL, via phase comparison. The DPLL controller supports three independent
sources of reference clocks:
•
•
•
XOSC32K: this clock is provided by the 32K External Crystal Oscillator (XOSC32K).
XOSC: this clock is provided by the External Multipurpose Crystal Oscillator (XOSC).
GCLK: this clock is provided by the Generic Clock Controller.
When the controller is enabled, the relationship between the reference clock frequency and the output
clock frequency is:
�CK = �CKR × LDR + 1 +
LDRFRAC
1
× PRESC
16
2
Where fCK is the frequency of the DPLL output clock, LDR is the loop divider ratio integer part, LDRFRAC
is the loop divider ratio fractional part, fCKR is the frequency of the selected reference clock, and PRESC
is the output prescaler value.
Figure 21-2. DPLL Block Diagram
XIN32
XOUT32
XOSC32K
XIN
XOUT
XOSC
DIVIDER
DPLLPRESC
DPLLCTRLB.FILTER
DPLLCTRLB.DIV
CKR
GCLK
TDC
DIGITAL FILTER
RATIO
DPLLCTRLB.REFCLK
DCO
CKDIV4
CKDIV2
CKDIV1
CG
CLK_DPLL
CK
DPLLRATIO
When the controller is disabled, the output clock is low. If the Loop Divider Ratio Fractional part bit field in
the DPLL Ratio register (DPLLRATIO.LDRFRAC) is zero, the DPLL works in integer mode. Otherwise,
the fractional mode is activated. Note that the fractional part has a negative impact on the jitter of the
DPLL.
Example (integer mode only): assuming FCKR = 32kHz and FCK = 48MHz, the
multiplication ratio is 1500. It means that LDR shall be set to 1499.
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Example (fractional mode): assuming FCKR = 32kHz and FCK = 48.006MHz, the
multiplication ratio is 1500.1875 (1500 + 3/16). Thus LDR is set to 1499 and LDRFRAC
to 3.
Related Links
GCLK - Generic Clock Controller on page 127
OSC32KCTRL – 32KHz Oscillators Controller on page 225
21.6.5.1. Basic Operation
Initialization, Enabling, Disabling, and Resetting
The DPLLC is enabled by writing a '1' to the Enable bit in the DPLL Control A register
(DPLLCTRLA.ENABLE). The DPLLC is disabled by writing a zero to this bit.
The DPLLSYNCBUSY.ENABLE is set when the DPLLCTRLA.ENABLE bit is modified. It is cleared when
the DPLL output clock CK has sampled the bit at the high level after enabling the DPLL. When disabling
the DPLL, DPLLSYNCBUSY.ENABLE is cleared when the output clock is no longer running.
Figure 21-3. Enable Synchronization Busy Operation
CLK_APB_OSCCTRL
ENABLE
CK
SYNCBUSY.ENABLE
The frequency of the DPLL output clock CK is stable when the module is enabled and when the Lock bit
in the DPLL Status register is set (DPLLSTATUS.LOCK).
When the Lock Time bit field in the DPLL Control B register (DPLLCTRLB.LTIME) is non-zero, a user
defined lock time is used to validate the lock operation. In this case the lock time is constant. If
DPLLCTRLB.LTIME=0, the lock signal is linked with the status bit of the DPLL, and the lock time varies
depending on the filter selection and the final target frequency.
When the Wake Up Fast bit (DPLLCTRLB.WUF) is set, the wake up fast mode is activated. In this mode
the clock gating cell is enabled at the end of the startup time. At this time the final frequency is not stable,
as it is still during the acquisition period, but it allows to save several milliseconds. After first acquisition,
the Lock Bypass bit (DPLLCTRLB.LBYPASS) indicates if the lock signal is discarded from the control of
the clock gater (CG) generating the output clock CLK_DPLL.
Table 21-3. CLK_DPLL Behavior from Startup to First Edge Detection
WUF
LTIME
0
0
0
CLK_DPLL Behavior
Normal Mode: First Edge when lock is asserted
Not Equal To Zero Lock Timer Timeout mode: First Edge when the timer down-counts to 0.
1
X
Wake Up Fast Mode: First Edge when CK is active (startup time)
Table 21-4. CLK_DPLL Behavior after First Edge Detection
LBYPASS
CLK_DPLL Behavior
0
Normal Mode: the CLK_DPLL is turned off when lock signal is low.
1
Lock Bypass Mode: the CLK_DPLL is always running, lock is irrelevant.
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Figure 21-4. CK and CLK_DPLL Output from DPLL Off Mode to Running Mode
CKR
ENABLE
CK
CLK_DPLL
LOCK
t startup_time
t lock_time
CK STABLE
Reference Clock Switching
When a software operation requires reference clock switching, the recommended procedure is to turn the
DPLL into the standby mode, modify the DPLLCTRLB.REFCLK to select the desired reference source,
and activate the DPLL again.
Output Clock Prescaler
The DPLL controller includes an output prescaler. This prescaler provides three selectable output clocks
CK, CKDIV2 and CKDIV4. The Prescaler bit field in the DPLL Prescaler register (DPLLPRESC.PRESC)
is used to select a new output clock prescaler. When the prescaler field is modified, the
DPLLSYNCBUSY.DPLLPRESC bit is set. It will be cleared by hardware when the synchronization is over.
Figure 21-5. Output Clock Switching Operation
CKR
PRESC
0
1
CK
CKDIV2
CLK_DPLL
SYNCBUSY.PRESC
DPLL_LOCK
CK STABLE
CK SWITCHING
CK STABLE
Loop Divider Ratio Updates
The DPLL Controller supports on-the-fly update of the DPLL Ratio Control (DPLLRATIO) register,
allowing to modify the loop divider ratio and the loop divider ratio fractional part when the DPLL is
enabled.
STATUS.DPLLLDRTO is set when the DPLLRATIO register has been modified and the DPLL analog cell
has successfully sampled the updated value. At that time the DPLLSTATUS.LOCK bit is cleared and set
again by hardware when the output frequency reached a stable state.
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Figure 21-6. RATIOCTRL register update operation
CKR
LDR
LDRFRAC
mult0
mult1
CK
CLK_DPLL
LOCK
LOCKL
Digital Filter Selection
The PLL digital filter (PI controller) is automatically adjusted in order to provide a good compromise
between stability and jitter. Nevertheless a software operation can override the filter setting using the
Filter bit field in the DPLL Control B register (DPLLCTRLB.FILTER). The Low Power Enable bit
(DPLLCTRLB.LPEN) can be use to bypass the Time to Digital Converter (TDC) module.
21.6.6.
DMA Operation
Not applicable.
21.6.7.
Interrupts
The OSCCTRL has the following interrupt sources:
•
•
•
•
XOSCRDY - Multipurpose Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSCRDY
bit is detected
CLKFAIL - Clock Failure. A 0-to-1 transition on the STATUS.CLKFAIL bit is detected
OSC48MRDY - 48MHz Internal Oscillator Ready: A 0-to-1 transition on the STATUS.OSC48MRDY
bit is detected
DPLL-related:
– DPLLLOCKR - DPLL Lock Rise: A 0-to-1 transition of the STATUS.DPLLLOCKR bit is
detected
– DPLLLOCKF - DPLL Lock Fall: A 0-to-1 transition of the STATUS.DPLLLOCKF bit is detected
– DPLLLTTO - DPLL Lock Timer Time-out: A 0-to-1 transition of the STATUS.DPLLLTTO bit is
detected
– DPLLLDRTO - DPLL Loop Divider Ratio Update Complete. A 0-to-1 transition of the
STATUS.DPLLLDRTO bit is detected
All these interrupts are synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG) is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable
Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable
Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the
OSCCTRL is reset. See the INTFLAG register for details on how to clear interrupt flags.
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The OSCCTRL has one common interrupt request line for all the interrupt sources. The user must read
the INTFLAG register to determine which interrupt condition is present. Refer to the INTFLAG register for
details.
Note: The interrupts must be globally enabled for interrupt requests to be generated.
21.6.8.
Events
The CFD can generate the following output event:
•
Clock Failure (CLKFAIL): Generated when the Clock Failure status bit is set in the Status register
(STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.CLKSW)
in the Status register is set.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD
output event. Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for
details on configuring the event system.
21.6.9.
Synchronization
OSC48M
Due to the multiple clock domains, values in the OSC48M control registers need to be synchronized to
other clock domains.
When executing an operation that requires synchronization, the relevant synchronization bit in the
Synchronization Busy register (OSC48MSYNCBUSY) will be set immediately, and cleared when
synchronization is complete.
The following registers need synchronization when written:
•
OSC48M Divider register (OSC48MDIV)
DPLL96M
Due to the multiple clock domains, some registers in the DPLL96M must be synchronized when
accessed.
When executing an operation that requires synchronization, the relevant synchronization bit in the
Synchronization Busy register (DPLLSYNCBUSY) will be set immediately, and cleared when
synchronization is complete.
The following bits need synchronization when written:
•
Enable bit in control register A (DPLLCTRLA.ENABLE)
•
DPLL Ratio register (DPLLRATIO)
•
DPLL Prescaler register (DPLLPRESC)
Related Links
Register Synchronization on page 123
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21.7.
Offset
Register Summary
Name
0x00
0x01
0x02
Bit Pos.
7:0
INTENCLR
0x03
15:8
7:0
15:8
INTENSET
31:24
0x08
7:0
INTFLAG
0x0B
7:0
STATUS
0x0F
0x11
XOSCRDY
DPLLLTO
DPLLLCKF
DPLLLCKR
CLKFAIL
XOSCRDY
DPLLLCKF
DPLLLCKR
OSC48MRDY
DPLLLDRTO
DPLLLTO
CLKSW
CLKFAIL
XOSCRDY
DPLLLDRTO
DPLLLTO
DPLLLCKF
DPLLLCKR
CFDEN
XTALEN
ENABLE
OSC48MRDY
23:16
31:24
XOSCCTRL
7:0
15:8
CFDPRESC
7:0
0x13
EVCTRL
7:0
0x14
OSC48MCTRL
7:0
0x15
OSC48MDIV
7:0
0x16
OSC48MSTUP
7:0
0x17
Reserved
0x18
ONDEMAND RUNSTDBY
SWBACK
STARTUP[3:0]
AMPGC
0x19
OSC48MSYNCBUS
15:8
Y
23:16
0x1B
GAIN[2:0]
CFDPRESC[2:0]
CFDEO
ONDEMAND RUNSTDBY
ENABLE
DIV[3:0]
STARTUP[2:0]
7:0
0x1A
0x1C
CLKFAIL
DPLLLDRTO
31:24
15:8
0x12
DPLLLCKF
OSC48MRDY
15:8
0x0D
0x10
DPLLLTO
23:16
0x0C
0x0E
DPLLLCKR
DPLLLDRTO
23:16
0x07
0x09
XOSCRDY
31:24
0x05
0x0A
CLKFAIL
23:16
0x04
0x06
OSC48MRDY
OSC48MDIV
31:24
DPLLCTRLA
7:0
ONDEMAND RUNSTDBY
ENABLE
0x1D
...
Reserved
0x1F
0x20
0x21
0x22
7:0
DPLLRATIO
0x23
15:8
LDR[11:8]
23:16
LDRFRAC[3:0]
31:24
0x24
7:0
0x25
15:8
0x26
DPLLCTRLB
0x27
0x28
LDR[7:0]
23:16
31:24
DPLLPRESC
7:0
REFCLK[1:0]
WUF
LBYPASS
LPEN
FILTER[1:0]
LTIME[2:0]
DIV[7:0]
DIV[10:8]
PRESC[1:0]
0x29
...
Reserved
0x2B
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Offset
Name
Bit Pos.
0x2C
DPLLSYNCBUSY
7:0
DPLLPRESC DPLLRATIO
ENABLE
0x2D
...
Reserved
0x2F
0x30
DPLLSTATUS
7:0
CLKRDY
LOCK
0x31
...
Reserved
0x37
0x38
0x39
0x3A
0x3B
21.8.
7:0
CAL48M
FCAL[5:0]
15:8
23:16
FRANGE[1:0]
TCAL[5:0]
31:24
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection
is denoted by the "PAC Write-Protection" property in each individual register description. Refer to the
Register Access Protection section and the PAC - Peripheral Access Controller chapter for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" or "Write.Synchronized" property in each individual register description. Refer to the
Synchronization section for details.
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21.8.1.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
Access
Reset
5
4
11
10
9
8
DPLLLDRTO
DPLLLTO
DPLLLCKF
DPLLLCKR
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
OSC48MRDY
CLKFAIL
XOSCRDY
R/W
R/W
R/W
0
0
0
Bit 11 – DPLLLDRTO: DPLL Loop Divider Ratio Update Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Loop Divider Ratio Update Complete Interrupt Enable bit, which
disables the DPLL Loop Divider Ratio Update Complete interrupt.
Value
Description
0
The DPLL Loop Divider Ratio Update Complete interrupt is disabled.
1
The DPLL Loop Divider Ratio Update Complete interrupt is enabled, and an interrupt request
will be generated when the DPLL Loop Divider Ratio Update Complete Interrupt flag is set.
Bit 10 – DPLLLTO: DPLL Lock Timeout Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock
Timeout interrupt.
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Value
Description
0
The DPLL Lock Timeout interrupt is disabled.
1
The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated
when the DPLL Lock Timeout Interrupt flag is set.
Bit 9 – DPLLLCKF: DPLL Lock Fall Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall
interrupt.
Value
Description
0
The DPLL Lock Fall interrupt is disabled.
1
The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the
DPLL Lock Fall Interrupt flag is set.
Bit 8 – DPLLLCKR: DPLL Lock Rise Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise
interrupt.
Value
Description
0
The DPLL Lock Rise interrupt is disabled.
1
The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when
the DPLL Lock Rise Interrupt flag is set.
Bit 4 – OSC48MRDY: OSC48M Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the OSC48M Ready Interrupt Enable bit, which disables the OSC48M
Ready interrupt.
Value
Description
0
The OSC48M Ready interrupt is disabled.
1
The OSC48M Ready interrupt is enabled, and an interrupt request will be generated when
the OSC48M Ready Interrupt flag is set.
Bit 1 – CLKFAIL: Clock Failure Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the XOSC Clock Failure Interrupt Enable bit, which disables the XOSC
Clock Failure interrupt.
Value
Description
0
The XOSC Clock Failure interrupt is disabled.
1
The XOSC Clock Failure interrupt is enabled, and an interrupt request will be generated
when the XOSC Clock Failure Interrupt flag is set.
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Bit 0 – XOSCRDY: XOSC Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready
interrupt.
Value
Description
0
The XOSC Ready interrupt is disabled.
1
The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the
XOSC Ready Interrupt flag is set.
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21.8.2.
Interrupt Enable Set
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
Access
Reset
5
4
11
10
9
8
DPLLLDRTO
DPLLLTO
DPLLLCKF
DPLLLCKR
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
OSC48MRDY
CLKFAIL
XOSCRDY
R/W
R/W
R/W
0
0
0
Bit 11 – DPLLLDRTO: DPLL Loop Divider Ratio Update Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the DPLL Loop Ratio Update Complete Interrupt Enable bit, which enables
the DPLL Loop Ratio Update Complete interrupt.
Value
Description
0
The DPLL Loop Divider Ratio Update Complete interrupt is disabled.
1
The DPLL Loop Ratio Update Complete interrupt is enabled, and an interrupt request will be
generated when the DPLL Loop Ratio Update Complete Interrupt flag is set.
Bit 10 – DPLLLTO: DPLL Lock Timeout Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock
Timeout interrupt.
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Value
Description
0
The DPLL Lock Timeout interrupt is disabled.
1
The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated
when the DPLL Lock Timeout Interrupt flag is set.
Bit 9 – DPLLLCKF: DPLL Lock Fall Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the DPLL Lock Fall Interrupt Enable bit, which enables the DPLL Lock Fall
interrupt.
Value
Description
0
The DPLL Lock Fall interrupt is disabled.
1
The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the
DPLL Lock Fall Interrupt flag is set.
Bit 8 – DPLLLCKR: DPLL Lock Rise Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise
interrupt.
Value
Description
0
The DPLL Lock Rise interrupt is disabled.
1
The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when
the DPLL Lock Rise Interrupt flag is set.
Bit 4 – OSC48MRDY: OSC48M Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the OSC48M Ready Interrupt Enable bit, which enables the OSC48M Ready
interrupt.
Value
Description
0
The OSC48M Ready interrupt is disabled.
1
The OSC48M Ready interrupt is enabled, and an interrupt request will be generated when
the OSC48M Ready Interrupt flag is set.
Bit 1 – CLKFAIL: XOSC Clock Failure Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the XOSC Clock Failure Interrupt Enable bit, which enables the XOSC Clock
Failure Interrupt.
Value
Description
0
The XOSC Clock Failure Interrupt is disabled.
1
The XOSC Clock Failure Interrupt is enabled, and an interrupt request will be generated
when the XOSC Clock Failure Interrupt flag is set.
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Bit 0 – XOSCRDY: XOSC Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready
interrupt.
Value
Description
0
The XOSC Ready interrupt is disabled.
1
The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the
XOSC Ready Interrupt flag is set.
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21.8.3.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x08
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
DPLLLDRTO
DPLLLTO
DPLLLCKF
DPLLLCKR
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
OSC48MRDY
CLKFAIL
XOSCRDY
R/W
R/W
R/W
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
5
4
Access
Reset
Bit 11 – DPLLLDRTO: DPLL Loop Divider Ratio Update Complete
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DPLL Loop Divider Ratio Update Complete bit in the Status
register (STATUS.DPLLLDRTO) and will generate an interrupt request if INTENSET.DPLLLDRTO is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Loop Divider Ratio Update Complete interrupt flag.
Bit 10 – DPLLLTO: DPLL Lock Timeout
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DPLL Lock Timeout bit in the Status register
(STATUS.DPLLLTO) and will generate an interrupt request if INTENSET.DPLLLTO is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Lock Timeout interrupt flag.
Bit 9 – DPLLLCKF: DPLL Lock Fall
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DPLL Lock Fall bit in the Status register (STATUS.DPLLLCKF)
and will generate an interrupt request if INTENSET.DPLLLCKF is '1'.
Writing '0' to this bit has no effect.
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Writing '1' to this bit clears the DPLL Lock Fall interrupt flag.
Bit 8 – DPLLLCKR: DPLL Lock Rise
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DPLL Lock Rise bit in the Status register (STATUS.DPLLLCKR)
and will generate an interrupt request if INTENSET.DPLLLCKR is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Lock Rise interrupt flag.
Bit 4 – OSC48MRDY: OSC48M Ready
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the OSC48M Ready bit in the Status register
(STATUS.OSC48MRDY) and will generate an interrupt request if INTENSET.OSC48MRDY is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the OSC48M Ready interrupt flag.
Bit 1 – CLKFAIL: XOSC Failure Detection
This flag is cleared by writing '1' to it.
This flag is set on a 0-to-1 transition of the XOSC Clock Failure bit in the Status register
(STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the XOSC Clock Fail interrupt flag.
Bit 0 – XOSCRDY: XOSC Ready
This flag is cleared by writing '1' to it.
This flag is set on a 0-to-1 transition of the XOSC Ready bit in the Status register (STATUS.XOSCRDY)
and will generate an interrupt request if INTENSET.XOSCRDY is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the XOSC Ready interrupt flag.
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21.8.4.
Status
Name: STATUS
Offset: 0x0C
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
Bit
DPLLLDRTO
DPLLLTO
DPLLLCKF
DPLLLCKR
Access
R
R
R
R
Reset
0
0
0
0
3
2
1
0
Bit
7
6
5
4
OSC48MRDY
CLKSW
CLKFAIL
XOSCRDY
Access
R
R
R
R
Reset
0
0
0
0
Bit 11 – DPLLLDRTO: DPLL Loop Divider Ratio Update Complete
Value
Description
0
DPLL Loop Divider Ratio Update Complete not detected.
1
DPLL Loop Divider Ratio Update Complete detected.
Bit 10 – DPLLLTO: DPLL Lock Timeout
Value
Description
0
DPLL Lock time-out not detected.
1
DPLL Lock time-out detected.
Bit 9 – DPLLLCKF: DPLL Lock Fall
Value
Description
0
DPLL Lock fall edge not detected.
1
DPLL Lock fall edge detected.
Bit 8 – DPLLLCKR: DPLL Lock Rise
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Value
Description
0
DPLL Lock rise edge not detected.
1
DPLL Lock fall edge detected.
Bit 4 – OSC48MRDY: OSC48M Ready
Value
Description
0
OSC48M is not ready.
1
OSC48M is stable and ready to be used as a clock source.
Bit 2 – CLKSW: XOSC Clock Switch
Value
Description
0
XOSC is not switched and provides the external clock or crystal oscillator clock.
1
XOSC is switched and provides the safe clock.
Bit 1 – CLKFAIL: XOSC Clock Failure
Value
Description
0
No XOSC failure detected.
1
A XOSC failure was detected.
Bit 0 – XOSCRDY: XOSC Ready
Value
Description
0
XOSC is not ready.
1
XOSC is stable and ready to be used as a clock source.
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21.8.5.
External Multipurpose Crystal Oscillator (XOSC) Control
Name: XOSCCTRL
Offset: 0x10
Reset: 0x0080
Property: PAC Write-Protection
Bit
15
14
13
12
11
STARTUP[3:0]
Access
Reset
Bit
10
9
AMPGC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
5
0
7
6
4
3
2
1
ONDEMAND
RUNSTDBY
SWBACK
CFDEN
XTALEN
ENABLE
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
Access
Reset
8
GAIN[2:0]
Bits 15:12 – STARTUP[3:0]: Start-Up Time
These bits select start-up time for the oscillator.
The OSCULP32K oscillator is used to clock the start-up counter.
Table 21-5. Start-Up Time for External Multipurpose Crystal Oscillator
STARTUP[3:0] Number of OSCULP32K
Clock Cycles
Number of XOSC
Clock Cycles
Approximate Equivalent
Time [µs]
0x0
1
3
31
0x1
2
3
61
0x2
4
3
122
0x3
8
3
244
0x4
16
3
488
0x5
32
3
977
0x6
64
3
1953
0x7
128
3
3906
0x8
256
3
7813
0x9
512
3
15625
0xA
1024
3
31250
0xB
2048
3
62500µs
0xC
4096
3
125000
0xD
8192
3
250000
0xE
16384
3
500000
0xF
32768
3
1000000
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Note: 1. Actual startup time is 1 OSCULP32K cycle + 3 XOSC cycles.
2. The given time neglects the three XOSC cycles before OSCULP32K cycle.
Bit 11 – AMPGC: Automatic Amplitude Gain Control
Note: This bit must be set only after the XOSC has settled, indicated by the XOSC Ready flag in the
Status register (STATUS.XOSCRDY).
Value
Description
0
The automatic amplitude gain control is disabled.
1
The automatic amplitude gain control is enabled. Amplitude gain will be automatically
adjusted during Crystal Oscillator operation.
Bits 10:8 – GAIN[2:0]: Oscillator Gain
These bits select the gain for the oscillator. The listed maximum frequencies are recommendations, and
might vary based on capacitive load and crystal characteristics. Those bits must be properly configured
even when the Automatic Amplitude Gain Control is active.
Value
Recommended Max Frequency [MHz]
0x0
2
0x1
4
0x2
8
0x3
16
0x4
30
0x5-0x7
Reserved
Bit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows the oscillator to be enabled or disabled, depending on peripheral
clock requests.
If the ONDEMAND bit has been previously written to '1', the oscillator will be running only when requested
by a peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a
disabled state.
If On Demand is disabled, the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active.
Value
Description
0
The oscillator is always on, if enabled.
1
The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock
source. The oscillator is disabled if no peripheral is requesting the clock source.
Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the XOSC behaves during standby sleep mode, together with the ONDEMAND bit:
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Value
Description
0
The XOSC is not running in Standby sleep mode if no peripheral requests the clock.
1
The XOSC is running in Standby sleep mode. If ONDEMAND=1, the XOSC will be running
when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be
running in Standby sleep mode.
Bit 4 – SWBACK: Clock Switch Back
This bit controls the XOSC output switch back to the external clock or crystal oscillator in case of clock
recovery:
Value
Description
0
The clock switch back is disabled.
1
The clock switch back is enabled. This bit is reset once the XOSC putput clock is switched
back to the external clock or crystal oscillator.
Bit 3 – CFDEN: Clock Failure Detector Enable
This bit controls the clock failure detector:
Value
Description
0
The Clock Failure Detector is disabled.
1
the Clock Failure Detector is enabled.
Bit 2 – XTALEN: Crystal Oscillator Enable
This bit controls the connections between the I/O pads and the external clock or crystal oscillator:
Value
Description
0
External clock connected on XIN. XOUT can be used as general-purpose I/O.
1
Crystal connected to XIN/XOUT.
Bit 1 – ENABLE: Oscillator Enable
Value
Description
0
The oscillator is disabled.
1
The oscillator is enabled.
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21.8.6.
Clock Failure Detector Prescaler
Name: CFDPRESC
Offset: 0x12
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
CFDPRESC[2:0]
Access
Reset
R/W
R/W
R/W
0
0
0
Bits 2:0 – CFDPRESC[2:0]: Clock Failure Detector Prescaler
These bits select the prescaler for the clock failure detector.
The OSC48M oscillator is used to clock the CFD prescaler. The CFD safe clock frequency is the
OSC48M frequency divided by 2^CFDPRESC.
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21.8.7.
Event Control
Name: EVCTRL
Offset: 0x13
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
CFDEO
Access
R/W
Reset
0
Bit 0 – CFDEO: Clock Failure Detector Event Out
This bit indicates whether the Clock Failure detector event output is enabled or not and an output event
will be generated when the Clock Failure detector detects a clock failure
Value
Description
0
Clock Failure detector event output is disabled and no event will be generated.
1
Clock Failure detector event output is enabled and an event will be generated.
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21.8.8.
48MHz Internal Oscillator (OSC48M) Control
Name: OSC48MCTRL
Offset: 0x14
Reset: 0x82
Property: PAC Write-Protection
Bit
7
6
ONDEMAND
RUNSTDBY
ENABLE
R/W
R/W
R/W
1
0
1
Access
Reset
5
4
3
2
1
0
Bit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows the oscillator to be enabled or disabled depending on peripheral
clock requests.
If the ONDEMAND bit has been previously written to '1', the oscillator will only be running when requested
by a peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a
disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active.
Value
Description
0
The oscillator is always on, if enabled.
1
The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock
source. The oscillator is disabled if no peripheral is requesting the clock source.
Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the OSC48M behaves during standby sleep mode.
Value
Description
0
The OSC48M is disabled in standby sleep mode if no peripheral requests the clock.
1
The OSC48M is not stopped in standby sleep mode. If ONDEMAND=1, the OSC48M will be
running when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will
always be running in standby sleep mode.
Bit 1 – ENABLE: Oscillator Enable
Value
Description
0
The oscillator is disabled.
1
The oscillator is enabled.
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21.8.9.
OSC48M Divider
Name: OSC48MDIV
Offset: 0x15
Reset: 0x0B
Property: Bit
7
6
5
4
3
2
1
0
DIV[3:0]
Access
Reset
R/W
R/W
R/W
R/W
1
0
1
1
Bits 3:0 – DIV[3:0]: Oscillator Divider Selection
These bits control the oscillator frequency range by adjusting the division ratio. The oscillator frequency is
48MHz divided by DIV+1.
Value
Description
0000
48MHz
0001
24MHz
0010
16MHz
0011
12MHz
0100
9.6MHz
0101
8MHz
0110
6.86MHz
0111
6MHz
1000
5.33MHz
1001
4.8MHz
1010
4.36MHz
1011
4MHz
1100
3.69MHz
1101
3.43MHz
1110
3.2MHz
1111
3MHz
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21.8.10. OSC48M Startup
Name: OSC48MSTUP
Offset: 0x16
Reset: 0x07
Property: Bit
7
6
5
4
3
2
1
0
STARTUP[2:0]
Access
Reset
R/W
R/W
R/W
1
1
1
Bits 2:0 – STARTUP[2:0]: Oscillator Startup Delay
These bits select the oscillator start-up delay in oscillator cycles.
Table 21-6. Oscillator Divider Selection
STARTUP[2:0]
Number of OSCM48M Clock
Cycles
Approximate Equivalent Time
0x0
8
166ns
0x1
16
333ns
0x2
32
667ns
0x3
64
1.333μs
0x4
128
2.667μs
0x5
256
5.333μs
0x6
512
10.667μs
0x7
1024
21.333μs
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21.8.11. OSC48M Synchronization Busy
Name: OSC48MSYNCBUSY
Offset: 0x18
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
OSC48MDIV
Access
R/W
Reset
1
Bit 2 – OSC48MDIV: Oscillator Divider Synchronization Status
This bit is set when OSC48MDIV register is written.
This bit is cleared when OSC48MDIV synchronization is completed.
Value
Description
0
No synchronized access.
1
Synchronized access is ongoing.
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21.8.12. DPLL Control A
Name: DPLLCTRLA
Offset: 0x1C
Reset: 0x80
Property: PAC Write-Protection, Write-Synchronized (ENABLE)
Bit
7
6
ONDEMAND
RUNSTDBY
ENABLE
R/W
R/W
R/W
1
0
0
Access
Reset
5
4
3
2
1
0
Bit 7 – ONDEMAND: On Demand Clock Activation
The On Demand operation mode allows the DPLL to be enabled or disabled depending on peripheral
clock requests.
If the ONDEMAND bit has been previously written to '1', the DPLL will only be running when requested by
a peripheral. If there is no peripheral requesting the DPLL’s clock source, the DPLL will be in a disabled
state.
If On Demand is disabled the DPLL will always be running when enabled.
In standby sleep mode, the On Demand operation is still active.
Value
Description
0
The DPLL is always on, if enabled.
1
The DPLL is enabled when a peripheral is requesting the DPLL to be used as a clock
source. The DPLL is disabled if no peripheral is requesting the clock source.
Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the DPLL behaves during standby sleep mode:
Value
Description
0
The DPLL is disabled in standby sleep mode if no peripheral requests the clock.
1
The DPLL is not stopped in standby sleep mode. If ONDEMAND=1, the DPLL will be running
when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be
running in standby sleep mode.
Bit 1 – ENABLE: DPLL Enable
The software operation of enabling or disabling the DPLL takes a few clock cycles, so the
DPLLSYNCBUSY.ENABLE status bit indicates when the DPLL is successfully enabled or disabled.
Value
Description
0
The DPLL is disabled.
1
The DPLL is enabled.
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21.8.13. DPLL Ratio Control
Name: DPLLRATIO
Offset: 0x20
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
Reset
Bit
LDRFRAC[3:0]
Access
Reset
Bit
15
14
13
12
R/W
R/W
R/W
R/W
0
0
0
0
11
10
9
8
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
LDR[11:8]
Access
Reset
Bit
7
6
5
4
LDR[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 19:16 – LDRFRAC[3:0]: Loop Divider Ratio Fractional Part
Writing these bits selects the fractional part of the frequency multiplier. Due to synchronization there is a
delay between writing these bits and the effect on the DPLL output clock. The value written will read back
immediately and the DPLLRATIO bit in the DPLL Synchronization Busy register
(DPLLSYNCBUSY.DPLLRATIO) will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the
operation is completed.
Bits 11:0 – LDR[11:0]: Loop Divider Ratio
Writing these bits selects the integer part of the frequency multiplier. The value written to these bits will
read back immediately, and the DPLLRATIO bit in the DPLL Synchronization busy register
(DPLLSYNCBUSY.DPLLRATIO), will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the
operation is completed.
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21.8.14. DPLL Control B
Name: DPLLCTRLB
Offset: 0x24
Reset: 0x00
Property: Enable-Protected, PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
DIV[10:8]
Access
R/W
R/W
R/W
0
0
0
19
18
17
16
Reset
Bit
23
22
21
20
DIV[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
LBYPASS
Access
R/W
R/W
R/W
0
0
0
0
1
Reset
Bit
7
6
5
4
REFCLK[1:0]
Access
Reset
LTIME[2:0]
R/W
3
2
WUF
LPEN
0
FILTER[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 26:16 – DIV[10:0]: Clock Divider
These bits set the XOSC clock division factor and can be calculated with following formula:
f ��� =
�����
2� ��� + 1
Bit 12 – LBYPASS: Lock Bypass
Value
Description
0
DPLL Lock signal drives the DPLL controller internal logic.
1
DPLL Lock signal is always asserted.
Bits 10:8 – LTIME[2:0]: Lock Time
These bits select the lock time-out value:
Value
Name
Description
0x0
Default
No time-out. Automatic lock.
0x1
Reserved
0x2
Reserved
0x3
Reserved
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Value
Name
Description
0x4
8MS
Time-out if no lock within 8ms
0x5
9MS
Time-out if no lock within 9ms
0x6
10MS
Time-out if no lock within 10ms
0x7
11MS
Time-out if no lock within 11ms
Bits 5:4 – REFCLK[1:0]: Reference Clock Selection
Write these bits to select the DPLL clock reference:
Value
Name
Description
0x0
XOSC32K
XOSC32K clock reference
0x1
XOSC
XOSC clock reference
0x2
GCLK
GCLK clock reference
0x3
Reserved
Bit 3 – WUF: Wake Up Fast
Value
Description
0
DPLL clock is output after startup and lock time.
1
DPLL clock is output after startup time.
Bit 2 – LPEN: Low-Power Enable
Value
Description
0
The low-power mode is disabled. Time to Digital Converter is enabled.
1
The low-power mode is enabled. Time to Digital Converter is disabled. This will improve
power consumption but increase the output jitter.
Bits 1:0 – FILTER[1:0]: Proportional Integral Filter Selection
These bits select the DPLL filter type:
Value
Name
Description
0x0
DEFAULT
Default filter mode
0x1
LBFILT
Low bandwidth filter
0x2
HBFILT
High bandwidth filter
0x3
HDFILT
High damping filter
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21.8.15. DPLL Prescaler
Name: DPLLPRESC
Offset: 0x28
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
PRESC[1:0]
Access
Reset
R/W
R/W
0
0
Bits 1:0 – PRESC[1:0]: Output Clock Prescaler
These bits define the output clock prescaler setting.
Value
Name
Description
0x0
DIV1
DPLL output is divided by 1
0x1
DIV2
DPLL output is divided by 2
0x2
DIV4
DPLL output is divided by 4
0x3
Reserved
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21.8.16. DPLL Synchronization Busy
Name: DPLLSYNCBUSY
Offset: 0x2C
Reset: 0x00
Property: –
Bit
7
6
5
4
3
2
1
DPLLPRESC
DPLLRATIO
ENABLE
Access
R
R
R
Reset
0
0
0
0
Bit 3 – DPLLPRESC: DPLL Prescaler Synchronization Status
Value
Description
0
The DPLLRESC register has been synchronized.
1
The DPLLRESC register value has changed and its synchronization is in progress.
Bit 2 – DPLLRATIO: DPLL Loop Divider Ratio Synchronization Status
Value
Description
0
The DPLLRATIO register has been synchronized.
1
The DPLLRATIO register value has changed and its synchronization is in progress.
Bit 1 – ENABLE: DPLL Enable Synchronization Status
Value
Description
0
The DPLLCTRLA.ENABLE bit has been synchronized.
1
The DPLLCTRLA.ENABLE bit value has changed and its synchronization is in progress.
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21.8.17. DPLL Status
Name: DPLLSTATUS
Offset: 0x30
Reset: 0x00
Property: –
Bit
7
6
5
4
3
2
1
0
CLKRDY
LOCK
Access
R
R
Reset
0
0
Bit 1 – CLKRDY: Output Clock Ready
Value
Description
0
The DPLL output clock is off.
1
The DPLL output clock in on.
Bit 0 – LOCK: DPLL Lock status bit
Value
Description
0
The DPLL Lock signal is cleared, when the DPLL is disabled or when the DPLL is trying to
reach the target frequency.
1
The DPLL Lock signal is asserted when the desired frequency is reached.
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21.8.18. OSC48M Calibration
This register (bits 0 to 21) must be updated with the corresponding data in the NVM Software Calibration
Area: CAL48M 5V or CAL48M 3V3, depending on the VDD range. Refer to NVM Software Calibration
Area Mapping.
Note: This register is only available for Rev D silicon.
Name: CAL48M
Offset: 0x38
Reset: Calibrated value for VDD range 3.6 V to 5.5 V
Property: PAC Write-Protection
Bit
31
30
29
28
27
23
22
21
20
19
26
25
24
18
17
16
Access
Reset
Bit
TCAL[5:0]
Access
Reset
Bit
15
14
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
13
12
11
10
9
8
FRANGE[1:0]
Access
R/W
R/W
x
x
2
1
0
Reset
Bit
7
6
5
4
3
FCAL[5:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
Bits 21:16 – TCAL[5:0]: Temperature Calibration
Bits 9:8 – FRANGE[1:0]: Frequency Range
Bits 5:0 – FCAL[5:0]: Frequency Calibration
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22.
22.1.
OSC32KCTRL – 32KHz Oscillators Controller
Overview
The 32KHz Oscillators Controller (OSC32KCTRL) provides a user interface to the 32.768kHz oscillators:
XOSC32K, OSC32K, and OSCULP32K.
The OSC32KCTRL sub-peripherals can be enabled, disabled, calibrated, and monitored through interface
registers.
All sub-peripheral statuses are collected in the Status register (STATUS). They can additionally trigger
interrupts upon status changes via the INTENSET, INTENCLR, and INTFLAG registers.
22.2.
Features
•
•
•
•
•
32.768kHz Crystal Oscillator (XOSC32K)
– Programmable start-up time
– Crystal or external input clock on XIN32 I/O
– Clock failure detection with safe clock switch
– Clock failure event output
32.768kHz High Accuracy Internal Oscillator (OSC32K)
– Frequency fine tuning
– Programmable start-up time
32.768kHz Ultra Low Power Internal Oscillator (OSCULP32K)
– Ultra low power, always-on oscillator
– Frequency fine tuning
Calibration value loaded from Flash factory calibration at reset
1.024kHz clock outputs available
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22.3.
Block Diagram
Figure 22-1. OSC32KCTRL Block Diagram
OSC32KCTRL
XOUT32
XIN32
CFD
CLK_XOSC32K
XOSC32K
32K OSCILLATORS
CONTROL
CFD Event
CLK_OSCULP32K
OSCULP32K
CLK_OSC32K
OSC32K
STATUS
register
INTERRUPTS
GENERATOR
22.4.
Interrupts
Signal Description
Signal
Description
Type
XIN32
Analog Input
32.768kHz Crystal Oscillator or external clock generator input
XOUT32
Analog Output
32.768kHz Crystal Oscillator output
The I/O lines are automatically selected when XOSC32K is enabled.
Note: The signal of the external crystal oscillator may affect the jitter of neighboring pads.
22.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
22.5.1.
I/O Lines
I/O lines are configured by OSC32KCTRL when XOSC32K is enabled, and need no user configuration.
22.5.2.
Power Management
The OSC32KCTRL will continue to operate in any sleep mode where a 32KHz oscillator is running as
source clock. The OSC32KCTRL interrupts can be used to wake up the device from sleep modes.
Related Links
PM – Power Manager on page 177
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22.5.3.
Clocks
The OSC32KCTRL gathers controls for all 32KHz oscillators and provides clock sources to the Generic
Clock Controller (GCLK), Real-Time Counter (RTC), and Watchdog Timer (WDT).
The available clock sources are: XOSC32K, OSC32K, and OSCULP32K.
The OSC32KCTRL bus clock (CLK_OSC32KCTRL_APB) can be enabled and disabled in the Main Clock
module (MCLK).
Related Links
Peripheral Clock Masking on page 152
22.5.4.
Interrupts
The interrupt request lines are connected to the interrupt controller. Using the OSC32KCTRL interrupts
requires the interrupt controller to be configured first.
Related Links
Nested Vector Interrupt Controller on page 43
22.5.5.
Events
The events of this peripheral are connected to the Event System.
Related Links
EVSYS – Event System on page 487
22.5.6.
Debug Operation
When the CPU is halted in debug mode, OSC32KCTRL will continue normal operation. If OSC32KCTRL
is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar,
improper operation or data loss may result during debugging.
22.5.7.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except the following registers:
•
Interrupt Flag Status and Clear (INTFLAG) register
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
22.5.8.
Analog Connections
The external 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, along with any
required load capacitors. For details on recommended oscillator characteristics and capacitor load, refer
to the related links.
Related Links
Electrical Characteristics 85°C on page 900
22.5.9.
Calibration
The OSC32K calibration value from the production test must be loaded from the NVM Software
Calibration Area into the OSC32K register (OSC32K.CALIB) by software to achieve specified accuracy.
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Related Links
NVM Software Calibration Area Mapping on page 39
22.6.
Functional Description
22.6.1.
Principle of Operation
XOSC32K, OSC32K, and OSCULP32K are configured via OSC32KCTRL control registers. Through this
interface, the sub-peripherals are enabled, disabled, or have their calibration values updated.
The STATUS register gathers different status signals coming from the sub-peripherals of OSC32KCTRL.
The status signals can be used to generate system interrupts, and in some cases wake up the system
from standby mode, provided the corresponding interrupt is enabled.
22.6.2.
32KHz External Crystal Oscillator (XOSC32K) Operation
The XOSC32K can operate in two different modes:
•
•
External clock, with an external clock signal connected to XIN32
Crystal oscillator, with an external 32.768kHz crystal connected between XIN32 and XOUT32
At reset, the XOSC32K is disabled, and the XIN32/XOUT32 pins can either be used as General Purpose
I/O (GPIO) pins or by other peripherals in the system.
When XOSC32K is enabled, the operating mode determines the GPIO usage. When in crystal oscillator
mode, the XIN32 and XOUT32 pins are controlled by the OSC32KCTRL, and GPIO functions are
overridden on both pins. When in external clock mode, the only XIN32 pin will be overridden and
controlled by the OSC32KCTRL, while the XOUT32 pin can still be used as a GPIO pin.
The XOSC32K is enabled by writing a '1' to the Enable bit in the 32KHz External Crystal Oscillator
Control register (XOSC32K.ENABLE=1). The XOSC32K is disabled by writing a '0' to the Enable bit in the
32KHz External Crystal Oscillator Control register (XOSC32K.ENABLE=0).
To enable the XOSC32K as a crystal oscillator, the XTALEN bit in the 32KHz External Crystal Oscillator
Control register must be set (XOSC32K.XTALEN=1). If XOSC32K.XTALEN is '0', the external clock input
will be enabled.
The XOSC32K 32.768kHz output is enabled by setting the 32KHz Output Enable bit in the 32KHz
External Crystal Oscillator Control register (XOSC32K.EN32K=1). The XOSC32K also has a 1.024kHz
clock output. This is enabled by setting the 1KHz Output Enable bit in the 32KHz External Crystal
Oscillator Control register (XOSC32K.EN1K=1).
It is also possible to lock the XOSC32K configuration by setting the Write Lock bit in the 32KHz External
Crystal Oscillator Control register (XOSC32K.WRTLOCK=1). If set, the XOSC32K configuration is locked
until a Power-On Reset (POR) is detected.
The XOSC32K will behave differently in different sleep modes based on the settings of
XOSC32K.RUNSTDBY, XOSC32K.ONDEMAND, and XOSC32K.ENABLE. If
XOSC32KCTRL.ENABLE=0, the XOSC32K will be always stopped. For XOS32KCTRL.ENABLE=1, this
table is valid:
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Table 22-1. XOSC32K Sleep Behavior
CPU Mode
XOSC32KCTRL.
XOSC32KCTRL.
Sleep Behavior of XOSC32K and CFD
RUNSTDBY
ONDEMAND
Active or Idle
-
0
Always run
Active or Idle
-
1
Run if requested by peripheral
Standby
1
0
Always run
Standby
1
1
Run if requested by peripheral
Standby
0
-
Run if requested by peripheral
As a crystal oscillator usually requires a very long start-up time, the 32KHz External Crystal Oscillator will
keep running across resets when XOSC32K.ONDEMAND=0, except for power-on reset (POR). After a
reset or when waking up from a sleep mode where the XOSC32K was disabled, the XOSC32K will need
a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by
changing the Oscillator Start-Up Time bit group (XOSC32K.STARTUP) in the 32KHz External Crystal
Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no
unstable clock propagates to the digital logic.
Once the external clock or crystal oscillator is stable and ready to be used as a clock source, the
XOSC32K Ready bit in the Status register is set (STATUS.XOSC32KRDY=1). The transition of
STATUS.XOSC32KRDY from '0' to '1' generates an interrupt if the XOSC32K Ready bit in the Interrupt
Enable Set register is set (INTENSET.XOSC32KRDY=1).
The XOSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time
Counter (RTC). Before enabling the GCLK or the RTC module, the corresponding oscillator output must
be enabled (XOSC32K.EN32K or XOSC32K.EN1K) in order to ensure proper operation. In the same way,
the GCLK or RTC modules must be disabled before the clock selection is changed. For details on RTC
clock configuration, refer also to Real-Time Counter Clock Selection.
Related Links
GCLK - Generic Clock Controller on page 127
RTC – Real-Time Counter on page 292
22.6.3.
Clock Failure Detection Operation
The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator signal
provided by the external oscillator (XOSC32K). The CFD detects failing operation of the XOSC32K clock
with reduced latency, and allows to switch to a safe clock source in case of clock failure. The user can
also switch from the safe clock back to XOSC32K in case of recovery. The safe clock is derived from the
OSCULP32K oscillator with a configurable prescaler. This allows to configure the safe clock in order to
fulfill the operative conditions of the microcontroller.
In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to
run by a peripheral. See the Sleep Behavior table above when this is the case.
The user interface registers allow to enable, disable, and configure the CFD. The Status register provides
status flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event
when a failure is detected.
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Clock Failure Detection
The CFD is reset only at power-on (POR). The CFD does not monitor the XOSC32K clock when the
oscillator is disabled (XOSC32K.ENABLE=0).
Before starting CFD operation, the user must start and enable the safe clock source (OSCULP32K
oscillator).
CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register
(CFDCTRL.CFDEN). After starting or restarting the XOSC32K, the CFD does not detect failure until the
start-up time has elapsed. The start-up time is configured by the Oscillator Start-Up Time in the External
Multipurpose Crystal Oscillator Control register (XOSC32K.STARTUP). Once the XOSC32K Start-Up
Time is elapsed, the XOSC32K clock is constantly monitored.
During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the
XOSC32K. There must be at least one rising and one falling XOSC32K clock edge during 4 safe clock
periods to meet non-failure conditions. If no or insufficient activity is detected, the failure status is
asserted: The Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) and the Clock
Failure Detector interrupt flag bit in the Interrupt Flag register (INTFLAG.CLKFAIL) are set. If the CLKFAIL
bit in the Interrupt Enable Set register (INTENSET.CLKFAIL) is set, an interrupt is generated as well. If the
Event Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an output event is
generated, too.
After a clock failure was issued the monitoring of the XOSC32K clock is continued, and the Clock Failure
Detector status bit in the Status register (STATUS.CLKFAIL) reflects the current XOSC32K activity.
Clock Switch
When a clock failure is detected, the XOSC32K clock is replaced by the safe clock in order to maintain an
active clock during the XOSC32K clock failure. The safe clock source is the OSCULP32K oscillator clock.
Both 32KHz and 1KHz outputs of the XOSC32K are replaced by the respective OSCULP32K 32KHz and
1KHz outputs. The safe clock source can be scaled down by a configurable prescaler to ensure that the
safe clock frequency does not exceed the operating conditions selected by the application. When the
XOSC32K clock is switched to the safe clock, the Clock Switch bit in the Status register
(STATUS.CLKSW) is set.
When the CFD has switched to the safe clock, the XOSC32K is not disabled. If desired, the application
must take the necessary actions to disable the oscillator. The application must also take the necessary
actions to configure the system clocks to continue normal operations. In the case the application can
recover the XOSC32K, the application can switch back to the XOSC32K clock by writing a '1' to Switch
Back Enable bit in the Clock Failure Control register (CFDCTRL.SWBACK). Once the XOSC32K clock is
switched back, the Switch Back bit (CFDCTRL.SWBACK) is cleared by hardware.
Prescaler
The CFD has an internal configurable prescaler to generate the safe clock from the OSCULP32K
oscillator. The prescaler size allows to scale down the OSCULP32K oscillator so the safe clock frequency
is not higher than the XOSC32K clock frequency monitored by the CFD. The maximum division factor is
2.
The prescaler is applied on both outputs (32KHz and 1KHz) of the safe clock.
Example
For an external crystal oscillator at 32KHz and the OSCULP32K frequency is 32KHz, the
XOSC32K.CFDPRESC should be set to 0 for a safe clock of equal frequency.
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Event
If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock
failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock
failure will not be output on the Event Output.
Sleep Mode
The CFD is halted depending on configuration of the XOSC32K and the peripheral clock request. For
further details, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the
device from sleep modes.
22.6.4.
32KHz Internal Oscillator (OSC32K) Operation
The OSC32K provides a tunable, low-speed, and low-power clock source.
At reset, the OSC32K is disabled. It can be enabled by setting the Enable bit in the 32KHz Internal
Oscillator Control register (OSC32K.ENABLE=1). The OSC32K is disabled by clearing the Enable bit in
the 32KHz Internal Oscillator Control register (OSC32K.ENABLE=0).
The frequency of the OSC32K oscillator is controlled by OSC32K.CALIB, which is a calibration value in
the 32KHz Internal Oscillator Calibration bits in the 32KHz Internal Oscillator Control register. The CALIB
value must be must be loaded with production calibration values from the NVM Software Calibration Area.
When writing the Calibration bits, the user must wait for the STATUS.OSC32KRDY bit to go high before
the new value is committed to the oscillator.
The OSC32K has a 32.768kHz output which is enabled by setting the 32KHz Output Enable bit in the
32KHz Internal Oscillator Control register (OSC32K.EN32K=1). The OSC32K also has a 1.024kHz clock
output. This is enabled by setting the 1KHz Output Enable bit in the 32KHz Internal Oscillator Control
register (OSC32K.EN1K).
Before using the OSC32K, the Calibration field in the OSC32K register (OSC32K.CALIB) must be loaded
with production calibration values from the NVM Software Calibration Area.
The OSC32K will behave differently in different sleep modes based on the settings of
OSC32K.RUNSTDBY, OSC32K.ONDEMAND, and OSC32K.ENABLE. If OSC32KCTRL.ENABLE=0, the
OSC32K will be always stopped. For OS32KCTRL.ENABLE=1, this table is valid:
Table 22-2. OSC32K Sleep Behavior
CPU Mode
OSC32KCTRL.RUN
STDBY
OSC32KCTRL.OND Sleep Behavior
EMAND
Active or Idle
-
0
Always run
Active or Idle
-
1
Run if requested by peripheral
Standby
1
0
Always run
Standby
1
1
Run if requested by peripheral
Standby
0
-
Run if requested by peripheral
The OSC32K requires a start-up time. For this reason, OSC32K will keep running across resets when
OSC32K.ONDEMAND=0, except for power-on reset (POR).
After such a reset, or when waking up from a sleep mode where the OSC32K was disabled, the OSC32K
will need a certain amount of time to stabilize on the correct frequency.
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This startup time can be configured by changing the Oscillator Start-Up Time bit group
(OSC32K.STARTUP) in the OSC32K Control register. During the start-up time, the oscillator output is
masked to ensure that no unstable clock propagates to the digital logic.
Once the external clock or crystal oscillator is stable and ready to be used as a clock source, the
OSC32K Ready bit in the Status register is set (STATUS.OSC32KRDY=1). The transition of
STATUS.OSC32KRDY from '0' to '1' generates an interrupt if the OSC32K Ready bit in the Interrupt
Enable Set register is set (INTENSET.OSC32KRDY=1).
The OSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time
Counter (RTC). Before enabling the GCLK or the RTC module, the corresponding oscillator output must
be enabled (OSC32K.EN32K or OSC32K.EN1K) in order to ensure proper operation. In the same way,
the GCLK or RTC modules must be disabled before the clock selection is changed.
Related Links
NVM Software Calibration Area Mapping on page 39
RTC – Real-Time Counter on page 292
Real-Time Counter Clock Selection on page 233
22.6.5.
32KHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation
The OSCULP32K provides a tunable, low-speed, and ultra-low-power clock source. The OSCULP32K is
factory-calibrated under typical voltage and temperature conditions. The OSCULP32K should be
preferred to the OSC32K whenever the power requirements are prevalent over frequency stability and
accuracy.
The OSCULP32K is enabled by default after a power-on reset (POR) and will always run except during
POR. The frequency of the OSCULP32K oscillator is controlled by the value in the 32KHz Ultra Low
Power Internal Oscillator Calibration bits in the 32KHz Ultra Low Power Internal Oscillator Control register
(OSCULP32K.CALIB). This data is used to compensate for process variations.
OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during start-up. The
calibration value can be overridden by the user by writing to OSCULP32K.CALIB.
It is also possible to lock the OSCULP32K configuration by setting the Write Lock bit in the 32KHz Ultra
Low Power Internal Oscillator Control register (OSCULP32K.WRTLOCK=1). If set, the OSCULP32K
configuration is locked until a power-on reset (POR) is detected.
The OSCULP32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time
Counter (RTC). To ensure proper operation, the GCLK or RTC modules must be disabled before the clock
selection is changed.
Related Links
RTC – Real-Time Counter on page 292
Real-Time Counter Clock Selection on page 233
GCLK - Generic Clock Controller on page 127
22.6.6.
Watchdog Timer Clock Selection
The Watchdog Timer (WDT) uses the internal 1.024kHz OSCULP32K output clock. This clock is running
all the time and internally enabled when requested by the WDT module.
Related Links
WDT – Watchdog Timer on page 272
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22.6.7.
Real-Time Counter Clock Selection
Before enabling the RTC module, the RTC clock must be selected first. All oscillator outputs are valid as
RTC clock. The selection is done in the RTC Control register (RTCCTRL). To ensure a proper operation,
it is highly recommended to disable the RTC module first, before the RTC clock source selection is
changed.
Related Links
RTC – Real-Time Counter on page 292
22.6.8.
Interrupts
The OSC32KCTRL has the following interrupt sources:
•
•
•
XOSC32KRDY - 32KHz Crystal Oscillator Ready: A 0-to-1 transition on the
STATUS.XOSC32KRDY bit is detected
CLKFAIL - Clock Failure Detector: A 0-to-1 transition on the STATUS.CLKFAIL bit is detected
OSC32KRDY - 32KHz Internal Oscillator Ready: A 0-to-1 transition on the STATUS.OSC32KRDY
bit is detected
All these interrupts are synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be enabled
individually by setting the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled
by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is
generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request
remains active until the interrupt flag is cleared, the interrupt is disabled or the OSC32KCTRL is reset.
See the INTFLAG register for details on how to clear interrupt flags.
The OSC32KCTRL has one common interrupt request line for all the interrupt sources. The user must
read the INTFLAG register to determine which interrupt condition is present. Refer to the INTFLAG
register for details.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
Related Links
PM – Power Manager on page 177
Nested Vector Interrupt Controller on page 43
22.6.9.
Events
The CFD can generate the following output event:
•
Clock Failure Detector (CLKFAIL): Generated when the Clock Failure Detector status bit is set in
the Status register (STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit
(STATUS.SWBACK) in the Status register is set.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD
output event. Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for
details on configuring the event system.
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22.7.
Offset
Register Summary
Name
0x00
0x01
Bit Pos.
7:0
INTENCLR
23:16
0x03
31:24
0x04
7:0
INTENSET
23:16
0x07
31:24
0x08
7:0
INTFLAG
23:16
0x0B
31:24
0x0C
7:0
STATUS
OSC32KRDY
CLKFAIL
OSC32KRDY
Y
XOSC32KRD
Y
XOSC32KRD
Y
15:8
0x0A
0x0D
CLKFAIL
XOSC32KRD
15:8
0x06
0x09
OSC32KRDY
15:8
0x02
0x05
CLKFAIL
CLKSW
OSC32KRDY
XOSC32KRD
Y
15:8
0x0E
23:16
0x0F
31:24
0x10
...
Reserved
0x13
0x14
0x15
XOSC32K
7:0
15:8
0x16
CFDCTRL
7:0
0x17
EVCTRL
7:0
0x18
7:0
0x19
15:8
0x1A
OSC32K
0x1B
0x1C
0x1D
22.8.
ONDEMAND RUNSTDBY
EN1K
EN32K
XTALEN
WRTLOCK
ENABLE
STARTUP[2:0]
CFDPRESC
SWBACK
CFDEN
CFDEO
ONDEMAND RUNSTDBY
EN1K
EN32K
WRTLOCK
23:16
ENABLE
STARTUP[2:0]
CALIB[6:0]
31:24
OSCULP32K
7:0
15:8
WRTLOCK
CALIB[4:0]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be
accessed directly.
All registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
Optional Write-Protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in the register description. Write-protection does not apply to accesses through an
external debugger.
Related Links
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
234
PAC - Peripheral Access Controller on page 48
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Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
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22.8.1.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
2
CLKFAIL
Access
Reset
OSC32KRDY XOSC32KRDY
R/W
R/W
R/W
0
0
0
Bit 2 – CLKFAIL: XOSC32K Clock Failure Detection Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the XOSC32K Clock Failure Interrupt Enable bit, which disables the
XOSC32K Clock Failure interrupt.
Value
Description
0
The XOSC32K Clock Failure Detection is disabled.
1
The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated
when the XOSC32K Clock Failure Detection interrupt flag is set.
Bit 1 – OSC32KRDY: OSC32K Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K
Ready interrupt.
Value
Description
0
The OSC32K Ready interrupt is disabled.
1
The OSC32K Ready interrupt is enabled.
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Bit 0 – XOSC32KRDY: XOSC32K Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K
Ready interrupt.
Value
Description
0
The XOSC32K Ready interrupt is disabled.
1
The XOSC32K Ready interrupt is enabled.
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22.8.2.
Interrupt Enable Set
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
2
CLKFAIL
Access
Reset
OSC32KRDY XOSC32KRDY
R/W
R/W
R/W
0
0
0
Bit 2 – CLKFAIL: XOSC32K Clock Failure Detection Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the XOSC32K Clock Failure Interrupt Enable bit, which enables the
XOSC32K Clock Failure interrupt.
Value
Description
0
The XOSC32K Clock Failure Detection is disabled.
1
The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated
when the XOSC32K Clock Failure Detection interrupt flag is set.
Bit 1 – OSC32KRDY: OSC32K Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the OSC32K Ready Interrupt Enable bit, which enables the OSC32K Ready
interrupt.
Value
Description
0
The OSC32K Ready interrupt is disabled.
1
The OSC32K Ready interrupt is enabled.
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Bit 0 – XOSC32KRDY: XOSC32K Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K
Ready interrupt.
Value
Description
0
The XOSC32K Ready interrupt is disabled.
1
The XOSC32K Ready interrupt is enabled.
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22.8.3.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x08
Reset: 0x00000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
CLKFAIL
Access
Reset
OSC32KRDY XOSC32KRDY
R/W
R/W
R/W
0
0
0
Bit 2 – CLKFAIL: XOSC32K Clock Failure Detection
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the XOSC32K Clock Failure Detection bit in the Status
register (STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the XOSC32K Clock Failure Detection flag.
Bit 1 – OSC32KRDY: OSC32K Ready
This flag is cleared by writing a '1' to it.
This flag is set by a zero-to-one transition of the OSC32K Ready bit in the Status register
(STATUS.OSC32KRDY), and will generate an interrupt request if INTENSET.OSC32KRDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the OSC32K Ready interrupt flag.
Bit 0 – XOSC32KRDY: XOSC32K Ready
This flag is cleared by writing a '1' to it.
This flag is set by a zero-to-one transition of the XOSC32K Ready bit in the Status register
(STATUS.XOSC32KRDY), and will generate an interrupt request if INTENSET.XOSC32KRDY=1.
Writing a '0' to this bit has no effect.
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Writing a '1' to this bit clears the XOSC32K Ready interrupt flag.
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22.8.4.
Status
Name: STATUS
Offset: 0x0C
Reset: 0x00000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
CLKSW
OSC32KRDY XOSC32KRDY
Access
R
R
R
Reset
0
0
0
Bit 3 – CLKSW: XOSC32K Clock Switch
Value
Description
0
XOSC32K is not switched and provided the crystal oscillator.
1
XOSC32K is switched to be provided by the safe clock.
Bit 3 – CLKFAIL: XOSC32K Clock Failure Detector
Value
Description
0
XOSC32K is passing failure detection.
1
XOSC32K is not passing failure detection.
Bit 1 – OSC32KRDY: OSC32K Ready
Value
Description
0
OSC32K is not ready.
1
OSC32K is stable and ready to be used as a clock source.
Bit 0 – XOSC32KRDY: XOSC32K Ready
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Value
Description
0
XOSC32K is not ready.
1
XOSC32K is stable and ready to be used as a clock source.
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22.8.5.
32KHz External Crystal Oscillator (XOSC32K) Control
Name: XOSC32K
Offset: 0x14
Reset: 0x00000080
Property: PAC Write-Protection
Bit
15
14
13
12
11
10
9
WRTLOCK
Access
Reset
Bit
R/W
R/W
R/W
R/W
0
0
0
0
0
7
6
4
3
2
1
ONDEMAND
RUNSTDBY
EN1K
EN32K
XTALEN
ENABLE
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
Access
Reset
5
8
STARTUP[2:0]
Bit 12 – WRTLOCK: Write Lock
This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration.
Value
Description
0
The XOSC32K configuration is not locked.
1
The XOSC32K configuration is locked.
Bits 10:8 – STARTUP[2:0]: Oscillator Start-Up Time
These bits select the start-up time for the oscillator.
The OSCULP32K oscillator is used to clock the start-up counter.
Table 22-3. Start-Up Time for 32KHz External Crystal Oscillator
STARTUP[2:0] Number of OSCULP32K
Clock Cycles
Number of XOSC32K
Clock Cycles
Approximate Equivalent
Time
[s]
0x0
2048
3
0.06
0x1
4096
3
0.13
0x2
16384
3
0.5
0x3
32768
3
1
0x4
65536
3
2
0x5
131072
3
4
0x6
262144
3
8
0x7
-
-
Reserved
Note: 1. Actual Start-Up time is 1 OSCULP32K cycle + 3 XOSC32K cycles.
2. The given time assumes an XTAL frequency of 32.768kHz.
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Bit 7 – ONDEMAND: On Demand Control
This bit controls how the XOSC32K behaves when a peripheral clock request is detected. For details,
refer to XOSC32K Sleep Behavior.
Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the XOSC32K behaves during standby sleep mode. For details, refer to XOSC32K
Sleep Behavior.
Bit 4 – EN1K: 1KHz Output Enable
Value
Description
0
The 1KHz output is disabled.
1
The 1KHz output is enabled.
Bit 3 – EN32K: 32KHz Output Enable
Value
Description
0
The 32KHz output is disabled.
1
The 32KHz output is enabled.
Bit 2 – XTALEN: Crystal Oscillator Enable
This bit controls the connections between the I/O pads and the external clock or crystal oscillator.
Value
Description
0
External clock connected on XIN32. XOUT32 can be used as general-purpose I/O.
1
Crystal connected to XIN32/XOUT32.
Bit 1 – ENABLE: Oscillator Enable
Value
Description
0
The oscillator is disabled.
1
The oscillator is enabled.
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22.8.6.
Clock Failure Detector Control
Name: CFDCTRL
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
Access
Reset
2
1
0
CFDPRESC
SWBACK
CFDEN
R/W
R/W
R/W
0
0
0
Bit 2 – CFDPRESC: Clock Failure Detector Prescaler
This bit selects the prescaler for the Clock Failure Detector.
Value
Description
0
The CFD safe clock frequency is the OSCULP32K frequency
1
The CFD safe clock frequency is the OSCULP32K frequency divided by 2
Bit 1 – SWBACK: Clock Switch Back
This bit clontrols the XOSC32K output switch back to the external clock or crystal scillator in case of clock
recovery.
Value
Description
0
The clock switch is disabled.
1
The clock switch is enabled. This bit is reset when the XOSC32K output is switched back to
the external clock or crystal oscillator.
Bit 0 – CFDEN: Clock Failure Detector Enable
This bit selects the Clock Failure Detector state.
Value
Description
0
The CFD is disabled.
1
The CFD is enabled.
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22.8.7.
Event Control
Name: EVCTRL
Offset: 0x17
Reset: 0x0
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
CFDEO
Access
R/W
Reset
0
Bit 0 – CFDEO: Clock Failure Detector Event Out
This bit controls whether the Clock Failure Detector event output is enabled and an event will be
generated when the CFD detects a clock failure.
Value
Description
0
Clock Failure Detector Event output is disabled, no event will be generated.
1
Clock Failure Detector Event output is enabled, an event will be generated.
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22.8.8.
32KHz Internal Oscillator (OSC32K) Control
Name: OSC32K
Offset: 0x18
Reset: 0x0000 0080 (Writing action by User required)
Property: PAC Write-Protection
Bit
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
Access
Reset
Bit
CALIB[6:0]
Access
Reset
Bit
15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
14
13
12
11
10
9
8
WRTLOCK
Access
Reset
Bit
R/W
R/W
R/W
0
0
0
0
0
7
6
3
2
1
ONDEMAND
RUNSTDBY
EN1K
EN32K
ENABLE
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
Access
Reset
5
STARTUP[2:0]
R/W
4
Bits 22:16 – CALIB[6:0]: Oscillator Calibration
These bits control the oscillator calibration. The calibration values must be loaded by the user from the
NVM Software Calibration Area.
Bit 12 – WRTLOCK: Write Lock
This bit locks the OSC32K register for future writes, effectively freezing the OSC32K configuration.
Value
Description
0
The OSC32K configuration is not locked.
1
The OSC32K configuration is locked.
Bits 10:8 – STARTUP[2:0]: Oscillator Start-Up Time
These bits select start-up time for the oscillator.
The OSCULP32K oscillator is used as input clock to the start-up counter.
Table 22-4. Start-Up Time for 32KHz Internal Oscillator
STARTUP[2:0]
Number of OSC32K clock cycles
Approximate Equivalent Time [ms]
0x0
3
0.092
0x1
4
0.122
0x2
6
0.183
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STARTUP[2:0]
Number of OSC32K clock cycles
Approximate Equivalent Time [ms]
0x3
10
0.305
0x4
18
0.549
0x5
34
1.038
0x6
66
2.014
0x7
130
3.967
Note: 1. Start-up time is given by STARTUP + three OSC32K cycles.
2. The given time assumes an XTAL frequency of 32.768kHz.
Bit 7 – ONDEMAND: On Demand Control
This bit controls how the OSC32K behaves when a peripheral clock request is detected. For details, refer
to OSC32K Sleep Behavior.
Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the OSC32K behaves during standby sleep mode. For details, refer to OSC32K
Sleep Behavior.
Bit 3 – EN1K: 1KHz Output Enable
Value
Description
0
The 1KHz output is disabled.
1
The 1KHz output is enabled.
Bit 2 – EN32K: 32KHz Output Enable
Value
Description
0
The 32KHz output is disabled.
1
The 32KHz output is enabled.
Bit 1 – ENABLE: Oscillator Enable
Value
Description
0
The oscillator is disabled.
1
The oscillator is enabled.
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22.8.9.
32KHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
Name: OSCULP32K
Offset: 0x1C
Reset: 0x0000XX06
Property: PAC Write-Protection
Bit
15
14
13
12
11
WRTLOCK
Access
10
9
8
CALIB[4:0]
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
x
Bit
7
4
3
2
1
0
6
5
Access
Reset
Bit 15 – WRTLOCK: Write Lock
This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration.
Value
Description
0
The OSCULP32K configuration is not locked.
1
The OSCULP32K configuration is locked.
Bits 12:8 – CALIB[4:0]: Oscillator Calibration
These bits control the oscillator calibration.
These bits are loaded from Flash Calibration at startup.
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23.
SUPC – Supply Controller
23.1.
Overview
The Supply Controller (SUPC) manages the voltage reference and power supply of the device.
The SUPC controls the voltage regulators for the core (VDDCORE) domain. It sets the voltage regulators
according to the sleep modes, or the user configuration. In active mode, the voltage regulators can be
selected on the fly between LDO (low-dropout) type regulator or Buck converter.
The SUPC embeds two Brown-Out Detectors. BODVDD monitors the voltage applied to the device (VDD)
and BODCORE monitors the internal voltage to the core (VDDCORE). The BOD can monitor the supply
voltage continuously (continuous mode) or periodically (sampling mode).
The SUPC generates also a selectable reference voltage which can be used by analog modules like the
ADC.
23.2.
Features
•
•
•
•
Voltage Regulator System
– Main voltage regulator: LDO in active mode (MAINVREG)
– Low Power voltage regulator in mode (LPVREG)
Voltage Reference System
– Reference voltage for ADC
VDD Brown-Out Detector (BODVDD)
– Programmable threshold
– Threshold value loaded from NVM User Row at startup
– Triggers resets or interrupts. Action loaded from NVM User Row
– Operating modes:
• Continuous mode
• Sampled mode for low power applications with programmable sample frequency
– Hysteresis value from Flash User Calibration
VDDCORE Brown-Out Detector (BODCORE)
– Internal non-configurable Brown-Out Detector
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23.3.
Block Diagram
Figure 23-1. SUPC Block Diagram
VDD
BODVDD
Main VREG
VREG
BODVDD
BODCORE
BODCORE
LDO
VDDCORE
PM
sleep mode
LP VREG
Core
domain
temperature sensor
VREF
23.4.
VREF
reference voltage
Signal Description
Not appclicable.
Related Links
I/O Multiplexing and Considerations on page 28
23.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
23.5.1.
I/O Lines
I/O lines are configured by SUPC either when the SUPC output (signal OUT) is enabled or when the
PSOK input is enabled. The I/O lines need no user configuration.
23.5.2.
Power Management
The SUPC can operate in all sleep modes.
Related Links
PM – Power Manager on page 177
23.5.3.
Clocks
The SUPC bus clock (CLK_SUPC_APB) can be enabled and disabled in the Main Clock module.
A 32KHz clock, asynchronous to the user interface clock (CLK_SUPC_APB), is required to run BODVDD
and BODCORE in sampled mode. Due to this asynchronicity, writing to certain registers will require
synchronization between the clock domains. Refer to Synchronization for further details.
Related Links
OSC32KCTRL – 32KHz Oscillators Controller on page 225
Peripheral Clock Masking on page 152
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23.5.4.
DMA
Not applicable.
23.5.5.
Interrupts
The interrupt request lines are connected to the interrupt controller. Using the SUPC interrupts requires
the interrupt controller to be configured first.
Related Links
Nested Vector Interrupt Controller on page 43
23.5.6.
Events
Not applicable.
23.5.7.
Debug Operation
When the CPU is halted in debug mode, the SUPC continues normal operation. If the SUPC is configured
in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
If debugger cold-plugging is detected by the system, BODVDD and BODCORE resets will be masked.
The BOD resets keep running under hot-plugging. This allows to correct a BODVDD user level too high
for the available supply.
23.5.8.
Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
Note: Not all registers with write-access can be write-protected.
PAC Write-Protection is not available for the following registers:
•
Interrupt Flag Status and Clear register (INTFLAG)
Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual
register description.
Related Links
PAC - Peripheral Access Controller on page 48
23.5.9.
Analog Connections
Not applicable.
23.6.
Functional Description
23.6.1.
Voltage Regulator System Operation
23.6.1.1. Enabling, Disabling, and Resetting
The LDO main voltage regulator is enabled after any Reset. The main voltage regulator (MAINVREG) can
be disabled by writing the Enable bit in the VREG register (VREG.ENABLE) to zero. The main voltage
regulator output supply level is automatically defined by the sleep mode selected in the Power Manager
module.
Related Links
PM – Power Manager on page 177
23.6.1.2. Initialization
After a Reset, the LDO voltage regulator supplying VDDCORE is enabled.
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23.6.1.3. Sleep Mode Operation
In mode, the low power voltage regulator (LPVREG) is used to supply VDDCORE.
Related Links
Sleep Mode Controller on page 179
23.6.2.
Voltage Reference System Operation
23.6.2.1. Initialization
The voltage reference output disabled after any Reset.
23.6.2.2. Enabling, Disabling, and Resetting
The voltage reference output is enabled/disabled by setting/clearing the Voltage Reference Output
Enable bit in the Voltage Reference register (VREF.VREFOE).
23.6.2.3. Selecting a Voltage Reference
The SEL bit group in the VREF register (VREF.SEL) selects the reference voltage to be applied to analog
modules, e.g. the ADC.
23.6.2.4. Sleep Mode Operation
The Voltage Reference output behavior during sleep mode can be configured using the Run in Standby
bit and the On Demand bit in the Voltage Reference register (VREF.RUNSTDBY, VREF.ONDEMAND),
see the following table:
Table 23-1. VREF Sleep Mode Operation
VREF.ONDEMAND VREF.RUNSTDBY Voltage Reference Sleep behavior
23.6.3.
-
-
Disable
0
0
Always run in all sleep modes except standby sleep mode
0
1
Always run in all sleep modes including standby sleep mode
1
0
Only run if requested by the ADC, in all sleep modes except
standby sleep mode
1
1
Only run if requested by the ADC, in all sleep modes including
standby sleep mode
Brown-Out Detectors
23.6.3.1. Initialization
Before a Brown-Out Detector (BODVDD) is enabled, it must be configured, as outlined by the following:
•
Set the BOD threshold level (BODVDD.LEVEL)
•
Set the configuration in active, standby, backup modes (BODVDD.ACTCDG,
BODVDD.STDBYCFG, BODVDD.BKUP)
•
Set the prescaling value if the BOD will run in sampling mode (BODVDD.PSEL)
•
Set the action and hysteresis (BODVDD.ACTION and BODVDD.HYST)
The BODVDD register is Enable-Protected, meaning that they can only be written when the respective
BOD is disabled (BODVDD.ENABLE=0 and SYNCBUSY.BODVDDEN=0). As long as the Enable bit is '1',
any writes to Enable-Protected registers will be discarded, and an APB error will be generated. The
Enable bits are not Enable-Protected.
23.6.3.2. Enabling, Disabling, and Resetting
After power or user reset, the BODVDD and BODCORE register values are loaded from the NVM User
Row.
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The BODVDD is enabled by writing a '1' to the Enable bit in the BOD control register
(BODVDD.ENABLE). The BOD is disabled by writing a '0' to the BODVDD.ENABLE.
Related Links
NVM User Row Mapping on page 38
23.6.3.3. VDD Brown-Out Detector (BODVDD)
The VDD Brown-Out Detector (BODVDD) is able to monitor the VDD supply and compares the voltage
with the brown-out threshold level set in the BODVDD Level field (BODVDD.LEVEL) in the BODVDD
register.
When VDD crosses below the brown-out threshold level, the BODVDD can generate either an interrupt or
a Reset, depending on the BODVDD Action bit field (BODVDD.ACTION).
The BODVDD detection status can be read from the BODVDD Detection bit in the Status register
(STATUS.BODVDDDET).
At start-up or at Power-On Reset (POR), the BODVDD register values are loaded from the NVM User
Row.
Related Links
NVM User Row Mapping on page 38
23.6.3.4. VDDCORE Brown-Out Detector (BODCORE)
The BODCORE is calibrated in production and its calibration configuration is stored in the NVM User
Row. This configuration must not be changed to assure the correct behavior of the BODCORE. The
BODCORE generates a reset when VDDCORE crosses below the preset brown-out level. The
BODCORE is always disabled in standby sleep mode.
Related Links
NVM User Row Mapping on page 38
23.6.3.5. Continuous Mode
Continuous mode is the default mode for BODVDD.
The BODVDD is continuously monitoring the VDD supply voltage if it is enabled (BODVDD.ENABLE=1)
and if the BODVDD Configuration bit in the BODVDD register is cleared (BODVDD.ACTCFG=0 for active
mode, BODVDD.STDBYCFG=0 for standby mode).
23.6.3.6. Sampling Mode
The Sampling Mode is a low-power mode where the BODVDD is being repeatedly enabled on a sampling
clock’s ticks. The BODVDD will monitor the supply voltage for a short period of time and then go to a lowpower disabled state until the next sampling clock tick.
Sampling mode is enabled in Active mode for BODVDD by writing the ACTCFG bit
(BODVDD.ACTCFG=1). Sampling mode is enabled in Standby mode by writing to the STDBYCFG bit
(BODVDD.STBYCFG=1). The frequency of the clock ticks (Fclksampling) is controlled by the Prescaler
Select bit groups in the BODVDD register (BODVDD.PSEL).
������������ =
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2
PSEL + 1
The prescaler signal (Fclkprescaler) is a 1KHz clock, output by the 32KHz Ultra Low Power Oscillator
OSCULP32K.
As the sampling clock is different from the APB clock domain, synchronization among the clocks is
necessary. See also Synchronization.
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23.6.3.7. Hysteresis
A hysteresis on the trigger threshold of a BOD will reduce the sensitivity to ripples on the monitored
voltage: instead of switching RESET at each crossing of VBOD, the thresholds for switching RESET on
and off are separated (VBOD- and VBOD+, respectively).
Figure 23-2. BOD Hysteresis Principle
Hysteresis OFF:
VCC
VBOD
RESET
Hysteresis ON:
VCC
VBOD-
VBOD+
RESET
Enabling the BODVDD hysteresis by writing the Hysteresis bit in the BODVDD register (BODVDD.HYST)
to '1' will add hysteresis to the BODVDD threshold level.
The hysteresis functionality can be used in both Continuous and Sampling Mode.
23.6.3.8. Sleep Mode Operation
Standby Mode
The BODVDD can be used in standby mode if the BOD is enabled and the corresponding Run in Standby
bit is written to '1' (BODVDD.RUNSTDBY).
The BODVDD can be configured to work in either Continuous or Sampling Mode by writing a '1' to the
Configuration in Standby Sleep Mode bit (BODVDD.STDBYCFG).
23.6.4.
Interrupts
The SUPC has the following interrupt sources, which are either synchronous or asynchronous wake-up
sources:
•
•
•
BODVDD Ready (BODVDDRDY), synchronous
BODVDD Detection (BODVDDDET), asynchronous
BODVDD Synchronization Ready (BVDDSRDY), synchronous
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG) is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable
Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable
Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or
the SUPC is reset. See the INTFLAG register for details on how to clear interrupt flags. The SUPC has
one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register
to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
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Related Links
Nested Vector Interrupt Controller on page 43
Sleep Mode Controller on page 179
23.6.5.
Synchronization
The prescaler counters that are used to trigger brown-out detections operate asynchronously from the
peripheral bus. As a consequence, the BODVDD Enable bit (BODVDD.ENABLE) need synchronization
when written.
The Write-Synchronization of the Enable bit is triggered by writing a '1' to the Enable bit of the BODVDD
Control register. The Synchronization Ready bit (STATUS.BVDDSRDY) in the STATUS register will be
cleared when the Write-Synchronization starts, and set again when the Write-Synchronization is
complete. Writing to the same register while the Write-Synchronization is ongoing (STATUS.BVDDSRDY
is '0') will generate an error without stalling the APB bus.
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23.7.
Offset
Register Summary
Name
0x00
0x01
0x02
Bit Pos.
7:0
INTENCLR
0x03
15:8
23:16
31:24
0x04
7:0
0x05
15:8
0x06
INTENSET
31:24
0x08
7:0
0x09
INTFLAG
0x0B
15:8
31:24
7:0
0x0D
15:8
STATUS
31:24
0x10
7:0
0x11
BODVDD
0x13
BVDDSRDY BODVDDDET BODVDDRDY
23:16
0x0F
0x12
BVDDSRDY BODVDDDET BODVDDRDY
23:16
0x0C
0x0E
BVDDSRDY BODVDDDET BODVDDRDY
23:16
0x07
0x0A
BVDDSRDY BODVDDDET BODVDDRDY
RUNSTDBY
15:8
STDBYCFG
ACTION[1:0]
HYST
ENABLE
PSEL[3:0]
23:16
ACTCFG
LEVEL[5:0]
31:24
0x14
...
Reserved
0x17
0x18
7:0
0x19
15:8
0x1A
VREG
31:24
0x1C
7:0
0x1E
0x1F
23.8.
VREF
ENABLE
23:16
0x1B
0x1D
RUNSTDBY
ONDEMAND RUNSTDBY
VREFOE
15:8
23:16
SEL[3:0]
31:24
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). PAC Writeprotection is denoted by the "PAC Write-Protection" property in each individual register description. Refer
to Register Access Protection for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Write-Synchronized" or the "Read-Synchronized" property in each individual register description. Refer to
Synchronization for details.
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23.8.1.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
2
BVDDSRDY
Access
BODVDDDET BODVDDRDY
R/W
R/W
R/W
0
0
0
Reset
Bit 2 – BVDDSRDY: BODVDD Synchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the BODVDD Synchronization Ready Interrupt Enable bit, which disables
the BODVDD Synchronization Ready interrupt.
Value
Description
0
The BODVDD Synchronization Ready interrupt is disabled.
1
The BODVDD Synchronization Ready interrupt is enabled, and an interrupt request will be
generated when the BODVDD Synchronization Ready Interrupt flag is set.
Bit 1 – BODVDDDET: BODVDD Detection Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the BODVDD Detection Interrupt Enable bit, which disables the BODVDD
Detection interrupt.
Value
Description
0
The BODVDD Detection interrupt is disabled.
1
The BODVDD Detection interrupt is enabled, and an interrupt request will be generated
when the BODVDD Detection Interrupt flag is set.
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Bit 0 – BODVDDRDY: BODVDD Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the BODVDD Ready Interrupt Enable bit, which disables the BODVDD
Ready interrupt.
Value
Description
0
The BODVDD Ready interrupt is disabled.
1
The BODVDD Ready interrupt is enabled, and an interrupt request will be generated when
the BODVDD Ready Interrupt flag is set.
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23.8.2.
Interrupt Enable Set
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
2
BVDDSRDY
Access
BODVDDDET BODVDDRDY
R/W
R/W
R/W
0
0
0
Reset
Bit 2 – BVDDSRDY: BODVDD Synchronization Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the BODVDD Synchronization Ready Interrupt Enable bit, which enables
the BODVDD Synchronization Ready interrupt.
Value
Description
0
The BODVDD Synchronization Ready interrupt is disabled.
1
The BODVDD Synchronization Ready interrupt is enabled, and an interrupt request will be
generated when the BODVDD Synchronization Ready Interrupt flag is set.
Bit 1 – BODVDDDET: BODVDD Detection Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the BODVDD Detection Interrupt Enable bit, which enables the BODVDD
Detection interrupt.
Value
Description
0
The BODVDD Detection interrupt is disabled.
1
The BODVDD Detection interrupt is enabled, and an interrupt request will be generated
when the BODVDD Detection Interrupt flag is set.
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Bit 0 – BODVDDRDY: BODVDD Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the BODVDD Ready Interrupt Enable bit, which enables the BODVDD
Ready interrupt.
Value
Description
0
The BODVDD Ready interrupt is disabled.
1
The BODVDD Ready interrupt is enabled, and an interrupt request will be generated when
the BODVDD Ready Interrupt flag is set.
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23.8.3.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x08
Reset: 0x0000010X - X= determined from NVM User Row (0xX=0bx00y)
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
BVDDSRDY
Access
Reset
BODVDDDET BODVDDRDY
R/W
R/W
R/W
0
0
y
Bit 2 – BVDDSRDY: BODVDD Synchronization Ready
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the BODVDD Synchronization Ready bit in the Status
register (STATUS.BVDDSRDY) and will generate an interrupt request if INTENSET.BVDDSRDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the BODVDD Synchronization Ready interrupt flag.
Bit 1 – BODVDDDET: BODVDD Detection
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the BODVDD Detection bit in the Status register
(STATUS.BODVDDDET) and will generate an interrupt request if INTENSET.BODVDDDET=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the BODVDD Detection interrupt flag.
Bit 0 – BODVDDRDY: BODVDD Ready
This flag is cleared by writing a '1' to it.
This flag is set on a zero-to-one transition of the BODVDD Ready bit in the Status register
(STATUS.BODVDDRDY) and will generate an interrupt request if INTENSET.BODVDDRDY=1.
Writing a '0' to this bit has no effect.
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Writing a '1' to this bit clears the BODVDD Ready interrupt flag.
The BODVDD can be enabled.
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23.8.4.
Status
Name: STATUS
Offset: 0x0C
Reset: Determined from NVM User Row
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
BVDDSRDY
BODVDDDET BODVDDRDY
Access
R
R
R
Reset
0
0
y
Bit 2 – BVDDSRDY: BODVDD Synchronization Ready
Value
Description
0
BODVDD synchronization is ongoing.
1
BODVDD synchronization is complete.
Bit 1 – BODVDDDET: BODVDD Detection
Value
Description
0
No BODVDD detection.
1
BODVDD has detected that the I/O power supply is going below the BODVDD reference
value.
Bit 0 – BODVDDRDY: BODVDD Ready
The BODVDD can be enabled at start-up from NVM User Row.
Value
Description
0
BODVDD is not ready.
1
BODVDD is ready.
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23.8.5.
VDD Brown-Out Detector (BODVDD) Control
Name: BODVDD
Offset: 0x10
Reset: Determined from NVM User Row
Property: Write-Synchronized, Enable-Protected, PAC Write-Protection
Bit
31
30
29
28
27
23
22
21
20
19
26
25
24
18
17
16
Access
Reset
Bit
LEVEL[5:0]
Access
Reset
Bit
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
13
12
11
10
9
8
15
14
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
7
4
PSEL[3:0]
Access
ACTCFG
6
5
RUNSTDBY
STDBYCFG
R/W
R/W
R/W
0
0
y
Access
Reset
3
2
1
HYST
ENABLE
R/W
R/W
R/W
y
0
z
ACTION[1:0]
0
Bits 21:16 – LEVEL[5:0]: BODVDD Threshold Level on VDD
These bits set the triggering voltage threshold for the BODVDD when the BODVDD monitors VDD except
in backup sleep mode.
These bits are loaded from NVM User Row at start-up.
This bit field is not synchronized.
Bits 15:12 – PSEL[3:0]: Prescaler Select
Selects the prescaler divide-by output for the BODVDD sampling mode. The input clock comes from the
OSCULP32K 1KHz output.
Value
Name
Description
0x0
DIV2
Divide clock by 2
0x1
DIV4
Divide clock by 4
0x2
DIV8
Divide clock by 8
0x3
DIV16
Divide clock by 16
0x4
DIV32
Divide clock by 32
0x5
DIV64
Divide clock by 64
0x6
DIV128
Divide clock by 128
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Value
Name
Description
0x7
DIV256
Divide clock by 256
0x8
DIV512
Divide clock by 512
0x9
DIV1024
Divide clock by 1024
0xA
DIV2048
Divide clock by 2048
0xB
DIV4096
Divide clock by 4096
0xC
DIV8192
Divide clock by 8192
0xD
DIV16384
Divide clock by 16384
0xE
DIV32768
Divide clock by 32768
0xF
DIV65536
Divide clock by 65536
Bit 8 – ACTCFG: BODVDD Configuration in Active Sleep Mode
This bit is not synchronized.
Value
Description
0
In active mode, the BODVDD operates in continuous mode.
1
In active mode, the BODVDD operates in sampling mode.
Bit 6 – RUNSTDBY: Run in Standby
This bit is not synchronized.
Value
Description
0
In standby sleep mode, the BODVDD is disabled.
1
In standby sleep mode, the BODVDD is enabled.
Bit 5 – STDBYCFG: BODVDD Configuration in Standby Sleep Mode
If the RUNSTDBY bit is set to '1', the STDBYCFG bit sets the BODVDD configuration in standby sleep
mode.
This bit is not synchronized.
Value
Description
0
In standby sleep mode, the BODVDD is enabled and configured in continuous mode.
1
In standby sleep mode, the BODVDD is enabled and configured in sampling mode.
Bits 4:3 – ACTION[1:0]: BODVDD Action
These bits are used to select the BODVDD action when the supply voltage crosses below the BODVDD
threshold.
These bits are loaded from NVM User Row at start-up.
This bit field is not synchronized.
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Value
Name
Description
0x0
NONE
No action
0x1
RESET
The BODVDD generates a reset
0x2
INT
0x3
-
The BODVDD generates an interrupt
Reserved
Bit 2 – HYST: Hysteresis
This bit indicates whether hysteresis is enabled for the BODVDD threshold voltage.
This bit is loaded from NVM User Row at start-up.
This bit is not synchronized.
Value
Description
0
No hysteresis.
1
Hysteresis enabled.
Bit 1 – ENABLE: Enable
This bit is loaded from NVM User Row at start-up.
This bit is not enable-protected.
Value
Description
0
BODVDD is disabled.
1
BODVDD is enabled.
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23.8.6.
Voltage Regulator System (VREG) Control
Name: VREG
Offset: 0x18
Reset: 0x00000002
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
RUNSTDBY
ENABLE
R/W
R/W
0
1
Bit 6 – RUNSTDBY: Run in Standby
Value
Description
0
The voltage regulator is in low power mode in Standby sleep mode.
1
The voltage regulator is in normal mode in Standby sleep mode.
Bit 1 – ENABLE: Enable
Value
Description
0
The voltage regulator is disabled.
1
The voltage regulator is enabled.
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23.8.7.
Voltage References System (VREF) Control
Name: VREF
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
23
22
21
20
19
18
25
24
17
16
Access
Reset
Bit
SEL[3:0]
Access
R/W
R/W
R/W
R/W
0
0
0
0
Reset
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
VREFOE
R/W
R/W
R/W
0
0
0
Access
Reset
Bit
Access
Reset
Bits 19:16 – SEL[3:0]: Voltage Reference Selection
These bits select the Voltage Reference for the ADC.
Value
Description
0x0
1.024V voltage reference typical value.
0x2
2.048V voltage reference typical value.
0x3
4.096V voltage reference typical value.
Others
Reserved
Bit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows to enable or disable the voltage reference depending on
peripheral requests.
Value
Description
0
The voltage reference is always on, if enabled.
1
The voltage reference is enabled when a peripheral is requesting it. The voltage reference is
disabled if no peripheral is requesting it.
Bit 6 – RUNSTDBY: Run In Standby
The bit controls how the voltage reference behaves during standby sleep mode.
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Value
Description
0
The voltage reference is halted during standby sleep mode.
1
The voltage reference is not stopped in standby sleep mode. If VREF.ONDEMAND=1, the
voltage reference will be running when a peripheral is requesting it. If VREF.ONDEMAND=0,
the voltage reference will always be running in standby sleep mode.
Bit 2 – VREFOE: Voltage Reference Output Enable
Value
Description
0
The Voltage Reference output is not available as an ADC input channel.
1
The Voltage Reference output is routed to an ADC input channel.
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24.
24.1.
WDT – Watchdog Timer
Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it
possible to recover from error situations such as runaway or deadlocked code. The WDT is configured to
a predefined time-out period, and is constantly running when enabled. If the WDT is not cleared within the
time-out period, it will issue a system reset. An early-warning interrupt is available to indicate an
upcoming watchdog time-out condition.
The window mode makes it possible to define a time slot (or window) inside the total time-out period
during which the WDT must be cleared. If the WDT is cleared outside this window, either too early or too
late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a
code error causes the WDT to be cleared frequently.
When enabled, the WDT will run in active mode and all sleep modes. It is asynchronous and runs from a
CPU-independent clock source. The WDT will continue operation and issue a system reset or interrupt
even if the main clocks fail.
24.2.
Features
•
•
•
•
•
•
Issues a system reset if the Watchdog Timer is not cleared before its time-out period
Early Warning interrupt generation
Asynchronous operation from dedicated oscillator
Two types of operation
– Normal
– Window mode
Selectable time-out periods
– From 8 cycles to 16,384 cycles in Normal mode
– From 16 cycles to 32,768 cycles in Window mode
Always-On capability
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24.3.
Block Diagram
Figure 24-1. WDT Block Diagram
0
CLEAR
OSC32KCTRL
CLK_WDT_OSC
COUNT
PER/WINDOWS/EWOFFSET
Early Warning Interrupt
Reset
24.4.
Signal Description
Not applicable.
24.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
24.5.1.
I/O Lines
Not applicable.
24.5.2.
Power Management
The WDT can continue to operate in any sleep mode where the selected source clock is running. The
WDT interrupts can be used to wake up the device from sleep modes. The events can trigger other
operations in the system without exiting sleep modes.
Related Links
PM – Power Manager on page 177
24.5.3.
Clocks
The WDT bus clock (CLK_WDT_APB) can be enabled and disabled (masked) in the Main Clock module
(MCLK).
A 1KHz oscillator clock (CLK_WDT_OSC) is required to clock the WDT internal counter. This clock must
be configured and enabled in the 32KHz Oscillator Controller (OSC32KCTRL) before using the WDT.
CLK_WDT_OSC is normally sourced from the clock of the internal ultra-low-power oscillator,
OSCULP32K. Due to the ultra-low-power design, the oscillator is not very accurate, and so the exact
time-out period may vary from device to device. This variation must be kept in mind when designing
software that uses the WDT to ensure that the time-out periods used are valid for all devices.
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The counter clock CLK_WDT_OSC is asynchronous to the bus clock (CLK_WDT_APB). Due to this
asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer
to Synchronization for further details.
Related Links
Peripheral Clock Masking on page 152
OSC32KCTRL – 32KHz Oscillators Controller on page 225
24.5.4.
DMA
Not applicable.
24.5.5.
Interrupts
The interrupt request line is connected to the interrupt controller. Using the WDT interrupt(s) requires the
interrupt controller to be configured first.
Related Links
Nested Vector Interrupt Controller on page 43
Overview on page 43
Interrupt Line Mapping on page 43
24.5.6.
Events
Not applicable.
24.5.7.
Debug Operation
When the CPU is halted in debug mode the WDT will halt normal operation.
24.5.8.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except the following registers:
•
Interrupt Flag Status and Clear (INTFLAG) register
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
24.5.9.
Analog Connections
Not applicable.
24.6.
Functional Description
24.6.1.
Principle of Operation
The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to
recover from error situations such as runaway code, by issuing a Reset. When enabled, the WDT is a
constantly running timer that is configured to a predefined time-out period. Before the end of the time-out
period, the WDT should be set back, or else, a system Reset is issued.
The WDT has two modes of operation, Normal mode and Window mode. Both modes offer the option of
Early Warning interrupt generation. The description for each of the basic modes is given below. The
settings in the Control A register (CTRLA) and the Interrupt Enable register (handled by INTENCLR/
INTENSET) determine the mode of operation:
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Table 24-1. WDT Operating Modes
24.6.2.
CTRLA.ENABLE
CTRLA.WEN
Interrupt Enable
Mode
0
x
x
Stopped
1
0
0
Normal mode
1
0
1
Normal mode with Early Warning interrupt
1
1
0
Window mode
1
1
1
Window mode with Early Warning interrupt
Basic Operation
24.6.2.1. Initialization
The following bits are enable-protected, meaning that they can only be written when the WDT is disabled
(CTRLA.ENABLE=0):
•
•
•
Control A register (CTRLA), except the Enable bit (CTRLA.ENABLE)
Configuration register (CONFIG)
Early Warning Interrupt Control register (EWCTRL)
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is
written to '1', but not at the same time as CTRLA.ENABLE is written to '0'.
The WDT can be configured only while the WDT is disabled. The WDT is configured by defining the
required Time-Out Period bits in the Configuration register (CONFIG.PER). If Window mode operation is
desired, the Window Enable bit in the Control A register must be set (CTRLA.WEN=1) and the Window
Period bits in the Configuration register (CONFIG.WINDOW) must be defined.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
24.6.2.2. Configurable Reset Values
After a Power-on Reset, some registers will be loaded with initial values from the NVM User Row.
This includes the following bits and bit groups:
•
•
•
•
•
•
Enable bit in the Control A register, CTRLA.ENABLE
Always-On bit in the Control A register, CTRLA.ALWAYSON
Watchdog Timer Windows Mode Enable bit in the Control A register, CTRLA.WEN
Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register,
CONFIG.WINDOW
Time-Out Period bits in the Configuration register, CONFIG.PER
Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register,
EWCTRL.EWOFFSET
Related Links
NVM User Row Mapping on page 38
24.6.2.3. Enabling, Disabling, and Resetting
The WDT is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The
WDT is disabled by writing a '0' to CTRLA.ENABLE.
The WDT can be disabled only if the Always-On bit in the Control A register (CTRLA.ALWAYSON) is '0'.
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24.6.2.4. Normal Mode
In Normal mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is
enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). Once enabled, the
WDT will issue a system reset if a time-out occurs. This can be prevented by clearing the WDT at any
time during the time-out period.
The WDT is cleared and a new WDT time-out period is started by writing 0xA5 to the Clear register
(CLEAR). Writing any other value than 0xA5 to CLEAR will issue an immediate system reset.
There are 12 possible WDT time-out (TOWDT) periods, selectable from 8ms to 16s.
By default, the early warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in
the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is
disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear register
(INTENCLR.EW).
If the Early Warning Interrupt is enabled, an interrupt is generated prior to a WDT time-out condition. In
Normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control register,
EWCTRL.EWOFFSET, define the time when the early warning interrupt occurs. The Normal mode
operation is illustrated in the figure Normal-Mode Operation.
Figure 24-2. Normal-Mode Operation
System Reset
WDT Count
Timely WDT Clear
PER[3:0]=1
WDT Timeout
Early Warning Interrupt
EWOFFSET[3:0]=0
5
10
15
20
25
30
TOWDT
35
t [ms]
24.6.2.5. Window Mode
In Window mode operation, the WDT uses two different time specifications: the WDT can only be cleared
by writing 0xA5 to the CLEAR register after the closed window time-out period (TOWDTW), during the
subsequent Normal time-out period (TOWDT). If the WDT is cleared before the time window opens (before
TOWDTW is over), the WDT will issue a system reset.
Both parameters TOWDTW and TOWDT are periods in a range from 8ms to 16s, so the total duration of the
WDT time-out period is the sum of the two parameters.
The closed window period is defined by the Window Period bits in the Configuration register
(CONFIG.WINDOW), and the open window period is defined by the Period bits in the Configuration
register (CONFIG.PER).
By default, the Early Warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in
the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is
disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear
(INTENCLR.EW) register.
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If the Early Warning interrupt is enabled in Window mode, the interrupt is generated at the start of the
open window period, i.e. after TOWDTW. The Window mode operation is illustrated in figure Window-Mode
Operation.
Figure 24-3. Window-Mode Operation
WDT Count
Timely WDT Clear
Open
PER[3:0]=0
Early Warning Interrupt
Early WDT Clear
Closed
WINDOW[3:0]=0
WDT Timeout
5
24.6.3.
10
15
20
TOWDTW
25
30
TOWDT
35
t [ms]
DMA Operation
Not applicable.
24.6.4.
Interrupts
The WDT has the following interrupt source:
•
Early Warning (EW): Indicates that the counter is approaching the time-out condition.
– This interrupt is an asynchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable
Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable
Clear (INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the WDT
is reset. See the INTFLAG register description for details on how to clear interrupt flags. All interrupt
requests from the peripheral are ORed together on system level to generate one combined interrupt
request to the NVIC. The user must read the INTFLAG register to determine which interrupt condition is
present.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
Related Links
Nested Vector Interrupt Controller on page 43
Overview on page 43
Interrupt Line Mapping on page 43
PM – Power Manager on page 177
Sleep Mode Controller on page 179
24.6.5.
Events
Not applicable.
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24.6.6.
Sleep Mode Operation
The WDT will continue to operate in any sleep mode where the source clock is active except backup
mode. The WDT interrupts can be used to wake up the device from a sleep mode. An interrupt request
will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise the
CPU will wake up directly, without triggering an interrupt. In this case, the CPU will continue executing
from the instruction following the entry into sleep.
24.6.7.
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following registers are synchronized when written:
•
•
•
Enable bit in Control A register (CTRLA.ENABLE)
Window Enable bit in Control A register (CTRLA.WEN)
Always-On bit in control Control A (CTRLA.ALWAYSON)
The following registers are synchronized when read:
•
Watchdog Clear register (CLEAR)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register
description.
24.6.8.
Additional Features
24.6.8.1. Always-On Mode
The Always-On mode is enabled by setting the Always-On bit in the Control A register
(CTRLA.ALWAYSON=1). When the Always-On mode is enabled, the WDT runs continuously, regardless
of the state of CTRLA.ENABLE. Once written, the Always-On bit can only be cleared by a power-on reset.
The Configuration (CONFIG) and Early Warning Control (EWCTRL) registers are read-only registers
while the CTRLA.ALWAYSON bit is set. Thus, the time period configuration bits (CONFIG.PER,
CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed.
Enabling or disabling Window mode operation by writing the Window Enable bit (CTRLA.WEN) is allowed
while in Always-On mode, but note that CONFIG.PER cannot be changed.
The Interrupt Clear and Interrupt Set registers are accessible in the Always-On mode. The Early Warning
interrupt can still be enabled or disabled while in the Always-On mode, but note that
EWCTRL.EWOFFSET cannot be changed.
Table WDT Operating Modes With Always-On shows the operation of the WDT for
CTRLA.ALWAYSON=1.
Table 24-2. WDT Operating Modes With Always-On
WEN
Interrupt Enable
Mode
0
0
Always-on and normal mode
0
1
Always-on and normal mode with Early Warning interrupt
1
0
Always-on and window mode
1
1
Always-on and window mode with Early Warning interrupt
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24.6.8.2. Early Warning
The Early Warning interrupt notifies that the WDT is approaching its time-out condition. The Early
Warning interrupt behaves differently in Normal mode and in Window mode.
In Normal mode, the Early Warning interrupt generation is defined by the Early Warning Offset in the
Early Warning Control register (EWCTRL.EWOFFSET). The Early Warning Offset bits define the number
of CLK_WDT_OSC clocks before the interrupt is generated, relative to the start of the watchdog time-out
period.
The user must take caution when programming the Early Warning Offset bits. If these bits define an Early
Warning interrupt generation time greater than the watchdog time-out period, the watchdog time-out
system reset is generated prior to the Early Warning interrupt. Consequently, the Early Warning interrupt
will never be generated.
In window mode, the Early Warning interrupt is generated at the start of the open window period. In a
typical application where the system is in sleep mode, the Early Warning interrupt can be used to wake up
and clear the Watchdog Timer, after which the system can perform other tasks or return to sleep mode.
If the WDT is operating in Normal mode with CONFIG.PER = 0x2 and
EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16
CLK_WDT_OSC clock cycles after the start of the time-out period. The time-out system
reset is generated 32 CLK_WDT_OSC clock cycles after the start of the watchdog timeout period.
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24.7.
Register Summary
Offset
Name
Bit Pos.
0x00
CTRLA
7:0
0x01
CONFIG
7:0
0x02
EWCTRL
7:0
ALWAYSON
WEN
WINDOW[3:0]
ENABLE
PER[3:0]
EWOFFSET[3:0]
0x03
Reserved
0x04
INTENCLR
7:0
EW
0x05
INTENSET
7:0
EW
0x06
INTFLAG
7:0
EW
0x07
Reserved
0x08
0x09
0x0A
7:0
SYNCBUSY
0x0B
0x0C
24.8.
CLEAR
ALWAYSON
WEN
ENABLE
15:8
23:16
31:24
CLEAR
7:0
CLEAR[7:0]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "WriteSynchronized" or the "Read-Synchronized" property in each individual register description. For details,
refer to Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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24.8.1.
Control A
Name: CTRLA
Offset: 0x00
Reset: N/A - Loaded from NVM User Row at startup
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
2
1
ALWAYSON
7
WEN
ENABLE
R/W
R/W
R/W
-
-
-
Access
Reset
6
5
4
3
0
Bit 7 – ALWAYSON: Always-On
This bit allows the WDT to run continuously. After being set, this bit cannot be written to '0', and the WDT
will remain enabled until a power-on Reset is received. When this bit is '1', the Control A register
(CTRLA), the Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be
read-only, and any writes to these registers are not allowed.
Writing a '0' to this bit has no effect.
This bit is not Enable-Protected.
This bit is loaded from NVM User Row at startup.
Value
Description
0
The WDT is enabled and disabled through the ENABLE bit.
1
The WDT is enabled and can only be disabled by a power-on reset (POR).
Bit 2 – WEN: Watchdog Timer Window Mode Enable
This bit enables Window mode. It can only be written if the peripheral is disabled unless
CTRLA.ALWAYSON=1. The initial value of this bit is loaded from Flash Calibration.
This bit is loaded from NVM User Row at startup.
Value
Description
0
Window mode is disabled (normal operation).
1
Window mode is enabled.
Bit 1 – ENABLE: Enable
This bit enables or disables the WDT. It can only be written if CTRLA.ALWAYSON=0.
Due to synchronization, there is delay between writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately, and the Enable bit in the
Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared
when the operation is complete.
This bit is not Enable-Protected.
This bit is loaded from NVM User Row at startup.
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Value
Description
0
The WDT is disabled.
1
The WDT is enabled.
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24.8.2.
Configuration
Name: CONFIG
Offset: 0x01
Reset: Loaded from NVM User Row at startup
Property: PAC Write-Protection, Enable-Protected
Bit
7
6
5
4
3
2
WINDOW[3:0]
Access
Reset
1
0
PER[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
Bits 7:4 – WINDOW[3:0]: Window Mode Time-Out Period
In Window mode, these bits determine the watchdog closed window period as a number of cycles of the
1.024kHz CLK_WDT_OSC clock.
These bits are loaded from NVM User Row at startup.
Value
Name
Description
0x0
CYC8
8 clock cycles
0x1
CYC16
16 clock cycles
0x2
CYC32
32 clock cycles
0x3
CYC64
64 clock cycles
0x4
CYC128
128 clock cycles
0x5
CYC256
256 clock cycles
0x6
CYC512
512 clock cycles
0x7
CYC1024
1024 clock cycles
0x8
CYC2048
2048 clock cycles
0x9
CYC4096
4096 clock cycles
0xA
CYC8192
8192 clock cycles
0xB
CYC16384
16384 clock cycles
0xC - 0xF -
Reserved
Bits 3:0 – PER[3:0]: Time-Out Period
These bits determine the watchdog time-out period as a number of 1.024kHz CLK_WDTOSC clock
cycles. In Window mode operation, these bits define the open window period.
These bits are loaded from NVM User Row at startup.
Value
Name
Description
0x0
CYC8
8 clock cycles
0x1
CYC16
16 clock cycles
0x2
CYC32
32 clock cycles
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Value
Name
Description
0x3
CYC64
64 clock cycles
0x4
CYC128
128 clock cycles
0x5
CYC256
256 clock cycles
0x6
CYC512
512 clock cycles
0x7
CYC1024
1024 clock cycles
0x8
CYC2048
2048 clock cycles
0x9
CYC4096
4096 clock cycles
0xA
CYC8192
8192 clock cycles
0xB
CYC16384
16384 clock cycles
0xC - 0xF -
Reserved
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24.8.3.
Early Warning Control
Name: EWCTRL
Offset: 0x02
Reset: N/A - Loaded from NVM User Row at startup
Property: PAC Write-Protection, Enable-Protected
Bit
7
6
5
4
3
2
1
0
EWOFFSET[3:0]
Access
Reset
R/W
R/W
R/W
R/W
-
-
-
-
Bits 3:0 – EWOFFSET[3:0]: Early Warning Interrupt Time Offset
These bits determine the number of GCLK_WDT clock cycles between the start of the watchdog time-out
period and the generation of the Early Warning interrupt. These bits are loaded from NVM User Row at
startup.
Value
Name
Description
0x0
CYC8
8 clock cycles
0x1
CYC16
16 clock cycles
0x2
CYC32
32 clock cycles
0x3
CYC64
64 clock cycles
0x4
CYC128
128 clock cycles
0x5
CYC256
256 clock cycles
0x6
CYC512
512 clock cycles
0x7
CYC1024
1024 clock cycles
0x8
CYC2048
2048 clock cycles
0x9
CYC4096
4096 clock cycles
0xA
CYC8192
8192 clock cycles
0xB
CYC16384
16384 clock cycles
0xC - 0xF -
Reserved
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24.8.4.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
EW
Access
R/W
Reset
0
Bit 0 – EW: Early Warning Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Early Warning Interrupt Enable bit, which disables the Early Warning
interrupt.
Value
Description
0
The Early Warning interrupt is disabled.
1
The Early Warning interrupt is enabled.
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24.8.5.
Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
EW
Access
R/W
Reset
0
Bit 0 – EW: Early Warning Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit sets the Early Warning Interrupt Enable bit, which enables the Early Warning
interrupt.
Value
Description
0
The Early Warning interrupt is disabled.
1
The Early Warning interrupt is enabled.
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24.8.6.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x06
Reset: 0x00
Property: N/A
Bit
7
6
5
4
3
2
1
0
EW
Access
R/W
Reset
0
Bit 0 – EW: Early Warning
This flag is cleared by writing a '1' to it.
This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in
EWCTRL.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Early Warning interrupt flag.
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24.8.7.
Synchronization Busy
Name: SYNCBUSY
Offset: 0x08
Reset: 0x00000000
Property: Read-Only
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
CLEAR
ALWAYSON
WEN
ENABLE
Access
R
R
R
R
Reset
0
0
0
0
Bit 4 – CLEAR: Clear Synchronization Busy
Value
Description
0
Write synchronization of the CLEAR register is complete.
1
Write synchronization of the CLEAR register is ongoing.
Bit 3 – ALWAYSON: Always-On Synchronization Busy
Value
Description
0
Write synchronization of the CTRLA.ALWAYSON bit is complete.
1
Write synchronization of the CTRLA.ALWAYSON bit is ongoing.
Bit 2 – WEN: Window Enable Synchronization Busy
Value
Description
0
Write synchronization of the CTRLA.WEN bit is complete.
1
Write synchronization of the CTRLA.WEN bit is ongoing.
Bit 1 – ENABLE: Enable Synchronization Busy
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Value
Description
0
Write synchronization of the CTRLA.ENABLE bit is complete.
1
Write synchronization of the CTRLA.ENABLE bit is ongoing.
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24.8.8.
Clear
Name: CLEAR
Offset: 0x0C
Reset: 0x00
Property: Write-Synchronized
Bit
7
6
5
4
3
2
1
0
CLEAR[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7:0 – CLEAR[7:0]: Watchdog Clear
In Normal mode, writing 0xA5 to this register during the watchdog time-out period will clear the Watchdog
Timer and the watchdog time-out period is restarted.
In Window mode, any writing attempt to this register before the time-out period started (i.e., during
TOWDTW) will issue an immediate system Reset. Writing 0xA5 during the time-out period TOWDT will clear
the Watchdog Timer and the complete time-out sequence (first TOWDTW then TOWDT) is restarted.
In both modes, writing any other value than 0xA5 will issue an immediate system Reset.
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25.
RTC – Real-Time Counter
25.1.
Overview
The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs
continuously to keep track of time. The RTC can wake up the device from sleep modes using the alarm/
compare wake up, periodic wake up, or overflow wake up mechanisms.
The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare
interrupts and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger
an overflow interrupt and peripheral event, and can be reset on the occurrence of an alarm/compare
match. This allows periodic interrupts and peripheral events at very long and accurate intervals.
The 10-bit programmable prescaler can scale down the clock source. By this, a wide range of resolutions
and time-out periods can be configured. With a 32.768kHz clock source, the minimum counter tick
interval is 30.5µs, and time-out periods can range up to 36 hours. For a counter tick interval of 1s, the
maximum time-out period is more than 136 years.
25.2.
Features
•
•
•
•
•
•
•
25.3.
32-bit counter with 10-bit prescaler
Multiple clock sources
32-bit or 16-bit counter mode
One 32-bit or two 16-bit compare values
Clock/Calendar mode
– Time in seconds, minutes, and hours (12/24)
– Date in day of month, month, and year
– Leap year correction
Digital prescaler correction/tuning for increased accuracy
Overflow, alarm/compare match and prescaler interrupts and events
– Optional clear on alarm/compare match
Block Diagram
Figure 25-1. RTC Block Diagram (Mode 0 — 32-Bit Counter)
0x00000000
MATCHCLR
OSC32KCTRL
CLK_RTC_OSC
CLK_RTC_CNT
PRESCALER
OVF
COUNT
=
Periodic Events
CMPn
COMPn
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Figure 25-2. RTC Block Diagram (Mode 1 — 16-Bit Counter)
0x0000
OSC32KCTRL
CLK_RTC_OSC
CLK_RTC_CNT
PRESCALER
Periodic Events
COUNT
PER
=
OVF
=
CMPn
COMPn
Figure 25-3. RTC Block Diagram (Mode 2 — Clock/Calendar)
0x00000000
MATCHCLR
OSC32KCTRL
CLK_RTC_OSC
CLK_RTC_CNT
PRESCALER
Periodic Events
OVF
CLOCK
=
MASKn
ALARMn
25.4.
Signal Description
Not applicable.
25.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
25.5.1.
I/O Lines
Not applicable.
25.5.2.
Power Management
The RTC will continue to operate in any sleep mode where the selected source clock is running. The RTC
interrupts can be used to wake up the device from sleep modes. Events connected to the event system
can trigger other operations in the system without exiting sleep modes. Refer to the Power Manager for
details on the different sleep modes.
The RTC will be reset only at power-on (POR) or by setting the Software Reset bit in the Control A
register (CTRLA.SWRST=1).
Related Links
PM – Power Manager on page 177
25.5.3.
Clocks
The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Main Clock module MCLK, and
the default state of CLK_RTC_APB can be found in Peripheral Clock Masking section.
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A 32KHz or 1KHz oscillator clock (CLK_RTC_OSC) is required to clock the RTC. This clock must be
configured and enabled in the 32KHz oscillator controller (OSC32KCTRL) before using the RTC.
This oscillator clock is asynchronous to the bus clock (CLK_RTC_APB). Due to this asynchronicity, writing
to certain registers will require synchronization between the clock domains. Refer to Synchronization for
further details.
Related Links
OSC32KCTRL – 32KHz Oscillators Controller on page 225
Peripheral Clock Masking on page 152
25.5.4.
DMA
Related Links
DMAC – Direct Memory Access Controller on page 346
25.5.5.
Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupt requires the
Interrupt Controller to be configured first.
Related Links
Nested Vector Interrupt Controller on page 43
25.5.6.
Events
The events are connected to the Event System.
Related Links
EVSYS – Event System on page 487
25.5.7.
Debug Operation
When the CPU is halted in debug mode the RTC will halt normal operation. The RTC can be forced to
continue operation during debugging. Refer to DBGCTRL for details.
25.5.8.
Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC),
except the following registers:
•
Interrupt Flag Status and Clear (INTFLAG) register
Write-protection is denoted by the "PAC Write-Protection" property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to the PAC - Peripheral
Access Controller for details.
Related Links
PAC - Peripheral Access Controller on page 48
25.5.9.
Analog Connections
A 32.768kHz crystal can be connected to the XIN32 and XOUT32 pins, along with any required load
capacitors. For details on recommended crystal characteristics and load capacitors.
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25.6.
Functional Description
25.6.1.
Principle of Operation
The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events
at a specified time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format
of the 32-bit counter depends on the RTC operating mode.
The RTC can function in one of these modes:
•
Mode 0 - COUNT32: RTC serves as 32-bit counter
•
Mode 1 - COUNT16: RTC serves as 16-bit counter
•
Mode 2 - CLOCK: RTC serves as clock/calendar with alarm functionality
25.6.2.
Basic Operation
25.6.2.1. Initialization
The following bits are enable-protected, meaning that they can only be written when the RTC is disabled
(CTRLA.ENABLE=0):
•
•
•
•
Operating Mode bits in the Control A register (CTRLA.MODE)
Prescaler bits in the Control A register (CTRLA.PRESCALER)
Clear on Match bit in the Control A register (CTRLA.MATCHCLR)
Clock Representation bit in the Control A register (CTRLA.CLKREP)
The following register is enable-protected
•
Event Control register (EVCTRL)
Enable-protected bits and registers can be changed only when the RTC is disabled (CTRLA.ENABLE=0).
If the RTC is enabled (CTRLA.ENABLE=1), these operations are necessary: first write
CTRLA.ENABLE=0 and check whether the write synchronization has finished, then change the desired
bit field value. Enable-protected bits in can be written at the same time as CTRLA.ENABLE is written to
'1', but not at the same time as CTRLA.ENABLE is written to '0'.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
The RTC prescaler divides the source clock for the RTC counter.
Note: In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter
for correct operation.
The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula:
�CLK_RTC_CNT =
�CLK_RTC_OSC
2PRESCALER
The frequency of the oscillator clock, CLK_RTC_OSC, is given by fCLK_RTC_OSC, and fCLK_RTC_CNT is the
frequency of the internal prescaled RTC clock, CLK_RTC_CNT.
25.6.2.2. Enabling, Disabling, and Resetting
The RTC is enabled by setting the Enable bit in the Control A register (CTRLA.ENABLE=1). The RTC is
disabled by writing CTRLA.ENABLE=0.
The RTC is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). All
registers in the RTC, except DEBUG, will be reset to their initial state, and the RTC will be disabled. The
RTC must be disabled before resetting it.
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25.6.2.3. 32-Bit Counter (Mode 0)
When the RTC Operating Mode bits in the Control A register are zero (CTRLA.MODE=00), the counter
operates in 32-bit Counter mode. The block diagram of this mode is shown in Figure 25-1 RTC Block
Diagram (Mode 0 — 32-Bit Counter). When the RTC is enabled, the counter will increment on every 0to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of
0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow Interrupt flag in the Interrupt Flag
Status and Clear register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit
format.
The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare
match occurs, the Compare 0 Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.CMP0) is set on the next 0-to-1 transition of CLK_RTC_CNT.
If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is '1', the counter is cleared on the
next counter cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic
interrupts or events with longer periods than the prescaler events. Note that when CTRLA.MATCHCLR is
'1', INTFLAG.CMP0 and INTFLAG.OVF will both be set simultaneously on a compare match with
COMP0.
25.6.2.4. 16-Bit Counter (Mode 1)
When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are 1, the counter operates
in 16-bit Counter mode as shown in Figure 25-2 RTC Block Diagram (Mode 1 — 16-Bit Counter). When
the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit
Counter mode, the 16-bit Period register (PER) holds the maximum value of the counter. The counter will
increment until it reaches the PER value, and then wrap to 0x0000. This sets the Overflow Interrupt flag in
the Interrupt Flag Status and Clear register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit
format.
The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0..1). When a
compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.CMPn, n=0..1) is set on the next 0-to-1 transition of CLK_RTC_CNT.
25.6.2.5. Clock/Calendar (Mode 2)
When the RTC Operating Mode bit field in the Control A register (CTRLA.MODE) is '2', the counter
operates in Clock/Calendar mode, as shown in Figure 25-3 RTC Block Diagram (Mode 2 — Clock/
Calendar). When the RTC is enabled, the counter will increment on every 0-to-1 transition of
CLK_RTC_CNT. The selected clock source and RTC prescaler must be configured to provide a 1Hz clock
to the counter for correct operation in this mode.
The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date
format. Time is represented as:
•
•
•
Seconds
Minutes
Hours
Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the
Control A register (CTRLA.CLKREP). This bit can be changed only while the RTC is disabled.
Date is represented as:
•
Day as the numeric day of the month (starting at 1)
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•
•
Month as the numeric month of the year (1 = January, 2 = February, etc.)
Year as a value counting the offset from a reference value that must be defined in software
The date is automatically adjusted for leap years, assuming every year divisible by 4 is a leap year.
Therefore, the reference value must be a leap year, e.g. 2000. The RTC will increment until it reaches the
top value of 23:59:59 December 31 of year 63, and then wrap to 00:00:00 January 1 of year 0. This will
set the Overflow Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.OVF).
The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm
match occurs, the Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers
(INTFLAG.ALARM0) is set on the next 0-to-1 transition of CLK_RTC_CNT.
A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register
(MASK0.SEL). These bits determine which time/date fields of the clock and alarm values are valid for
comparison and which are ignored.
If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is set, the counter is cleared on
the next counter cycle when an alarm match with ALARM0 occurs. This allows the RTC to generate
periodic interrupts or events with longer periods than it would be possible with the prescaler events only
(see Periodic Intervals).
Note: When CTRLA.MATCHCLR is 1, INTFLAG.ALARM0 and INTFLAG.OVF will both be set
simultaneously on an alarm match with ALARM0.
25.6.3.
DMA Operation
Not applicable.
25.6.4.
Interrupts
The RTC has the following interrupt sources:
•
•
•
•
Overflow (OVF): Indicates that the counter has reached its top value and wrapped to zero.
Compare (CMPn): Indicates a match between the counter value and the compare register.
Alarm (ALARM): Indicates a match between the clock value and the alarm register.
Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to Periodic Intervals for
details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually
enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled
by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1).
An interrupt request is generated when the interrupt flag is raised and the corresponding interrupt is
enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is
disabled or the RTC is reset. See the description of the INTFLAG registers for details on how to clear
interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined
interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The user must
read the INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to the Nested
Vector Interrupt Controller for details.
Related Links
Nested Vector Interrupt Controller on page 43
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25.6.5.
Events
The RTC can generate the following output events:
•
•
•
•
Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero.
Compare (CMPn): Indicates a match between the counter value and the compare register.
Alarm (ALARM): Indicates a match between the clock value and the alarm register.
Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to Periodic Intervals for
details.
Setting the Event Output bit in the Event Control Register (EVCTRL.xxxEO=1) enables the corresponding
output event. Writing a zero to this bit disables the corresponding output event. Refer to the EVSYS Event System for details on configuring the event system.
Related Links
EVSYS – Event System on page 487
25.6.6.
Sleep Mode Operation
The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts
can be used to wake up the device from a sleep mode. RTC events can trigger other operations in the
system without exiting the sleep mode.
An interrupt request will be generated after the wake-up if the Interrupt Controller is configured
accordingly. Otherwise the CPU will wake up directly, without triggering any interrupt. In this case, the
CPU will continue executing right from the first instruction that followed the entry into sleep.
25.6.7.
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
•
•
Software Reset bit in Control A register, CTRLA.SWRST
Enable bit in Control A register, CTRLA.ENABLE
The following registers are synchronized when written:
•
•
•
•
•
•
•
Counter Value register, COUNT
Clock Value register, CLOCK
Counter Period register, PER
Compare n Value registers, COMPn
Alarm n Value registers, ALARMn
Frequency Correction register, FREQCORR
Alarm n Mask register, MASKn
The following registers are synchronized when read:
•
•
The Counter Value register, COUNT, if the Counter Read Sync Enable bit in CTRLA
(CTRLA.COUNTSYNC) is '1'
The Clock Value register, CLOCK, if the Clock Read Sync Enable bit in CTRLA
(CTRLA.CLOCKSYNC) is '1'
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
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Required read-synchronization is denoted by the "Read-Synchronized" property in the register
description.
Related Links
Register Synchronization on page 123
25.6.8.
Additional Features
25.6.8.1. Periodic Intervals
The RTC prescaler can generate interrupts and events at periodic intervals, allowing flexible system tick
creation. Any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an interrupt/event.
When one of the eight Periodic Event Output bits in the Event Control register (EVCTRL.PEREO[n=0..7])
is '1', an event is generated on the 0-to-1 transition of the related bit in the prescaler, resulting in a
periodic event frequency of:
�PERIODIC(n) =
�CLK_RTC_OSC
2n+3
fCLK_RTC_OSC is the frequency of the internal prescaler clock CLK_RTC_OSC, and n is the position of the
EVCTRL.PEREOn bit. For example, PER0 will generate an event every eight CLK_RTC_OSC cycles,
PER1 every 16 cycles, etc. This is shown in the figure below.
Periodic events are independent of the prescaler setting used by the RTC counter, except if
CTRLA.PRESCALER is zero. Then, no periodic events will be generated.
Figure 25-4. Example Periodic Events
CLK_RTC_OSC
PER0
PER1
PER2
PER3
25.6.8.2. Frequency Correction
The RTC Frequency Correction module employs periodic counter corrections to compensate for a tooslow or too-fast oscillator. Frequency correction requires that CTRLA.PRESCALER is greater than 1.
The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in
approximately 1ppm steps. Digital correction is achieved by adding or skipping a single count in the
prescaler once every 4096 CLK_RTC_OSC cycles. The Value bit group in the Frequency Correction
register (FREQCORR.VALUE) determines the number of times the adjustment is applied over 240 of
these periods. The resulting correction is as follows:
Correction in ppm =
FREQCORR.VALUE
⋅ 106ppm
4096 ⋅ 240
This results in a resolution of 1.017ppm.
The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the
correction. A positive value will add counts and increase the period (reducing the frequency), and a
negative value will reduce counts per period (speeding up the frequency).
Digital correction also affects the generation of the periodic events from the prescaler. When the
correction is applied at the end of the correction cycle period, the interval between the previous periodic
event and the next occurrence may also be shortened or lengthened depending on the correction value.
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25.7.
Offset
0x00
Register Summary - COUNT32
Name
Bit Pos.
7:0
MATCHCLR
15:8
COUNTSYNC
0x04
7:0
PEREO7
0x05
15:8
OVFEO
0x01
CTRLA
MODE[1:0]
ENABLE
SWRST
PRESCALER[3:0]
0x02
...
Reserved
0x03
0x06
EVCTRL
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
INTENCLR
INTENSET
INTFLAG
DBGCTRL
0x0F
Reserved
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
CMPEO0
23:16
7:0
PER7
15:8
OVF
7:0
PER7
15:8
OVF
7:0
PER7
15:8
OVF
7:0
0x11
15:8
SYNCBUSY
0x13
PER6
PER5
PER4
PER3
PER2
PER1
PER0
CMP0
PER6
PER5
PER4
PER3
PER2
PER1
PER6
PER5
PER4
PER3
PER2
PER1
PER0
CMP0
PER0
CMP0
7:0
0x10
0x14
PEREO5
31:24
0x0E
0x12
PEREO6
DBGRUN
COMP0
COUNT
FREQCORR
ENABLE
SWRST
COUNTSYNC
23:16
31:24
FREQCORR
7:0
SIGN
VALUE[5:0]
0x15
...
Reserved
0x17
0x18
0x19
0x1A
7:0
COUNT
0x1B
COUNT[7:0]
15:8
COUNT[15:8]
23:16
COUNT[23:16]
31:24
COUNT[31:24]
0x1C
...
Reserved
0x1F
0x20
7:0
COMP[7:0]
0x21
15:8
COMP[15:8]
23:16
COMP[23:16]
0x23
31:24
COMP[31:24]
0x24
7:0
COMP[7:0]
0x22
0x25
0x26
COMPn0
COMPn1
0x27
15:8
COMP[15:8]
23:16
COMP[23:16]
31:24
COMP[31:24]
0x28
7:0
COMP[7:0]
0x29
15:8
COMP[15:8]
23:16
COMP[23:16]
31:24
COMP[31:24]
0x2A
0x2B
COMPn2
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Offset
Name
Bit Pos.
0x2C
7:0
COMP[7:0]
0x2D
15:8
COMP[15:8]
23:16
COMP[23:16]
31:24
COMP[31:24]
0x2E
0x2F
25.8.
COMPn3
Register Description - COUNT32
This Register Description section is valid if the RTC is in COUNT32 mode (CTRLA.MODE=0).
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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25.8.1.
Control A in COUNT32 mode (CTRLA.MODE=0)
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
COUNTSYNC
Access
Reset
Bit
R/W
R/W
R/W
R/W
0
0
0
0
0
7
Reset
8
R/W
6
5
4
3
MATCHCLR
Access
9
PRESCALER[3:0]
2
MODE[1:0]
1
0
ENABLE
SWRST
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit 15 – COUNTSYNC: COUNT Read Synchronization Enable
The COUNT register requires synchronization when reading. Disabling the synchronization will prevent
reading valid values from the COUNT register.
This bit is not enable-protected.
Value
Description
0
COUNT read synchronization is disabled
1
COUNT read synchronization is enabled
Bits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter
clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These
bits are not synchronized.
Value
Name
Description
0x0
OFF
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x2
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x3
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x4
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x5
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x6
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x7
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x8
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x9
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0xA
DIV512
CLK_RTC_CNT = GCLK_RTC/512
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Value
Name
Description
0xB
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xC-0xF
-
Reserved
Bit 7 – MATCHCLR: Clear on Match
This bit defines if the counter is cleared or not on a match.
This bit is not synchronized.
Value
Description
0
The counter is not cleared on a Compare/Alarm 0 match
1
The counter is cleared on a Compare/Alarm 0 match
Bits 3:2 – MODE[1:0]: Operating Mode
This bit group defines the operating mode of the RTC.
This bit is not synchronized.
Value
Name
Description
0x0
COUNT32
Mode 0: 32-bit counter
0x1
COUNT16
Mode 1: 16-bit counter
0x2
CLOCK
Mode 2: Clock/calendar
0x3
-
Reserved
Bit 1 – ENABLE: Enable
Due to synchronization there is a delay between writing CTRLA.ENABLE and until the peripheral is
enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in
the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be
cleared when the operation is complete.
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
Bit 0 – SWRST: Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC
will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same
write-operation will be discarded.
Due to synchronization there is a delay between writing CTRLA.SWRST and until the reset is complete.
CTRLA.SWRST will be cleared when the reset is complete.
Value
Description
0
There is not reset operation ongoing
1
The reset operation is ongoing
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25.8.2.
Event Control in COUNT32 mode (CTRLA.MODE=0)
Name: EVCTRL
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
Bit
OVFEO
CMPEO0
R/W
R/W
Reset
0
0
Bit
7
6
5
4
3
2
1
0
PEREO7
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Access
Reset
Bit 15 – OVFEO: Overflow Event Output Enable
Value
Description
0
Overflow event is disabled and will not be generated.
1
Overflow event is enabled and will be generated for every overflow.
Bit 8 – CMPEO0: Compare 0 Event Output Enable
Value
Description
0
Compare 0 event is disabled and will not be generated.
1
Compare 0 event is enabled and will be generated for every compare match.
Bits 7:0 – PEREOn: Periodic Interval n Event Output Enable [n = 7..0]
Value
Description
0
Periodic Interval n event is disabled and will not be generated.
1
Periodic Interval n event is enabled and will be generated.
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25.8.3.
Interrupt Enable Clear in COUNT32 mode (CTRLA.MODE=0)
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
Access
Reset
Bit
Access
Reset
14
13
12
11
10
9
8
OVF
CMP0
R/W
R/W
0
0
7
6
5
4
3
2
1
0
PER7
PER6
PER5
PER4
PER3
PER2
PER1
PER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 15 – OVF: Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 8 – CMP0: Compare 0 Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Compare 0 Interrupt Enable bit, which disables the Compare interrupt.
Value
Description
0
The Compare 0 interrupt is disabled.
1
The Compare 0 interrupt is enabled.
Bits 7:0 – PERn: Periodic Interval n Interrupt Enable [n = 7..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic
Interval n interrupt.
Value
Description
0
Periodic Interval n interrupt is disabled.
1
Periodic Interval n interrupt is enabled.
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25.8.4.
Interrupt Enable Set in COUNT32 mode (CTRLA.MODE=0)
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x0A
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
Access
Reset
Bit
Access
Reset
14
13
12
11
10
9
8
OVF
CMP0
R/W
R/W
0
0
7
6
5
4
3
2
1
0
PER7
PER6
PER5
PER4
PER3
PER2
PER1
PER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 15 – OVF: Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 8 – CMP0: Compare 0 Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Compare 0 Interrupt Enable bit, which enables the Compare 0 interrupt.
Value
Description
0
The Compare 0 interrupt is disabled.
1
The Compare 0 interrupt is enabled.
Bits 7:0 – PERn: Periodic Interval n Interrupt Enable [n = 7..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic
Interval n interrupt.
Value
Description
0
Periodic Interval n interrupt is disabled.
1
Periodic Interval n interrupt is enabled.
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25.8.5.
Interrupt Flag Status and Clear in COUNT32 mode (CTRLA.MODE=0)
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTFLAG
Offset: 0x0C
Reset: 0x0000
Property: Bit
Access
Reset
Bit
Access
Reset
15
14
13
12
11
10
9
8
OVF
CMP0
R/W
R/W
0
0
7
6
5
4
3
2
1
0
PER7
PER6
PER5
PER4
PER3
PER2
PER1
PER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 15 – OVF: Overflow
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt
request will be generated if INTENCLR/SET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
Bit 8 – CMP0: Compare 0
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an
interrupt request will be generated if INTENCLR/SET.COMP0 is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Compare 0 interrupt flag.
Bits 7:0 – PERn: Periodic Interval n [n = 7..0]
This flag is cleared by writing a '1' to the flag.
This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if
INTENCLR/SET.PERx is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Periodic Interval n interrupt flag.
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25.8.6.
Debug Control
Name: DBGCTRL
Offset: 0x0E
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGRUN
Access
R/W
Reset
0
Bit 0 – DBGRUN: Debug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The RTC is halted when the CPU is halted by an external debugger.
1
The RTC continues normal operation when the CPU is halted by an external debugger.
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25.8.7.
Synchronization Busy in COUNT32 mode (CTRLA.MODE=0)
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
COUNTSYNC
Access
R
Reset
0
Bit
7
COMP0
COUNT
FREQCORR
ENABLE
SWRST
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 15 – COUNTSYNC: Count Read Sync Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.COUNTSYNC bit is complete.
1
Write synchronization for CTRLA.COUNTSYNC bit is ongoing.
Bit 5 – COMP0: Compare 0 Synchronization Busy Status
Value
Description
0
Write synchronization for COMP0 register is complete.
1
Write synchronization for COMP0 register is ongoing.
Bit 3 – COUNT: Count Value Synchronization Busy Status
Value
Description
0
Read/write synchronization for COUNT register is complete.
1
Read/write synchronization for COUNT register is ongoing.
Bit 2 – FREQCORR: Frequency Correction Synchronization Busy Status
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Value
Description
0
Read/write synchronization for FREQCORR register is complete.
1
Read/write synchronization for FREQCORR register is ongoing.
Bit 1 – ENABLE: Enable Synchronization Busy Status
Value
Description
0
Read/write synchronization for CTRLA.ENABLE bit is complete.
1
Read/write synchronization for CTRLA.ENABLE bit is ongoing.
Bit 0 – SWRST: Software Reset Synchronization Busy Status
Value
Description
0
Read/write synchronization for CTRLA.SWRST bit is complete.
1
Read/write synchronization for CTRLA.SWRST bit is ongoing.
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25.8.8.
Frequency Correlation
Name: FREQCORR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit
7
6
5
4
3
SIGN
Access
Reset
2
1
0
VALUE[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 7 – SIGN: Correction Sign
Value
Description
0
The correction value is positive, i.e., frequency will be decreased.
1
The correction value is negative, i.e., frequency will be increased.
Bits 5:0 – VALUE[5:0]: Correction Value
These bits define the amount of correction applied to the RTC prescaler.
Value
Description
0
Correction is disabled and the RTC frequency is unchanged.
1 - 127
The RTC frequency is adjusted according to the value.
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25.8.9.
Counter Value in COUNT32 mode (CTRLA.MODE=0)
Name: COUNT
Offset: 0x18
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit
31
30
29
28
27
26
25
24
COUNT[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
COUNT[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COUNT[15:8]
Access
COUNT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – COUNT[31:0]: Counter Value
These bits define the value of the 32-bit RTC counter in mode 0.
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25.8.10. Compare n Value in COUNT32 mode (CTRLA.MODE=0)
Name: COMPn
Offset: 0x20 + n*0x04 [n=0..3]
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
COMP[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
COMP[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COMP[15:8]
Access
COMP[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – COMP[31:0]: Compare Value
The 32-bit value of COMPn is continuously compared with the 32-bit COUNT value. When a match
occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is
set on the next counter cycle, and the counter value is cleared if CTRLA.MATCHCLR is one.
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25.9.
Offset
0x00
0x01
Register Summary - COUNT16
Name
CTRLA
Bit Pos.
7:0
MODE[1:0]
15:8
COUNTSYNC
0x04
7:0
PEREO7
0x05
15:8
OVFEO
ENABLE
SWRST
PRESCALER[3:0]
0x02
...
Reserved
0x03
0x06
EVCTRL
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
INTENCLR
INTENSET
INTFLAG
DBGCTRL
0x0F
Reserved
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
CMPEO1
CMPEO0
23:16
7:0
PER7
15:8
OVF
7:0
PER7
15:8
OVF
7:0
PER7
15:8
OVF
7:0
0x11
15:8
SYNCBUSY
0x13
PER6
PER5
PER4
PER3
PER2
PER6
PER5
PER4
PER3
PER2
PER6
PER5
PER4
PER3
PER2
PER1
PER0
CMP1
CMP0
PER1
PER0
CMP1
CMP0
PER1
PER0
CMP1
CMP0
7:0
0x10
0x14
PEREO5
31:24
0x0E
0x12
PEREO6
DBGRUN
COMP1
COMP0
PER
COUNT
FREQCORR
ENABLE
SWRST
COUNTSYNC
23:16
31:24
FREQCORR
7:0
SIGN
VALUE[5:0]
0x15
...
Reserved
0x17
0x18
0x19
COUNT
7:0
COUNT[7:0]
15:8
COUNT[15:8]
0x1A
...
Reserved
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
COMPn0
COMPn1
COMPn2
COMPn3
COMPn4
COMPn5
7:0
COMP[7:0]
15:8
COMP[15:8]
7:0
COMP[7:0]
15:8
COMP[15:8]
7:0
COMP[7:0]
15:8
COMP[15:8]
7:0
COMP[7:0]
15:8
COMP[15:8]
7:0
COMP[7:0]
15:8
COMP[15:8]
7:0
COMP[7:0]
15:8
COMP[15:8]
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25.10. Register Description - COUNT16
This Register Description section is valid if the RTC is in COUNT16 mode (CTRLA.MODE=1).
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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25.10.1. Control A in COUNT16 mode (CTRLA.MODE=1)
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
COUNTSYNC
Access
9
8
PRESCALER[3:0]
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
MODE[1:0]
Access
Reset
1
0
ENABLE
SWRST
R/W
R/W
R/W
R/W
0
0
0
0
Bit 15 – COUNTSYNC: COUNT Read Synchronization Enable
The COUNT register requires synchronization when reading. Disabling the synchronization will prevent
reading valid values from the COUNT register.
This bit is not enable-protected.
Value
Description
0
COUNT read synchronization is disabled
1
COUNT read synchronization is enabled
Bits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter
clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These
bits are not synchronized.
Value
Name
Description
0x0
OFF
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x2
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x3
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x4
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x5
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x6
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x7
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x8
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x9
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0xA
DIV512
CLK_RTC_CNT = GCLK_RTC/512
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Value
Name
Description
0xB
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xC-0xF
-
Reserved
Bits 3:2 – MODE[1:0]: Operating Mode
This field defines the operating mode of the RTC. This bit is not synchronized.
Value
Name
Description
0x0
COUNT32
Mode 0: 32-bit counter
0x1
COUNT16
Mode 1: 16-bit counter
0x2
CLOCK
Mode 2: Clock/calendar
0x3
-
Reserved
Bit 1 – ENABLE: Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the
Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared
when the operation is complete.
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
Bit 0 – SWRST: Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC
will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same
write-operation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST will be cleared when the reset is complete.
Value
Description
0
There is not reset operation ongoing
1
The reset operation is ongoing
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25.10.2. Event Control in COUNT16 mode (CTRLA.MODE=1)
Name: EVCTRL
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OVFEO
CMPEO1
CMPEO0
R/W
R/W
R/W
Reset
0
0
0
Bit
7
6
5
4
3
2
1
0
PEREO7
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Access
Reset
Bit 15 – OVFEO: Overflow Event Output Enable
Value
Description
0
Overflow event is disabled and will not be generated.
1
Overflow event is enabled and will be generated for every overflow.
Bits 9:8 – CMPEOn: Compare n Event Output Enable [n = 1..0]
Value
Description
0
Compare n event is disabled and will not be generated.
1
Compare n event is enabled and will be generated for every compare match.
Bits 7:0 – PEREOn: Periodic Interval n Event Output Enable [n = 7..0]
Value
Description
0
Periodic Interval n event is disabled and will not be generated. [n = 7..0]
1
Periodic Interval n event is enabled and will be generated. [n = 7..0]
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318
25.10.3. Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1)
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
Access
Reset
Bit
Access
Reset
14
13
12
11
10
9
8
OVF
CMP1
CMP0
R/W
R/W
R/W
0
0
0
7
6
5
4
3
2
1
0
PER7
PER6
PER5
PER4
PER3
PER2
PER1
PER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 15 – OVF: Overflow Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit,
which disables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bits 9:8 – CMPn: Compare n Interrupt Enable [n = 1..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare n Interrupt Enable bit,
which disables the Compare n interrupt.
Value
Description
0
The Compare n interrupt is disabled.
1
The Compare n interrupt is enabled.
Bits 7:0 – PERn: Periodic Interval n Interrupt Enable [n = 7..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt
Enable bit, which disables the Periodic Interval n interrupt.
Value
Description
0
Periodic Interval n interrupt is disabled.
1
Periodic Interval n interrupt is enabled.
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25.10.4. Interrupt Enable Set in COUNT16 mode (CTRLA.MODE=1)
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x0A
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
Access
Reset
Bit
Access
Reset
14
13
12
11
10
9
8
OVF
CMP1
CMP0
R/W
R/W
R/W
0
0
0
7
6
5
4
3
2
1
0
PER7
PER6
PER5
PER4
PER3
PER2
PER1
PER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 15 – OVF: Overflow Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which
enables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bits 9:8 – CMPn: Compare n Interrupt Enable [n = 1..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Compare n Interrupt Enable bit,
which and enables the Compare n interrupt.
Value
Description
0
The Compare n interrupt is disabled.
1
The Compare n interrupt is enabled.
Bits 7:0 – PERn: Periodic Interval n Interrupt Enable [n = 7..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable
bit, which enables the Periodic Interval n interrupt.
Value
Description
0
Periodic Interval n interrupt is disabled.
1
Periodic Interval n interrupt is enabled.
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25.10.5. Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.MODE=1)
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTFLAG
Offset: 0x0C
Reset: 0x0000
Property: Bit
Access
Reset
Bit
Access
Reset
15
14
13
12
11
10
9
8
OVF
CMP1
CMP0
R/W
R/W
R/W
0
0
0
7
6
5
4
3
2
1
0
PER7
PER6
PER5
PER4
PER3
PER2
PER1
PER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 15 – OVF: Overflow
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt
request will be generated if INTENCLR/SET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
Bits 9:8 – CMPn: Compare n [n = 1..0]
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an
interrupt request will be generated if INTENCLR/SET.COMPx is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Compare n interrupt flag.
Bits 7:0 – PERn: Periodic Interval n [n = 7..0]
This flag is cleared by writing a '1' to the flag.
This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if
INTENCLR/SET.PERx is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Periodic Interval n interrupt flag.
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25.10.6. Debug Control
Name: DBGCTRL
Offset: 0x0E
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGRUN
Access
R/W
Reset
0
Bit 0 – DBGRUN: Debug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The RTC is halted when the CPU is halted by an external debugger.
1
The RTC continues normal operation when the CPU is halted by an external debugger.
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25.10.7. Synchronization Busy in COUNT16 mode (CTRLA.MODE=1)
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
COUNTSYNC
Access
R
Reset
0
Bit
7
COMP1
COMP0
PER
COUNT
FREQCORR
ENABLE
SWRST
Access
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
Bit 15 – COUNTSYNC: Count Read Sync Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.COUNTSYNC bit is complete.
1
Write synchronization for CTRLA.COUNTSYNC bit is ongoing.
Bits 6:5 – COMPn: Compare n Synchronization Busy Status [n = 1..0]
Value
Description
0
Write synchronization for COMPn register is complete.
1
Write synchronization for COMPn register is ongoing.
Bit 4 – PER: Period Synchronization Busy Status
Value
Description
0
Write synchronization for PER register is complete.
1
Write synchronization for PER register is ongoing.
Bit 3 – COUNT: Count Value Synchronization Busy Status
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Value
Description
0
Read/write synchronization for COUNT register is complete.
1
Read/write synchronization for COUNT register is ongoing.
Bit 2 – FREQCORR: Frequency Correction Synchronization Busy Status
Value
Description
0
Read/write synchronization for FREQCORR register is complete.
1
Read/write synchronization for FREQCORR register is ongoing.
Bit 1 – ENABLE: Enable Synchronization Busy Status
Value
Description
0
Read/write synchronization for CTRLA.ENABLE bit is complete.
1
Read/write synchronization for CTRLA.ENABLE bit is ongoing.
Bit 0 – SWRST: Software Reset Synchronization Busy Status
Value
Description
0
Read/write synchronization for CTRLA.SWRST bit is complete.
1
Read/write synchronization for CTRLA.SWRST bit is ongoing.
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25.10.8. Frequency Correlation
Name: FREQCORR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit
7
6
5
4
3
SIGN
Access
Reset
2
1
0
VALUE[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 7 – SIGN: Correction Sign
Value
Description
0
The correction value is positive, i.e., frequency will be decreased.
1
The correction value is negative, i.e., frequency will be increased.
Bits 5:0 – VALUE[5:0]: Correction Value
These bits define the amount of correction applied to the RTC prescaler.
Value
Description
0
Correction is disabled and the RTC frequency is unchanged.
1 - 127
The RTC frequency is adjusted according to the value.
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25.10.9. Counter Value in COUNT16 mode (CTRLA.MODE=1)
Name: COUNT
Offset: 0x18
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit
15
14
13
12
11
10
9
8
COUNT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 15:0 – COUNT[15:0]: Counter Value
These bits define the value of the 16-bit RTC counter in COUNT16 mode (CTRLA.MODE=1).
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25.10.10. Counter Period in COUNT16 mode (CTRLA.MODE=1)
Name: PER
Offset: 0x18
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
PER[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PER[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 15:0 – PER[15:0]: Counter Period
These bits define the value of the 16-bit RTC period in COUNT16 mode (CTRLA.MODE=1).
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25.10.11. Compare n Value in COUNT16 mode (CTRLA.MODE=1)
Name: COMPn
Offset: 0x20 + n*0x02 [n=0..5]
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
COMP[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COMP[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 15:0 – COMP[15:0]: Compare Value
The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match
occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is
set on the next counter cycle.
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25.11. Register Summary - CLOCK
Offset
0x00
Name
Bit Pos.
7:0
MATCHCLR
15:8
CLOCKSYNC
0x04
7:0
PEREO7
0x05
15:8
OVFEO
0x01
CTRLA
CLKREP
MODE[1:0]
ENABLE
SWRST
PRESCALER[3:0]
0x02
...
Reserved
0x03
0x06
EVCTRL
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
INTENCLR
INTENSET
INTFLAG
DBGCTRL
0x0F
Reserved
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
ALARMO0
23:16
7:0
PER7
15:8
OVF
7:0
PER7
15:8
OVF
7:0
PER7
15:8
OVF
7:0
0x11
15:8
SYNCBUSY
0x13
PER6
PER5
PER4
PER3
PER2
PER1
PER0
ALARM0
PER6
PER5
PER4
PER3
PER2
PER1
PER6
PER5
PER4
PER3
PER2
PER1
PER0
ALARM0
PER0
ALARM0
7:0
0x10
0x14
PEREO5
31:24
0x0E
0x12
PEREO6
DBGRUN
ALARM0
CLOCKSYNC
COUNT
FREQCORR
ENABLE
SWRST
MASK0
23:16
31:24
FREQCORR
7:0
SIGN
VALUE[5:0]
0x15
...
Reserved
0x17
0x18
0x19
0x1A
7:0
CLOCK
0x1B
MINUTE[1:0]
15:8
23:16
SECOND[5:0]
HOUR[3:0]
MINUTE[5:2]
MONTH[1:0]
DAY[4:0]
31:24
HOUR[4:4]
YEAR[5:0]
MONTH[3:2]
0x1C
...
Reserved
0x1F
0x20
7:0
0x21
15:8
0x22
ALARMn0
23:16
0x23
31:24
0x24
7:0
0x25
0x26
ALARMn1
0x27
7:0
15:8
ALARMn2
23:16
31:24
MINUTE[5:2]
MONTH[1:0]
DAY[4:0]
HOUR[4:4]
YEAR[5:0]
MINUTE[1:0]
MONTH[3:2]
SECOND[5:0]
HOUR[3:0]
MINUTE[5:2]
MONTH[1:0]
DAY[4:0]
31:24
0x28
0x2B
SECOND[5:0]
HOUR[3:0]
15:8
23:16
0x29
0x2A
MINUTE[1:0]
HOUR[4:4]
YEAR[5:0]
MINUTE[1:0]
MONTH[3:2]
SECOND[5:0]
HOUR[3:0]
MINUTE[5:2]
MONTH[1:0]
DAY[4:0]
YEAR[5:0]
HOUR[4:4]
MONTH[3:2]
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Offset
Name
Bit Pos.
0x2C
7:0
0x2D
15:8
0x2E
0x2F
ALARMn3
23:16
MINUTE[1:0]
SECOND[5:0]
HOUR[3:0]
MINUTE[5:2]
MONTH[1:0]
31:24
DAY[4:0]
YEAR[5:0]
HOUR[4:4]
MONTH[3:2]
25.12. Register Description - CLOCK
This Register Description section is valid if the RTC is in Clock/Calendar mode (CTRLA.MODE=2).
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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25.12.1. Control A in Clock/Calendar mode (CTRLA.MODE=2)
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
CLOCKSYNC
Access
Reset
Bit
R/W
R/W
R/W
R/W
0
0
0
0
0
7
6
CLKREP
R/W
R/W
R/W
0
0
0
Reset
8
R/W
MATCHCLR
Access
9
PRESCALER[3:0]
5
4
3
2
1
0
ENABLE
SWRST
R/W
R/W
R/W
0
0
0
MODE[1:0]
Bit 15 – CLOCKSYNC: CLOCK Read Synchronization Enable
The CLOCK register requires synchronization when reading. Disabling the synchronization will prevent
reading valid values from the CLOCK register.
This bit is not enable-protected.
Value
Description
0
CLOCK read synchronization is disabled
1
CLOCK read synchronization is enabled
Bits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter
clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These
bits are not synchronized.
Value
Name
Description
0x0
OFF
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x2
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x3
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x4
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x5
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x6
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x7
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x8
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x9
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0xA
DIV512
CLK_RTC_CNT = GCLK_RTC/512
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Value
Name
Description
0xB
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xC-0xF
-
Reserved
Bit 7 – MATCHCLR: Clear on Match
This bit is valid only in Mode 0 (COUNT32) and Mode 2 (CLOCK). This bit can be written only when the
peripheral is disabled. This bit is not synchronized.
Value
Description
0
The counter is not cleared on a Compare/Alarm 0 match
1
The counter is cleared on a Compare/Alarm 0 match
Bit 6 – CLKREP: Clock Representation
This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value
(CLOCK) register. This bit can be written only when the peripheral is disabled. This bit is not
synchronized.
Value
Description
0
24 Hour
1
12 Hour (AM/PM)
Bits 3:2 – MODE[1:0]: Operating Mode
This field defines the operating mode of the RTC. This bit is not synchronized.
Value
Name
Description
0x0
COUNT32
Mode 0: 32-bit counter
0x1
COUNT16
Mode 1: 16-bit counter
0x2
CLOCK
Mode 2: Clock/calendar
0x3
-
Reserved
Bit 1 – ENABLE: Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the
Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared
when the operation is complete.
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
Bit 0 – SWRST: Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC
will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same
write-operation will be discarded.
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Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST will be cleared when the reset is complete.
Value
Description
0
There is not reset operation ongoing
1
The reset operation is ongoing
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25.12.2. Event Control in Clock/Calendar mode (CTRLA.MODE=2)
Name: EVCTRL
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
Bit
OVFEO
ALARMO0
R/W
R/W
Reset
0
0
Bit
7
6
5
4
3
2
1
0
PEREO7
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Access
Reset
Bit 15 – OVFEO: Overflow Event Output Enable
Value
Description
0
Overflow event is disabled and will not be generated.
1
Overflow event is enabled and will be generated for every overflow.
Bit 8 – ALARMO0: Alarm 0 Event Output Enable
Value
Description
0
Alarm 0 event is disabled and will not be generated.
1
Alarm 0 event is enabled and will be generated for every compare match.
Bits 7:0 – PEREOn: Periodic Interval n Event Output Enable [n = 7..0]
Value
Description
0
Periodic Interval n event is disabled and will not be generated.
1
Periodic Interval n event is enabled and will be generated.
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25.12.3. Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2)
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
Access
Reset
Bit
Access
Reset
14
13
12
11
10
9
8
OVF
ALARM0
R/W
R/W
0
0
7
6
5
4
3
2
1
0
PER7
PER6
PER5
PER4
PER3
PER2
PER1
PER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 15 – OVF: Overflow Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit,
which disables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 8 – ALARM0: Alarm 0 Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Alarm 0 Interrupt Enable bit, which
disables the Alarm interrupt.
Value
Description
0
The Alarm 0 interrupt is disabled.
1
The Alarm 0 interrupt is enabled.
Bits 7:0 – PERn: Periodic Interval n Interrupt Enable [n = 7..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt
Enable bit, which disables the Periodic Interval n interrupt.
Value
Description
0
Periodic Interval n interrupt is disabled.
1
Periodic Interval n interrupt is enabled.
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25.12.4. Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2)
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x0A
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
Access
Reset
Bit
Access
Reset
14
13
12
11
10
9
8
OVF
ALARM0
R/W
R/W
0
0
7
6
5
4
3
2
1
0
PER7
PER6
PER5
PER4
PER3
PER2
PER1
PER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 15 – OVF: Overflow Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which
enables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 8 – ALARM0: Alarm 0 Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Alarm 0 Interrupt Enable bit, which
enables the Alarm 0 interrupt.
Value
Description
0
The Alarm 0 interrupt is disabled.
1
The Alarm 0 interrupt is enabled.
Bits 7:0 – PERn: Periodic Interval n Interrupt Enable [n = 7..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable
bit, which enables the Periodic Interval n interrupt.
Value
Description
0
Periodic Interval n interrupt is disabled.
1
Periodic Interval n interrupt is enabled.
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25.12.5. Interrupt Flag Status and Clear in Clock/Calendar mode (CTRLA.MODE=2)
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTFLAG
Offset: 0x0C
Reset: 0x0000
Property: Bit
Access
Reset
Bit
Access
Reset
15
14
13
12
11
10
9
8
OVF
ALARM0
R/W
R/W
0
0
7
6
5
4
3
2
1
0
PER7
PER6
PER5
PER4
PER3
PER2
PER1
PER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 15 – OVF: Overflow
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt
request will be generated if INTENCLR/SET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
Bit 8 – ALARM0: Alarm 0
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an
interrupt request will be generated if INTENCLR/SET.ALARM0 is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Alarm 0 interrupt flag.
Bits 7:0 – PERn: Periodic Interval n [n = 7..0]
This flag is cleared by writing a '1' to the flag.
This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if
INTENCLR/SET.PERx is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Periodic Interval n interrupt flag.
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25.12.6. Debug Control
Name: DBGCTRL
Offset: 0x0E
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGRUN
Access
R/W
Reset
0
Bit 0 – DBGRUN: Debug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The RTC is halted when the CPU is halted by an external debugger.
1
The RTC continues normal operation when the CPU is halted by an external debugger.
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25.12.7. Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2)
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
CLOCKSYNC
MASK0
Access
R
R
Reset
0
0
Bit
7
6
5
4
ALARM0
COUNT
FREQCORR
ENABLE
SWRST
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 15 – CLOCKSYNC: Clock Read Sync Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.CLOCKSYNC bit is complete.
1
Write synchronization for CTRLA.CLOCKSYNC bit is ongoing.
Bit 11 – MASK0: Mask 0 Synchronization Busy Status
Value
Description
0
Write synchronization for MASK0 register is complete.
1
Write synchronization for MASK0 register is ongoing.
Bit 5 – ALARM0: Alarm 0 Synchronization Busy Status
Value
Description
0
Write synchronization for ALARM0 register is complete.
1
Write synchronization for ALARM0 register is ongoing.
Bit 3 – COUNT: Count Value Synchronization Busy Status
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Value
Description
0
Read/write synchronization for COUNT register is complete.
1
Read/write synchronization for COUNT register is ongoing.
Bit 2 – FREQCORR: Frequency Correction Synchronization Busy Status
Value
Description
0
Read/write synchronization for FREQCORR register is complete.
1
Read/write synchronization for FREQCORR register is ongoing.
Bit 1 – ENABLE: Enable Synchronization Busy Status
Value
Description
0
Read/write synchronization for CTRLA.ENABLE bit is complete.
1
Read/write synchronization for CTRLA.ENABLE bit is ongoing.
Bit 0 – SWRST: Software Reset Synchronization Busy Status
Value
Description
0
Read/write synchronization for CTRLA.SWRST bit is complete.
1
Read/write synchronization for CTRLA.SWRST bit is ongoing.
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25.12.8. Frequency Correlation
Name: FREQCORR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit
7
6
5
4
3
SIGN
Access
Reset
2
1
0
VALUE[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 7 – SIGN: Correction Sign
Value
Description
0
The correction value is positive, i.e., frequency will be decreased.
1
The correction value is negative, i.e., frequency will be increased.
Bits 5:0 – VALUE[5:0]: Correction Value
These bits define the amount of correction applied to the RTC prescaler.
Value
Description
0
Correction is disabled and the RTC frequency is unchanged.
1 - 127
The RTC frequency is adjusted according to the value.
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25.12.9. Clock Value in Clock/Calendar mode (CTRLA.MODE=2)
Name: CLOCK
Offset: 0x18
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit
31
30
29
28
27
26
25
YEAR[5:0]
Access
24
MONTH[3:2]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
MONTH[1:0]
Access
DAY[4:0]
16
HOUR[4:4]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
HOUR[3:0]
Access
MINUTE[5:2]
MINUTE[1:0]
Access
Reset
SECOND[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:26 – YEAR[5:0]: Year
The year offset with respect to the reference year (defined in software).
The year is considered a leap year if YEAR[1:0] is zero.
Bits 25:22 – MONTH[3:0]: Month
1 – January
2 – February
...
12 – December
Bits 21:17 – DAY[4:0]: Day
Day starts at 1 and ends at 28, 29, 30, or 31, depending on the month and year.
Bits 16:12 – HOUR[4:0]: Hour
When CTRLA.CLKREP=0, the Hour bit group is in 24-hour format, with values 0-23. When
CTRLA.CLKREP=1, HOUR[3:0] has values 1-12, and HOUR[4] represents AM (0) or PM (1).
Bits 11:6 – MINUTE[5:0]: Minute
0 – 59
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Bits 5:0 – SECOND[5:0]: Second
0 – 59
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25.12.10. Alarm n Value in Clock/Calendar mode (CTRLA.MODE=2)
The 32-bit value of ALARMn is continuously compared with the 32-bit CLOCK value, based on the
masking set by MASKn.SEL. When a match occurs, the Alarm n interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG.ALARMn) is set on the next counter cycle, and the counter is cleared if
CTRLA.MATCHCLR is '1'.
Name: ALARMn
Offset: 0x20 + n*0x04 [n=0..3]
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized
Bit
31
30
29
28
27
26
25
YEAR[5:0]
Access
24
MONTH[3:2]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
MONTH[1:0]
Access
DAY[4:0]
16
HOUR[4:4]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
HOUR[3:0]
Access
MINUTE[5:2]
MINUTE[1:0]
Access
Reset
SECOND[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:26 – YEAR[5:0]: Year
The alarm year. Years are only matched if MASKn.SEL is 6
Bits 25:22 – MONTH[3:0]: Month
The alarm month. Months are matched only if MASKn.SEL is greater than 4.
Bits 21:17 – DAY[4:0]: Day
The alarm day. Days are matched only if MASKn.SEL is greater than 3.
Bits 16:12 – HOUR[4:0]: Hour
The alarm hour. Hours are matched only if MASKn.SEL is greater than 2.
Bits 11:6 – MINUTE[5:0]: Minute
The alarm minute. Minutes are matched only if MASKn.SEL is greater than 1.
Bits 5:0 – SECOND[5:0]: Second
The alarm second. Seconds are matched only if MASKn.SEL is greater than 0.
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25.12.11. Alarm n Mask in Clock/Calendar mode (CTRLA.MODE=2)
Name: MASKn
Offset: 0x24 + n*0x01 [n=0..3]
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
SEL[2:0]
Access
Reset
R/W
R/W
R/W
0
0
0
Bits 2:0 – SEL[2:0]: Alarm Mask Selection
These bits define which bit groups of Alarm n are valid.
Value
Name
Description
0x0
OFF
Alarm Disabled
0x1
SS
Match seconds only
0x2
MMSS
Match seconds and minutes only
0x3
HHMMSS
Match seconds, minutes, and hours only
0x4
DDHHMMSS
Match seconds, minutes, hours, and days only
0x5
MMDDHHMMSS
Match seconds, minutes, hours, days, and months only
0x6
YYMMDDHHMMSS
Match seconds, minutes, hours, days, months, and years
0x7
-
Reserved
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26.
DMAC – Direct Memory Access Controller
26.1.
Overview
The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a
Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and
peripherals, and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum
CPU intervention, and frees up CPU time. With access to all peripherals, the DMAC can handle automatic
transfer of data between communication modules.
The DMA part of the DMAC has several DMA channels which all can receive different types of transfer
triggers to generate transfer requests from the DMA channels to the arbiter, see also the Block Diagram.
The arbiter will grant one DMA channel at a time to act as the active channel. When an active channel
has been granted, the fetch engine of the DMAC will fetch a transfer descriptor from the SRAM and store
it in the internal memory of the active channel, which will execute the data transmission.
An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel.
The DMAC will write back the updated transfer descriptor from the internal memory of the active channel
to SRAM, and grant the higher prioritized channel to start transfer as the new active channel. Once a
DMA channel is done with its transfer, interrupts and events can be generated optionally.
The DMAC has four bus interfaces:
•
•
•
•
The data transfer bus is used for performing the actual DMA transfer.
The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC.
The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data
transfer can be started or continued.
The write-back bus is used to write the transfer descriptor back to SRAM.
All buses are AHB master interfaces but the AHB/APB Bridge bus, which is an APB slave interface.
The CRC engine can be used by software to detect an accidental error in the transferred data and to take
corrective action, such as requesting the data to be sent again or simply not using the incorrect data.
26.2.
Features
•
•
•
•
Data transfer from:
– Peripheral to peripheral
– Peripheral to memory
– Memory to peripheral
– Memory to memory
Transfer trigger sources
– Software
– Events from Event System
– Dedicated requests from peripherals
SRAM based transfer descriptors
– Single transfer using one descriptor
– Multi-buffer or circular buffer modes by linking multiple descriptors
Up to 6channels
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•
•
•
•
•
•
•
•
26.3.
– Enable 6independent transfers
– Automatic descriptor fetch for each channel
– Suspend/resume operation support for each channel
Flexible arbitration scheme
– 4 configurable priority levels for each channel
– Fixed or round-robin priority scheme within each priority level
From 1 to 256KB data transfer in a single block transfer
Multiple addressing modes
– Static
– Configurable increment scheme
Optional interrupt generation
– On block transfer complete
– On error detection
– On channel suspend
4 event inputs
– One event input for each of the 4 least significant DMA channels
– Can be selected to trigger normal transfers, periodic transfers or conditional transfers
– Can be selected to suspend or resume channel operation
4 event outputs
– One output event for each of the 4 least significant DMA channels
– Selectable generation on AHB, block, or transaction transfer complete
Error management supported by write-back function
– Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer
CRC polynomial software selectable to
– CRC-16 (CRC-CCITT)
®
– CRC-32 (IEEE 802.3)
Block Diagram
Figure 26-1. DMAC Block Diagram
26.4.
Signal Description
Not applicable.
26.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
26.5.1.
I/O Lines
Not applicable.
26.5.2.
Power Management
The DMAC will continue to operate in any sleep mode where the selected source clock is running. The
DMAC’s interrupts can be used to wake up the device from sleep modes. Events connected to the event
system can trigger other operations in the system without exiting sleep modes. On hardware or software
reset, all registers are set to their reset value.
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Related Links
PM – Power Manager on page 177
26.5.3.
Clocks
The DMAC bus clock (CLK_DMAC_APB) must be configured and enabled in the Main Clock module
before using the DMAC.
This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but
can be divided by a prescaler and may run even when the module clock is turned off.
Related Links
Peripheral Clock Masking on page 152
26.5.4.
DMA
Not applicable.
26.5.5.
Interrupts
The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the
interrupt controller to be configured first.
Related Links
Nested Vector Interrupt Controller on page 43
26.5.6.
Events
The events are connected to the event system.
Related Links
EVSYS – Event System on page 487
26.5.7.
Debug Operation
When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to
continue operation during debugging. Refer to DBGCTRL for details.
26.5.8.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except the following registers:
•
•
•
Interrupt Pending register (INTPEND)
Channel ID register (CHID)
Channel Interrupt Flag Status and Clear register (CHINTFLAG)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
26.5.9.
Analog Connections
Not applicable.
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26.6.
Functional Description
26.6.1.
Principle of Operation
The DMAC consists of a DMA module and a CRC module.
26.6.1.1. DMA
The DMAC can transfer data between memories and peripherals without interaction from the CPU. The
data transferred by the DMAC are called transactions, and these transactions can be split into smaller
data transfers. Figure 'DMA Transfer Sizes' shows the relationship between the different transfer sizes:
Figure 26-2. DMA Transfer Sizes
Link Enabled
Beat transfer
Link Enabled
Burst transfer
Link Enabled
Block transfer
DMA transaction
•
•
•
•
Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat
Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE)
Burst transfer: Defined as n beat transfers, where n will differ from one device family to another. A
burst transfer is atomic, cannot be interrupted and the length of the burst is selected by writing the
Burst Length bit group in each Channel n Control A register (CHCTRLA.BURSTLEN).
Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range
from 1 to 64k beats. In contrast to the burst transfer, a block transfer can be interrupted.
Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing
to the second and so forth, as shown in the figure above. A DMA transaction is the complete
transfer of all blocks within a linked list.
A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must
remain in SRAM. For further details on the transfer descriptor refer to Transfer Descriptors.
The figure above shows several block transfers linked together, which are called linked descriptors. For
further information about linked descriptors, refer to Linked Descriptors.
A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can
be configured to be either a software trigger, an event trigger, or one of the dedicated peripheral triggers.
The transfer trigger will result in a DMA transfer request from the specific channel to the arbiter. If there
are several DMA channels with pending transfer requests, the arbiter chooses which channel is granted
access to become the active channel. The DMA channel granted access as the active channel will carry
out the transaction as configured in the transfer descriptor. A current transaction can be interrupted by a
higher prioritized channel after each burst transfer, but will resume the block transfer when the according
DMA channel is granted access as the active channel again.
For each beat transfer, an optional output event can be generated. For each block transfer, optional
interrupts and an optional output event can be generated. When a transaction is completed, dependent of
the configuration, the DMA channel will either be suspended or disabled.
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26.6.1.2. CRC
The internal CRC engine supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and
CRC-32 (IEEE 802.3). It can be used on a selectable DMA channel, or on the I/O interface. Refer to CRC
Operation for details.
26.6.2.
Basic Operation
26.6.2.1. Initialization
The following DMAC registers are enable-protected, meaning that they can only be written when the
DMAC is disabled (CTRL.DMAENABLE=0):
•
•
Descriptor Base Memory Address register (BASEADDR)
Write-Back Memory Base Address register (WRBADDR)
The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and
CRC are disabled (CTRL.DMAENABLE=0 and CTRL.CRCENABLE=0):
•
Software Reset bit in Control register (CTRL.SWRST)
The following DMA channel register is enable-protected, meaning that it can only be written when the
corresponding DMA channel is disabled (CHCTRLA.ENABLE=0):
•
Channel Control B (CHCTRLB) register, except the Command bit (CHCTRLB.CMD) and the
Channel Arbitration Level bit (CHCTRLB.LVL)
The following DMA channel bit is enable-protected, meaning that it can only be written when the
corresponding DMA channel is disabled:
•
Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST)
The following CRC registers are enable-protected, meaning that they can only be written when the CRC
is disabled (CTRL.CRCENABLE=0):
•
•
CRC Control register (CRCCTRL)
CRC Checksum register (CRCCHKSUM)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
Before the DMAC is enabled it must be configured, as outlined by the following steps:
•
•
•
The SRAM address of where the descriptor memory section is located must be written to the
Description Base Address (BASEADDR) register
The SRAM address of where the write-back section should be located must be written to the WriteBack Memory Base Address (WRBADDR) register
Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control
register (CTRL.LVLENx=1)
Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must
be configured, as outlined by the following steps:
•
DMA channel configurations
– The channel number of the DMA channel to configure must be written to the Channel ID
(CHID) register
– Trigger action must be selected by writing the Trigger Action bit group in the Channel Control
B register (CHCTRLB.TRIGACT)
– Trigger source must be selected by writing the Trigger Source bit group in the Channel
Control B register (CHCTRLB.TRIGSRC)
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•
Transfer Descriptor
– The size of each access of the data transfer bus must be selected by writing the Beat Size bit
group in the Block Transfer Control register (BTCTRL.BEATSIZE)
– The transfer descriptor must be made valid by writing a one to the Valid bit in the Block
Transfer Control register (BTCTRL.VALID)
– Number of beats in the block transfer must be selected by writing the Block Transfer Count
(BTCNT) register
– Source address for the block transfer must be selected by writing the Block Transfer Source
Address (SRCADDR) register
–
Destination address for the block transfer must be selected by writing the Block Transfer
Destination Address (DSTADDR) register
If CRC calculation is needed, the CRC engine must be configured before it is enabled, as outlined by the
following steps:
•
•
•
The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control
register (CRCCTRL.CRCSRC)
The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the
CRC Control register (CRCCTRL.CRCPOLY)
If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit
group in the CRC Control register (CRCCTRL.CRCBEATSIZE)
Related Links
BASEADDR on page 391
CHCTRLA on page 394
CHCTRLB on page 395
CRCCHKSUM on page 378
CRCCTRL on page 374
CTRL on page 372
WRBADDR on page 392
BTCTRL on page 404
BTCNT on page 407
DSTADDR on page 409
SRCADDR on page 408
26.6.2.2. Enabling, Disabling, and Resetting
The DMAC is enabled by writing the DMA Enable bit in the Control register (CTRL.DMAENABLE) to '1'.
The DMAC is disabled by writing a '0' to CTRL.DMAENABLE.
A DMA channel is enabled by writing the Enable bit in the Channel Control A register
(CHCTRLA.ENABLE) to '1', after writing the corresponding channel id to the Channel ID bit group in the
Channel ID register (CHID.ID). A DMA channel is disabled by writing a '0' to CHCTRLA.ENABLE.
The CRC is enabled by writing a '1' to the CRC Enable bit in the Control register (CTRL.CRCENABLE).
The CRC is disabled by writing a '0' to CTRL.CRCENABLE.
The DMAC is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST) while
the DMAC and CRC are disabled. All registers in the DMAC except DBGCTRL will be reset to their initial
state.
A DMA channel is reset by writing a '1' to the Software Reset bit in the Channel Control A register
(CHCTRLA.SWRST), after writing the corresponding channel id to the Channel ID bit group in the
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Channel ID register (CHID.ID). The channel registers will be reset to their initial state. The corresponding
DMA channel must be disabled in order for the reset to take effect.
26.6.2.3. Transfer Descriptors
Together with the channel configurations the transfer descriptors decides how a block transfer should be
executed. Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one), and receives a
transfer trigger, its first transfer descriptor has to be initialized and valid (BTCTRL.VALID). The first
transfer descriptor describes the first block transfer of a transaction.
All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section
Base Address (BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tell
the DMAC where to find the descriptor memory section and the write-back memory section.
The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all
DMA channels. As BASEADDR points only to the first transfer descriptor of channel 0 (see figure below),
all first transfer descriptors must be stored in a contiguous memory section, where the transfer descriptors
must be ordered according to their channel number. For further details on linked descriptors, refer to
Linked Descriptors.
The write-back memory section is the section where the DMAC stores the transfer descriptors for the
ongoing block transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing
transfer descriptors will be stored in a contiguous memory section where the transfer descriptors are
ordered according to their channel number. The figure below shows an example of linked descriptors on
DMA channel 0. For further details on linked descriptors, refer to Linked Descriptors.
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Figure 26-3. Memory Sections
0x00000000
DSTADDR
DESCADDR
Channel 0 – Last Descriptor
SRCADDR
BTCNT
BTCTRL
DESCADDR
DSTADDR
DESCADDR
Channel 0 – Descriptor n-1
SRCADDR
BTCNT
BTCTRL
Descriptor Section
Channel n – First Descriptor
DESCADDR
BASEADDR
Channel 2 – First Descriptor
Channel 1 – First Descriptor
Channel 0 – First Descriptor
DSTADDR
SRCADDR
BTCNT
BTCTRL
Write-Back Section
Channel n Ongoing Descriptor
WRBADDR
Channel 2 Ongoing Descriptor
Channel 1 Ongoing Descriptor
Channel 0 Ongoing Descriptor
Device Memory Space
Undefined
Undefined
Undefined
Undefined
Undefined
The size of the descriptor and write-back memory sections is dependent on the number of the most
significant enabled DMA channel m, as shown below:
���� = 128bits ⋅ � + 1
For memory optimization, it is recommended to always use the less significant DMA channels if not all
channels are required.
The descriptor and write-back memory sections can either be two separate memory sections, or they can
share memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is
that the same transaction for a channel can be repeated without having to modify the first transfer
descriptor. The benefit of having descriptor memory and write-back memory in the same section is that it
requires less SRAM. In addition, the latency from fetching the first descriptor of a transaction to the first
burst transfer is executed, is reduced.
26.6.2.4. Arbitration
If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer
request to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the
queue of channels having pending transfers, and the corresponding Pending Channel x bit in the Pending
Channels registers (PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter
will choose which DMA channel will be the next active channel. The active channel is the DMA channel
being granted access to perform its next burst transfer. When the arbiter has granted a DMA channel
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access to the DMAC, the corresponding bit PENDCH.PENDCHx will be cleared. See also the following
figure.
If the upcoming burst transfer is the first for the transfer request, the corresponding Busy Channel x bit in
the Busy Channels register will be set (BUSYCH.BUSYCHx=1), and it will remain '1' for the subsequent
granted burst transfers.
When the channel has performed its granted burst transfer(s) it will be either fed into the queue of
channels with pending transfers, set to be waiting for a new transfer trigger, suspended, or disabled. This
depends on the channel and block transfer configuration. If the DMA channel is fed into the queue of
channels with pending transfers, the corresponding BUSYCH.BUSYCHx will remain '1'. If the DMA
channel is set to wait for a new transfer trigger, suspended, or disabled, the corresponding
BUSYCH.BUSYCHx will be cleared.
If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of
pending channels, but the corresponding PENDCH.PENDCHx will remain set. When the same DMA
channel is resumed, it will be added to the queue of pending channels again.
If a DMA channel gets disabled (CHCTRLA.ENABLE=0) while it has a pending transfer, it will be removed
from the queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared.
Figure 26-4. Arbiter Overview
Arbiter
Channel Pending
Priority
decoder
Channel Suspend
Channel 0
Channel Priority Level
Channel Burst Done
Burst Done
Channel Pending
Transfer Request
Channel Number
Channel Suspend
Active
Channel
Channel N
Channel Priority Level
Channel Burst Done
Level Enable
Active.LVLEXx
PRICTRLx.LVLPRI
CTRL.LVLENx
Priority Levels
When a channel level is pending or the channel is transferring data, the corresponding Level Executing
bit is set in the Active Channel and Levels register (ACTIVE.LVLEXx).
Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by
writing to the Channel Arbitration Level bit group in the Channel Control B register (CHCTRLB.LVL). As
long as all priority levels are enabled, a channel with a higher priority level number will have priority over a
channel with a lower priority level number. Each priority level x is enabled by setting the corresponding
Priority Level x Enable bit in the Control register (CTRL.LVLENx=1).
Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically:
Static Arbitration within a priority level is selected by writing a '0' to the Level x Round-Robin Scheduling
Enable bit in the Priority Control 0 register (PRICTRL0.RRLVLENx).
When static arbitration is selected, the arbiter will prioritize a low channel number over a high channel
number as shown in the figure below. When using the static arbitration there is a risk of high channel
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numbers never being granted access as the active channel. This can be avoided using a dynamic
arbitration scheme.
Figure 26-5. Static Priority Scheduling
Lowest Channel
Channel 0
Highest Priority
.
.
.
Channel x
Channel x+1
.
.
.
Highest Channel
Lowest Priority
Channel N
Dynamic Arbitration within a priority level is selected by writing a '1' to PRICTRL0.RRLVLENx.
The dynamic arbitration scheme in the DMAC is round-robin. With the round-robin scheme, the channel
number of the last channel being granted access will have the lowest priority the next time the arbiter has
to grant access to a channel within the same priority level, as shown in Figure 26-6 Dynamic (RoundRobin) Priority Scheduling. The channel number of the last channel being granted access as the active
channel is stored in the Level x Channel Priority Number bit group in the Priority Control 0 register
(PRICTRL0.LVLPRIx) for the corresponding priority level.
Figure 26-6. Dynamic (Round-Robin) Priority Scheduling
Channel x last acknowledge request
Channel (x+1) last acknowledge request
Channel 0
Channel 0
.
.
.
Channel x
Channel x+1
Lowest Priority
Channel x
Highest Priority
Channel x+1
Lowest Priority
Channel x+2
Highest Priority
.
.
.
Channel N
Channel N
26.6.2.5. Data Transmission
Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its
corresponding transfer descriptor has to be initialized, and the arbiter has to grant the DMA channel
access as the active channel.
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Once the arbiter has granted a DMA channel access as the active channel (refer to Figure 26-1 DMAC
Block Diagram) the transfer descriptor for the DMA channel will be fetched from SRAM using the fetch
bus, and stored in the internal memory for the active channel. For a new block transfer, the transfer
descriptor will be fetched from the descriptor memory section (BASEADDR); For an ongoing block
transfer, the descriptor will be fetched from the write-back memory section (WRBADDR). By using the
data transfer bus, the DMAC will read the data from the current source address and write it to the current
destination address. For further details on how the current source and destination addresses are
calculated, refer to the section on Addressing.
The arbitration procedure is performed after each burst transfer. If the current DMA channel is granted
access again, the block transfer counter (BTCNT) of the internal transfer descriptor will be decremented
by the number of beats in a burst, the optional output event Beat will be generated if configured and
enabled, and the active channel will perform a new burst transfer. If a different DMA channel than the
current active channel is granted access, the block transfer counter value will be written to the write-back
section before the transfer descriptor of the newly granted DMA channel is fetched into the internal
memory of the active channel.
When a block transfer has come to its end (BTCNT is zero), the Valid bit in the Block Transfer Control
register will be cleared (BTCTRL.VALID=0) before the entire transfer descriptor is written to the write-back
memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the optional
output event Block, will be generated if configured and enabled. After the last block transfer in a
transaction, the Next Descriptor Address register (DESCADDR) will hold the value 0x00000000, and the
DMA channel will either be suspended or disabled, depending on the configuration in the Block Action bit
group in the Block Transfer Control register (BTCTRL.BLOCKACT). If the transaction has further block
transfers pending, DESCADDR will hold the SRAM address to the next transfer descriptor to be fetched.
The DMAC will fetch the next descriptor into the internal memory of the active channel and write its
content to the write-back section for the channel, before the arbiter gets to choose the next active
channel.
26.6.2.6. Transfer Triggers and Actions
A DMA transfer through a DMA channel can be started only when a DMA transfer request is detected,
and the DMA channel has been granted access to the DMA. A transfer request can be triggered from
software, from a peripheral, or from an event. There are dedicated Trigger Source selections for each
DMA Channel Control B (CHCTRLB.TRIGSRC).
The trigger actions are available in the Trigger Action bit group in the Channel Control B register
(CHCTRLB.TRIGACT). By default, a trigger generates a request for a block transfer operation. If a single
descriptor is defined for a channel, the channel is automatically disabled when a block transfer has been
completed. If a list of linked descriptors is defined for a channel, the channel is automatically disabled
when the last descriptor in the list is executed. If the list still has descriptors to execute, the channel will
be waiting for the next block transfer trigger. When enabled again, the channel will wait for the next block
transfer trigger. The trigger actions can also be configured to generate a request for a beat transfer
(CHCTRLB.TRIGACT=0x2) or transaction transfer (CHCTRLB.TRIGACT=0x3) instead of a block transfer
(CHCTRLB.TRIGACT=0x0).
Figure 26-7 Trigger Action and Transfers shows an example where triggers are used with two linked
block descriptors.
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Figure 26-7. Trigger Action and Transfers
Beat Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
Block Transfer
Data Transfer
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
Block Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
Block Transfer
Data Transfer
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
Transaction Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
Block Transfer
Data Transfer
BEAT
BEAT
If the trigger source generates a transfer request for a channel during an ongoing transfer, the new
transfer request will be kept pending (CHSTATUS.PEND=1), and the new transfer can start after the
ongoing one is done. Only one pending transfer can be kept per channel. If the trigger source generates
more transfer requests while one is already pending, the additional ones will be lost. All channels pending
status flags are also available in the Pending Channels register (PENDCH).
When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register
(CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All
channel busy status flags are also available in the Busy Channels register (BUSYCH) in DMAC.
26.6.2.7. Addressing
Each block transfer needs to have both a source address and a destination address defined. The source
address is set by writing the Transfer Source Address (SRCADDR) register, the destination address is set
by writing the Transfer Destination Address (SRCADDR) register.
The addressing of this DMAC module can be static or incremental, for either source or destination of a
block transfer, or both.
Incrementation for the source address of a block transfer is enabled by writing the Source Address
Incrementation Enable bit in the Block Transfer Control register (BTCTRL.SRCINC=1). The step size of
the incrementation is configurable and can be chosen by writing the Step Selection bit in the Block
Transfer Control register (BTCTRL.STEPSEL=1) and writing the desired step size in the Address
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Increment Step Size bit group in the Block Transfer Control register (BTCTRL.STEPSIZE). If
BTCTRL.STEPSEL=0, the step size for the source incrementation will be the size of one beat.
When source address incrementation is configured (BTCTRL.SRCINC=1), SRCADDR is calculated as
follows:
If BTCTRL.STEPSEL=1:
SRCADDR = SRCADDR����� + ����� ⋅ �������� + 1 ⋅ 2STEPSIZE
If BTCTRL.STEPSEL=0:
SRCADDR = SRCADDR����� + ����� ⋅ �������� + 1
•
•
•
•
SRCADDRSTART is the source address of the first beat transfer in the block transfer
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation
The following figure shows an example where DMA channel 0 is configured to increment the source
address by one beat after each beat transfer (BTCTRL.SRCINC=1), and DMA channel 1 is configured to
increment the source address by two beats (BTCTRL.SRCINC=1, BTCTRL.STEPSEL=1, and
BTCTRL.STEPSIZE=0x1). As the destination address for both channels are peripherals, destination
incrementation is disabled (BTCTRL.DSTINC=0).
Figure 26-8. Source Address Increment
SRC Data Buffer
a
b
c
d
e
f
Incrementation for the destination address of a block transfer is enabled by setting the Destination
Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC=1). The step
size of the incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing
BTCTRL.STEPSIZE to the desired step size. If BTCTRL.STEPSEL=1, the step size for the destination
incrementation will be the size of one beat.
When the destination address incrementation is configured (BTCTRL.DSTINC=1), SRCADDR must be
set and calculated as follows:
������� = ������������ + �����
where BTCTRL.STEPSEL is zero
������� = ������������ + ����� • �������� + 1
where BTCTRL.STEPSEL is one
• �������� + 1 • 2��������
•
DSTADDRSTART is the destination address of the first beat transfer in the block transfer
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•
•
•
BTCNT is the initial number of beats remaining in the block transfer
BEATSIZE is the configured number of bytes in a beat
STEPSIZE is the configured number of beats for each incrementation
Figure 26-9 Destination Address Incrementshows an example where DMA channel 0 is configured to
increment destination address by one beat (BTCTRL.DSTINC=1) and DMA channel 1 is configured to
increment destination address by two beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and
BTCTRL.STEPSIZE=0x1). As the source address for both channels are peripherals, source
incrementation is disabled (BTCTRL.SRCINC=0).
Figure 26-9. Destination Address Increment
DST Data Buffer
a
b
c
d
26.6.2.8. Error Handling
If a bus error is received from an AHB slave during a DMA data transfer, the corresponding active
channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt
Status and Clear register (CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is
generated. The transfer counter will not be decremented and its current value is written-back in the writeback memory section before the channel is disabled.
When the DMAC fetches an invalid descriptor (BTCTRL.VALID=0) or when the channel is resumed and
the DMA fetches the next descriptor with null address (DESCADDR=0x00000000), the corresponding
channel operation is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status
and Clear register (CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status
register (CHSTATUS.FERR) is set. If enabled, the optional suspend interrupt is generated.
26.6.3.
Additional Features
26.6.3.1. Linked Descriptors
A transaction can consist of either a single block transfer or of several block transfers. When a transaction
consist of several block transfers it is called linked descriptors.
Figure Figure 26-3 Memory Sections illustrates how linked descriptors work. When the first block transfer
is completed on DMA channel 0, the DMAC fetches the next transfer descriptor which is pointed to by the
value stored in the Next Descriptor Address (DESCADDR) register of the first transfer descriptor.
Fetching the next transfer descriptor (DESCADDR) is continued until the last transfer descriptor. When
the block transfer for the last transfer descriptor is executed and DESCADDR=0x00000000, the
transaction is terminated. For further details on how the next descriptor is fetched from SRAM, refer to
section Data Transmission.
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Adding Descriptor to the End of a List
To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with
DESCADDR=0x00000000 indicating that it is the new last descriptor in the list, and modify the
DESCADDR value of the current last descriptor to the address of the newly created descriptor.
Modifying a Descriptor in a List
In order to add descriptors to a linked list, the following actions must be performed:
1.
2.
3.
4.
5.
6.
7.
Enable the Suspend interrupt for the DMA channel.
Enable the DMA channel.
Reserve memory space in SRAM to configure a new descriptor.
Configure the new descriptor:
– Set the next descriptor address (DESCADDR)
– Set the destination address (DSTADDR)
– Set the source address (SRCADDR)
– Configure the block transfer control (BTCTRL) including
• Optionally enable the Suspend block action
• Set the descriptor VALID bit
Clear the VALID bit for the existing list and for the descriptor which has to be updated.
Read DESCADDR from the Write-Back memory.
– If the DMA has not already fetched the descriptor which requires changes (i.e., DESCADDR
is wrong):
• Update the DESCADDR location of the descriptor from the List
• Optionally clear the Suspend block action
• Set the descriptor VALID bit to '1'
• Optionally enable the Resume software command
– If the DMA is executing the same descriptor as the one which requires changes:
• Set the Channel Suspend software command and wait for the Suspend interrupt
• Update the next descriptor address (DESCRADDR) in the write-back memory
• Clear the interrupt sources and set the Resume software command
• Update the DESCADDR location of the descriptor from the List
• Optionally clear the Suspend block action
• Set the descriptor VALID bit to '1'
Go to step 4 if needed.
Adding a Descriptor Between Existing Descriptors
To insert a new descriptor 'C' between two existing descriptors ('A' and 'B'), the descriptor currently
executed by the DMA must be identified.
1.
2.
3.
If DMA is executing descriptor B, descriptor C cannot be inserted.
If DMA has not started to execute descriptor A, follow the steps:
2.1.
Set the descriptor A VALID bit to '0'.
2.2.
Set the DESCADDR value of descriptor A to point to descriptor C instead of descriptor B.
2.3.
Set the DESCADDR value of descriptor C to point to descriptor B.
2.4.
Set the descriptor A VALID bit to '1'.
If DMA is executing descriptor A:
3.1.
Apply the software suspend command to the channel and
3.2.
Perform steps 2.1 through 2.4.
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3.3.
Apply the software resume command to the channel.
26.6.3.2. Channel Suspend
The channel operation can be suspended at any time by software by writing a '1' to the Suspend
command in the Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing
burst transfer is completed, the channel operation is suspended and the suspend command is
automatically cleared.
When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register
is set (CHINTFLAG.SUSP=1) and the optional suspend interrupt is generated.
By configuring the block action to suspend by writing Block Action bit group in the Block Transfer Control
register (BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed
a block transfer. The DMA channel will be kept enabled and will be able to receive transfer triggers, but it
will be removed from the arbitration scheme.
If an invalid transfer descriptor (BTCTRL.VALID=0) is fetched from SRAM, the DMA channel will be
suspended, and the Channel Fetch Error bit in the Channel Status register(CHASTATUS.FERR) will be
set.
Note: Only enabled DMA channels can be suspended. If a channel is disabled when it is attempted to
be suspended, the internal suspend command will be ignored.
For more details on transfer descriptors, refer to section Transfer Descriptors.
Related Links
CHCTRLB on page 395
CHINTFLAG on page 401
BTCTRL on page 404
26.6.3.3. Channel Resume and Next Suspend Skip
A channel operation can be resumed by software by setting the Resume command in the Command bit
field of the Channel Control B register (CHCTRLB.CMD). If the channel is already suspended, the
channel operation resumes from where it previously stopped when the Resume command is detected.
When the Resume command is issued before the channel is suspended, the next suspend action is
skipped and the channel continues the normal operation.
Figure 26-10. Channel Suspend/Resume Operation
CHENn
Memory Descriptor
Fetch
Transfer
Descriptor 2
(suspend enabled)
Descriptor 1
(suspend enabled)
Descriptor 0
(suspend disabled)
Block
Transfer 0
Block
Transfer 1
Channel
suspended
Block
Transfer 2
Descriptor 3
(last)
Block
Transfer 3
Resume Command
Suspend skipped
Related Links
CHCTRLB on page 395
26.6.3.4. Event Input Actions
The event input actions are available only on the least significant DMA channels. For details on channels
with event input support, refer to the in the Event system documentation.
Before using event input actions, the event controller must be configured first according to the following
table, and the Channel Event Input Enable bit in the Channel Control B register (CHCTRLB.EVIE) must
be written to '1'. Refer also to Events.
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Table 26-1. Event Input Action
Action
CHCTRLB.EVACT
CHCTRLB.TRGSRC
None
NOACT
-
Normal Transfer
TRIG
DISABLE
Conditional Transfer on Strobe
TRIG
any peripheral
Conditional Transfer
CTRIG
Conditional Block Transfer
CBLOCK
Channel Suspend
SUSPEND
Channel Resume
RESUME
Skip Next Block Suspend
SSKIP
Normal Transfer
The event input is used to trigger a beat or burst transfer on peripherals.
The event is acknowledged as soon as the event is received. When received, both the Channel Pending
status bit in the Channel Status register (CHSTATUS.PEND) and the corresponding Channel n bit in the
Pending Channels register (PENDCH.PENDCHn) are set. If the event is received while the channel is
pending, the event trigger is lost.
The figure below shows an example where beat transfers are enabled by internal events.
Figure 26-11. Beat Event Trigger Action
CHENn
Peripheral Trigger
Trigger Lost
Event
PENDCHn
BUSYCHn
Block Transfer
Data Transfer
BEAT
Block Transfer
BEAT
BEAT
BEAT
BEAT
BEAT
Conditional Transfer on Strobe
The event input is used to trigger a transfer on peripherals with pending transfer requests. This event
action is intended to be used with peripheral triggers, e.g. for timed communication protocols or periodic
transfers between peripherals: only when the peripheral trigger coincides with the occurrence of a
(possibly cyclic) event the transfer is issued.
The event is acknowledged as soon as the event is received. The peripheral trigger request is stored
internally when the previous trigger action is completed (i.e. the channel is not pending) and when an
active event is received. If the peripheral trigger is active, the DMA will wait for an event before the
peripheral trigger is internally registered. When both event and peripheral transfer trigger are active, both
CHSTATUS.PEND and PENDCH.PENDCHn are set. A software trigger will now trigger a transfer.
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The figure below shows an example where the peripheral beat transfer is started by a conditional strobe
event action.
Figure 26-12. Periodic Event with Beat Peripheral Triggers
Trigger Lost
Trigger Lost
Event
Peripheral Trigger
PENDCHn
Block Transfer
Data Transfer
BEAT
Conditional Transfer
The event input is used to trigger a conditional transfer on peripherals with pending transfer requests. As
example, this type of event can be used for peripheral-to-peripheral transfers, where one peripheral is the
source of event and the second peripheral is the source of the trigger.
Each peripheral trigger is stored internally when the event is received. When the peripheral trigger is
stored internally, the Channel Pending status bit is set (CHSTATUS.PEND), the respective Pending
Channel n Bit in the Pending Channels register is set (PENDCH.PENDCHn), and the event is
acknowledged. A software trigger will now trigger a transfer.
The figure below shows an example where conditional event is enabled with peripheral beat trigger
requests.
Figure 26-13. Conditional Event with Beat Peripheral Triggers
Event
Peripheral Trigger
PENDCHn
Data Transfer
Block Transfer
BEAT
BEAT
Conditional Block Transfer
The event input is used to trigger a conditional block transfer on peripherals.
Before starting transfers within a block, an event must be received. When received, the event is
acknowledged when the block transfer is completed. A software trigger will trigger a transfer.
The figure below shows an example where conditional event block transfer is started with peripheral beat
trigger requests.
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Figure 26-14. Conditional Block Transfer with Beat Peripheral Triggers
Event
Peripheral Trigger
PENDCHn
Block Transfer
Data Transfer
Block Transfer
BEAT
BEAT
BEAT
BEAT
Channel Suspend
The event input is used to suspend an ongoing channel operation. The event is acknowledged when the
current AHB access is completed. For further details on Channel Suspend, refer to Channel Suspend.
Channel Resume
The event input is used to resume a suspended channel operation. The event is acknowledged as soon
as the event is received and the Channel Suspend Interrupt Flag (CHINTFLAG.SUSP) is cleared. For
further details refer to Channel Suspend.
Skip Next Block Suspend
This event can be used to skip the next block suspend action. If the channel is suspended before the
event rises, the channel operation is resumed and the event is acknowledged. If the event rises before a
suspend block action is detected, the event is kept until the next block suspend detection. When the block
transfer is completed, the channel continues the operation (not suspended) and the event is
acknowledged.
26.6.3.5. Event Output Selection
Event output selection is available only for the least significant DMA channels. The pulse width of an
event output from a channel is one AHB clock cycle.
The output of channel events is enabled by writing a '1' to the Channel Event Output Enable bit in the
Control B register (CHCTRLB.EVOE). The event output cause is selected by writing to the Event Output
Selection bits in the Block Transfer Control register (BTCTRL.EVOSEL). It is possible to generate events
after each block transfer (BTCTRL.EVOSEL=0x1) or beat transfer (BTCTRL.EVOSEL=0x3). To enable an
event being generated when a transaction is complete, the block event selection must be set in the last
transfer descriptor only.
The figure Figure 26-15 Event Output Generation shows an example where the event output generation
is enabled in the first block transfer, and disabled in the second block.
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Figure 26-15. Event Output Generation
Beat Event Output
Block Transfer
Data Transfer
Block Transfer
BEAT
BEAT
BEAT
BEAT
Event Output
Block Event Output
Block Transfer
Data Transfer
BEAT
Block Transfer
BEAT
BEAT
BEAT
Event Output
Related Links
CHCTRLB on page 395
BTCTRL on page 404
26.6.3.6. Aborting Transfers
Transfers on any channel can be aborted gracefully by software by disabling the corresponding DMA
channel. It is also possible to abort all ongoing or pending transfers by disabling the DMAC.
When a DMA channel disable request or DMAC disable request is detected:
•
•
Ongoing transfers of the active channel will be disabled when the ongoing beat transfer is
completed and the write-back memory section is updated. This prevents transfer corruption before
the channel is disabled.
All other enabled channels will be disabled in the next clock cycle.
The corresponding Channel Enable bit in the Channel Control A register is cleared
(CHCTRLA.ENABLE=0) when the channel is disabled.
The corresponding DMAC Enable bit in the Control register is cleared (CTRL.DMAENABLE=0) when the
entire DMAC module is disabled.
26.6.3.7. CRC Operation
A cyclic redundancy check (CRC) is an error detection technique used to find errors in data. It is
commonly used to determine whether the data during a transmission, or data present in data and
program memories has been corrupted or not. A CRC takes a data stream or a block of data as input and
generates a 16- or 32-bit output that can be appended to the data and used as a checksum.
When the data is received, the device or application repeats the calculation: If the new CRC result does
not match the one calculated earlier, the block contains a data error. The application will then detect this
and may take a corrective action, such as requesting the data to be sent again or simply not using the
incorrect data.
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The CRC engine in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and
CRC-32 (IEEE 802.3). Typically, applying CRC-n (CRC-16 or CRC-32) to a data block of arbitrary length
will detect any single alteration that is ≤n bits in length, and will detect the fraction 1-2-n of all longer error
bursts.
•
•
CRC-16:
– Polynomial: x16+ x12+ x5+ 1
– Hex value: 0x1021
CRC-32:
– Polynomial: x32+x26+ x23+ x22+x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x + 1
–
Hex value: 0x04C11DB7
The data source for the CRC engine can either be one of the DMA channels or the APB bus interface,
and must be selected by writing to the CRC Input Source bits in the CRC Control register
(CRCCTRL.CRCSRC). The CRC engine then takes data input from the selected source and generates a
checksum based on these data. The checksum is available in the CRC Checksum register
(CRCCHKSUM). When CRC-32 polynomial is used, the final checksum read is bit reversed and
complemented, as shown in Figure 26-16 CRC Generator Block Diagram.
The CRC polynomial is selected by writing to the CRC Polynomial Type bit in the CRC Control register
(CRCCTRL.CRCPOLY), the default is CRC-16. The CRC engine operates on byte only. When the DMA is
used as data source for the CRC engine, the DMA channel beat size setting will be used. When used with
APB bus interface, the application must select the CRC Beat Size bit field of CRC Control register
(CRCCTRL.CRCBEATSIZE). 8-, 16-, or 32-bit bus transfer access type is supported. The corresponding
number of bytes will be written in the CRCDATAIN register and the CRC engine will operate on the input
data in a byte by byte manner.
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Figure 26-16. CRC Generator Block Diagram
DMAC
Channels
CRCDATAIN
CRCCTRL
8
16
8
CRC-16
32
CRC-32
crc32
CHECKSUM
bit-reverse +
complement
Checksum
read
CRC on CRC-16 or CRC-32 calculations can be performed on data passing through any DMA
DMA
channel. Once a DMA channel is selected as the source, the CRC engine will continuously
data
generate the CRC on the data passing through the DMA channel. The checksum is available
for readout once the DMA transaction is completed or aborted. A CRC can also be generated
on SRAM, Flash, or I/O memory by passing these data through a DMA channel. If the latter is
done, the destination register for the DMA data can be the data input (CRCDATAIN) register in
the CRC engine.
CRC using the I/O Before using the CRC engine with the I/O interface, the application must set the
interface
CRC Beat Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE).
8/16/32-bit bus transfer type can be selected.
CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the
data to the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the
register by the CPU, and CRC is done continuously for each byte. This means if a 32-bit data is written to
the CRCDATAIN register the CRC engine takes four cycles to calculate the CRC. The CRC complete is
signaled by a set CRCBUSY bit in the CRCSTATUS register. New data can be written only when
CRCBUSY flag is not set.
26.6.4.
DMA Operation
Not applicable.
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26.6.5.
Interrupts
The DMAC channels have the following interrupt sources:
•
•
•
Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding
channel. Refer to Data Transmission for details.
Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an
invalid descriptor has been fetched. Refer to Error Handling for details.
Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to
Channel Suspend and Data Transmission for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt
Flag Status and Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt
can be individually enabled by setting the corresponding bit in the Channel Interrupt Enable Set register
(CHINTENSET=1), and disabled by setting the corresponding bit in the Channel Interrupt Enable Clear
register (CHINTENCLR=1).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the DMAC
is reset or the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear interrupt
flags. All interrupt requests are ORed together on system level to generate one combined interrupt
request to the NVIC.
The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with
pending interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to
determine which interrupt condition is present for the corresponding channel. It is also possible to read
the Interrupt Pending register (INTPEND), which provides the lowest channel number with pending
interrupt and the respective interrupt flags.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
Related Links
Nested Vector Interrupt Controller on page 43
26.6.6.
Events
The DMAC can generate the following output events:
•
Channel (CH): Generated when a block transfer for a given channel has been completed, or when
a beat transfer within a block transfer for a given channel has been completed. Refer to Event
Output Selection for details.
Setting the Channel Control B Event Output Enable bit (CHCTRLB.EVOE=1) enables the corresponding
output event configured in the Event Output Selection bit group in the Block Transfer Control register
(BTCTRL.EVOSEL). Clearing CHCTRLB.EVOE=0 disables the corresponding output event.
The DMAC can take the following actions on an input event:
•
•
•
•
•
•
Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals
are enabled
Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled
Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are
enabled
Channel Suspend Operation (SUSPEND): suspend a channel operation
Channel Resume Operation (RESUME): resume a suspended channel operation
Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition
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Setting the Channel Control B Event Input Enable bit (CHCTRLB.EVIE=1) enables the corresponding
action on input event. clearing this bit disables the corresponding action on input event. Note that several
actions can be enabled for incoming events. If several events are connected to the peripheral, any
enabled action will be taken for any of the incoming events. For further details on event input actions,
refer to Event Input Actions.
Related Links
EVSYS – Event System on page 487
CHCTRLB on page 395
BTCTRL on page 404
26.6.7.
Sleep Mode Operation
Each DMA channel can be configured to operate in any sleep mode. To be able to run in standby, the
RUNSTDBY bit in Channel Control A register (CHCTRLA.RUNSTDBY) must be written to '1'. The DMAC
can wake up the device using interrupts from any sleep mode or perform actions through the Event
System.
Note: In standby sleep mode, the DMAC can only access RAM when it is not back biased
(PM.STDBYCFG.BBIASxx=0x0)
26.6.8.
Synchronization
Not applicable.
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26.7.
Offset
0x00
0x01
0x02
0x03
Register Summary
Name
CTRL
CRCCTRL
0x04
0x05
0x06
CRCDATAIN
Bit Pos.
7:0
CRCENABLE DMAENABLE
15:8
LVLEN3
7:0
15:8
CRCDATAIN[7:0]
15:8
CRCDATAIN[15:8]
23:16
CRCDATAIN[23:16]
31:24
CRCDATAIN[31:24]
0x08
7:0
CRCCHKSUM[7:0]
0x09
CRCCHKSUM
0x0B
15:8
CRCCHKSUM[15:8]
23:16
CRCCHKSUM[23:16]
31:24
CRCCHKSUM[31:24]
0x0C
CRCSTATUS
7:0
0x0D
DBGCTRL
7:0
0x0E
QOSCTRL
7:0
0x0F
Reserved
0x10
0x11
0x12
0x13
CRCBUSY
DBGRUN
DQOS[1:0]
SWTRIG5
SWTRIG4
FQOS[1:0]
SWTRIG3
WRBQOS[1:0]
SWTRIG2
SWTRIG1
SWTRIG0
15:8
23:16
31:24
0x14
7:0
RRLVLEN0
LVLPRI0[3:0]
0x15
15:8
RRLVLEN1
LVLPRI1[3:0]
23:16
RRLVLEN2
LVLPRI2[3:0]
31:24
RRLVLEN3
LVLPRI3[3:0]
0x16
LVLEN0
CRCBEATSIZE[1:0]
CRCZERO
7:0
SWTRIGCTRL
LVLEN1
CRCSRC[5:0]
7:0
0x07
0x0A
LVLEN2
CRCPOLY[1:0]
SWRST
PRICTRL0
0x17
0x18
...
Reserved
0x1F
0x20
0x21
INTPEND
7:0
15:8
ID[3:0]
PEND
BUSY
FERR
SUSP
TCMPL
TERR
0x22
...
Reserved
0x23
0x24
7:0
0x25
15:8
0x26
INTSTATUS
31:24
0x28
7:0
0x29
BUSYCH
0x2B
CHINT2
CHINT1
CHINT0
BUSYCH5
BUSYCH4
BUSYCH3
BUSYCH2
BUSYCH1
BUSYCH0
PENDCH5
PENDCH4
PENDCH3
PENDCH2
PENDCH1
PENDCH0
15:8
31:24
7:0
0x2D
15:8
0x2F
CHINT3
23:16
0x2C
0x2E
CHINT4
23:16
0x27
0x2A
CHINT5
PENDCH
23:16
31:24
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Offset
Name
Bit Pos.
0x30
7:0
0x31
15:8
0x32
ACTIVE
LVLEX3
ABUSY
23:16
31:24
BTCNT[15:8]
7:0
BASEADDR[7:0]
BASEADDR
0x37
15:8
BASEADDR[15:8]
23:16
BASEADDR[23:16]
31:24
BASEADDR[31:24]
0x38
7:0
WRBADDR[7:0]
0x39
15:8
WRBADDR[15:8]
23:16
WRBADDR[23:16]
31:24
WRBADDR[31:24]
0x3A
WRBADDR
0x3B
LVLEX0
ENABLE
SWRST
BTCNT[7:0]
0x33
0x35
LVLEX1
ID[4:0]
0x34
0x36
LVLEX2
0x3C
...
Reserved
0x3E
0x3F
CHID
7:0
0x40
CHCTRLA
7:0
ID[3:0]
0x41
...
Reserved
0x43
0x44
7:0
0x45
15:8
0x46
CHCTRLB
0x47
23:16
LVL[1:0]
EVOE
EVIE
EVACT[2:0]
TRIGSRC[5:0]
TRIGACT[1:0]
31:24
CMD[1:0]
0x48
...
Reserved
0x4B
0x4C
CHINTENCLR
7:0
SUSP
TCMPL
TERR
0x4D
CHINTENSET
7:0
SUSP
TCMPL
TERR
0x4E
CHINTFLAG
7:0
SUSP
TCMPL
TERR
0x4F
CHSTATUS
7:0
FERR
BUSY
PEND
26.8.
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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26.8.1.
Control
Name: CTRL
Offset: 0x00
Reset: 0x00X0
Property: PAC Write-Protection, Enable-Protected
Bit
15
14
13
12
Access
Reset
Bit
7
6
5
4
11
10
9
8
LVLEN3
LVLEN2
LVLEN1
LVLEN0
R/W
R/W
R/W
R/W
0
0
0
0
3
Access
Reset
2
1
0
CRCENABLE
DMAENABLE
SWRST
R/W
R/W
R/W
0
0
0
Bit 2 – CRCENABLE: CRC Enable
Writing a '0' to this bit will disable the CRC calculation when the CRC Status Busy flag is cleared
(CRCSTATUS. CRCBUSY). The bit is zero when the CRC is disabled.
Writing a '1' to this bit will enable the CRC calculation.
Value
Description
0
The CRC calculation is disabled.
1
The CRC calculation is enabled.
Bit 1 – DMAENABLE: DMA Enable
Setting this bit will enable the DMA module.
Writing a '0' to this bit will disable the DMA module. When writing a '0' during an ongoing transfer, the bit
will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The
internal data transfer buffer will be empty once the ongoing burst transfer is completed.
This bit is not enable-protected.
Value
Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST: Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and
CRCENABLE are '0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the
DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access
error.
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Value
Description
0
There is no Reset operation ongoing.
1
A Reset operation is ongoing.
Bits 11,10,9,8 – LVLENx: Priority Level x Enable [x=3..0]
When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When
cleared, all requests with the corresponding level will be ignored.
For details on arbitration schemes, refer to the Arbitration section.
These bits are not enable-protected.
Value
Description
0
Transfer requests for Priority level x will not be handled.
1
Transfer requests for Priority level x will be handled.
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26.8.2.
CRC Control
Name: CRCCTRL
Offset: 0x02
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit
15
14
13
12
11
10
9
8
CRCSRC[5:0]
Access
Reset
Bit
7
6
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
5
4
3
1
0
2
CRCPOLY[1:0]
Access
Reset
CRCBEATSIZE[1:0]
R/W
R/W
R/W
R/W
0
0
0
0
Bits 13:8 – CRCSRC[5:0]: CRC Input Source
These bits select the input source for generating the CRC, as shown in the table below. The selected
source is locked until either the CRC generation is completed or the CRC module is disabled. This means
the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the
CRCBUSY status bit. CRC generation complete is generated and signaled from the selected source
when used with the DMA channel.
Value
Name
Description
0x00
NOACT
No action
0x01
IO
I/O interface
0x02-0x1 F
Reserved
0x20
CHN
DMA channel 0
0x21
CHN
DMA channel 1
0x22
CHN
DMA channel 2
0x23
CHN
DMA channel 3
0x24
CHN
DMA channel 4
0x25
CHN
DMA channel 5
0x26
CHN
DMA channel 6
0x27
CHN
DMA channel 7
0x28
CHN
DMA channel 8
0x29
CHN
DMA channel 9
0x2A
CHN
DMA channel 10
0x2B
CHN
DMA channel 11
0x2C
CHN
DMA channel 12
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Value
Name
Description
0x2D
CHN
DMA channel 13
0x2E
CHN
DMA channel 14
0x2F
CHN
DMA channel 15
0x30
CHN
DMA channel 16
0x31
CHN
DMA channel 17
0x32
CHN
DMA channel 18
0x33
CHN
DMA channel 19
0x34
CHN
DMA channel 20
0x35
CHN
DMA channel 21
0x36
CHN
DMA channel 22
0x37
CHN
DMA channel 23
0x38
CHN
DMA channel 24
0x39
CHN
DMA channel 25
0x3A
CHN
DMA channel 26
0x3B
CHN
DMA channel 27
0x3C
CHN
DMA channel 28
0x3D
CHN
DMA channel 29
0x3E
CHN
DMA channel 30
0x3F
CHN
DMA channel 31
Bits 3:2 – CRCPOLY[1:0]: CRC Polynomial Type
These bits define the size of the data transfer for each bus access when the CRC is used with I/O
interface, as shown in the table below.
Value
Name
Description
0x0
CRC16
CRC-16 (CRC-CCITT)
0x1
CRC32
CRC32 (IEEE 802.3)
0x2-0x3
Reserved
Bits 1:0 – CRCBEATSIZE[1:0]: CRC Beat Size
These bits define the size of the data transfer for each bus access when the CRC is used with I/O
interface.
Value
Name
Description
0x0
BYTE
8-bit bus transfer
0x1
HWORD
16-bit bus transfer
0x2
WORD
32-bit bus transfer
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Value
0x3
Name
Description
Reserved
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26.8.3.
CRC Data Input
Name: CRCDATAIN
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
CRCDATAIN[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
CRCDATAIN[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CRCDATAIN[15:8]
Access
CRCDATAIN[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – CRCDATAIN[31:0]: CRC Data Input
These bits store the data for which the CRC checksum is computed. After the CRCDATAIN register has
been written, the number of cycles for the new CRC checksum to be ready is dependent of the
configuration of the CRC Beat Size bit group in the CRC Control register(CRCCTRL.CRCBEATSIZE).
Each byte needs one clock cycle to be calculated.
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26.8.4.
CRC Checksum
The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC.
Name: CRCCHKSUM
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
CRCCHKSUM[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
CRCCHKSUM[23:16]
Access
CRCCHKSUM[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CRCCHKSUM[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – CRCCHKSUM[31:0]: CRC Checksum
These bits store the generated CRC result. When CRC-16 is enabled, the 16 msb will always read '0'.
These bits should only be read when CRC Module Busy bit in the CRC Status register
CRCSTATUS.BUSY=0.
If CRC-16 is selected and CRCSTATUS.BUSY=0 (CRC generation is completed), this bit group will
contain a valid checksum.
If CRC-32 is selected and CRCSTATUS.BUSY=0 (CRC generation is completed), this bit group will
contain a valid reversed checksum, i.e.: bit 31 is swapped with bit 0, bit 30 with bit 1, etc.
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26.8.5.
CRC Status
Name: CRCSTATUS
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
CRCZERO
CRCBUSY
Access
R
R/W
Reset
0
0
Bit 1 – CRCZERO: CRC Zero
This bit is cleared when a new CRC source is selected.
This bit is set when the CRC generation is complete and the CRC Checksum is zero.
When running CRC-32 and appending the checksum at the end of the packet (as little endian), the final
checksum should be 0x2144df1c, and not zero. However, if the checksum is complemented before it is
appended (as little endian) to the data, the final result in the checksum register will be zero. See the
description of CRCCHKSUM to read out different versions of the checksum.
Bit 0 – CRCBUSY: CRC Module Busy
This flag is cleared by writing a one to it when used with I/O interface. When used with a DMA channel,
the bit is set when the corresponding DMA channel is enabled, and cleared when the corresponding DMA
channel is disabled. This register bit cannot be cleared by the application when the CRC is used with a
DMA channel.
This bit is set when a source configuration is selected and as long as the source is using the CRC
module.
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26.8.6.
Debug Control
Name: DBGCTRL
Offset: 0x0D
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGRUN
Access
R/W
Reset
0
Bit 0 – DBGRUN: Debug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The DMAC is halted when the CPU is halted by an external debugger.
1
The DMAC continues normal operation when the CPU is halted by an external debugger.
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26.8.7.
Quality of Service Control
Name: QOSCTRL
Offset: 0x0E
Reset: 0x2A
Property: PAC Write-Protection
Bit
7
6
5
4
3
DQOS[1:0]
Access
2
1
FQOS[1:0]
0
WRBQOS[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
0
Reset
Bits 5:4 – DQOS[1:0]: Data Transfer Quality of Service
These bits define the memory priority access during the data transfer operation.
DQOS[1:0]
Name
Description
0x0
DISABLE
Background (no sensitive operation)
0x1
LOW
Sensitive Bandwidth
0x2
MEDIUM
Sensitive Latency
0x3
HIGH
Critical Latency
Bits 3:2 – FQOS[1:0]: Fetch Quality of Service
These bits define the memory priority access during the fetch operation.
FQOS[1:0]
Name
Description
0x0
DISABLE
Background (no sensitive operation)
0x1
LOW
Sensitive Bandwidth
0x2
MEDIUM
Sensitive Latency
0x3
HIGH
Critical Latency
Bits 1:0 – WRBQOS[1:0]: Write-Back Quality of Service
These bits define the memory priority access during the write-back operation.
WRBQOS[1:0]
Name
Description
0x0
DISABLE
Background (no sensitive operation)
0x1
LOW
Sensitive Bandwidth
0x2
MEDIUM
Sensitive Latency
0x3
HIGH
Critical Latency
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26.8.8.
Software Trigger Control
Name: SWTRIGCTRL
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SWTRIG5
SWTRIG4
SWTRIG3
SWTRIG2
SWTRIG1
SWTRIG0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 5:0 – SWTRIGn: Channel n Software Trigger [n = 5..0]
This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for
the corresponding channel is either set, or by writing a '1' to it.
This bit is set if CHSTATUS.PEND is already '1' when writing a '1' to that bit.
Writing a '0' to this bit will clear the bit.
Writing a '1' to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND=0 for
channel x. CHSTATUS.PEND will be set and SWTRIGn will remain cleared.
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26.8.9.
Priority Control 0
Name: PRICTRL0
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
RRLVLEN3
Access
Reset
Bit
24
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
19
18
17
16
23
22
21
20
RRLVLEN2
Access
25
LVLPRI3[3:0]
LVLPRI2[3:0]
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
15
11
10
9
8
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
3
2
1
0
14
13
12
RRLVLEN1
Access
Reset
Bit
7
LVLPRI1[3:0]
6
5
4
RRLVLEN0
Access
Reset
LVLPRI0[3:0]
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit 31 – RRLVLEN3: Level 3 Round-Robin Arbitration Enable
This bit controls which arbitration scheme is selected for DMA channels with priority level 3. For details on
arbitration schemes, refer to Arbitration.
Value
Description
0
Static arbitration scheme for channels with level 3 priority.
1
Round-robin arbitration scheme for channels with level 3 priority.
Bits 27:24 – LVLPRI3[3:0]: Level 3 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3=1) for priority level 3, this register holds
the channel number of the last DMA channel being granted access as the active channel with priority
level 3.
When static arbitration is enabled (PRICTRL0.RRLVLEN3=0) for priority level 3, and the value of this bit
group is non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN3 written to
'0').
Bit 23 – RRLVLEN2: Level 2 Round-Robin Arbitration Enable
This bit controls which arbitration scheme is selected for DMA channels with priority level 2. For details on
arbitration schemes, refer to Arbitration.
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Value
Description
0
Static arbitration scheme for channels with level 2 priority.
1
Round-robin arbitration scheme for channels with level 2 priority.
Bits 19:16 – LVLPRI2[3:0]: Level 2 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2=1) for priority level 2, this register holds
the channel number of the last DMA channel being granted access as the active channel with priority
level 2.
When static arbitration is enabled (PRICTRL0.RRLVLEN2=0) for priority level 2, and the value of this bit
group is non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN2 written to
'0').
Bit 15 – RRLVLEN1: Level 1 Round-Robin Scheduling Enable
For details on arbitration schemes, refer to Arbitration.
Value
Description
0
Static arbitration scheme for channels with level 1 priority.
1
Round-robin arbitration scheme for channels with level 1 priority.
Bits 11:8 – LVLPRI1[3:0]: Level 1 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1=1) for priority level 1, this register holds
the channel number of the last DMA channel being granted access as the active channel with priority
level 1.
When static arbitration is enabled (PRICTRL0.RRLVLEN1=0) for priority level 1, and the value of this bit
group is non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN1 written to
'0').
Bit 7 – RRLVLEN0: Level 0 Round-Robin Scheduling Enable
For details on arbitration schemes, refer to Arbitration.
Value
Description
0
Static arbitration scheme for channels with level 0 priority.
1
Round-robin arbitration scheme for channels with level 0 priority.
Bits 3:0 – LVLPRI0[3:0]: Level 0 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0=1) for priority level 0, this register holds
the channel number of the last DMA channel being granted access as the active channel with priority
level 0.
When static arbitration is enabled (PRICTRL0.RRLVLEN0=0) for priority level 0, and the value of this bit
group is non-zero, it will not affect the static priority scheme.
This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN0 written to
'0').
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26.8.10. Interrupt Pending
This register allows the user to identify the lowest DMA channel with pending interrupt.
Name: INTPEND
Offset: 0x20
Reset: 0x0000
Property: Bit
15
14
13
10
9
8
PEND
BUSY
FERR
12
SUSP
TCMPL
TERR
Access
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
Bit
7
6
5
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
4
11
ID[3:0]
Access
Reset
Bit 15 – PEND: Pending
This bit will read '1' when the channel selected by Channel ID field (ID) is pending.
Bit 14 – BUSY: Busy
This bit will read '1' when the channel selected by Channel ID field (ID) is busy.
Bit 13 – FERR: Fetch Error
This bit will read '1' when the channel selected by Channel ID field (ID) fetched an invalid descriptor.
Bit 10 – SUSP: Channel Suspend
This bit will read '1' when the channel selected by Channel ID field (ID) has pending Suspend interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel ID (ID) Suspend interrupt flag.
Bit 9 – TCMPL: Transfer Complete
This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Complete
interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag.
Bit 8 – TERR: Transfer Error
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error
interrupt.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel ID (ID) Transfer Error interrupt flag.
Bits 3:0 – ID[3:0]: Channel ID
These bits store the lowest channel number with pending interrupts. The number is valid if Suspend
(SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is
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refreshed when a new channel (with channel number less than the current one) with pending interrupts is
detected, or when the application clears the corresponding channel interrupt sources. When no pending
channels interrupts are available, these bits will always return zero value when read.
When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled.
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26.8.11. Interrupt Status
Name: INTSTATUS
Offset: 0x24
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
CHINT5
CHINT4
CHINT3
CHINT2
CHINT1
CHINT0
Access
R
R
R
R
R
R
Reset
0
0
0
0
0
0
Bits 5:0 – CHINTn: Channel n Pending Interrupt [n=5..0]
This bit is set when Channel n has a pending interrupt/the interrupt request is received.
This bit is cleared when the corresponding Channel n interrupts are disabled or the interrupts sources are
cleared.
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26.8.12. Busy Channels
Name: BUSYCH
Offset: 0x28
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
BUSYCH5
BUSYCH4
BUSYCH3
BUSYCH2
BUSYCH1
BUSYCH0
Access
R
R
R
R
R
R
Reset
0
0
0
0
0
0
Bits 5:0 – BUSYCHn: Busy Channel n [x=5..0]
This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for
DMA channel n is detected, or when DMA channel n is disabled.
This bit is set when DMA channel n starts a DMA transfer.
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26.8.13. Pending Channels
Name: PENDCH
Offset: 0x2C
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
PENDCH5
PENDCH4
PENDCH3
PENDCH2
PENDCH1
PENDCH0
Access
R
R
R
R
R
R
Reset
0
0
0
0
0
0
Bits 5:0 – PENDCHn: Pending Channel n [n=5..0]
This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel n is
started, when a bus error for DMA channel n is detected or when DMA channel n is disabled. For details
on trigger action settings, refer to CHCTRLB.TRIGACT.
This bit is set when a transfer is pending on DMA channel n.
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26.8.14. Active Channel and Levels
Name: ACTIVE
Offset: 0x30
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
BTCNT[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
BTCNT[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
ABUSY
ID[4:0]
Access
R
R
R
R
R
R
Reset
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
LVLEX3
LVLEX2
LVLEX1
LVLEX0
Access
R
R
R
R
Reset
0
0
0
0
Bits 31:16 – BTCNT[15:0]: Active Channel Block Transfer Count
These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active
channel and written back in the corresponding Write-Back channel memory location when the arbiter
grants a new channel access. The value is valid only when the active channel active busy flag (ABUSY)
is set.
Bit 15 – ABUSY: Active Channel Busy
This bit is cleared when the active transfer count is written back in the write-back memory section.
This bit is set when the next descriptor transfer count is read from the write-back memory section.
Bits 12:8 – ID[4:0]: Active Channel ID
These bits hold the channel index currently stored in the active channel registers. The value is updated
each time the arbiter grants a new channel transfer access request.
Bits 3,2,1,0 – LVLEXx: Level x Channel Trigger Request Executing [x=3..0]
This bit is set when a level-x channel trigger request is executing or pending.
This bit is cleared when no request is pending or being executed.
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26.8.15. Descriptor Memory Section Base Address
Name: BASEADDR
Offset: 0x34
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
BASEADDR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
BASEADDR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
BASEADDR[15:8]
Access
BASEADDR[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – BASEADDR[31:0]: Descriptor Memory Base Address
These bits store the Descriptor memory section base address. The value must be 128-bit aligned.
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26.8.16. Write-Back Memory Section Base Address
Name: WRBADDR
Offset: 0x38
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
WRBADDR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
WRBADDR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
WRBADDR[15:8]
Access
WRBADDR[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – WRBADDR[31:0]: Write-Back Memory Base Address
These bits store the Write-Back memory base address. The value must be 128-bit aligned.
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26.8.17. Channel ID
Name: CHID
Offset: 0x3F
Reset: 0x00
Property: Bit
7
6
5
4
3
2
1
0
ID[3:0]
Access
Reset
R/W
R/W
R/W
R/W
0
0
0
0
Bits 3:0 – ID[3:0]: Channel ID
These bits define the channel number that will be affected by the channel registers (CH*). Before reading
or writing a channel register, the channel ID bit group must be written first.
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26.8.18. Channel Control A
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHCTRLA
Offset: 0x40
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit
7
6
5
4
3
Access
Reset
2
1
0
ENABLE
SWRST
R/W
R/W
0
0
Bit 1 – ENABLE: Channel Enable
Writing a '0' to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer
buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the
ongoing burst transfer is completed.
Writing a '1' to this bit will enable the DMA channel.
This bit is not enable-protected.
Value
Description
0
DMA channel is disabled.
1
DMA channel is enabled.
Bit 0 – SWRST: Channel Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the channel registers to their initial state. The bit can be set when the
channel is disabled (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is
automatically cleared when the reset is completed.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
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26.8.19. Channel Control B
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHCTRLB
Offset: 0x44
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
CMD[1:0]
Access
Reset
Bit
23
22
R/W
R/W
0
0
21
20
19
18
17
16
13
12
11
10
9
8
TRIGACT[1:0]
Access
R/W
R/W
Reset
0
0
Bit
15
14
TRIGSRC[5:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
2
1
0
Reset
Bit
7
6
5
LVL[1:0]
Access
Reset
4
3
EVOE
EVIE
EVACT[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bits 25:24 – CMD[1:0]: Software Command
These bits define the software commands. Refer to Channel Suspend and Channel Resume and Next
Suspend Skip.
These bits are not enable-protected.
CMD[1:0]
Name
Description
0x0
NOACT
No action
0x1
SUSPEND
Channel suspend operation
0x2
RESUME
Channel resume operation
0x3
-
Reserved
Bits 23:22 – TRIGACT[1:0]: Trigger Action
These bits define the trigger action used for a transfer.
TRIGACT[1:0]
Name
Description
0x0
BLOCK
One trigger required for each block transfer
0x1
-
Reserved
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TRIGACT[1:0]
Name
Description
0x2
BEAT
One trigger required for each beat transfer
0x3
TRANSACTION
One trigger required for each transaction
Bits 13:8 – TRIGSRC[5:0]: Trigger Source
These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and
trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT.
Table 26-2. Peripheral Trigger Source
Value
Name
Description
0x00
DISABLE
Only software/event triggers
0x01
-
Reserved
0x02
SERCOM0 RX
SERCOM0 RX Trigger
0x03
SERCOM0 TX
SERCOM0TX Trigger
0x04
SERCOM1 RX
SERCOM1 RX Trigger
0x05
SERCOM1 TX
SERCOM1 TX Trigger
0x06
SERCOM2 RX
SERCOM2 RX Trigger
0x07
SERCOM2 TX
SERCOM2 TX Trigger
0x08
SERCOM3 RX
SERCOM3 RX Trigger
0x09
SERCOM3 TX
SERCOM3 TX Trigger
0x0A
-
Reserved
0x0B
-
Reserved
0x0C
-
Reserved
0x0D
-
Reserved
0x0E
-
Reserved
0x0F
-
Reserved
0x10
TCC0 OVF
TCC0 Overflow Trigger
0x11
TCC0 MC0
TCC0 Match/Compare 0 Trigger
0x12
TCC0 MC1
TCC0 Match/Compare 1 Trigger
0x13
TCC0 MC2
TCC0 Match/Compare 2 Trigger
0x14
TCC0 MC3
TCC0 Match/Compare 3 Trigger
0x15
TCC1 OVF
TCC1 Overflow Trigger
0x16
TCC1 MC0
TCC1 Match/Compare 0 Trigger
0x17
TCC1 MC1
TCC1 Match/Compare 1 Trigger
0x18
TCC2 OVF
TCC2 Overflow Trigger
0x19
TCC2 MC0
TCC2 Match/Compare 0 Trigger
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Value
Name
Description
0x1A
TCC2 MC1
TCC2 Match/Compare 1 Trigger
0x1B
TC0 OVF
TC0 Overflow Trigger
0x1C
TC0 MC0
TC0 Match/Compare 0 Trigger
0x1D
TC0 MC1
TC0 Match/Compare 1 Trigger
0x1E
TC1 OVF
TC1 Overflow Trigger
0x1F
TC1 MC0
TC1 Match/Compare 0 Trigger
0x20
TC1 MC1
TC1 Match/Compare 1 Trigger
0x21
TC2 OVF
TC2 Overflow Trigger
0x22
TC2 MC0
TC2 Match/Compare 0 Trigger
0x23
TC2 MC1
TC2 Match/Compare 1 Trigger
0x24
TC3 OVF
TC3 Overflow Trigger
0x25
TC3 MC0
TC3 Match/Compare 0 Trigger
0x26
TC3 MC1
TC3 Match/Compare 1 Trigger
0x27
TC4 OVF
TC4 Overflow Trigger
0x28
TC4 MC0
TC4 Match/Compare 0 Trigger
0x29
TC4 MC1
TC4 Match/Compare 1 Trigger
0x2A
ADC0 RESRDY
ADC0 Result Ready Trigger
0x2E
PTC EOC
PTC End of Conversion Trigger
0x2F
PTC WCOMP
PTC Window Compare Trigger
0x30
PTC SEQ
PTC Sequence Trigger
Bits 6:5 – LVL[1:0]: Channel Arbitration Level
These bits define the arbitration level used for the DMA channel, where a high level has priority over a
low level. For further details on arbitration schemes, refer to Arbitration.
These bits are not enable-protected.
TRIGACT[1:0]
Name
Description
0x0
LVL0
Channel Priority Level 0
0x1
LVL1
Channel Priority Level 1
0x2
LVL2
Channel Priority Level 2
0x3
LVL3
Channel Priority Level 3
Bit 4 – EVOE: Channel Event Output Enable
This bit indicates if the Channel event generation is enabled. The event will be generated for every
condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL).
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This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection
and Event Generator Selection of the Event System for details.
Value
Description
0
Channel event generation is disabled.
1
Channel event generation is enabled.
Bit 3 – EVIE: Channel Event Input Enable
This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection
and Event Generator Selection of the Event System for details.
Value
Description
0
Channel event action will not be executed on any incoming event.
1
Channel event action will be executed on any incoming event.
Bits 2:0 – EVACT[2:0]: Event Input Action
These bits define the event input action, as shown below. The action is executed only if the corresponding
EVIE bit in CHCTRLB register of the channel is set.
These bits are available only for the least significant DMA channels. Refer to table: User Multiplexer
Selection and Event Generator Selection of the Event System for details.
EVACT[2:0]
Name
Description
0x0
NOACT
No action
0x1
TRIG
Normal Transfer and Conditional Transfer on Strobe
trigger
0x2
CTRIG
Conditional transfer trigger
0x3
CBLOCK
Conditional block transfer
0x4
SUSPEND
Channel suspend operation
0x5
RESUME
Channel resume operation
0x6
SSKIP
Skip next block suspend action
0x7
-
Reserved
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26.8.20. Channel Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register.
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHINTENCLR
Offset: 0x4C
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
Access
Reset
2
1
0
SUSP
TCMPL
TERR
R/W
R/W
R/W
0
0
0
Bit 2 – SUSP: Channel Suspend Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel
Suspend interrupt.
Value
Description
0
The Channel Suspend interrupt is disabled.
1
The Channel Suspend interrupt is enabled.
Bit 1 – TCMPL: Channel Transfer Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the
Channel Transfer Complete interrupt.
Value
Description
0
The Channel Transfer Complete interrupt is disabled. When block action is set to none, the
TCMPL flag will not be set when a block transfer is completed.
1
The Channel Transfer Complete interrupt is enabled.
Bit 0 – TERR: Channel Transfer Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the
Channel Transfer Error interrupt.
Value
Description
0
The Channel Transfer Error interrupt is disabled.
1
The Channel Transfer Error interrupt is enabled.
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26.8.21. Channel Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register.
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHINTENSET
Offset: 0x4D
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
Access
Reset
2
1
0
SUSP
TCMPL
TERR
R/W
R/W
R/W
0
0
0
Bit 2 – SUSP: Channel Suspend Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel
Suspend interrupt.
Value
Description
0
The Channel Suspend interrupt is disabled.
1
The Channel Suspend interrupt is enabled.
Bit 1 – TCMPL: Channel Transfer Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the
Channel Transfer Complete interrupt.
Value
Description
0
The Channel Transfer Complete interrupt is disabled.
1
The Channel Transfer Complete interrupt is enabled.
Bit 0 – TERR: Channel Transfer Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel
Transfer Error interrupt.
Value
Description
0
The Channel Transfer Error interrupt is disabled.
1
The Channel Transfer Error interrupt is enabled.
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26.8.22. Channel Interrupt Flag Status and Clear
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHINTFLAG
Offset: 0x4E
Reset: 0x00
Property: Bit
7
6
5
4
3
2
1
0
SUSP
TCMPL
TERR
R/W
R/W
R/W
0
0
0
Access
Reset
Bit 2 – SUSP: Channel Suspend
This flag is cleared by writing a '1' to it.
This flag is set when a block transfer with suspend block action is completed, when a software suspend
command is executed, when a suspend event is received or when an invalid descriptor is fetched by the
DMA.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Channel Suspend interrupt flag for the corresponding channel.
For details on available software commands, refer to CHCTRLB.CMD.
For details on available event input actions, refer to CHCTRLB.EVACT.
For details on available block actions, refer to BTCTRL.BLOCKACT.
Bit 1 – TCMPL: Channel Transfer Complete
This flag is cleared by writing a '1' to it.
This flag is set when a block transfer is completed and the corresponding interrupt block action is
enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transfer Complete interrupt flag for the corresponding channel.
Bit 0 – TERR: Channel Transfer Error
This flag is cleared by writing a '1' to it.
This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid
descriptor.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transfer Error interrupt flag for the corresponding channel.
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26.8.23. Channel Status
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHSTATUS
Offset: 0x4F
Reset: 0x00
Property: Bit
7
6
5
4
3
2
1
0
FERR
BUSY
PEND
Access
R
R
R
Reset
0
0
0
Bit 2 – FERR: Channel Fetch Error
This bit is cleared when a software resume command is executed.
This bit is set when an invalid descriptor is fetched.
Bit 1 – BUSY: Channel Busy
This bit is cleared when the channel trigger action is completed, when a bus error is detected or when the
channel is disabled.
This bit is set when the DMA channel starts a DMA transfer.
Bit 0 – PEND: Channel Pending
This bit is cleared when the channel trigger action is started, when a bus error is detected or when the
channel is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT.
This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is
received.
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26.9.
Offset
0x00
0x01
0x02
0x03
Register Summary - SRAM
Name
BTCTRL
BTCNT
0x04
0x05
0x06
SRCADDR
Bit Pos.
7:0
15:8
BLOCKACT[1:0]
STEPSIZE[2:0]
7:0
STEPSEL
DSTINC
15:8
BTCNT[15:8]
7:0
SRCADDR[7:0]
15:8
SRCADDR[15:8]
23:16
SRCADDR[23:16]
31:24
SRCADDR[31:24]
0x08
7:0
DSTADDR[7:0]
0x09
DSTADDR
15:8
DSTADDR[15:8]
23:16
DSTADDR[23:16]
DSTADDR[31:24]
0x0B
31:24
0x0C
7:0
DESCADDR[7:0]
0x0D
15:8
DESCADDR[15:8]
23:16
DESCADDR[23:16]
31:24
DESCADDR[31:24]
0x0E
0x0F
DESCADDR
SRCINC
VALID
BEATSIZE[1:0]
BTCNT[7:0]
0x07
0x0A
EVOSEL[1:0]
26.10. Register Description - SRAM
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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26.10.1. Block Transfer Control
The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: BTCTRL
Offset: 0x00
Reset: Property: Bit
15
14
13
STEPSIZE[2:0]
12
11
10
STEPSEL
DSTINC
SRCINC
9
4
3
2
8
BEATSIZE[1:0]
Access
Reset
Bit
7
6
5
BLOCKACT[1:0]
1
EVOSEL[1:0]
0
VALID
Access
Reset
Bits 15:13 – STEPSIZE[2:0]: Address Increment Step Size
These bits select the address increment step size. The setting apply to source or destination address,
depending on STEPSEL setting.
STEPSIZE[2:0]
Name
Description
0x0
X1
Next ADDR = ADDR + (BEATSIZE+1) * 1
0x1
X2
Next ADDR = ADDR + (BEATSIZE+1) * 2
0x2
X4
Next ADDR = ADDR + (BEATSIZE+1) * 4
0x3
X8
Next ADDR = ADDR + (BEATSIZE+1) * 8
0x4
X16
Next ADDR = ADDR + (BEATSIZE+1) * 16
0x5
X32
Next ADDR = ADDR + (BEATSIZE+1) * 32
0x6
X64
Next ADDR = ADDR + (BEATSIZE+1) * 64
0x7
X128
Next ADDR = ADDR + (BEATSIZE+1) * 128
Bit 12 – STEPSEL: Step Selection
This bit selects if source or destination addresses are using the step size settings.
STEPSEL
Name
Description
0x0
DST
Step size settings apply to the destination address
0x1
SRC
Step size settings apply to the source address
Bit 11 – DSTINC: Destination Address Increment Enable
Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed
during the data transfer.
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Writing a '1' to this bit will enable the destination address incrementation. By default, the destination
address is incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the
STEPSIZE register.
Value
Description
0
The Destination Address Increment is disabled.
1
The Destination Address Increment is enabled.
Bit 10 – SRCINC: Source Address Increment Enable
Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed
during the data transfer.
Writing a '1' to this bit will enable the source address incrementation. By default, the source address is
incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE
register.
Value
Description
0
The Source Address Increment is disabled.
1
The Source Address Increment is enabled.
Bits 9:8 – BEATSIZE[1:0]: Beat Size
These bits define the size of one beat. A beat is the size of one data transfer bus access, and the setting
apply to both read and write accesses.
BEATSIZE[1:0]
Name
Description
0x0
BYTE
8-bit bus transfer
0x1
HWORD
16-bit bus transfer
0x2
WORD
32-bit bus transfer
0x3
Reserved
Bits 4:3 – BLOCKACT[1:0]: Block Action
These bits define what actions the DMAC should take after a block transfer has completed.
BLOCKACT[1:0]
Name
Description
0x0
NOACT
Channel will be disabled if it is the last block transfer in
the transaction
0x1
INT
Channel will be disabled if it is the last block transfer in
the transaction and block interrupt
0x2
SUSPEND
Channel suspend operation is completed
0x3
BOTH
Both channel suspend operation and block interrupt
Bits 2:1 – EVOSEL[1:0]: Event Output Selection
These bits define the event output selection.
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EVOSEL[1:0]
Name
Description
0x0
DISABLE
Event generation disabled
0x1
BLOCK
Event strobe when block transfer complete
0x2
Reserved
0x3
BEAT
Event strobe when beat transfer complete
Bit 0 – VALID: Descriptor Valid
Writing a '0' to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation
when fetching the corresponding descriptor.
The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an
error is detected during the block transfer, or when the block transfer is completed.
Value
Description
0
The descriptor is not valid.
1
The descriptor is valid.
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26.10.2. Block Transfer Count
The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: BTCNT
Offset: 0x02
Reset: Property: Bit
15
14
13
12
11
10
9
8
3
2
1
0
BTCNT[15:8]
Access
Reset
Bit
7
6
5
4
BTCNT[7:0]
Access
Reset
Bits 15:0 – BTCNT[15:0]: Block Transfer Count
This bit group holds the 16-bit block transfer count.
During a transfer, the internal counter value is decremented by one after each beat transfer. The internal
counter is written to the corresponding write-back memory section for the DMA channel when the DMA
channel loses priority, is suspended or gets disabled. The DMA channel can be disabled by a complete
transfer, a transfer error or by software.
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26.10.3. Block Transfer Source Address
The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: SRCADDR
Offset: 0x04
Reset: Property: Bit
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
SRCADDR[31:24]
Access
Reset
Bit
23
22
21
20
19
SRCADDR[23:16]
Access
Reset
Bit
15
14
13
12
11
SRCADDR[15:8]
Access
Reset
Bit
7
6
5
4
3
SRCADDR[7:0]
Access
Reset
Bits 31:0 – SRCADDR[31:0]: Transfer Source Address
This bit group holds the source address corresponding to the last beat transfer address in the block
transfer.
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26.10.4. Block Transfer Destination Address
The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: DSTADDR
Offset: 0x08
Reset: Property: Bit
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
DSTADDR[31:24]
Access
Reset
Bit
23
22
21
20
19
DSTADDR[23:16]
Access
Reset
Bit
15
14
13
12
11
DSTADDR[15:8]
Access
Reset
Bit
7
6
5
4
3
DSTADDR[7:0]
Access
Reset
Bits 31:0 – DSTADDR[31:0]: Transfer Destination Address
This bit group holds the destination address corresponding to the last beat transfer address in the block
transfer.
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26.10.5. Next Descriptor Address
The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name: DESCADDR
Offset: 0x0C
Reset: Property: Bit
31
30
29
28
27
26
25
24
18
17
16
10
9
8
2
1
0
DESCADDR[31:24]
Access
Reset
Bit
23
22
21
20
19
DESCADDR[23:16]
Access
Reset
Bit
15
14
13
12
11
DESCADDR[15:8]
Access
Reset
Bit
7
6
5
4
3
DESCADDR[7:0]
Access
Reset
Bits 31:0 – DESCADDR[31:0]: Next Descriptor Address
This bit group holds the SRAM address of the next descriptor. The value must be 128-bit aligned. If the
value of this SRAM register is 0x00000000, the transaction will be terminated when the DMAC tries to
load the next transfer descriptor.
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27.
EIC – External Interrupt Controller
27.1.
Overview
The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each
interrupt line can be individually masked and can generate an interrupt on rising, falling, or both edges, or
on high or low levels. Each external pin has a configurable filter to remove spikes. Each external pin can
also be configured to be asynchronous in order to wake up the device from sleep modes where all clocks
have been disabled. External pins can also generate an event.
A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external
interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt
mode.
27.2.
Features
•
•
•
•
•
•
•
•
27.3.
Up to 32 external pins, plus one non-maskable pin
Dedicated, individually maskable interrupt for each pin
Interrupt on rising, falling, or both edges
synchronous or asynchronous edge detection mode
Interrupt on high or low levels
Asynchronous interrupts for sleep modes without clock
Filtering of external pins
Event generation
Block Diagram
Figure 27-1. EIC Block Diagram
FILTENx
SENSEx[2:0]
Interrupt
EXTINTx
Filter
Edge/Level
Detection
Wake
Event
NMIFILTEN
inwake_extint
evt_extint
NMISENSE[2:0]
Interrupt
NMI
Filter
intreq_extint
Edge/Level
Detection
Wake
intreq_nmi
inwake_nmi
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27.4.
Signal Description
Signal Name
Type
Description
EXTINT[31..0]
Digital Input
External interrupt pin
NMI
Digital Input
Non-maskable interrupt pin
One signal can be mapped on several pins.
Related Links
I/O Multiplexing and Considerations on page 28
27.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
27.5.1.
I/O Lines
Using the EIC’s I/O lines requires the I/O pins to be configured.
Related Links
PORT - I/O Pin Controller on page 455
27.5.2.
Power Management
All interrupts are available in all sleep modes, but the EIC can be configured to automatically mask some
interrupts in order to prevent device wake-up.
The EIC will continue to operate in any sleep mode where the selected source clock is running. The EIC’s
interrupts can be used to wake up the device from sleep modes. Events connected to the Event System
can trigger other operations in the system without exiting sleep modes.
Related Links
PM – Power Manager on page 177
27.5.3.
Clocks
The EIC bus clock (CLK_EIC_APB) can be enabled and disabled by the Main Clock Controller, the
default state of CLK_EIC_APB can be found in the Peripheral Clock Masking section.
Some optional functions need a peripheral clock, which can either be a generic clock (GCLK_EIC, for
wider frequency selection) or a Ultra Low Power 32KHz clock (CLK_ULP32K, for highest power
efficiency). One of the clock sources must be configured and enabled before using the peripheral:
GCLK_EIC is configured and enabled in the Generic Clock Controller.
CLK_ULP32K is provided by the internal ultra-low-power (OSCULP32K) oscillator in the OSC32KCTRL
module.
Both GCLK_EIC and CLK_ULP32K are asynchronous to the user interface clock (CLK_EIC_APB). Due
to this asynchronicity, writes to certain registers will require synchronization between the clock domains.
Refer to Synchronization for further details.
Related Links
MCLK – Main Clock on page 149
Peripheral Clock Masking on page 152
GCLK - Generic Clock Controller on page 127
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OSC32KCTRL – 32KHz Oscillators Controller on page 225
27.5.4.
DMA
Not applicable.
27.5.5.
Interrupts
There are two interrupt request lines, one for the external interrupts (EXTINT) and one for non-maskable
interrupt (NMI).
The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires
the interrupt controller to be configured first.
The NMI interrupt request line is also connected to the interrupt controller, but does not require the
interrupt to be configured.
Related Links
Nested Vector Interrupt Controller on page 43
27.5.6.
Events
The events are connected to the Event System. Using the events requires the Event System to be
configured first.
Related Links
EVSYS – Event System on page 487
27.5.7.
Debug Operation
When the CPU is halted in debug mode, the EIC continues normal operation. If the EIC is configured in a
way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
27.5.8.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except the following registers:
•
•
Interrupt Flag Status and Clear register (INTFLAG)
Non-Maskable Interrupt Flag Status and Clear register (NMIFLAG)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
27.5.9.
Analog Connections
Not applicable.
27.6.
Functional Description
27.6.1.
Principle of Operation
The EIC detects edge or level condition to generate interrupts to the CPU interrupt controller or events to
the Event System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering,
clocked by GCLK_EIC or by CLK_ULP32K.
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27.6.2.
Basic Operation
27.6.2.1. Initialization
The EIC must be initialized in the following order:
1.
2.
3.
4.
5.
Enable CLK_EIC_APB
If required, configure the NMI by writing the Non-Maskable Interrupt Control register (NMICTRL)
When the NMI is used or synchronous edge detection or filtering are required, enable GCLK_EIC
or CLK_ULP32K.
GCLK_EIC is used when a frequency higher than 32KHz is required for filtering, CLK_ULP32K is
recommended when power consumption is the priority. For CLK_ULP32K write a '1' to the Clock
Selection bit in the Control A register (CTRLA.CKSEL).
Configure the EIC input sense and filtering by writing the Configuration n register (CONFIGn0,
CONFIGn1, CONFIGn2, CONFIGn3).
Enable the EIC.
The following bits are enable-protected, meaning that it can only be written when the EIC is disabled
(CTRLA.ENABLE=0):
•
Clock Selection bit in Control A register (CTRLA.CKSEL)
The following registers are enable-protected:
•
•
Event Control register (EVCTRL)
Configuration n register (CONFIG0, CONFIG1...)
Enable-protected bits in the CTRLA register can be written at the same time when setting
CTRLA.ENABLE to '1', but not at the same time as CTRLA.ENABLE is being cleared.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
27.6.2.2. Enabling, Disabling, and Resetting
The EIC is enabled by writing a '1' the Enable bit in the Control A register (CTRLA.ENABLE). The EIC is
disabled by writing CTRLA.ENABLE to '0'.
The EIC is reset by setting the Software Reset bit in the Control register (CTRLA.SWRST). All registers in
the EIC will be reset to their initial state, and the EIC will be disabled.
Refer to the CTRLA register description for details.
27.6.3.
External Pin Processing
Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or
both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing
the Input Sense x bits in the Config n register (CONFIGn0, CONFIGn1, CONFIGn2,
CONFIGn3.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status
and Clear register (INTFLAG) is set when the interrupt condition is met.
When the interrupt flag has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a
new interrupt condition is met. In level-sensitive mode, when interrupt has been cleared,
INTFLAG.EXTINT[x] will be set immediately if the EXTINTx pin still matches the interrupt condition.
Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC or CLK_ULP32K.
Filtering is enabled if bit Filter Enable x in the Configuration n register (CONFIGn0, CONFIGn1,
CONFIGn2, CONFIGn3.FILTENx) is written to '1'. The majority vote filter samples the external pin three
times with GCLK_EIC or CLK_ULP32K and outputs the value when two or more samples are equal.
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Table 27-1. Majority Vote Filter
Samples [0, 1, 2]
Filter Output
[0,0,0]
0
[0,0,1]
0
[0,1,0]
[0,1,1]
0
intreq_extint[x]
1
[1,0,0]
0
[1,0,1]
1
[1,1,0]
1
[1,1,1]
1
When an external interrupt is configured for level detection and when filtering is disabled, detection is
done asynchronously. Asynchronuous detection does not require GCLK_EIC or CLK_ULP32K, but
interrupt and events can still be generated.
If filtering or edge detection is enabled, the EIC automatically requests GCLK_EIC or CLK_ULP32K to
operate. The selection between these two clocks is done by writing the Clock Selection bits in the Control
A register (CTRLA.CKSEL). GCLK_EIC must be enabled in the GCLK module.
Figure 27-2. Interrupt Detections
GCLK_EIC
CLK_EIC_APB
EXTINTx
intreq_extint[x]
(level detection / no filter)
No interrupt
intreq_extint[x]
(level detection / filter)
intreq_extint[x]
(edge detection / no filter)
No interrupt
(edge detection / filter)
clear INTFLAG.EXTINT[x]
The detection delay depends on the detection mode.
Table 27-2. Interrupt Latency
Detection mode
Latency (worst case)
Level without filter
Five CLK_EIC_APB periods
Level with filter
Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods
Edge without filter
Four GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods
Edge with filter
Six GCLK_EIC/CLK_ULP32K periods + five CLK_EIC_APB periods
Related Links
GCLK - Generic Clock Controller on page 127
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27.6.4.
Additional Features
27.6.4.1. Non-Maskable Interrupt (NMI)
The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is
configured with the dedicated NMI Control register (NMICTRL). To select the sense for NMI, write to the
NMISENSE bit group in the NMI Control register (NMICTRL.NMISENSE). NMI filtering is enabled by
writing a '1' to the NMI Filter Enable bit (NMICTRL.NMIFILTEN).
If edge detection or filtering is required, enable GCLK_EIC or CLK_ULP32K.
NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC is not required to be
enabled.
When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set
(NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt
request when set.
27.6.4.2. Asynchronous Edge Detection Mode
The EXTINT edge detection can be operated synchronously or asynchronously, selected by the
Asynchronous Control Mode bit for external pin x in the External Interrupt Asynchronous Mode register
(ASYNCH.ASYNCH[x]). The EIC edge detection is operated synchronously when the Asynchronous
Control Mode bit (ASYNCH.ASYNCH[x]) is '0' (default value). It is operated asynchronously when
ASYNCH.ASYNCH[x] is written to '1'.
In Synchronous Edge Detection Mode, the external interrupt (EXTINT) or the non-maskable interrupt
(NMI) pins are sampled using the EIC clock as defined by the Clock Selection bit in the Control A register
(CTRLA.CKSEL). The External Interrupt flag (INTFLAG.EXTINT[x]) or Non-Maskable Interrupt flag
(NMIFLAG.NMI) is set when the last sampled state of the pin differs from the previously sampled state. In
this mode, the EIC clock is required.
The Synchronous Edge Detection Mode can be used in Idle sleep mode.
In Asynchronous Edge Detection Mode, the external interrupt (EXTINT) pins or the non-maskable
interrupt (NMI) pins set the External Interrupt flag or Non-Maskable Interrupt flag (INTFLAG.EXTINT[x] or
NMIFLAG) directly. In this mode, the EIC clock is not requested.
The asynchronous edge detection mode can be used in all sleep modes.
27.6.5.
DMA Operation
Not applicable.
27.6.6.
Interrupts
The EIC has the following interrupt sources:
•
•
External interrupt pins (EXTINTx). See Basic Operation.
Non-maskable interrupt pin (NMI). See Additional Features.
Each interrupt source has an associated interrupt flag. The interrupt flag in the Interrupt Flag Status and
Clear register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt,
except NMI, can be individually enabled by setting the corresponding bit in the Interrupt Enable Set
register (INTENSET=1), and disabled by setting the corresponding bit in the Interrupt Enable Clear
register (INTENCLR=1).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EIC
is reset. See the INTFLAG register for details on how to clear interrupt flags. The EIC has one common
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interrupt request line for all the interrupt sources, and one interrupt request line for the NMI. The user
must read the INTFLAG (or NMIFLAG) register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
Related Links
Processor and Architecture on page 41
27.6.7.
Events
The EIC can generate the following output events:
•
External event from pin (EXTINTx).
Setting an Event Output Control register (EVCTRL.EXTINTEO) enables the corresponding output event.
Clearing this bit disables the corresponding output event. Refer to Event System for details on configuring
the Event System.
When the condition on pin EXTINTx matches the configuration in the CONFIGn register, the
corresponding event is generated, if enabled.
27.6.8.
Sleep Mode Operation
In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the
configuration in CONFIGn0, CONFIGn1, CONFIGn2, CONFIGn3 register, and the corresponding bit in
the Interrupt Enable Set register (INTENSET) is written to '1'.
Figure 27-3. Wake-up Operation Example (High-Level Detection, No Filter, Interrupt Enable Set)
CLK_EIC_APB
EXTINTx
intwake_extint[x]
intreq_extint[x]
wake from sleep mode
27.6.9.
clear INTFLAG.EXTINT[x]
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
•
•
Software Reset bit in control register (CTRLA.SWRST)
Enable bit in control register (CTRLA.ENABLE)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
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27.7.
Register Summary
Offset
Name
Bit Pos.
0x00
CTRLA
7:0
CKSEL
0x01
NMICTRL
7:0
ASYNCH
0x02
0x03
NMIFLAG
7:0
15:8
31:24
0x08
7:0
0x09
EVCTRL
NMI
ENABLE
15:8
EXTINTEO[15:8]
23:16
EXTINTEO[23:16]
EXTINTEO[31:24]
0x0B
31:24
7:0
EXTINT[7:0]
0x0D
15:8
EXTINT[15:8]
INTENCLR
23:16
EXTINT[23:16]
0x0F
31:24
EXTINT[31:24]
0x10
7:0
EXTINT[7:0]
0x11
15:8
EXTINT[15:8]
23:16
EXTINT[23:16]
0x13
31:24
EXTINT[31:24]
0x14
7:0
EXTINT[7:0]
0x15
15:8
EXTINT[15:8]
0x12
0x16
INTENSET
INTFLAG
23:16
EXTINT[23:16]
0x17
31:24
EXTINT[31:24]
0x18
7:0
ASYNCH[7:0]
0x19
0x1A
ASYNCH
15:8
ASYNCH[15:8]
23:16
ASYNCH[23:16]
0x1B
31:24
0x1C
7:0
FILTEN1
SENSE1[2:0]
FILTEN0
SENSE0[2:0]
0x1D
15:8
FILTEN3
SENSE3[2:0]
FILTEN2
SENSE2[2:0]
0x1E
CONFIGn0
ASYNCH[31:24]
23:16
FILTEN5
SENSE5[2:0]
FILTEN4
SENSE4[2:0]
0x1F
31:24
FILTEN7
SENSE7[2:0]
FILTEN6
SENSE6[2:0]
0x20
7:0
FILTEN1
SENSE1[2:0]
FILTEN0
SENSE0[2:0]
0x21
15:8
FILTEN3
SENSE3[2:0]
FILTEN2
SENSE2[2:0]
23:16
FILTEN5
SENSE5[2:0]
FILTEN4
SENSE4[2:0]
0x23
31:24
FILTEN7
SENSE7[2:0]
FILTEN6
SENSE6[2:0]
0x24
7:0
FILTEN1
SENSE1[2:0]
FILTEN0
SENSE0[2:0]
0x25
15:8
FILTEN3
SENSE3[2:0]
FILTEN2
SENSE2[2:0]
0x22
0x26
CONFIGn1
CONFIGn2
23:16
FILTEN5
SENSE5[2:0]
FILTEN4
SENSE4[2:0]
0x27
31:24
FILTEN7
SENSE7[2:0]
FILTEN6
SENSE6[2:0]
0x28
7:0
FILTEN1
SENSE1[2:0]
FILTEN0
SENSE0[2:0]
0x29
0x2A
0x2B
CONFIGn3
SWRST
EXTINTEO[7:0]
0x0C
0x0E
NMISENSE[2:0]
23:16
0x07
0x0A
SWRST
15:8
0x05
SYNCBUSY
NMIFILTEN
7:0
0x04
0x06
ENABLE
15:8
FILTEN3
SENSE3[2:0]
FILTEN2
SENSE2[2:0]
23:16
FILTEN5
SENSE5[2:0]
FILTEN4
SENSE4[2:0]
31:24
FILTEN7
SENSE7[2:0]
FILTEN6
SENSE6[2:0]
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27.8.
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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27.8.1.
Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized, Enable-Protected
Bit
7
6
5
Access
Reset
1
0
CKSEL
4
3
2
ENABLE
SWRST
R/W
R/W
R/W
0
0
0
Bit 4 – CKSEL: Clock Selection
The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32KHz is required for
filtering) or by CLK_ULP32K (when power consumption is the priority).
This bit is not Write-Synchronized.
Value
Description
0
The EIC is clocked by GCLK_EIC.
1
The EIC is clocked by CLK_ULP32K.
Bit 1 – ENABLE: Enable
Due to synchronization there is a delay between writing to CTRLA.ENABLE until the peripheral is
enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in
the Synchronization Busy register will be set (SYNCBUSY.ENABLE=1). SYNCBUSY.ENABLE will be
cleared when the operation is complete.
This bit is not Enable-Protected.
Value
Description
0
The EIC is disabled.
1
The EIC is enabled.
Bit 0 – SWRST: Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same
write operation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete.
CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.
This bit is not Enable-Protected.
Value
Description
0
There is no ongoing reset operation.
1
The reset operation is ongoing.
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27.8.2.
Non-Maskable Interrupt Control
Name: NMICTRL
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
Access
4
3
ASYNCH
NMIFILTEN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Reset
2
1
0
NMISENSE[2:0]
Bit 4 – ASYNCH: Asynchronous Edge Detection Mode
The NMI edge detection can be operated synchronously or asynchronously to the EIC clock.
Value
Description
0
The NMI edge detection is synchronously operated.
1
The NMI edge detection is asynchronously operated.
Bit 3 – NMIFILTEN: Non-Maskable Interrupt Filter Enable
Value
Description
0
NMI filter is disabled.
1
NMI filter is enabled.
Bits 2:0 – NMISENSE[2:0]: Non-Maskable Interrupt Sense
These bits define on which edge or level the NMI triggers.
Value
Name
Description
0x0
NONE
No detection
0x1
RISE
Rising-edge detection
0x2
FALL
Falling-edge detection
0x3
BOTH
Both-edge detection
0x4
HIGH
High-level detection
0x5
LOW
Low-level detection
0x6 - 0x7 -
Reserved
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27.8.3.
Non-Maskable Interrupt Flag Status and Clear
Name: NMIFLAG
Offset: 0x02
Reset: 0x0000
Property: Bit
15
14
13
12
11
10
9
7
6
5
4
3
2
1
8
Access
Reset
Bit
0
NMI
Access
R/W
Reset
0
Bit 0 – NMI: Non-Maskable Interrupt
This flag is cleared by writing a '1' to it.
This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt
request.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the non-maskable interrupt flag.
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27.8.4.
Synchronization Busy
Name: SYNCBUSY
Offset: 0x04
Reset: 0x00000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
ENABLE
SWRST
Access
R
R
Reset
0
0
Bit 1 – ENABLE: Enable Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.ENABLE bit is complete.
1
Write synchronization for CTRLA.ENABLE bit is ongoing.
Bit 0 – SWRST: Software Reset Synchronization Busy Status
Value
Description
0
Write synchronization for CTRLA.SWRST bit is complete.
1
Write synchronization for CTRLA.SWRST bit is ongoing.
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27.8.5.
Event Control
Name: EVCTRL
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
EXTINTEO[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
EXTINTEO[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
EXTINTEO[15:8]
Access
EXTINTEO[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – EXTINTEO[31:0]: External Interrupt x Event Output
These bits enable the event associated with the EXTINTx pin.
Value
Description
0
Event from pin EXTINTx is disabled.
1
Event from pin EXTINTx is enabled and will be generated when EXTINTx pin matches the
external interrupt sensing configuration.
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27.8.6.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x0C
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
23
22
21
20
26
25
24
R/W
R/W
R/W
R/W
0
0
0
0
19
18
17
16
EXTINT[31:24]
Access
EXTINT[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
EXTINT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
EXTINT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – EXTINT[31:0]: External Interrupt x Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the External Interrupt x Enable bit, which disables the external interrupt.
Value
Description
0
The external interrupt x is disabled.
1
The external interrupt x is enabled.
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27.8.7.
Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
23
22
21
20
26
25
24
R/W
R/W
R/W
R/W
0
0
0
0
19
18
17
16
EXTINT[31:24]
Access
EXTINT[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
EXTINT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
EXTINT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – EXTINT[31:0]: External Interrupt x Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the External Interrupt x Enable bit, which enables the external interrupt.
Value
Description
0
The external interrupt x is disabled.
1
The external interrupt x is enabled.
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27.8.8.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x14
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
EXTINT[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
EXTINT[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
EXTINT[15:8]
Access
EXTINT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – EXTINT[31:0]: External Interrupt x
This flag is cleared by writing a '1' to it.
This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an
interrupt request if INTENCLR/SET.EXTINT[x] is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the External Interrupt x flag.
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27.8.9.
External Interrupt Asynchronous Mode
Name: ASYNCH
Offset: 0x18
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
ASYNCH[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
ASYNCH[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ASYNCH[15:8]
Access
ASYNCH[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – ASYNCH[31:0]: Asynchronous Edge Detection Mode
Value
Description
0
The EXTINT edge detection is synchronously operated.
1
The EXTINT edge detection is asynchronously operated.
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27.8.10. Configuration n
Name: CONFIGn0, CONFIGn1, CONFIGn2, CONFIGn3
Offset: 0x1C + n*0x04 [n=0..3]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
FILTEN7
Access
Reset
Bit
28
27
26
FILTEN6
25
24
SENSE6[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
FILTEN5
Access
29
SENSE7[2:0]
SENSE5[2:0]
FILTEN4
SENSE4[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
FILTEN3
Access
Reset
Bit
SENSE3[2:0]
Reset
SENSE2[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
FILTEN1
Access
FILTEN2
R/W
SENSE1[2:0]
FILTEN0
SENSE0[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 3,7,11,15,19,23,27,31 – FILTENx: Filter x Enable [x = 7..0]
Value
Description
0
Filter is disabled for EXTINT[n*8+1] input.
1
Filter is enabled for EXTINT[n*8+1] input.
Bits 0:2,4:6,8:10,12:14,16:18,20:22,24:26,28:30 – SENSEx: Input Sense x Configuration
These bits define on which edge or level the interrupt or event for EXTINT[n*8+x] will be generated.
Value
Name
Description
0x0
NONE
No detection
0x1
RISE
Rising-edge detection
0x2
FALL
Falling-edge detection
0x3
BOTH
Both-edge detection
0x4
HIGH
High-level detection
0x5
LOW
Low-level detection
0x6 - 0x7 -
Reserved
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28.
NVMCTRL – Non-Volatile Memory Controller
28.1.
Overview
Non-Volatile Memory (NVM) is a reprogrammable Flash memory that retains program and data storage
even with power off. It embeds a main array and a separate smaller array intended for EEPROM
emulation (RWWEE) that can be programmed while reading the main array. The NVM Controller
(NVMCTRL) connects to the AHB and APB bus interfaces for system access to the NVM block. The AHB
interface is used for reads and writes to the NVM block, while the APB interface is used for commands
and configuration.
28.2.
Features
•
•
•
•
•
•
•
•
•
•
•
28.3.
32-bit AHB interface for reads and writes
Read While Write EEPROM emulation area
All NVM sections are memory mapped to the AHB, including calibration and system configuration
32-bit APB interface for commands and control
Programmable wait states for read optimization
16 regions can be individually protected or unprotected
Additional protection for boot loader
Supports device protection through a security bit
Interface to Power Manager for power-down of Flash blocks in sleep modes
Can optionally wake up on exit from sleep or on first access
Direct-mapped cache
Block Diagram
Figure 28-1. Block Diagram
NVMCTRL
AHB
NVM Block
Cache
main array
NVM Interface
APB
Command and
Control
RWWEE array
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28.4.
Signal Description
Not applicable.
28.5.
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described below.
28.5.1.
Power Management
The NVMCTRL will continue to operate in any sleep mode where the selected source clock is running.
The NVMCTRL interrupts can be used to wake up the device from sleep modes.
The Power Manager will automatically put the NVM block into a low-power state when entering sleep
mode. This is based on the Control B register (CTRLB) SLEEPPRM bit setting. Refer to the
CTRLB.SLEEPPRM register description for more details.
Related Links
PM – Power Manager on page 177
28.5.2.
Clocks
Two synchronous clocks are used by the NVMCTRL. One is provided by the AHB bus
(CLK_NVMCTRL_AHB) and the other is provided by the APB bus (CLK_NVMCTRL_APB). For higher
system frequencies, a programmable number of wait states can be used to optimize performance. When
changing the AHB bus frequency, the user must ensure that the NVM Controller is configured with the
proper number of wait states. Refer to the Electrical Characteristics for the exact number of wait states to
be used for a particular frequency range.
Related Links
Electrical Characteristics 85°C on page 900
28.5.3.
Interrupts
The NVM Controller interrupt request line is connected to the interrupt controller. Using the NVMCTRL
interrupt requires the interrupt controller to be programmed first.
28.5.4.
Debug Operation
When an external debugger forces the CPU into debug mode, the peripheral continues normal operation.
Access to the NVM block can be protected by the security bit. In this case, the NVM block will not be
accessible. See the section on the NVMCTRL Security Bit for details.
28.5.5.
Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC),
except the following registers:
•
•
Interrupt Flag Status and Clear register (INTFLAG)
Status register (STATUS)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
Related Links
PAC - Peripheral Access Controller on page 48
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28.5.6.
Analog Connections
Not applicable.
28.6.
Functional Description
28.6.1.
Principle of Operation
The NVM Controller is a slave on the AHB and APB buses. It responds to commands, read requests and
write requests, based on user configuration.
28.6.1.1. Initialization
After power up, the NVM Controller goes through a power-up sequence. During this time, access to the
NVM Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is
operational without any need for user configuration.
28.6.2.
Memory Organization
Refer to the Physical Memory Map for memory sizes and addresses for each device.
The NVM is organized into rows, where each row contains four pages, as shown in the NVM Row
Organization figure. The NVM has a row-erase granularity, while the write granularity is by page. In other
words, a single row erase will erase all four pages in the row, while four write operations are used to write
the complete row.
Figure 28-2. NVM Row Organization
Row n
Page (n*4) + 3
Page (n*4) + 2
Page (n*4) + 1
Page (n*4) + 0
The NVM block contains a calibration and auxiliary space plus a dedicated EEPROM emulation space
that are memory mapped. Refer to the NVM Organization figure below for details.
The calibration and auxiliary space contains factory calibration and system configuration information.
These spaces can be read from the AHB bus in the same way as the main NVM main address space.
In addition, a boot loader section can be allocated at the beginning of the main array, and an EEPROM
section can be allocated at the end of the NVM main address space.
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Figure 28-3. NVM Memory Organization
Calibration and
Auxillary Space
NVM Base Address + 0x00800000
RWWEE
Address Space
NVM Base Address + 0x00400000
NVM Base Address + NVM Size
NVM Main
Address Space
NVM Base Address
The lower rows in the NVM main address space can be allocated as a boot loader section by using the
BOOTPROT fuses, and the upper rows can be allocated to EEPROM, as shown in the figure below.
The boot loader section is protected by the lock bit(s) corresponding to this address space and by the
BOOTPROT[2:0] fuse. The EEPROM rows can be written regardless of the region lock status.
The number of rows protected by BOOTPROT is given in Boot Loader Size, the number of rows allocated
to the EEPROM are given in EEPROM Size.
Figure 28-4. EEPROM and Boot Loader Allocation
NVM Base Address + NVM Size
NVM Base Address + NVM Size - EEPROM Size
Program
Allocation
BOOT
Allocation
NVM Base Address + BOOTPROT Size
NVM Base Address
Related Links
Physical Memory Map on page 37
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28.6.3.
Region Lock Bits
The NVM block is grouped into 16 equally sized regions. The region size is dependent on the Flash
memory size, and is given in the table below. Each region has a dedicated lock bit preventing writing and
erasing pages in the region. After production, all regions will be unlocked.
Table 28-1. Region Size
Memory Size [KB]
Region Size [KB]
256
16
128
8
64
4
32
2
To lock or unlock a region, the Lock Region and Unlock Region commands are provided. Writing one of
these commands will temporarily lock/unlock the region containing the address loaded in the ADDR
register. ADDR can be written by software, or the automatically loaded value from a write operation can
be used. The new setting will stay in effect until the next Reset, or until the setting is changed again using
the Lock and Unlock commands. The current status of the lock can be determined by reading the LOCK
register.
To change the default lock/unlock setting for a region, the user configuration section of the auxiliary space
must be written using the Write Auxiliary Page command. Writing to the auxiliary space will take effect
after the next Reset. Therefore, a boot of the device is needed for changes in the lock/unlock setting to
take effect. Refer to the Physical Memory Map for calibration and auxiliary space address mapping.
Related Links
Physical Memory Map on page 37
28.6.4.
Command and Data Interface
The NVM Controller is addressable from the APB bus, while the NVM main address space is addressable
from the AHB bus. Read and automatic page write operations are performed by addressing the NVM
main address space or the RWWEE address space directly, while other operations such as manual page
writes and row erases must be performed by issuing commands through the NVM Controller.
To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a
command is issued, INTFLAG.READY will be cleared until the command has completed. Any commands
written while INTFLAG.READY is low will be ignored.
Read the CTRLA register description for more details.
The CTRLB register must be used to control the power reduction mode, read wait states, and the write
mode.
28.6.4.1. NVM Read
Reading from the NVM main address space is performed via the AHB bus by addressing the NVM main
address space or auxiliary address space directly. Read data is available after the configured number of
read wait states (CTRLB.RWS) set in the NVM Controller.
The number of cycles data are delayed to the AHB bus is determined by the read wait states. Examples
of using zero and one wait states are shown in Figure Read Wait State Examples below.
Reading the NVM main address space while a programming or erase operation is ongoing on the NVM
main array results in an AHB bus stall until the end of the operation. Reading the NVM main array does
not stall the bus when the RWWEE array is being programmed or erased.
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Figure 28-5. Read Wait State Examples
0 Wait States
AHB Command
Rd 0
Idle
Rd 1
AHB Slave Ready
AHB Slave Data
Data 1
Data 0
1 Wait States
AHB Command
Rd 0
Idle
Rd 1
AHB Slave Ready
AHB Slave Data
Data 0
Data 1
28.6.4.2. RWWEE Read
Reading from the RWW EEPROM address space is performed via the AHB bus by addressing the
RWWEE address space directly. Refer to the figures in Memory Organization for details.
Read timings are similar to regular NVM read timings when access size is Byte or half-Word. The AHB
data phase is twice as long in case of full-Word-size access.
It is not possible to read the RWWEE area while the NVM main array is being written or erased, whereas
the RWWEE area can be written or erased while the main array is being read.
The RWWEE address space is not cached, therefore it is recommended to limit access to this area for
performance and power consumption considerations.
28.6.4.3. NVM Write
The NVM Controller requires that an erase must be done before programming. The entire NVM main
address space and the RWWEE address space can be erased by a debugger Chip Erase command.
Alternatively, rows can be individually erased by the Erase Row command or the RWWEE Erase Row
command to erase the NVM main address space or the RWWEE address space, respectively.
After programming the NVM main array, the region that the page resides in can be locked to prevent
spurious write or erase sequences. Locking is performed on a per-region basis, and so, locking a region
will lock all pages inside the region.
Data to be written to the NVM block are first written to and stored in an internal buffer called the page
buffer. The page buffer contains the same number of bytes as an NVM page. Writes to the page buffer
must be 16 or 32 bits. 8-bit writes to the page buffer are not allowed and will cause a system exception.
Internally, writes to the page buffer are on a 64-bit basis through the page buffer load data register
(PBLDATA1 and PBLDATA0). The PBLDATA register is a holding register for writes to the same 64-bit
page buffer section. Data within a 64-bit section can be written in any order. Crossing a 64-bit boundary
will reset the PBLDATA register to all ones. The following example assumes startup from reset where the
current address is 0 and PBLDATA is all ones. Only 64 bits of the page buffer are written at a time, but
128 bits are shown for reference.
Sequential 32-bit Write Example:
•
32-bit 0x1 written to address 0
– Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, PBLDATA[63:32], 0x00000001}
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•
•
– PBLDATA[63:0] = {PBLDATA[63:32], 0x00000001}
32-bit 0x2 written to address 1
– Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, 0x00000002, PBLDATA[31:0]
– PBLDATA[63:0] = 0x00000002, PBLDATA[31:0]}
32-bit 0x3 written to address 2 (crosses 64-bit boundary)
– Page buffer[127:0] = 0xFFFFFFFF_00000003_00000002_00000001
– PBLDATA[63:0] = 0xFFFFFFFF_00000003
Random access writes to 32-bit words within the page buffer will overwrite the opposite word within the
same 64-bit section with ones. In the following example, notice that 0x00000001 is overwritten with
0xFFFFFFFF from the third write due to the 64-bit boundary crossing. Only 64 bits of the page buffer are
written at a time, but 128 bits are shown for reference.
Random Access 32-bit Write Example:
•
32-bit 0x1 written to address 2
– Page buffer[127:0] = 0xFFFFFFFF_00000001_FFFFFFFF_FFFFFFFF
– PBLDATA[63:0] = 0xFFFFFFFF_00000001
•
32-bit 0x2 written to address 1
– Page buffer[127:0] = 0xFFFFFFFF_00000001_00000002_FFFFFFFF
– PBLDATA[63:0] = 0x00000002_FFFFFFFF
•
32-bit 0x3 written to address 3
– Page buffer[127:0] = 0x00000003_FFFFFFFF_00000002_FFFFFFFF
– PBLDATA[63:0] = 0x00000003_0xFFFFFFFF
Both the NVM main array and the RWWEE array share the same page buffer. Writing to the NVM block
via the AHB bus is performed by a load operation to the page buffer. For each AHB bus write, the address
is stored in the ADDR register. After the page buffer has been loaded with the required number of bytes,
the page can be written to the NVM main array or the RWWEE array by setting CTRLA.CMD to 'Write
Page' or 'RWWEE Write Page', respectively, and setting the key value to CMDEX. The LOAD bit in the
STATUS register indicates whether the page buffer has been loaded or not. Before writing the page to
memory, the accessed row must be erased.
Automatic page writes are enabled by writing the manual write bit to zero (CTRLB.MANW=0). This will
trigger a write operation to the page addressed by ADDR when the last location of the page is written.
Because the address is automatically stored in ADDR during the I/O bus write operation, the last given
address will be present in the ADDR register. There is no need to load the ADDR register manually,
unless a different page in memory is to be written.
Procedure for Manual Page Writes (CTRLB.MANW=1)
The row to be written to must be erased before the write command is given.
•
•
•
Write to the page buffer by addressing the NVM main address space directly
Write the page buffer to memory: CTRL.CMD='Write Page' and CMDEX
The READY bit in the INTFLAG register will be low while programming is in progress, and access
through the AHB will be stalled
Procedure for Automatic Page Writes (CTRLB.MANW=0)
The row to be written to must be erased before the last write to the page buffer is performed.
Note that partially written pages must be written with a manual write.
•
Write to the page buffer by addressing the NVM main address space directly.
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•
When the last location in the page buffer is written, the page is automatically written to NVM main
address space.
INTFLAG.READY will be zero while programming is in progress and access through the AHB will
be stalled.
28.6.4.4. Page Buffer Clear
The page buffer is automatically set to all '1' after a page write is performed. If a partial page has been
written and it is desired to clear the contents of the page buffer, the Page Buffer Clear command can be
used.
28.6.4.5. Erase Row
Before a page can be written, the row containing that page must be erased. The Erase Row command
can be used to erase the desired row in the NVM main address space. The RWWEE Erase Row can be
used to erase the desired row in the RWWEE array. Erasing the row sets all bits to '1'. If the row resides
in a region that is locked, the erase will not be performed and the Lock Error bit in the Status register
(STATUS.LOCKE) will be set.
Procedure for Erase Row
•
•
Write the address of the row to erase to ADDR. Any address within the row can be used.
Issue an Erase Row command.
28.6.4.6. Lock and Unlock Region
These commands are used to lock and unlock regions as detailed in section Region Lock Bits.
28.6.4.7. Set and Clear Power Reduction Mode
The NVM Controller and block can be taken in and out of power reduction mode through the Set and
Clear Power Reduction Mode commands. When the NVM Controller and block are in power reduction
mode, the Power Reduction Mode bit in the Status register (STATUS.PRM) is set.
28.6.5.
NVM User Configuration
The NVM user configuration resides in the auxiliary space. Refer to the Physical Memory Map of the
device for calibration and auxiliary space address mapping.
The bootloader resides in the main array starting at offset zero. The allocated boot loader section is writeprotected.
Table 28-2. Boot Loader Size
BOOTPROT [2:0]
Rows Protected by BOOTPROT
Boot Loader Size in Bytes
0x7(1)
None
0
0x6
2
512
0x5
4
1024
0x4
8
2048
0x3
16
4096
0x2
32
8192
0x1
64
16384
0x0
128
32768
Note: 1) Default value is 0x7.
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The EEPROM[2:0] bits indicate the EEPROM size, see the table below. The EEPROM resides in the
upper rows of the NVM main address space and is writable, regardless of the region lock status.
Table 28-3. EEPROM Size
EEPROM[2:0]
Rows Allocated to EEPROM
EEPROM Size in Bytes
7
None
0
6
1
256
5
2
512
4
4
1024
3
8
2048
2
16
4096
1
32
8192
0
64
16384
Related Links
Physical Memory Map on page 37
28.6.6.
Security Bit
The security bit allows the entire chip to be locked from external access for code security. The security bit
can be written by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the
security bit is through a debugger Chip Erase command. After issuing the SSB command, the PROGE
error bit can be checked.
In order to increase the security level it is recommended to enable the internal BODVDD when the
security bit is set.
Related Links
DSU - Device Service Unit on page 71
28.6.7.
Cache
The NVM Controller cache reduces the device power consumption and improves system performance
when wait states are required. Only the NVM main array address space is cached. It is a direct-mapped
cache that implements 8 lines of 64 bits (i.e., 64 Bytes). NVM Controller cache can be enabled by writing
a '0' to the Cache Disable bit in the Control B register (CTRLB.CACHEDIS).
The cache can be configured to three different modes using the Read Mode bit group in the Control B
register (CTRLB.READMODE).
The INVALL command can be issued using the Command bits in the Control A register to invalidate all
cache lines (CTRLA.CMD=INVALL). Commands affecting NVM content automatically invalidate cache
lines.
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28.7.
Offset
0x00
0x01
Register Summary
Name
CTRLA
Bit Pos.
7:0
CMD[6:0]
15:8
CMDEX[7:0]
0x02
...
Reserved
0x03
0x04
7:0
0x05
15:8
0x06
CTRLB
0x07
MANW
RWS[3:0]
SLEEPPRM[1:0]
23:16
CACHEDIS[1:0]
0x08
7:0
NVMP[7:0]
0x09
15:8
NVMP[15:8]
0x0A
PARAM
0x0B
0x0C
READMODE[1:0]
31:24
23:16
31:24
INTENCLR
RWWEEP[3:0]
PSZ[2:0]
RWWEEP[11:4]
7:0
ERROR
READY
7:0
ERROR
READY
7:0
ERROR
READY
LOAD
PRM
0x0D
...
Reserved
0x0F
0x10
INTENSET
0x11
...
Reserved
0x13
0x14
INTFLAG
0x15
...
Reserved
0x17
0x18
0x19
STATUS
7:0
NVME
LOCKE
PROGE
15:8
SB
0x1A
...
Reserved
0x1B
0x1C
0x1D
0x1E
7:0
ADDR
0x1F
0x20
0x21
15:8
23:16
31:24
LOCK
7:0
LOCK[7:0]
15:8
LOCK[15:8]
0x22
...
Reserved
0x27
0x28
7:0
PBLDATA[7:0]
0x29
15:8
PBLDATA[15:8]
23:16
PBLDATA[23:16]
31:24
PBLDATA[31:24]
0x2A
0x2B
PBLDATA0
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Offset
Name
Bit Pos.
0x2C
7:0
PBLDATA[7:0]
0x2D
15:8
PBLDATA[15:8]
23:16
PBLDATA[23:16]
31:24
PBLDATA[31:24]
0x2E
0x2F
28.8.
PBLDATA1
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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28.8.1.
Control A
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
Reset
0
0
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CMDEX[7:0]
Access
CMD[6:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Reset
Bits 15:8 – CMDEX[7:0]: Command Execution
When this bit group is written to the key value 0xA5, the command written to CMD will be executed. If a
value different from the key value is tried, the write will not be performed and the PROGE status bit will
set. PROGE is also set if a previously written command is not completed yet.
The key value must be written at the same time as CMD. If a command is issued through the APB bus on
the same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then
be executed when the NVM block and the AHB bus are idle.
INTFLAG.READY must be '1' when the command is issued.
Bit 0 of the CMDEX bit group will read back as '1' until the command is issued.
Bits 6:0 – CMD[6:0]: Command
These bits define the command to be executed when the CMDEX key is written.
CMD[6:0]
Group Configuration Description
0x00-0x01 -
Reserved
0x02
ER
Erase Row - Erases the row addressed by the ADDR register in the
NVM main array.
0x03
-
Reserved
0x04
WP
Write Page - Writes the contents of the page buffer to the page
addressed by the ADDR register.
0x05
EAR
Erase Auxiliary Row - Erases the auxiliary row addressed by the
ADDR register. This command can be given only when the security
bit is not set and only to the User Configuration Row.
0x06
WAP
Write Auxiliary Page - Writes the contents of the page buffer to the
page addressed by the ADDR register. This command can be given
only when the security bit is not set and only to the User
Configuration Row.
0x07-0x0E -
Reserved
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CMD[6:0]
Group Configuration Description
0x0F
WL
Write Lockbits- write the LOCK register
0x1A-0x19 -
Reserved
0x1A
RWWEEER
RWWEE Erase Row - Erases the row addressed by the ADDR
register in the RWWEE array.
0x1B
-
Reserved
0x1C
RWWEEWP
RWWEE Write Page - Writes the contents of the page buffer to the
page addressed by the ADDR register in the RWWEE array.
0x1D-0x3F -
Reserved
0x40
LR
Lock Region - Locks the region containing the address location in
the ADDR register.
0x41
UR
Unlock Region - Unlocks the region containing the address location
in the ADDR register.
0x42
SPRM
Sets the Power Reduction Mode.
0x43
CPRM
Clears the Power Reduction Mode.
0x44
PBC
Page Buffer Clear - Clears the page buffer.
0x45
SSB
Set Security Bit - Sets the security bit by writing 0x00 to the first
byte in the lockbit row.
0x46
INVALL
Invalidates all cache lines.
0x47-0x7F -
Reserved
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28.8.2.
Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000080
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
Reset
Bit
CACHEDIS[1:0]
Access
Reset
Bit
15
14
13
12
READMODE[1:0]
R/W
R/W
R/W
R/W
0
0
0
0
11
10
9
8
SLEEPPRM[1:0]
Access
R/W
R/W
0
0
2
1
0
Reset
Bit
7
6
5
4
3
MANW
Access
Reset
RWS[3:0]
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
Bits 19:18 – CACHEDIS[1:0]: Cache Disable
These bits are used to enable/disable caching of the NVM and RWW EEPROM sections. The same
cache is used for both sections.
Table 28-4. Cache Disabled
CACHEDIS[1:0]
RWW EEPROM
NVM Cache
0x0
Disabled
Enabled
0x1
Disabled
Disabled
0x2
Enabled
Enabled
0x3
Reserved
Reserved
Value
Description
0
The cache is enabled
1
The cache is disabled
Bits 17:16 – READMODE[1:0]: NVMCTRL Read Mode
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Value
Name
Description
0x0
NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a
cache miss. Gives the best system performance.
0x1
LOW_POWER
Reduces power consumption of the cache system, but inserts a wait
state each time there is a cache miss. This mode may not be relevant
if CPU performance is required, as the application will be stalled and
may lead to increased run time.
0x2
DETERMINISTIC
The cache system ensures that a cache hit or miss takes the same
amount of time, determined by the number of programmed Flash wait
states. This mode can be used for real-time applications that require
deterministic execution timings.
0x3
Reserved
Bits 9:8 – SLEEPPRM[1:0]: Power Reduction Mode during Sleep
Indicates the Power Reduction Mode during sleep.
Value
Name
Description
0x0
WAKEUPACCESS
NVM block enters low-power mode when entering sleep.
NVM block exits low-power mode upon first access.
0x1
WAKEUPINSTANT
NVM block enters low-power mode when entering sleep.
NVM block exits low-power mode when exiting sleep.
0x2
Reserved
0x3
DISABLED
Auto power reduction disabled.
Bit 7 – MANW: Manual Write
Note that reset value of this bit is '1'.
Value
Description
0
Writing to the last word in the page buffer will initiate a write operation to the page addressed
by the last write operation. This includes writes to memory and auxiliary rows.
1
Write commands must be issued through the CTRLA.CMD register.
Bits 4:1 – RWS[3:0]: NVM Read Wait States
These bits control the number of wait states for a read operation. '0' indicates zero wait states, '1'
indicates one wait state, etc., up to 15 wait states.
This register is initialized to 0 wait states. Software can change this value based on the NVM access time
and system frequency.
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28.8.3.
NVM Parameter
Name: PARAM
Offset: 0x08
Reset: 0x000XXXXX
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
RWWEEP[11:4]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RWWEEP[3:0]
PSZ[2:0]
Access
R
R
R
R
R
R
R
Reset
0
0
0
0
x
x
x
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
x
x
x
x
x
x
x
x
Bit
7
6
5
4
3
2
1
0
NVMP[15:8]
NVMP[7:0]
Access
R
R
R
R
R
R
R
R
Reset
x
x
x
x
x
x
x
x
Bits 31:20 – RWWEEP[11:0]: Read While Write EEPROM emulation area Pages
Indicates the number of pages in the RWW EEPROM emulation address space.
Bits 18:16 – PSZ[2:0]: Page Size
Indicates the page size. Not all devices of the device families will provide all the page sizes indicated in
the table.
Value
Name
Description
0x0
8
8 bytes
0x1
16
16 bytes
0x2
32
32 bytes
0x3
64
64 bytes
0x4
128
128 bytes
0x5
256
256 bytes
0x6
512
512 bytes
0x7
1024
1024 bytes
Bits 15:0 – NVMP[15:0]: NVM Pages
Indicates the number of pages in the NVM main address space.
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28.8.4.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
Access
Reset
1
0
ERROR
READY
R/W
R/W
0
0
Bit 1 – ERROR: Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
Bit 0 – READY: NVM Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
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28.8.5.
Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x10
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
Access
Reset
1
0
ERROR
READY
R/W
R/W
0
0
Bit 1 – ERROR: Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit sets the ERROR interrupt enable.
This bit will read as the current value of the ERROR interrupt enable.
Bit 0 – READY: NVM Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit sets the READY interrupt enable.
This bit will read as the current value of the READY interrupt enable.
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28.8.6.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x14
Reset: 0x00
Property: –
Bit
7
6
5
4
3
2
Access
Reset
1
0
ERROR
READY
R/W
R
0
0
Bit 1 – ERROR: Error
This flag is set on the occurrence of an NVME, LOCKE or PROGE error.
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
No errors have been received since the last clear.
1
At least one error has occurred since the last clear.
Bit 0 – READY: NVM Ready
Value
Description
0
The NVM controller is busy programming or erasing.
1
The NVM controller is ready to accept a new command.
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28.8.7.
Status
Name: STATUS
Offset: 0x18
Reset: 0x0X00
Property: –
Bit
15
14
13
12
11
10
9
8
SB
Access
R
Reset
x
Bit
7
6
5
Access
Reset
4
3
2
1
0
NVME
LOCKE
PROGE
LOAD
PRM
R/W
R/W
R/W
R/W
R
0
0
0
0
0
Bit 8 – SB: Security Bit Status
Value
Description
0
The Security bit is inactive.
1
The Security bit is active.
Bit 4 – NVME: NVM Error
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
No programming or erase errors have been received from the NVM controller since this bit
was last cleared.
1
At least one error has been registered from the NVM Controller since this bit was last
cleared.
Bit 3 – LOCKE: Lock Error Status
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
No programming of any locked lock region has happened since this bit was last cleared.
1
Programming of at least one locked lock region has happened since this bit was last cleared.
Bit 2 – PROGE: Programming Error Status
This bit can be cleared by writing a '1' to its bit location.
Value
Description
0
No invalid commands or bad keywords were written in the NVM Command register since this
bit was last cleared.
1
An invalid command and/or a bad keyword was/were written in the NVM Command register
since this bit was last cleared.
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Bit 1 – LOAD: NVM Page Buffer Active Loading
This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after
an NVM load has been performed, this flag is set. It remains set until a page write or a page buffer clear
(PBCLR) command is given.
This bit can be cleared by writing a '1' to its bit location.
Bit 0 – PRM: Power Reduction Mode
This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction
mode in two ways: through the command interface or automatically when entering sleep with SLEEPPRM
set accordingly.
PRM can be cleared in three ways: through AHB access to the NVM block, through the command
interface (SPRM and CPRM) or when exiting sleep with SLEEPPRM set accordingly.
Value
Description
0
NVM is not in power reduction mode.
1
NVM is in power reduction mode.
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28.8.8.
Address
Name: ADDR
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
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28.8.9.
Lock Section
Name: LOCK
Offset: 0x20
Reset: 0xXXXX
Property: –
Bit
15
14
13
12
11
10
9
8
LOCK[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
LOCK[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
x
Bits 15:0 – LOCK[15:0]: Region Lock Bits
In order to set or clear these bits, the CMD register must be used.
Default state after erase will be unlocked (0x0000).
Value
Description
0
The corresponding lock region is locked.
1
The corresponding lock region is not locked.
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28.8.10. Page Buffer Load Data 0
Name: PBLDATA0
Offset: 0x28
Reset: 0xFFFFFFFF
Property: Bit
31
30
29
28
27
26
25
24
PBLDATA[31:24]
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
1
1
Bit
23
22
21
20
19
18
17
16
PBLDATA[23:16]
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
1
1
Bit
7
6
5
4
3
2
1
0
PBLDATA[15:8]
PBLDATA[7:0]
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
1
1
Bits 31:0 – PBLDATA[31:0]: Page Buffer Load Data
The PBLDATA register is a holding register for partial AHB writes to the same 64-bit page buffer section.
Page buffer loads are performed on a 64-bit basis.
This is a read only register.
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28.8.11. Page Buffer Load Data 1
Name: PBLDATA1
Offset: 0x2C
Reset: 0xFFFFFFFF
Property: Bit
31
30
29
28
27
26
25
24
PBLDATA[31:24]
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
1
1
Bit
23
22
21
20
19
18
17
16
PBLDATA[23:16]
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
1
1
Bit
7
6
5
4
3
2
1
0
PBLDATA[15:8]
PBLDATA[7:0]
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
1
1
Bits 31:0 – PBLDATA[31:0]: Page Buffer Load Data (Bits 63:32])Once the dimension element
functions are supported the bit descrioption must be updated to bit names becomes
PBLDATA[63:32] in the register table.
The PBLDATA register is a holding register for partial AHB writes to the same 64-bit page buffer section.
Page buffer loads are performed on a 64-bit basis.
This is a read only register.
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29.
PORT - I/O Pin Controller
29.1.
Overview
The IO Pin Controller (PORT) controls the I/O pins of the device. The I/O pins are organized in a series of
groups, collectively referred to as a PORT group. Each PORT group can have up to 32 pins that can be
configured and controlled individually or as a group. The number of PORT groups on a device may
depend on the package/number of pins. Each pin may either be used for general-purpose I/O under direct
application control or be assigned to an embedded device peripheral. When used for general-purpose
I/O, each pin can be configured as input or output, with highly configurable driver and pull settings.
All I/O pins have true read-modify-write functionality when used for general-purpose I/O; the direction or
the output value of one or more pins may be changed (set, reset or toggled) explicitly without
unintentionally changing the state of any other pins in the same port group by a single, atomic 8-, 16- or
32-bit write.
The PORT is connected to the high-speed bus matrix through an AHB/APB bridge. The Pin Direction,
Data Output Value and Data Input Value registers may also be accessed using the low-latency CPU local
bus (IOBUS; ARM® single-cycle I/O port).
29.2.
Features
•
•
•
•
•
•
•
Selectable input and output configuration for each individual pin
Software-controlled multiplexing of peripheral functions on I/O pins
Flexible pin configuration through a dedicated Pin Configuration register
Configurable output driver and pull settings:
– Totem-pole (push-pull)
– Pull configuration
– Driver strength
Configurable input buffer and pull settings:
– Internal pull-up or pull-down
– Input sampling criteria
– Input buffer can be disabled if not needed for lower power consumption
Input event:
– Up to four input event pins for each PORT group
– SET/CLEAR/TOGGLE event actions for each event input on output value of a pin
– Can be output to pin
Power saving using STANDBY mode
– No access to configuration registers
– Possible access to data registers (DIR, OUT or IN)
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29.3.
Block Diagram
Figure 29-1. PORT Block Diagram
PORT
Peripheral Mux Select
Control
Status
Port Line
Bundles
IP Line Bundles
Pad Line
Bundles
PORTMUX
and
I/O
PADS
Analog Pad
Connections
PERIPHERALS
Digital Controls of Analog Blocks
29.4.
ANALOG
BLOCKS
Signal Description
Table 29-1. Signal description for PORT
Signal name
Type
Description
Pxy
Digital I/O
General-purpose I/O pin y in group x
Refer to the I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One
signal can be mapped on several pins.
Related Links
I/O Multiplexing and Considerations on page 28
29.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly as following.
29.5.1.
I/O Lines
The I/O lines of the PORT are mapped to pins of the physical device. The following naming scheme is
used:
Each line bundle with up to 32 lines is assigned an identifier 'xy', with letter x=A, B, C… and two-digit
number y=00, 01, …31. Examples: A24, C03.
PORT pins are labeled 'Pxy' accordingly, for example PA24, PC03. This identifies each pin in the device
uniquely.
Each pin may be controlled by one or more peripheral multiplexer settings, which allow the pad to be
routed internally to a dedicated peripheral function. When the setting is enabled, the selected peripheral
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has control over the output state of the pad, as well as the ability to read the current physical pad state.
Refer to I/O Multiplexing and Considerations for details.
Device-specific configurations may cause some lines (and the corresponding Pxy pin) not to be
implemented.
Related Links
I/O Multiplexing and Considerations on page 28
29.5.2.
Power Management
During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
If the PORT peripheral is shut down, the latches in the pad will keep their current configuration in any
sleep mode, such as the output value and pull settings. However, the PORT configuration registers and
input synchronizers will lose their contents, and these will not be restored when PORT is powered up
again. Therefore, user must reconfigure the PORT peripheral at power-up to ensure it is in a well-defined
state before use.
The PORT will continue operating in any sleep mode where the selected module source clock is running
because the selected module source clock is still running.
29.5.3.
Clocks
The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Main Clock module, and the
default state of CLK_PORT_APB can be found in the Peripheral Clock Masking section in MCLK – Main
Clock.
The PORT is fed by two different clocks: a CPU main clock, which allows the CPU to access the PORT
through the low latency CPU local bus (IOBUS); an APB clock, which is a divided clock of the CPU main
clock and allows the CPU to access the registers of PORT through the high-speed matrix and the
AHB/APB bridge.
The priority of IOBUS accesses is higher than event accesses and APB accesses. The EVSYS and APB
will insert wait states in the event of concurrent PORT accesses.
The PORT input synchronizers use the CPU main clock so that the resynchronization delay is minimized
with respect to the APB clock.
Related Links
MCLK – Main Clock on page 149
29.5.4.
DMA
Not applicable.
29.5.5.
Interrupts
Not applicable.
29.5.6.
Events
The events of this peripheral are connected to the Event System.
Related Links
EVSYS – Event System on page 487
29.5.7.
Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
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data loss may result during debugging. This peripheral can be forced to halt operation during debugging refer to the Debug Control (DBGCTRL) register for details.
29.5.8.
Register Access Protection
All registers with write-access can be optionally write-protected by the Peripheral Access Controller
(PAC).
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection
does not apply for accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
29.5.9.
Analog Connections
Analog functions are connected directly between the analog blocks and the I/O pads using analog buses.
However, selecting an analog peripheral function for a given pin will disable the corresponding digital
features of the pad.
29.5.10. CPU Local Bus
The CPU local bus (IOBUS) is an interface that connects the CPU directly to the PORT. It is a singlecycle bus interface, which does not support wait states. It supports 8-bit, 16-bit and 32-bit sizes.
This bus is generally used for low latency operation. The Data Direction (DIR) and Data Output Value
(OUT) registers can be read, written, set, cleared or be toggled using this bus, and the Data Input Value
(IN) registers can be read.
Since the IOBUS cannot wait for IN register resynchronization, the Control register (CTRL) must be
configured to continuous sampling of all pins that need to be read via the IOBUS in order to prevent stale
data from being read.
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29.6.
Functional Description
Figure 29-2. Overview of the PORT
PORT
PAD
PULLEN
PULLENx
DRIVE
DRIVEx
Pull
Resistor
PG
OUT
OUTx
PAD
APB Bus
VDD
OE
DIRx
INEN
INENx
INx
NG
IN
Q
D
R
Q
D
R
Synchronizer
Input to Other Modules
29.6.1.
Analog Input/Output
Principle of Operation
Each PORT group of up to 32 pins is controlled by the registers in PORT, as described in the figure.
These registers in PORT are duplicated for each PORT group, with increasing base addresses. The
number of PORT groups may depend on the package/number of pins.
Figure 29-3. Overview of the peripheral functions multiplexing
PORTMUX
PORT bit y
Port y PINCFG
PMUXEN
Port y
Data+Config
Port y
PMUX[3:0]
Port y Peripheral
Mux Enable
Port y Line Bundle
0
Port y PMUX Select
Pad y
PAD y
Line Bundle
Periph Signal 0
0
Periph Signal 1
1
1
Peripheral Signals to
be muxed to Pad y
Periph Signal 15
15
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The I/O pins of the device are controlled by PORT peripheral registers. Each port pin has a corresponding
bit in the Data Direction (DIR) and Data Output Value (OUT) registers to enable that pin as an output and
to define the output state.
The direction of each pin in a PORT group is configured by the DIR register. If a bit in DIR is set to '1', the
corresponding pin is configured as an output pin. If a bit in DIR is set to '0', the corresponding pin is
configured as an input pin.
When the direction is set as output, the corresponding bit in the OUT register will set the level of the pin. If
bit y in OUT is written to '1', pin y is driven HIGH. If bit y in OUT is written to '0', pin y is driven LOW. Pin
configuration can be set by Pin Configuration (PINCFGy) registers, with y=00, 01, ..31 representing the
bit position.
The Data Input Value (IN) is set as the input value of a port pin with resynchronization to the PORT clock.
To reduce power consumption, these input synchronizers are clocked only when system requires reading
the input value. The value of the pin can always be read, whether the pin is configured as input or output.
If the Input Enable bit in the Pin Configuration registers (PINCFGy.INEN) is '0', the input value will not be
sampled.
In PORT, the Peripheral Multiplexer Enable bit in the PINCFGy register (PINCFGy.PMUXEN) can be
written to '1' to enable the connection between peripheral functions and individual I/O pins. The Peripheral
Multiplexing n (PMUXn) registers select the peripheral function for the corresponding pin. This will
override the connection between the PORT and that I/O pin, and connect the selected peripheral signal to
the particular I/O pin instead of the PORT line bundle.
29.6.2.
Basic Operation
29.6.2.1. Initialization
After reset, all standard function device I/O pads are connected to the PORT with outputs tri-stated and
input buffers disabled, even if there is no clock running.
However, specific pins, such as those used for connection to a debugger, may be configured differently,
as required by their special function.
29.6.2.2. Operation
Each I/O pin y can be controlled by the registers in PORT. Each PORT group has its own set of PORT
registers, the base address of the register set for pin y is at byte address PORT + ([y] * 0x4). The index
within that register set is [y].
To use pin number y as an output, write bit y of the DIR register to '1'. This can also be done by writing bit
y in the DIRSET register to '1' - this will avoid disturbing the configuration of other pins in that group. The
y bit in the OUT register must be written to the desired output value.
Similarly, writing an OUTSET bit to '1' will set the corresponding bit in the OUT register to '1'. Writing a bit
in OUTCLR to '1' will set that bit in OUT to zero. Writing a bit in OUTTGL to '1' will toggle that bit in OUT.
To use pin y as an input, bit y in the DIR register must be written to '0'. This can also be done by writing
bit y in the DIRCLR register to '1' - this will avoid disturbing the configuration of other pins in that group.
The input value can be read from bit y in register IN as soon as the INEN bit in the Pin Configuration
register (PINCFGy.INEN) is written to '1'.
Refer to I/O Multiplexing and Considerations for details on pin configuration and PORT groups.
By default, the input synchronizer is clocked only when an input read is requested. This will delay the
read operation by two CLK_PORT cycles. To remove the delay, the input synchronizers for each PORT
group of eight pins can be configured to be always active, but this will increase power consumption. This
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is enabled by writing '1' to the corresponding SAMPLINGn bit field of the CTRL register, see
CTRL.SAMPLING for details.
To use pin y as one of the available peripheral functions, the corresponding PMUXEN bit of the PINCFGy
register must be '1'. The PINCFGy register for pin y is at byte offset (PINCFG0 + [y]).
The peripheral function can be selected by setting the PMUXO or PMUXE in the PMUXn register. The
PMUXO/PMUXE is at byte offset PMUX0 + (y/2). The chosen peripheral must also be configured and
enabled.
Related Links
I/O Multiplexing and Considerations on page 28
29.6.3.
I/O Pin Configuration
The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in
a totem-pole or pull configuration.
As pull configuration is done through the Pin Configuration register, all intermediate PORT states during
switching of pin direction and pin values are avoided.
The I/O pin configurations are described further in this chapter, and summarized in Table 29-2 Pin
Configurations Summary.
29.6.3.1. Pin Configurations Summary
Table 29-2. Pin Configurations Summary
DIR
INEN
PULLEN
OUT
Configuration
0
0
0
X
Reset or analog I/O: all digital disabled
0
0
1
0
Pull-down; input disabled
0
0
1
1
Pull-up; input disabled
0
1
0
X
Input
0
1
1
0
Input with pull-down
0
1
1
1
Input with pull-up
1
0
X
X
Output; input disabled
1
1
X
X
Output; input enabled
29.6.3.2. Input Configuration
Figure 29-4. I/O configuration - Standard Input
PULLEN
PULLEN
INEN
DIR
0
1
0
DIR
OUT
IN
INEN
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Figure 29-5. I/O Configuration - Input with Pull
PULLEN
PULLEN
INEN
DIR
1
1
0
DIR
OUT
IN
INEN
Note: When pull is enabled, the pull value is defined by the OUT value.
29.6.3.3. Totem-Pole Output
When configured for totem-pole (push-pull) output, the pin is driven low or high according to the
corresponding bit setting in the OUT register. In this configuration there is no current limitation for sink or
source other than what the pin is capable of. If the pin is configured for input, the pin will float if no
external pull is connected.
Note: Enabling the output driver will automatically disable pull.
Figure 29-6. I/O Configuration - Totem-Pole Output with Disabled Input
PULLEN
PULLEN
INEN
DIR
0
0
1
PULLEN
INEN
DIR
0
1
1
PULLEN
INEN
DIR
1
0
0
DIR
OUT
IN
INEN
Figure 29-7. I/O Configuration - Totem-Pole Output with Enabled Input
PULLEN
DIR
OUT
IN
INEN
Figure 29-8. I/O Configuration - Output with Pull
PULLEN
DIR
OUT
IN
INEN
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29.6.3.4. Digital Functionality Disabled
Neither Input nor Output functionality are enabled.
Figure 29-9. I/O Configuration - Reset or Analog I/O: Digital Output, Input and Pull Disabled
PULLEN
PULLEN
INEN
DIR
0
0
0
DIR
OUT
IN
INEN
29.6.4.
Events
The PORT allows input events to control individual I/O pins. These input events are generated by the
EVSYS module and can originate from a different clock domain than the PORT module.
The PORT can perform the following actions:
•
•
•
•
Output (OUT): I/O pin will be set when the incoming event has a high level ('1') and cleared when
the incoming event has a low-level ('0').
Set (SET): I/O pin will be set when an incoming event is detected.
Clear (CLR): I/O pin will be cleared when an incoming event is detected.
Toggle (TGL): I/O pin will toggle when an incoming event is detected.
The event is output to pin without any internal latency. For SET, CLEAR and TOGGLE event actions, the
action will be executed up to three clock cycles after a rising edge.
The event actions can be configured with the Event Action m bit group in the Event Input Control
register( EVCTRL.EVACTm). Writing a '1' to a PORT Event Enable Input m of the Event Control register
(EVCTRL.PORTEIm) enables the corresponding action on input event. Writing '0' to this bit disables the
corresponding action on input event. Note that several actions can be enabled for incoming events. If
several events are connected to the peripheral, any enabled action will be taken for any of the incoming
events. Refer to EVSYS – Event System. for details on configuring the Event System.
Each event input can address one and only one I/O pin at a time. The selection of the pin is indicated by
the PORT Event Pin Identifier of the Event Input Control register (EVCTR.PIDn). On the other hand, one
I/O pin can be addressed by up to four different input events. To avoid action conflict on the output value
of the register (OUT) of this particular I/O pin, only one action is performed according to the table below.
Note that this truth table can be applied to any SET/CLR/TGL configuration from two to four active input
events.
Table 29-3. Priority on Simultaneous SET/CLR/TGL Event Actions
EVACT0
EVACT1
EVACT2
EVACT3
Executed Event Action
SET
SET
SET
SET
SET
CLR
CLR
CLR
CLR
CLR
All Other Combinations
TGL
Be careful when the event is output to pin. Due to the fact the events are received asynchronously, the
I/O pin may have unpredictable levels, depending on the timing of when the events are received. When
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several events are output to the same pin, the lowest event line will get the access. All other events will
be ignored.
Related Links
EVSYS – Event System on page 487
29.6.5.
PORT Access Priority
The PORT is accessed by different systems:
•
•
•
The ARM® CPU through the ARM® single-cycle I/O port (IOBUS)
The ARM® CPU through the high-speed matrix and the AHB/APB bridge (APB)
EVSYS through four asynchronous input events
The following priority is adopted:
1.
2.
3.
ARM® CPU IOBUS (No wait tolerated)
APB
EVSYS input events
For input events that require different actions on the same I/O pin, refer to Events.
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29.7.
Offset
Register Summary
Name
0x00
0x01
0x02
Bit Pos.
7:0
DIR
DIR[7:0]
15:8
DIR[15:8]
23:16
DIR[23:16]
0x03
31:24
DIR[31:24]
0x04
7:0
DIRCLR[7:0]
15:8
DIRCLR[15:8]
0x05
0x06
DIRCLR
23:16
DIRCLR[23:16]
0x07
31:24
DIRCLR[31:24]
0x08
7:0
DIRSET[7:0]
0x09
0x0A
DIRSET
15:8
DIRSET[15:8]
23:16
DIRSET[23:16]
DIRSET[31:24]
0x0B
31:24
0x0C
7:0
DIRTGL[7:0]
0x0D
15:8
DIRTGL[15:8]
0x0E
DIRTGL
23:16
DIRTGL[23:16]
0x0F
31:24
DIRTGL[31:24]
0x10
7:0
OUT[7:0]
0x11
0x12
OUT
15:8
OUT[15:8]
23:16
OUT[23:16]
0x13
31:24
OUT[31:24]
0x14
7:0
OUTCLR[7:0]
15:8
OUTCLR[15:8]
0x15
0x16
OUTCLR
23:16
OUTCLR[23:16]
0x17
31:24
OUTCLR[31:24]
0x18
7:0
OUTSET[7:0]
0x19
0x1A
OUTSET
15:8
OUTSET[15:8]
23:16
OUTSET[23:16]
OUTSET[31:24]
0x1B
31:24
0x1C
7:0
OUTTGL[7:0]
0x1D
15:8
OUTTGL[15:8]
0x1E
OUTTGL
23:16
OUTTGL[23:16]
0x1F
31:24
OUTTGL[31:24]
0x20
7:0
IN[7:0]
0x21
0x22
IN
15:8
IN[15:8]
23:16
IN[23:16]
0x23
31:24
IN[31:24]
0x24
7:0
SAMPLING[7:0]
15:8
SAMPLING[15:8]
0x25
0x26
CTRL
23:16
SAMPLING[23:16]
0x27
31:24
SAMPLING[31:24]
0x28
7:0
PINMASK[7:0]
0x29
0x2A
0x2B
WRCONFIG
15:8
PINMASK[15:8]
23:16
31:24
DRVSTR
HWSEL
WRPINCFG
PULLEN
WRPMUX
INEN
PMUXEN
PMUX[3:0]
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Offset
Name
Bit Pos.
0x2C
7:0
PORTEI0
EVACT0[1:0]
PID0[4:0]
0x2D
15:8
PORTEI1
EVACT1[1:0]
PID1[4:0]
23:16
PORTEI2
EVACT2[1:0]
PID2[4:0]
31:24
PORTEI3
EVACT3[1:0]
PID3[4:0]
0x2E
EVCTRL
0x2F
0x30
PMUXn0
7:0
PMUXO[3:0]
PMUXE[3:0]
0x31
PMUXn1
7:0
PMUXO[3:0]
PMUXE[3:0]
0x32
PMUXn2
7:0
PMUXO[3:0]
PMUXE[3:0]
0x33
PMUXn3
7:0
PMUXO[3:0]
PMUXE[3:0]
0x34
PMUXn4
7:0
PMUXO[3:0]
PMUXE[3:0]
0x35
PMUXn5
7:0
PMUXO[3:0]
PMUXE[3:0]
0x36
PMUXn6
7:0
PMUXO[3:0]
PMUXE[3:0]
0x37
PMUXn7
7:0
PMUXO[3:0]
PMUXE[3:0]
0x38
PMUXn8
7:0
PMUXO[3:0]
PMUXE[3:0]
0x39
PMUXn9
7:0
PMUXO[3:0]
PMUXE[3:0]
0x3A
PMUXn10
7:0
PMUXO[3:0]
PMUXE[3:0]
0x3B
PMUXn11
7:0
PMUXO[3:0]
PMUXE[3:0]
0x3C
PMUXn12
7:0
PMUXO[3:0]
PMUXE[3:0]
0x3D
PMUXn13
7:0
PMUXO[3:0]
PMUXE[3:0]
0x3E
PMUXn14
7:0
PMUXO[3:0]
PMUXE[3:0]
0x3F
PMUXn15
7:0
0x40
PINCFG0
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x41
PINCFG1
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x42
PINCFG2
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x43
PINCFG3
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x44
PINCFG4
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x45
PINCFG5
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x46
PINCFG6
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x47
PINCFG7
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x48
PINCFG8
7:0
DRVSTR
PULLEN
INEN
PMUXEN
PMUXO[3:0]
PMUXE[3:0]
0x49
PINCFG9
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x4A
PINCFG10
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x4B
PINCFG11
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x4C
PINCFG12
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x4D
PINCFG13
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x4E
PINCFG14
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x4F
PINCFG15
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x50
PINCFG16
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x51
PINCFG17
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x52
PINCFG18
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x53
PINCFG19
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x54
PINCFG20
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x55
PINCFG21
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x56
PINCFG22
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x57
PINCFG23
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x58
PINCFG24
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x59
PINCFG25
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x5A
PINCFG26
7:0
DRVSTR
PULLEN
INEN
PMUXEN
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
466
Offset
Name
Bit Pos.
0x5B
PINCFG27
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x5C
PINCFG28
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x5D
PINCFG29
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x5E
PINCFG30
7:0
DRVSTR
PULLEN
INEN
PMUXEN
0x5F
PINCFG31
7:0
DRVSTR
PULLEN
INEN
PMUXEN
29.8.
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
467
29.8.1.
Data Direction
This register allows the user to configure one or more I/O pins as an input or output. This register can be
manipulated without doing a read-modify-write operation by using the Data Direction Toggle (DIRTGL),
Data Direction Clear (DIRCLR) and Data Direction Set (DIRSET) registers.
Name: DIR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
DIR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DIR[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
DIR[7:0]
Access
Reset
Bits 31:0 – DIR[31:0]: Port Data Direction
These bits set the data direction for the individual I/O pins in the PORT group.
Value
Description
0
The corresponding I/O pin in the PORT group is configured as an input.
1
The corresponding I/O pin in the PORT group is configured as an output.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
468
29.8.2.
Data Direction Clear
This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle
(DIRTGL) and Data Direction Set (DIRSET) registers.
Name: DIRCLR
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
DIRCLR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIRCLR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DIRCLR[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
DIRCLR[7:0]
Access
Reset
Bits 31:0 – DIRCLR[31:0]: Port Data Direction Clear
Writing a '0' to a bit has no effect.
Writing a '1' to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an
input.
Value
Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The corresponding I/O pin in the PORT group is configured as input.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
469
29.8.3.
Data Direction Set
This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle
(DIRTGL) and Data Direction Clear (DIRCLR) registers.
Name: DIRSET
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
DIRSET[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIRSET[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DIRSET[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
DIRSET[7:0]
Access
Reset
Bits 31:0 – DIRSET[31:0]: Port Data Direction Set
Writing '0' to a bit has no effect.
Writing '1' to a bit will set the corresponding bit in the DIR register, which configures the I/O pin as an
output.
Value
Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The corresponding I/O pin in the PORT group is configured as an output.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
470
29.8.4.
Data Direction Toggle
This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modifywrite operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction
Set (DIRSET) and Data Direction Clear (DIRCLR) registers.
Name: DIRTGL
Offset: 0x0C
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
DIRTGL[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIRTGL[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DIRTGL[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
DIRTGL[7:0]
Access
Reset
Bits 31:0 – DIRTGL[31:0]: Port Data Direction Toggle
Writing '0' to a bit has no effect.
Writing '1' to a bit will toggle the corresponding bit in the DIR register, which reverses the direction of the
I/O pin.
Value
Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The direction of the corresponding I/O pin is toggled.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
471
29.8.5.
Data Output Value
This register sets the data output drive value for the individual I/O pins in the PORT.
This register can be manipulated without doing a read-modify-write operation by using the Data Output
Value Clear (OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL)
registers.
Name: OUT
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
OUT[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
OUT[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OUT[15:8]
Access
OUT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – OUT[31:0]: Port Data Output Value
For pins configured as outputs via the Data Direction register (DIR), these bits set the logical output drive
level.
For pins configured as inputs via the Data Direction register (DIR) and with pull enabled via the Pull
Enable bit in the Pin Configuration register (PINCFG.PULLEN), these bits will set the input pull direction.
Value
Description
0
The I/O pin output is driven low, or the input is connected to an internal pull-down.
1
The I/O pin output is driven high, or the input is connected to an internal pull-up.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
472
29.8.6.
Data Output Value Clear
This register allows the user to set one or more output I/O pin drive levels low, without doing a readmodify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT),
Data Output Value Toggle (OUTTGL) and Data Output Value Set (OUTSET) registers.
Name: OUTCLR
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
OUTCLR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
OUTCLR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
OUTCLR[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
OUTCLR[7:0]
Access
Reset
Bits 31:0 – OUTCLR[31:0]: PORT Data Output Value Clear
Writing '0' to a bit has no effect.
Writing '1' to a bit will clear the corresponding bit in the OUT register. Pins configured as outputs via the
Data Direction register (DIR) will be set to low output drive level. Pins configured as inputs via DIR and
with pull enabled via the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN) will set the
input pull direction to an internal pull-down.
Value
Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The corresponding I/O pin output is driven low, or the input is connected to an internal pulldown.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
473
29.8.7.
Data Output Value Set
This register allows the user to set one or more output I/O pin drive levels high, without doing a readmodify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT),
Data Output Value Toggle (OUTTGL) and Data Output Value Clear (OUTCLR) registers.
Name: OUTSET
Offset: 0x18
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
OUTSET[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
OUTSET[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
OUTSET[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
OUTSET[7:0]
Access
Reset
Bits 31:0 – OUTSET[31:0]: PORT Data Output Value Set
Writing '0' to a bit has no effect.
Writing '1' to a bit will set the corresponding bit in the OUT register, which sets the output drive level high
for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via
Data Direction register (DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will set
the input pull direction to an internal pull-up.
Value
Description
0
The corresponding I/O pin in the group will keep its configuration.
1
The corresponding I/O pin output is driven high, or the input is connected to an internal pullup.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
474
29.8.8.
Data Output Value Toggle
This register allows the user to toggle the drive level of one or more output I/O pins, without doing a readmodify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT),
Data Output Value Set (OUTSET) and Data Output Value Clear (OUTCLR) registers.
Name: OUTTGL
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
OUTTGL[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
OUTTGL[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
OUTTGL[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
OUTTGL[7:0]
Access
Reset
Bits 31:0 – OUTTGL[31:0]: PORT Data Output Value Toggle
Writing '0' to a bit has no effect.
Writing '1' to a bit will toggle the corresponding bit in the OUT register, which inverts the output drive level
for I/O pins configured as outputs via the Data Direction register (DIR). For pins configured as inputs via
Data Direction register (DIR) with pull enabled via the Pull Enable register (PULLEN), these bits will
toggle the input pull direction.
Value
Description
0
The corresponding I/O pin in the PORT group will keep its configuration.
1
The corresponding OUT bit value is toggled.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
475
29.8.9.
Data Input Value
Name: IN
Offset: 0x20
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
IN[31:24]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
IN[23:16]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
IN[15:8]
IN[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 31:0 – IN[31:0]: PORT Data Input Value
These bits are cleared when the corresponding I/O pin input sampler detects a logical low level on the
input pin.
These bits are set when the corresponding I/O pin input sampler detects a logical high level on the input
pin.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
476
29.8.10. Control
Name: CTRL
Offset: 0x24
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
SAMPLING[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
SAMPLING[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SAMPLING[15:8]
Access
SAMPLING[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – SAMPLING[31:0]: Input Sampling Mode
Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs via
the Data Direction register (DIR).
The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte
request continuous sampling, all pins in that eight pin sub-group will be continuously sampled.
Value
Description
0
The I/O pin input synchronizer is disabled.
1
The I/O pin input synchronizer is enabled.
Atmel SAM C20E / SAM C20G /SAM C20J [DATASHEET]
Atmel-42364H-SAM-C20_Datasheet_Preliminary-05/2016
477
29.8.11. Write Configuration
This write-only register is used to configure several pins simultaneously with the same configuration
and/or peripheral multiplexing.
In order to avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect.
Reading this register always returns zero.
Name: WRCONFIG
Offset: 0x28
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
HWSEL
WRPINCFG
WRPMUX
Access
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
Bit
23
20
19
18
17
16
DRVSTR
PULLEN
INEN
PMUXEN
Access
W
W
W
W
Reset
0
0
0
0
10
9
8
Bit
15
22
14
21
PMUX[3:0]
13
12
11
PINMASK[15:8]
Access
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PINMASK[7:0]
Access
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
Bit 31 – HWSEL: Half-Word Select
This bit selects the half-word field of a 32-PORT group to be reconfigured in the atomic write operation.
This bit will always read as zero.
Value
Description
0
The lower 16 pins of the PORT group will be configured.
1
The upper 16 pins of the PORT group will be configured.
Bit 30 – WRPINCFG: Write PINCFG
This bit determines whether the atomic write operation will update the Pin Configuration register
(PINCFGy) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
Writing '0' to this bit has no effect.
Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR,
WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN and WRCONFIG.PINMASK values.
This bit will always read as zero.
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Value
Description
0
The PINCFGy registers of the selected pins will not be updated.
1
The PINCFGy registers of the selected pins will be updated.
Bit 28 – WRPMUX: Write PMUX
This bit determines whether the atomic write operation will update the Peripheral Multiplexing register
(PMUXn) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
Writing '0' to this bit has no effect.
Writing '1' to this bit updates the pin multiplexer configuration of the selected pins with the written
WRCONFIG. PMUX value.
This bit will always read as zero.
Value
Description
0
The PMUXn registers of the selected pins will not be updated.
1
The PMUXn registers of the selected pins will be updated.
Bits 27:24 – PMUX[3:0]: Peripheral Multiplexing
These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins
selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX
bit is set.
These bits will always read as zero.
Bit 22 – DRVSTR: Output Driver Strength Selection
This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the
WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bit 18 – PULLEN: Pull Enable
This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the
WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bit 17 – INEN: Input Enable
This bit determines the new value written to PINCFGy.INEN for all pins selected by the
WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bit 16 – PMUXEN: Peripheral Multiplexer Enable
This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the
WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Bits 15:0 – PINMASK[15:0]: Pin Mask for Multiple Pin Configuration
These bits select the pins to be configured within the half-word group selected by the
WRCONFIG.HWSEL bit.
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These bits will always read as zero.
Value
Description
0
The configuration of the corresponding I/O pin in the half-word group will be left unchanged.
1
The configuration of the corresponding I/O pin in the half-word PORT group will be updated.
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29.8.12. Event Input Control
There are up to four input event pins for each PORT group. Each byte of this register addresses one
Event input pin.
Name: EVCTRL
Offset: 0x2C
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
PORTEI3
Access
Reset
Bit
Reset
Bit
Reset
Bit
Reset
26
EVACT3[1:0]
25
24
PID3[4:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
EVACT2[1:0]
PID2[4:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
EVACT1[1:0]
PID1[4:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PORTEI0
Access
27
R/W
PORTEI1
Access
28
R/W
PORTEI2
Access
29
EVACT0[1:0]
PID0[4:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31,23,15,7 – PORTEIx: PORT Event Input x Enable [x = 3..0]
Value
Description
0
The event action x (EVACTx) will not be triggered on any incoming event.
1
The event action x (EVACTx) will be triggered on any incoming event.
Bits 30:29, 22:21,14:13,6:5 – EVACTx: PORT Event Action x [x = 3..0]
These bits define the event action the PORT will perform on event input x. See also Table 29-4 PORT
Event x Action ( x = [3..0] ).
Bits 28:24,20:16,12:8,4:0 – PIDx: PORT Event Pin Identifier x [x = 3..0]
These bits define the I/O pin on which the event action will be performed, according to Table 29-5 PORT
Event x Pin Identifier ( x = [3..0] ).
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Table 29-4. PORT Event x Action ( x = [3..0] )
Value
Name
Description
0x0
OUT
Output register of pin will be set
to level of event.
0x1
SET
Set output register of pin on
event.
0x2
CLR
Clear output register of pin on
event.
0x3
TGL
Toggle output register of pin on
event.
Table 29-5. PORT Event x Pin Identifier ( x = [3..0] )
Value
Name
Description
0x0
PIN0
Event action to be executed on
PIN 0.
0x1
PIN1
Event action to be executed on
PIN 1.
...
...
...
0x31
PIN31
Event action to be executed on
PIN 31.
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29.8.13. Peripheral Multiplexing n
There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent
I/O lines. The n denotes the number of the set of I/O lines.
Name: PMUXn
Offset: 0x30 + n*0x01 [n=0..15]
Reset: 0x00000000
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
R/W
0
1
0
R/W
R/W
R/W
R/W
R/W
0
0
0
0
R/W
R/W
0
0
0
PMUXO[3:0]
Access
Reset
PMUXE[3:0]
Bits 7:4 – PMUXO[3:0]: Peripheral Multiplexing Odd
These bits select the peripheral function for odd-numbered pins (2*n + 1) of a PORT group, if the
corresponding PINCFGy.PMUXEN bit is '1'.
Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and
Considerations.
PMUXO[3:0]
Name
Description
0x0
A
Peripheral function A selected
0x1
B
Peripheral function B selected
0x2
C
Peripheral function C selected
0x3
D
Peripheral function D selected
0x4
E
Peripheral function E selected
0x5
F
Peripheral function F selected
0x6
G
Peripheral function G selected
0x7
H
Peripheral function H selected
0x8
I
Peripheral function I selected
0x9-0xF
-
Reserved
Bits 3:0 – PMUXE[3:0]: Peripheral Multiplexing Even
These bits select the peripheral function for even-numbered pins (2*n) of a PORT group, if the
corresponding PINCFGy.PMUXEN bit is '1'.
Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and
Considerations.
PMUXE[3:0]
Name
Description
0x0
A
Peripheral function A selected
0x1
B
Peripheral function B selected
0x2
C
Peripheral function C selected
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PMUXE[3:0]
Name
Description
0x3
D
Peripheral function D selected
0x4
E
Peripheral function E selected
0x5
F
Peripheral function F selected
0x6
G
Peripheral function G selected
0x7
H
Peripheral function H selected
0x8
I
Peripheral function I selected
0x9-0xF
-
Reserved
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29.8.14. Pin Configuration
There are up to 32 Pin Configuration registers in each PORT group, one for each I/O line.
Name: PINCFGn
Offset: 0x40 + n*0x01 [n=0..31]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
Access
Reset
2
1
0
DRVSTR
6
5
4
3
PULLEN
INEN
PMUXEN
R/W
R/W
R/W
R/W
0
0
0
0
Bit 6 – DRVSTR: Output Driver Strength Selection
This bit controls the output driver strength of an I/O pin configured as an output.
Value
Description
0
Pin drive strength is set to normal drive strength.
1
Pin drive strength is set to stronger drive strength.
Bit 2 – PULLEN: Pull Enable
This bit enables the internal pull-up or pull-down resistor of an I/O pin configured as an input.
Value
Description
0
Internal pull resistor is disabled, and the input is in a high-impedance configuration.
1
Internal pull resistor is enabled, and the input is driven to a defined logic level in the absence
of external input.
Bit 1 – INEN: Input Enable
This bit controls the input buffer of an I/O pin configured as either an input or output.
Writing a zero to this bit disables the input buffer completely, preventing read-back of the physical pin
state when the pin is configured as either an input or output.
Value
Description
0
Input buffer for the I/O pin is disabled, and the input value will not be sampled.
1
Input buffer for the I/O pin is enabled, and the input value will be sampled when required.
Bit 0 – PMUXEN: Peripheral Multiplexer Enable
This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register
(PMUXn) to enable or disable alternative peripheral control over an I/O pin direction and output drive
value.
Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR)
and output drive value via the Data Output Value register (OUT). The peripheral multiplexer value in
PMUXn is ignored. Writing '1' to this bit enables the peripheral selection in PMUXn to control the pad. In
this configuration, the physical pin state may still be read from the Data Input Value register (IN) if
PINCFGn.INEN is set.
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Value
Description
0
The peripheral multiplexer selection is disabled, and the PORT registers control the direction
and output drive value.
1
The peripheral multiplexer selection is enabled, and the selected peripheral function controls
the direction and output drive value.
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30.
30.1.
EVSYS – Event System
Overview
The Event System (EVSYS) allows autonomous, low-latency and configurable communication between
peripherals.
Several peripherals can be configured to generate and/or respond to signals known as events. The exact
condition to generate an event, or the action taken upon receiving an event, is specific to each peripheral.
Peripherals that respond to events are called event users. Peripherals that generate events are called
event generators. A peripheral can have one or more event generators and can have one or more event
users.
Communication is made without CPU intervention and without consuming system resources such as bus
or RAM bandwidth. This reduces the load on the CPU and other system resources, compared to a
traditional interrupt-based system.
30.2.
Features
•
•
•
•
•
•
•
•
30.3.
6 configurable event channels, where each channel can:
– Be connected to any event generator.
– Provide a pure asynchronous, resynchronized or synchronous path
68 event generators.
31 event users.
Configurable edge detector.
Peripherals can be event generators, event users, or both.
SleepWalking and interrupt for operation in sleep modes.
Software event generation.
Each event user can choose which channel to respond to.
Block Diagram
Figure 30-1. Event System Block Diagram
Clock Request [m:0]
Event Channel m
Event Channel 1
USER x+1
USER x
Event Channel 0
Asynchronous Path
USER.CHANNELx
CHANNEL0.PATH
SleepWalking
Detector
Synchronized Path
Edge Detector
PERIPHERAL0
Channel_EVT_m
EVT
D Q
To Peripheral x
R
EVT ACK
PERIPHERAL n
Channel_EVT_0
Q
D
Q
D
Q
D
Peripheral x
Event Acknowledge
Resynchronized Path
R
CHANNEL0.EVGEN
SWEVT.CHANNEL0
CHANNEL0.EDGSEL
D Q
D Q
D Q
R
R
R
R
R
GCLK_EVSYS_0
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30.4.
Signal Description
Not applicable.
30.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
30.5.1.
I/O Lines
Not applicable.
30.5.2.
Power Management
The EVSYS can be used to wake up the CPU from all sleep modes, even if the clock used by the EVSYS
channel and the EVSYS bus clock are disabled. Refer to the PM – Power Manager for details on the
different sleep modes.
In all sleep modes, although the clock for the EVSYS is stopped, the device still can wake up the EVSYS
clock. Some event generators can generate an event when their clocks are stopped. The generic clock
for the channel (GCLK_EVSYS_CHANNEL_n) will be restarted if that channel uses a synchronized path
or a resynchronized path. It does not need to wake the system from sleep.
Related Links
PM – Power Manager on page 177
30.5.3.
Clocks
The EVSYS bus clock (CLK_EVSYS_APB) can be enabled and disabled in the Main Clock module, and
the default state of CLK_EVSYS_APB can be found in Peripheral Clock Masking.
Each EVSYS channel has a dedicated generic clock (GCLK_EVSYS_CHANNEL_n). These are used for
event detection and propagation for each channel. These clocks must be configured and enabled in the
generic clock controller before using the EVSYS. Refer to GCLK - Generic Clock Controller for details.
Related Links
Peripheral Clock Masking on page 152
GCLK - Generic Clock Controller on page 127
30.5.4.
DMA
Not applicable.
30.5.5.
Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the EVSYS interrupts requires the
interrupt controller to be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
Nested Vector Interrupt Controller on page 43
30.5.6.
Events
Not applicable.
30.5.7.
Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
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data loss may result during debugging. This peripheral can be forced to halt operation during debugging refer to the Debug Control (DBGCTRL) register for details.
30.5.8.
Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except the following:
•
•
Channel Status (CHSTATUS)
Interrupt Flag Status and Clear register (INTFLAG)
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection
does not apply for accesses through an external debugger.
30.5.9.
Analog Connections
Not applicable.
30.6.
Functional Description
30.6.1.
Principle of Operation
The Event System consists of several channels which route the internal events from peripherals
(generators) to other internal peripherals or IO pins (users). Each event generator can be selected as
source for multiple channels, but a channel cannot be set to use multiple event generators at the same
time.
A channel path can be configured in asynchronous, synchronous or re-synchronized mode of operation.
The mode of operation must be selected based on the requirements of the application.
When using synchronous or resynchronized path, the Event System includes options to transfer events to
users when rising, falling or both edges are detected on on event generators.
For further details, refer to “Channel Path” of this chapter.
30.6.2.
Basic Operation
30.6.2.1. Initialization
Before enabling events routing within the system, the Event Users Multiplexer and Event Channels must
be configured. The Event Users Multiplexer must be configured first.
For further details about the event user multiplexer configuration, refer to “User Multiplexer Setup”.
For further details about the event channels configuration, refer to “Event System Channel”.
30.6.2.2. Enabling, Disabling, and Resetting
The EVSYS is always enabled.
The EVSYS is reset by writing a ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST).
All registers in the EVSYS will be reset to their initial state and all ongoing events will be canceled.
Refer to CTRLA.SWRST register for details.
30.6.2.3. User Multiplexer Setup
The user multiplexer defines the channel to be connected to which event user. Each user multiplexer is
dedicated to one event user. A user multiplexer receives all event channels output and must be
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configured to select one of these channels, as shown in Figure 30-1 Event System Block Diagram. The
channel is selected with the Channel bit group in the User register (USERm.CHANNEL).
The user multiplexer must always be configured before the channel. A list of all user multiplexers is found
in the User (USERm) register description.
Related Links
USERm on page 506
30.6.2.4. Event System Channel
An event channel can select one event from a list of event generators. Depending on configuration, the
selected event could be synchronized, resynchronized or asynchronously sent to the users. When
synchronization or resynchronization is required, the channel includes an internal edge detector, allowing
the Event System to generate internal events when rising, falling or both edges are detected on the
selected event generator.
An event channel is able to generate internal events for the specific software commands. A channel block
diagram is shown in Figure 30-1 Event System Block Diagram.
30.6.2.5. Event Generators
Each event channel can receive the events form all event generators. All event generators are listed in
the Event Generator bit field in the Channel n register (CHANNELn.EVGEN). For details on event
generation, refer to the corresponding module chapter. The channel event generator is selected by the
Event Generator bit group in the Channel register (CHANNELn.EVGEN). By default, the channels are not
connected to any event generators (ie, CHANNELn.EVGEN = 0)
30.6.2.6. Channel Path
There are three different ways to propagate the event from an event generator:
•
•
•
Asynchronous path
Synchronous path
Resynchronized path
The path is decided by writing to the Path Selection bit group of the Channel register (CHANNELn.PATH).
Asynchronous Path
When using the asynchronous path, the events are propagated from the event generator to the event
user without intervention from the Event System. The GCLK for this channel
(GCLK_EVSYS_CHANNEL_n) is not mandatory, meaning that an event will be propagated to the user
without any clock latency.
When the asynchronous path is selected, the channel cannot generate any interrupts, and the Channel
Status register (CHSTATUS) is always zero. The edge detection is not required and must be disabled by
software. Each peripheral event user has to select which event edge must trigger internal actions. For
further details, refer to each peripheral chapter description.
Synchronous Path
The synchronous path should be used when the event generator and the event channel share the same
generator for the generic clock. If they do not share the same clock, a logic change from the event
generator to the event channel might not be detected in the channel, which means that the event will not
be propagated to the event user. For details on generic clock generators, refer to GCLK - Generic Clock
Controller.
When using the synchronous path, the channel is able to generate interrupts. The channel busy n bit in
the Channel Status register (CHSTATUS.CHBUSYn) are also updated and available for use.
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Resynchronized Path
The resynchronized path are used when the event generator and the event channel do not share the
same generator for the generic clock. When the resynchronized path is used, resynchronization of the
event from the event generator is done in the channel. For details on generic clock generators, refer to
GCLK - Generic Clock Controller.
When the resynchronized path is used, the channel is able to generate interrupts. The channel busy n
bits in the Channel Status register (CHSTATUS.CHBUSYn) are also updated and available for use.
Related Links
GCLK - Generic Clock Controller on page 127
30.6.2.7. Edge Detection
When synchronous or resynchronized paths are used, edge detection must be enabled. The event
system can execute edge detection in three different ways:
•
•
•
Generate an event only on the rising edge
Generate an event only on the falling edge
Generate an event on rising and falling edges.
Edge detection is selected by writing to the Edge Selection bit group of the Channel register
(CHANNELn.EDGSEL).
30.6.2.8. Event Latency
An event from an event generator is propagated to an event user with different latency, depending on
event channel configuration.
•
•
•
Asynchronous Path: The maximum routing latency of an external event is related to the internal
signal routing and it is device dependent.
Synchronous Path: The maximum routing latency of an external event is one
GCLK_EVSYS_CHANNEL_n clock cycle.
Resynchronized Path: The maximum routing latency of an external event is three
GCLK_EVSYS_CHANNEL_n clock cycles.
The maximum propagation latency of a user event to the peripheral clock core domain is three peripheral
clock cycles.
The event generators, event channel and event user clocks ratio must be selected in relation with the
internal event latency constraints. Events propagation or event actions in peripherals may be lost if the
clock setup violates the internal latencies.
30.6.2.9. The Overrun Channel n Interrupt
The Overrun Channel n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVRn) will
be set, and the optional interrupt will be generated in the following cases:
•
•
One or more event users on channel n is not ready when there is a new event.
An event occurs when the previous event on channel m has not been handled by all event users
connected to that channel.
The flag will only be set when using synchronous or resynchronized paths. In the case of asynchronous
path, the INTFLAG.OVRn is always read as zero.
30.6.2.10. The Event Detected Channel n Interrupt
The Event Detected Channel n interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.EVDn) is set when an event coming from the event generator configured on channel n is
detected.
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The flag will only be set when using a synchronous or resynchronized paths. In the case of asynchronous
path, the INTFLAG.EVDn is always zero.
30.6.2.11. Channel Status
The Channel Status register (CHSTATUS) shows the status of the channels when using a synchronous or
resynchronized path. There are two different status bits in CHSTATUS for each of the available channels:
•
•
The CHSTATUS.CHBUSYn bit will be set when an event on the corresponding channel n has not
been handled by all event users connected to that channel.
The CHSTATUS.USRRDYn bit will be set when all event users connected to the corresponding
channel are ready to handle incoming events on that channel.
30.6.2.12. Software Event
A software event can be initiated on a channel by setting the Channel n bit in the Software Event register
(SWEVT.CHANNELn) to ‘1’. Then the software event can be serviced as any event generator; i.e., when
the bit is set to ‘1’, an event will be generated on the respective channel.
30.6.3.
Interrupts
The EVSYS has the following interrupt sources:
•
•
Overrun Channel n interrupt (OVRn): for details, refer to The Overrun Channel n Interrupt.
Event Detected Channel n interrupt (EVDn): for details, refer to The Event Detected Channel n
Interrupt.
These interrupts events are asynchronous wake-up sources. See Sleep Mode Controller. Each interrupt
source has an interrupt flag which is in the Interrupt Flag Status and Clear (INTFLAG) register. The flag is
set when the interrupt is issued. Each interrupt event can be individually enabled by setting a ‘1’ to the
corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by setting a ‘1’ to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt event is generated
when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt event works until
the interrupt flag is cleared, the interrupt is disabled, or the Event System is reset. See INTFLAG for
details on how to clear interrupt flags.
All interrupt events from the peripheral are ORed together on system level to generate one combined
interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The event user
must read the INTFLAG register to determine what the interrupt condition is.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested
Vector Interrupt Controller for details.
Related Links
Sleep Mode Controller on page 179
30.6.4.
Sleep Mode Operation
The EVSYS can generate interrupts to wake up the device from any sleep mode.
To be able to run in standby, the Run in Standby bit in the Channel register (CHANNELn.RUNSTDBY)
must be set to ‘1’. When the Generic Clock On Demand bit in Channel register
(CHANNELn.ONDEMAND) is set to ‘1’ and the event generator is detected, the event channel will
request its clock (GCLK_EVSYS_CHANNEL_n). The event latency for a resynchronized channel path will
increase by two GCLK_EVSYS_CHANNEL_n clock (i.e., up to five GCLK_EVSYS_CHANNEL_n clock
cycles).
A channel will behave differently in different sleep modes regarding to CHANNELn.RUNSTDBY and
CHANNELn.ONDEMAND, as shown in the table below:
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Table 30-1. Event Channel Sleep Behavior
CHANNELn.ONDEMAN CHANNELn.RUNSTDB
D
Y
Sleep Behavior
0
0
Only run in IDLE sleep mode if an event must be
propagated. Disabled in STANDBY sleep mode.
0
1
Always run in IDLE and STANDBY sleep modes.
1
0
Only run in IDLE sleep mode if an event must be
propagated. Disabled in STANDBY sleep mode.
Two GCLK_EVSYS_n latency added in RESYNC
path before the event is propagated internally.
1
1
Always run in IDLE and STANDBY sleep modes.
Two GCLK_EVSYS_n latency added in RESYNC
path before the event is propagated internally.
30.7.
Register Summary
30.7.1.
Common Registers
Offset
Name
Bit Pos.
0x00
CTRLA
7:0
0x01..0x0B
Reserved
0x0C
0x0D
0x0E
7:0
CHSTATUS
0x0F
7:0
15:8
INTENCLR
23:16
0x13
31:24
0x14
7:0
0x16
INTENSET
0x17
7:0
15:8
INTFLAG
23:16
0x1B
31:24
0x1C
7:0
0x1E
0x1F
USRRDY2
USRRDY1
USRRDY0
CHBUSY5
CHBUSY4
CHBUSY3
CHBUSY2
CHBUSY1
CHBUSY0
OVR5
OVR4
OVR3
OVR2
OVR1
OVR0
EVD5
EVD4
EVD3
EVD2
EVD1
EVD0
OVR5
OVR4
OVR3
OVR2
OVR1
OVR0
EVD5
EVD4
EVD3
EVD2
EVD1
EVD0
OVR5
OVR4
OVR3
OVR2
OVR1
OVR0
EVD5
EVD4
EVD3
EVD2
EVD1
EVD0
31:24
0x19
0x1D
USRRDY3
15:8
23:16
0x18
0x1A
USRRDY4
31:24
0x11
0x15
USRRDY5
15:8
23:16
0x10
0x12
SWRST
SWEVT
CHANNEL[5:0]
15:8
23:16
31:24
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30.7.2.
Offset
CHANNELn
Name
Bit
Pos.
0x20 +
7:0
0x4*n
0x21 +
0x4*n
0x22 +
15:8
EVGEN[7:0]
ONDEMAND RUNSTDBY
EDGSEL[1:0]
PATH[1:0]
CHANNELn
23:16
0x4*n
0x23 +
31:24
0x4*n
30.7.3.
USERm
Offset
Name
Bit
Pos.
0x80 +
7:0
0x4*m
0x81 +
0x4*m
0x82 +
0x4*m
0x83 +
0x4*m
30.8.
CHANNEL[7:0]
15:8
USERm
23:16
31:24
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
Refer to Register Access Protection and PAC - Peripheral Access Controller.
Related Links
PAC - Peripheral Access Controller on page 48
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30.8.1.
Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
SWRST
Access
W
Reset
0
Bit 0 – SWRST: Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the EVSYS to their initial state.
Note: Before applying a Software Reset it is recommended to disable the event generators.
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30.8.2.
Channel Status
Name: CHSTATUS
Offset: 0x0C
Reset: 0x000000FF
Property: –
Bit
31
30
23
22
29
28
27
26
25
24
Access
Reset
Bit
21
20
19
18
17
16
CHBUSY5
CHBUSY4
CHBUSY3
CHBUSY2
CHBUSY1
CHBUSY0
Access
R
R
R
R
R
R
Reset
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
USRRDY5
USRRDY4
USRRDY3
USRRDY2
USRRDY1
USRRDY0
Access
R
R
R
R
R
R
Reset
0
0
0
0
0
1
Bits 21:16 – CHBUSYn: Channel Busy n [n = 5..0]
This bit is cleared when channel n is idle.
This bit is set if an event on channel n has not been handled by all event users connected to channel n.
Bits 5:0 – USRRDYn: User Ready for Channel n [n = 5..0]
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel n are ready to handle incoming events on
channel n.
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30.8.3.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
23
22
29
28
27
26
25
24
Access
Reset
Bit
Access
Reset
Bit
15
14
7
6
21
20
19
18
17
16
EVD5
EVD4
EVD3
EVD2
EVD1
EVD0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
5
4
3
2
1
0
OVR5
OVR4
OVR3
OVR2
OVR1
OVR0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 21:16 – EVDn: Event Detected Channel n Interrupt Enable [n = 5..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the Event
Detected Channel n interrupt.
Value
Description
0
The Event Detected Channel n interrupt is disabled.
1
The Event Detected Channel n interrupt is enabled.
Bits 5:0 – OVRn: Overrun Channel n Interrupt Enable[n = 5..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun
Channel n interrupt.
Value
Description
0
The Overrun Channel n interrupt is disabled.
1
The Overrun Channel n interrupt is enabled.
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30.8.4.
Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
23
22
29
28
27
26
25
24
Access
Reset
Bit
Access
Reset
Bit
15
14
7
6
21
20
19
18
17
16
EVD5
EVD4
EVD3
EVD2
EVD1
EVD0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
5
4
3
2
1
0
OVR5
OVR4
OVR3
OVR2
OVR1
OVR0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 21:16 – EVDn: Event Detected Channel n Interrupt Enable [n = 5..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event
Detected Channel n interrupt.
Value
Description
0
The Event Detected Channel n interrupt is disabled.
1
The Event Detected Channel n interrupt is enabled.
Bits 5:0 – OVRn: Overrun Channel n Interrupt Enable [n = 5..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Overrun Channel n Interrupt Enable bit, which disables the Overrun
Channel n interrupt.
Value
Description
0
The Overrun Channel n interrupt is disabled.
1
The Overrun Channel n interrupt is enabled.
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30.8.5.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00000000
Property: –
Bit
31
30
23
22
29
28
27
26
25
24
Access
Reset
Bit
Access
Reset
Bit
21
20
19
18
17
16
EVD5
EVD4
EVD3
EVD2
EVD1
EVD0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OVR5
OVR4
OVR3
OVR2
OVR1
OVR0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Access
Reset
Bit
Access
Reset
Bits 21:16 – EVDn: Event Detected Channel n Interrupt Enable [n=5..0]
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the
channel, and an interrupt request will be generated if INTENCLR/SET.EVDn is '1'.
When the event channel path is asynchronous, the EVDn interrupt flag will not be set.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Event Detected Channel n interrupt flag.
Bits 5:0 – OVRn: Overrun Channel n Interrupt Enable [n=5..0]
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the
channel, and an interrupt request will be generated if INTENCLR/SET.OVRn is '1'.
When the event channel path is asynchronous, the OVRn interrupt flag will not be set.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Overrun Detected Channel n interrupt flag.
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30.8.6.
Software Event
Name: SWEVT
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CHANNEL5
CHANNEL4
CHANNEL3
CHANNEL2
CHANNEL1
CHANNEL0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 5:0 – CHANNELn: Channel n Software [n=5..0] Selection
Writing '0' to this bit has no effect.
Writing '1' to this bit will trigger a software event for the channel n.
These bits will always return zero when read.
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30.8.7.
Channel
This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all
the configuration data.
Name: CHANNELn
Offset: 0x20+n*0x4 [n=0..5]
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
15
14
ONDEMAND
RUNSTDBY
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
Bit
7
6
3
2
1
0
Access
EDGSEL[1:0]
5
4
8
PATH[1:0]
EVGEN[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 15 – ONDEMAND: Generic Clock On Demand
Value
Description
0
Generic clock for a channel is always on, if the channel is configured and generic clock
source is enabled.
1
Generic clock is requested on demand while an event is handled
Bit 14 – RUNSTDBY: Run in Standby
This bit is used to define the behavior during standby sleep mode.
Value
Description
0
The channel is disabled in standby sleep mode.
1
The channel is not stopped in standby sleep mode and depends on the
CHANNEL.ONDEMAND
Bits 11:10 – EDGSEL[1:0]: Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
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Value
Name
Description
0x0
NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path
0x1
RISING_EDGE
Event detection only on the rising edge of the signal from the event
generator
0x2
FALLING_EDGE
Event detection only on the falling edge of the signal from the event
generator
0x3
BOTH_EDGES
Event detection on rising and falling edges of the signal from the event
generator
Bits 9:8 – PATH[1:0]: Path Selection
These bits are used to choose which path will be used by the selected channel.
The path choice can be limited by the channel source, see the table in USERm.
Value
Name
Description
0x0
SYNCHRONOUS
Synchronous path
0x1
RESYNCHRONIZED
Resynchronized path
0x2
ASYNCHRONOUS
Asynchronous path
0x3
-
Reserved
Bits 7:0 – EVGEN[7:0]: Event Generator
These bits are used to choose the event generator to connect to the selected channel.
Value
Event Generator
Description
0x00
NONE
No event generator selected
0x01
OSCCTRL FAIL
XOSC Clock Failure
0x02
OSC32KCTRL FAIL
XOSC32K Clock Failure
0x03
RTC CMP0
Compare 0 (mode 0 and 1) or
Alarm 0 (mode 2)
0x04
RTC CMP1
Compare 1
0x05
RTC OVF
Overflow
0x06
RTC PER0
Period 0
0x07
RTC PER1
Period 1
0x08
RTC PER2
Period 2
0x09
RTC PER3
Period 3
0x0A
RTC PER4
Period 4
0x0B
RTC PER5
Period 5
0x0C
RTC PER6
Period 6
0x0D
RTC PER7
Period 7
0x0E
EIC EXTINT0
External Interrupt 0
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502
Value
Event Generator
Description
0x0F
EIC EXTINT1
External Interrupt 1
0x10
EIC EXTINT2
External Interrupt 2
0x11
EIC EXTINT3
External Interrupt 3
0x12
EIC EXTINT4
External Interrupt 4
0x13
EIC EXTINT5
External Interrupt 5
0x14
EIC EXTINT6
External Interrupt 6
0x15
EIC EXTINT7
External Interrupt 7
0x16
EIC EXTINT8
External Interrupt 8
0x17
EIC EXTINT9
External Interrupt 9
0x18
EIC EXTINT10
External Interrupt 10
0x19
EIC EXTINT11
External Interrupt 11
0x1A
EIC EXTINT12
External Interrupt 12
0x1B
EIC EXTINT13
External Interrupt 13
0x1C
EIC EXTINT14
External Interrupt 14
0x1D
EIC EXTINT15
External Interrupt 15
0x1E
-
Reserved
0x1F
DMAC CH0
Channel 0
0x20
DMAC CH1
Channel 1
0x21
DMAC CH2
Channel 2
0x22
DMAC CH3
Channel 3
0x23
TCC0 OVF
Overflow
0x24
TCC0 TRG
Trig
0x25
TCC0 CNT
Counter
0x26
TCC0 MC0
Match/Capture 1
0x27
TCC0 MC1
Match/Capture 1
0x28
TCC0 MC2
Match/Capture 2
0x29
TCC0 MC3
Match/Capture 3
0x2A
TCC1 OVF
Overflow
0x2B
TCC1 TRG
Trig
0x2C
TCC1 CNT
Counter
0x2D
TCC1 MC0
Match/Capture 0
0x2E
TCC1 MC1
Match/Capture 1
0x2F
TCC2 OVF
Overflow
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Value
Event Generator
Description
0x30
TCC2 TRG
Trig
0x31
TCC2 CNT
Counter
0x32
TCC2 MC0
Match/Capture 0
0x33
TCC2 MC1
Match/Capture 1
0x34
TC0 OVF
Overflow/Underflow
0x35
TC0 MC0
Match/Capture 0
0x36
TC0 MC1
Match/Capture 1
0x37
TC1 OVF
Overflow/Underflow
0x38
TC1 MC0
Match/Capture 0
0x39
TC1 MC1
Match/Capture 1
0x3A
TC2 OVF
Overflow/Underflow
0x3B
TC2 MC1
Match/Capture 0
0x3C
TC2 MC0
Match/Capture 1
0x3D
TC3 OVF
Overflow/Underflow
0x3E
TC3 MC0
Match/Capture 0
0x3F
TC3 MC1
Match/Capture 1
0x40
TC4 OVF
Overflow/Underflow
0x41
TC4 MC0
Match/Capture 0
0x42
TC4 MC1
Match/Capture 1
0x43
ADC0 RESRDY
Result Ready
0x44
ADC0 WINMON
Window Monitor
0x45
-
Reserved
0x46
-
Reserved
0x47
-
Reserved
0x48
-
Reserved
0x49
AC COMP0
Comparator 0
0x4A
AC COMP1
Comparator 1
0x4B
-
Reserved
0x4C
-
Reserved
0x4D
AC WIN0
Window 0
0x4E
-
Reserved
0x4F
-
Reserved
0x50
PTC EOC
End of Conversion
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504
Value
Event Generator
Description
0x51
PTC WCOMP
Window Comparator
0x52
CCL LUTOUT0
CCL output
0x53
CCL LUTOUT1
CCL output
0x54
CCL LUTOUT2
CCL output
0x55
CCL LUT3
CCL output
0x56
PAC ACCERR
Access Error
0x57-0xFF
-
Reserved
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505
30.8.8.
Event User m
Name: USERm
Offset: 0x80+m*0x4 [m=0..46]
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
CHANNEL[7:0]
Access
Reset
Bits 7:0 – CHANNEL[7:0]: Channel Event Selection
These bits are used to select the channel to connect to the event user.
Note that to select channel m, the value (m+1) must be written to the USER.CHANNEL bit group.
Value
Channel Number
0x00
No channel output selected
0x01
0
0x02
1
0x03
2
0x04
3
0x05
4
0x06
5
0x07
6
0x08-0xFF
Reserved
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Table 30-2. User Multiplexer Number
USERm
User Multiplexer
Description
Path Type
m=0
Reserved
-
Reserved
m=1
PORT EV0
Event 0
Asynchronous,
synchronous, and
resynchronized paths
m=2
PORT EV1
Event 1
Asynchronous,
synchronous, and
resynchronized paths
m=3
PORT EV2
Event 2
Asynchronous,
synchronous, and
resynchronized paths
m=4
PORT EV3
Event 3
Asynchronous,
synchronous, and
resynchronized paths
m=5
DMAC CH0
Channel 0
Asynchronous,
synchronous, and
resynchronized paths
m=6
DMAC CH1
Channel 1
Asynchronous,
synchronous, and
resynchronized paths
m=7
DMAC CH2
Channel 2
Asynchronous,
synchronous, and
resynchronized paths
m=8
DMAC CH3
Channel 3
Asynchronous,
synchronous, and
resynchronized paths
m=9
TCC0 EV0
-
Asynchronous,
synchronous, and
resynchronized paths
m = 10
TCC0 EV1
-
Asynchronous,
synchronous, and
resynchronized paths
m = 11
TCC0 MC0
Match/Capture 0
Asynchronous,
synchronous, and
resynchronized paths
m = 12
TCC0 MC1
Match/Capture 1
Asynchronous,
synchronous, and
resynchronized paths
m = 13
TCC0 MC2
Match/Capture 2
Asynchronous,
synchronous, and
resynchronized paths
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USERm
User Multiplexer
Description
Path Type
m = 14
TCC0 MC3
Match/Capture 3
Asynchronous,
synchronous, and
resynchronized paths
m = 15
TCC1 EV0
-
Asynchronous,
synchronous, and
resynchronized paths
m = 16
TCC1 EV1
-
Asynchronous,
synchronous, and
resynchronized paths
m = 17
TCC1 MC0
Match/Capture 0
Asynchronous,
synchronous, and
resynchronized paths
m = 18
TCC1 MC1
Match/Capture 1
Asynchronous,
synchronous, and
resynchronized paths
m = 19
TCC2 EV0
-
Asynchronous,
synchronous, and
resynchronized paths
m = 20
TCC2 EV1
-
Asynchronous,
synchronous, and
resynchronized paths
m = 21
TCC2 MC0
Match/Capture 0
Asynchronous,
synchronous, and
resynchronized paths
m = 22
TCC2 MC1
Match/Capture 1
Asynchronous,
synchronous, and
resynchronized paths
m = 23
TC0
-
Asynchronous,
synchronous, and
resynchronized paths
m = 24
TC1
-
Asynchronous,
synchronous, and
resynchronized paths
m = 25
TC2
-
Asynchronous,
synchronous, and
resynchronized paths
m = 26
TC3
-
Asynchronous,
synchronous, and
resynchronized paths
m = 27
TC4
-
Asynchronous,
synchronous, and
resynchronized paths
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USERm
User Multiplexer
Description
Path Type
m = 28
ADC0 START
ADC start conversion
Asynchronous path only
m = 29
ADC0 SYNC
Flush ADC
Asynchronous path only
m=30 to 33
Reserved
-
Reserved
m = 34
AC COMP0
Start comparator 0
Asynchronous path only
m = 35
AC COMP1
Start comparator 1
Asynchronous path only
m=36 to 38
Reserved
-
Reserved
m = 39
PTC STCONC
PTC start conversion
Asynchronous path only
m = 40
CCL LUTIN 0
CCL input
Asynchronous path only
m = 41
CCL LUTIN 1
CCL input
Asynchronous path only
m = 42
CCL LUTIN 2
CCL input
Asynchronous path only
m = 43
CCL LUTIN 3
CCL input
Asynchronous path only
others
Reserved
-
Reserved
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31.
SERCOM – Serial Communication Interface
31.1.
Overview
There are up to four instances of the serial communication interface (SERCOM) peripheral.
A SERCOM can be configured to support a number of modes: I2C, SPI, and USART. When SERCOM is
configured and enabled, all SERCOM resources will be dedicated to the selected mode.
The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address
matching functionality. It can use the internal generic clock or an external clock to operate in all sleep
modes.
31.2.
Features
•
Interface for configuring into one of the following:
•
•
•
•
•
I2C – Two-wire serial interface
SMBus™ compatible
– SPI – Serial peripheral interface
– USART – Universal synchronous and asynchronous serial receiver and transmitter
Single transmit buffer and double receive buffer
Baud-rate generator
Address match/mask logic
Operational in all sleep modes
Can be used with DMA
–
See the Related Links for full feature lists of the interface configurations.
31.3.
Block Diagram
Figure 31-1. SERCOM Block Diagram
SERCOM
Register Interface
CONTROL/STATUS
Mode Specific
TX/RX DATA
Serial Engine
Mode n
Mode 1
BAUD/ADDR
Transmitter
Baud Rate
Generator
Mode 0
Receiver
PAD[3:0]
Address
Match
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31.4.
Signal Description
See the respective SERCOM mode chapters for details.
Related Links
SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter on page 518
SERCOM SPI – SERCOM Serial Peripheral Interface on page 558
SERCOM I2C – SERCOM Inter-Integrated Circuit on page 591
31.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
31.5.1.
I/O Lines
Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT).
From USART Block Diagram one can see that the SERCOM has four internal pads, PAD[3:0]. The
signals from I2C, SPI and USART are routed through these SERCOM pads via a multiplexer. The
configuration of the multiplexer is available from the different SERCOM modes. Refer to the mode
specific chapters for details.
Related Links
SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter on page 518
SERCOM SPI – SERCOM Serial Peripheral Interface on page 558
SERCOM I2C – SERCOM Inter-Integrated Circuit on page 591
PORT: IO Pin Controller on page 455
Block Diagram on page 519
31.5.2.
Power Management
The SERCOM can operate in any sleep mode where the selected clock source is running. SERCOM
interrupts can be used to wake up the device from sleep modes.
Related Links
PM – Power Manager on page 177
31.5.3.
Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled
in the Main Clock.
The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The
core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a master. The
slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions. See specific mode chapters
for details.
These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the
SERCOM.
The generic clocks are asynchronous to the user interface clock (CLK_SERCOMx_APB). Due to this
asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer
to Synchronization for details.
Related Links
GCLK - Generic Clock Controller on page 127
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MCLK – Main Clock on page 149
31.5.4.
DMA
The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured
before the SERCOM DMA requests are used.
Related Links
DMAC – Direct Memory Access Controller on page 346
31.5.5.
Interrupts
The interrupt request line is connected to the Interrupt Controller (NVIC). The NVIC must be configured
before the SERCOM interrupts are used.
Related Links
Nested Vector Interrupt Controller on page 43
31.5.6.
Events
Not applicable.
31.5.7.
Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging refer to the Debug Control (DBGCTRL) register for details.
31.5.8.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except the following registers:
•
•
•
•
Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Address register (ADDR)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
31.5.9.
Analog Connections
Not applicable.
31.6.
Functional Description
31.6.1.
Principle of Operation
The basic structure of the SERCOM serial engine is shown in Figure 31-2 SERCOM Serial Engine.
Labels in capital letters are synchronous to the system clock and accessible by the CPU; labels in
lowercase letters can be configured to run on the GCLK_SERCOMx_CORE clock or an external clock.
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Figure 31-2. SERCOM Serial Engine
Address Match
Transmitter
BAUD
Selectable
Internal Clk
(GCLK)
Ext Clk
TX DATA
ADDR/ADDRMASK
baud rate generator
1/- /2- /16
tx shift register
Receiver
rx shift register
==
status
Baud Rate Generator
STATUS
rx buffer
RX DATA
The transmitter consists of a single write buffer and a shift register.
The receiver consists of a two-level receive buffer and a shift register.
The baud-rate generator is capable of running on the GCLK_SERCOMx_CORE clock or an external
clock.
Address matching logic is included for SPI and I2C operation.
31.6.2.
Basic Operation
31.6.2.1. Initialization
The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control
A register (CTRLA.MODE). Refer to table SERCOM Modes for details.
Table 31-1. SERCOM Modes
CTRLA.MODE
Description
0x0
USART with external clock
0x1
USART with internal clock
0x2
SPI in slave operation
0x3
SPI in master operation
0x4
I2C slave operation
0x5
I2C master operation
0x6-0x7
Reserved
For further initialization information, see the respective SERCOM mode chapters:
Related Links
SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter on page 518
SERCOM SPI – SERCOM Serial Peripheral Interface on page 558
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SERCOM I2C – SERCOM Inter-Integrated Circuit on page 591
31.6.2.2. Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and
disabled by writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of
this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled.
Refer to the CTRLA register description for details.
31.6.2.3. Clock Generation – Baud-Rate Generator
The baud-rate generator, as shown in Figure 31-3 Baud Rate Generator, generates internal clocks for
asynchronous and synchronous communication. The output frequency (fBAUD) is determined by the Baud
register (BAUD) setting and the baud reference frequency (fref). The baud reference clock is the serial
engine clock, and it can be internal or external.
For asynchronous communication, the /16 (divide-by-16) output is used when transmitting, whereas the /1
(divide-by-1) output is used while receiving.
For synchronous communication, the /2 (divide-by-2) output is used.
This functionality is automatically configured, depending on the selected operating mode.
Figure 31-3. Baud Rate Generator
Selectable
Internal Clk
(GCLK)
Baud Rate Generator
1
Ext Clk
CTRLA.MODE[0]
0
fref
Base
Period
/2
/1
/8
/2
/16
0
Tx Clk
1
1
CTRLA.MODE
0
1
Clock
Recovery
Rx Clk
0
Table 31-2 Baud Rate Equations contains equations for the baud rate (in bits per second) and the BAUD
register value for each operating mode.
For asynchronous operation, there are two different modes: In arithmetic mode, the BAUD register value
is 16 bits (0 to 65,535). In fractional mode, the BAUD register is 13 bits, while the fractional adjustment is
3 bits. In this mode the BAUD setting must be greater than or equal to 1.
For synchronous operation, the BAUD register value is 8 bits (0 to 255).
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Table 31-2. Baud Rate Equations
Operating Mode Condition
Asynchronous
Arithmetic
����� ≤
Asynchronous
Fractional
����� ≤
Synchronous
����� ≤
Baud Rate (Bits Per Second)
����
S
����� =
����
S
����� =
����
2
����� =
����
����
1−
S
65536
����
S ⋅ ���� +
��
8
����
2 ⋅ ���� + 1
BAUD Register Value Calculation
���� = 65536 ⋅ 1 − � ⋅
���� =
���� =
S - Number of samples per bit. Can be 16, 8, or 3.
����
��
−
� ⋅ �����
8
�����
����
����
−1
2 ⋅ �����
The Asynchronous Fractional option is used for auto-baud detection.
The baud rate error is represented by the following formula:
Error = 1 −
ExpectedBaudRate
ActualBaudRate
Asynchronous Arithmetic Mode BAUD Value Selection
The formula given for fBAUD calculates the average frequency over 65536 fref cycles. Although the BAUD
register can be set to any value between 0 and 65536, the actual average frequency of fBAUD over a
single frame is more granular. The BAUD register values that will affect the average frequency over a
single frame lead to an integer increase in the cycles per frame (CPF)
��� =
where
•
•
����
�+�
�����
D represent the data bits per frame
S represent the sum of start and first stop bits, if present.
Table 31-3 BAUD Register Value vs. Baud Frequency shows the BAUD register value versus baud
frequency fBAUD at a serial engine frequency of 48MHz. This assumes a D value of 8 bits and an S value
of 2 bits (10 bits, including start and stop bits).
Table 31-3. BAUD Register Value vs. Baud Frequency
BAUD Register Value
Serial Engine CPF
fBAUD at 48MHz Serial Engine Frequency (fREF)
0 – 406
160
3MHz
407 – 808
161
2.981MHz
809 – 1205
162
2.963MHz
...
...
...
65206
31775
15.11kHz
65207
31871
15.06kHz
65208
31969
15.01kHz
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31.6.3.
Additional Features
31.6.3.1. Address Match and Mask
The SERCOM address match and mask feature is capable of matching either one address, two unique
addresses, or a range of addresses with a mask, based on the mode selected. The match uses seven or
eight bits, depending on the mode.
Address With Mask
An address written to the Address bits in the Address register (ADDR.ADDR), and a mask written to the
Address Mask bits in the Address register (ADDR.ADDRMASK) will yield an address match. All bits that
are masked are not included in the match. Note that writing the ADDR.ADDRMASK to 'all zeros' will
match a single unique address, while writing ADDR.ADDRMASK to 'all ones' will result in all addresses
being accepted.
Figure 31-4. Address With Mask
ADDR
ADDRMASK
==
Match
rx shift register
Two Unique Addresses
The two addresses written to ADDR and ADDRMASK will cause a match.
Figure 31-5. Two Unique Addresses
ADDR
==
Match
rx shift register
==
ADDRMASK
Address Range
The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match.
ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the
upper limit and ADDR.ADDRMASK acting as the lower limit.
Figure 31-6. Address Range
ADDRMASK
31.6.4.
rx shift register
ADDR
== Match
DMA Operation
Not applicable.
31.6.5.
Interrupts
Interrupt sources are mode-specific. See the respective SERCOM mode chapters for details.
Each interrupt source has its own interrupt flag.
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The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt
condition is met.
Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable
Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear
register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or
the SERCOM is reset. For details on clearing interrupt flags, refer to the INTFLAG register description.
The SERCOM has one common interrupt request line for all the interrupt sources. The value of INTFLAG
indicates which interrupt condition occurred. The user must read the INTFLAG register to determine
which interrupt condition is present.
Note: Note that interrupts must be globally enabled for interrupt requests.
Related Links
Nested Vector Interrupt Controller on page 43
31.6.6.
Events
Not applicable.
31.6.7.
Sleep Mode Operation
The peripheral can operate in any sleep mode where the selected serial clock is running. This clock can
be external or generated by the internal baud-rate generator.
The SERCOM interrupts can be used to wake up the device from sleep modes. Refer to the different
SERCOM mode chapters for details.
31.6.8.
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register
description.
Related Links
Register Synchronization on page 123
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32.
SERCOM USART – SERCOM Universal Synchronous and
Asynchronous Receiver and Transmitter
32.1.
Overview
The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available
modes in the Serial Communication Interface (SERCOM).
The USART uses the SERCOM transmitter and receiver, see Block Diagram. Labels in uppercase letters
are synchronous to CLK_SERCOMx_APB and accessible for CPU. Labels in lowercase letters can be
programmed to run on the internal generic clock or an external clock.
The transmitter consists of a single write buffer, a shift register, and control logic for different frame
formats. The write buffer support data transmission without any delay between frames. The receiver
consists of a two-level receive buffer and a shift register. Status information of the received data is
available for error checking. Data and clock recovery units ensure robust synchronization and noise
filtering during asynchronous data reception.
Related Links
SERCOM – Serial Communication Interface on page 510
32.2.
USART Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full-duplex operation
Asynchronous (with clock reconstruction) or synchronous operation
Internal or external clock source for asynchronous and synchronous operation
Baud-rate generator
Supports serial frames with 5, 6, 7, 8 or 9 data bits and 1 or 2 stop bits
Odd or even parity generation and parity check
Selectable LSB- or MSB-first data transfer
Buffer overflow and frame error detection
Noise filtering, including false start-bit detection and digital low-pass filter
Collision detection
Can operate in all sleep modes
Operation at speeds up to half the system clock for internally generated clocks
Operation at speeds up to the system clock for externally generated clocks
RTS and CTS flow control
IrDA modulation and demodulation up to 115.2kbps
LIN master support
LIN slave support
– Auto-baud and break character detection
RS485 Support
Start-of-frame detection
Can work with DMA
Related Links
Features on page 510
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32.3.
Block Diagram
Figure 32-1. USART Block Diagram
BAUD
GCLK
(internal)
TX DATA
baud rate generator
/1 - /2 - /16
tx shift register
TxD
rx shift register
RxD
XCK
32.4.
status
rx buffer
STATUS
RX DATA
Signal Description
Table 32-1. SERCOM USART Signals
Signal Name
Type
Description
PAD[3:0]
Digital I/O
General SERCOM pins
One signal can be mapped to one of several pins.
Related Links
I/O Multiplexing and Considerations on page 28
32.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
32.5.1.
I/O Lines
Using the USART’s I/O lines requires the I/O pins to be configured using the I/O Pin Controller (PORT).
When the SERCOM is used in USART mode, the SERCOM controls the direction and value of the I/O
pins according to the table below. Both PORT control bits PINCFGn.PULLEN and PINCFGn.DRVSTR are
still effective. If the receiver or transmitter is disabled, these pins can be used for other purposes.
Table 32-2. USART Pin Configuration
Pin
Pin Configuration
TxD
Output
RxD
Input
XCK
Output or input
The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in
the Control A register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of
the USART signals in Table 32-2 USART Pin Configuration.
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Related Links
PORT: IO Pin Controller on page 455
32.5.2.
Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The
interrupts can wake up the device from sleep modes.
Related Links
PM – Power Manager on page 177
32.5.3.
Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be disabled and enabled
in the Main Clock Controller. Refer to Peripheral Clock Masking for details.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SERCOMx_CORE. This clock must
be configured and enabled in the Generic Clock Controller before using the SERCOMx_CORE. Refer to
GCLK - Generic Clock Controller for details.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writing to certain
registers will require synchronization to the clock domains. Refer to Synchronizationfor further details.
Related Links
Peripheral Clock Masking on page 152
GCLK - Generic Clock Controller on page 127
32.5.4.
DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
DMAC – Direct Memory Access Controller on page 346
32.5.5.
Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
Nested Vector Interrupt Controller on page 43
32.5.6.
Events
Not applicable.
32.5.7.
Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging refer to the Debug Control (DBGCTRL) register for details.
32.5.8.
Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
PAC Write-Protection is not available for the following registers:
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•
•
•
Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual
register description.
Write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
32.5.9.
Analog Connections
Not applicable.
32.6.
Functional Description
32.6.1.
Principle of Operation
The USART uses the following lines for data transfer:
•
•
•
RxD for receiving
TxD for transmitting
XCK for the transmission clock in synchronous operation
USART data transfer is frame based. A serial frame consists of:
•
•
•
•
1 start bit
From 5 to 9 data bits (MSB or LSB first)
No, even or odd parity bit
1 or 2 stop bits
A frame starts with the start bit followed by one character of data bits. If enabled, the parity bit is inserted
after the data bits and before the first stop bit. After the stop bit(s) of a frame, either the next frame can
follow immediately, or the communication line can return to the idle (high) state. The figure below
illustrates the possible frame formats. Brackets denote optional bits.
Figure 32-2. Frame Formats
Frame
(IDLE)
St
St
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Sp1
[Sp2]
[St/IDL]
Start bit. Signal is always low.
n, [n]
Data bits. 0 to [5..9]
[P]
Parity bit. Either odd or even.
Sp, [Sp]
IDLE
0
Stop bit. Signal is always high.
No frame is transferred on the communication line. Signal is always high in this state.
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32.6.2.
Basic Operation
32.6.2.1. Initialization
The following registers are enable-protected, meaning they can only be written when the USART is
disabled (CTRL.ENABLE=0):
•
•
•
Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits.
Control B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN)
bits.
Baud register (BAUD)
Any writes to these registers when the USART is enabled or is being enabled (CTRL.ENABLE is one) will
be discarded. Writes to these registers while the peripheral is being disabled, will be completed after the
disabling is complete.
When the USART is enabled or is being enabled (CTRLA.ENABLE=1), any writing attempt to these
registers will be discarded. If the peripheral is being disabled, writing to these registers will be executed
after disabling is completed. Enable-protection is denoted by the "Enable-Protection" property in the
register description.
Before the USART is enabled, it must be configured by these steps:
1.
Select either external (0x0) or internal clock (0x1) by writing the Operating Mode value in the
CTRLA register (CTRLA.MODE).
2. Select either asynchronous (0) or or synchronous (1) communication mode by writing the
Communication Mode bit in the CTRLA register (CTRLA.CMODE).
3. Select pin for receive data by writing the Receive Data Pinout value in the CTRLA register
(CTRLA.RXPO).
4. Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the
CTRLA register (CTRLA.TXPO).
5. Configure the Character Size field in the CTRLB register (CTRLB.CHSIZE) for character size.
6. Set the Data Order bit in the CTRLA register (CTRLA.DORD) to determine MSB- or LSB-first data
transmission.
7. To use parity mode:
7.1.
Enable parity mode by writing 0x1 to the Frame Format field in the CTRLA register
(CTRLA.FORM).
7.2.
Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd
parity.
8. Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register
(CTRLB.SBMODE).
9. When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate.
10. Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable
bits in the CTRLB register (CTRLB.RXEN and CTRLB.TXEN).
32.6.2.2. Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and
disabled by writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of
this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled.
Refer to the CTRLA register description for details.
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32.6.2.3. Clock Generation and Selection
For both synchronous and asynchronous modes, the clock used for shifting and sampling data can be
generated internally by the SERCOM baud-rate generator or supplied externally through the XCK line.
The synchronous mode is selected by writing a '1' to the Communication Mode bit in the Control A
register (CTRLA.CMODE), the asynchronous mode is selected by writing a zero to CTRLA.CMODE.
The internal clock source is selected by writing 0x1 to the Operation Mode bit field in the Control A
register (CTRLA.MODE), the external clock source is selected by writing 0x0 to CTRLA.MODE.
The SERCOM baud-rate generator is configured as in the figure below.
In asynchronous mode (CTRLA.CMODE=0), the 16-bit Baud register value is used.
In synchronous mode (CTRLA.CMODE=1), the eight LSBs of the Baud register are used. Refer to Clock
Generation – Baud-Rate Generator for details on configuring the baud rate.
Figure 32-3. Clock Generation
XCKInternal Clk
(GCLK)
CTRLA.MODE[0]
Baud Rate Generator
1
0
Base
Period
/2
/1
/8
/2
/8
0 Tx Clk
1
1
0
XCK
CTRLA.CMODE
1 Rx Clk
0
Related Links
Clock Generation – Baud-Rate Generator on page 514
Asynchronous Arithmetic Mode BAUD Value Selection on page 515
Synchronous Clock Operation
In synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK)
serves either as input or output. The dependency between clock edges, data sampling, and data change
is the same for internal and external clocks. Data input on the RxD pin is sampled at the opposite XCK
clock edge when data is driven on the TxD pin.
The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for
RxD sampling, and which is used for TxD change:
When CTRLA.CPOL is '0', the data will be changed on the rising edge of XCK, and sampled on the falling
edge of XCK.
When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK, and sampled on the rising
edge of XCK.
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Figure 32-4. Synchronous Mode XCK Timing
Change
XCK
CTRLA.CPOL=1
RxD / TxD
Change
Sample
XCK
CTRLA.CPOL=0
RxD / TxD
Sample
When the clock is provided through XCK (CTRLA.MODE=0x0), the shift registers operate directly on the
XCK clock. This means that XCK is not synchronized with the system clock and, therefore, can operate at
frequencies up to the system frequency.
32.6.2.4. Data Register
The USART Transmit Data register (TxDATA) and USART Receive Data register (RxDATA) share the
same I/O address, referred to as the Data register (DATA). Writing the DATA register will update the
TxDATA register. Reading the DATA register will return the contents of the RxDATA register.
32.6.2.5. Data Transmission
Data transmission is initiated by writing the data to be sent into the DATA register. Then, the data in
TxDATA will be moved to the shift register when the shift register is empty and ready to send a new
frame. After the shift register is loaded with data, the data frame will be transmitted.
When the entire data frame including stop bit(s) has been transmitted and no new data was written to
DATA, the Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC)
will be set, and the optional interrupt will be generated.
The Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates
that the register is empty and ready for new data. The DATA register should only be written to when
INTFLAG.DRE is set.
Disabling the Transmitter
The transmitter is disabled by writing '0' to the Transmitter Enable bit in the CTRLB register
(CTRLB.TXEN).
Disabling the transmitter will complete only after any ongoing and pending transmissions are completed,
i.e., there is no data in the transmit shift register and TxDATA to transmit.
32.6.2.6. Data Reception
The receiver accepts data when a valid start bit is detected. Each bit following the start bit will be sampled
according to the baud rate or XCK clock, and shifted into the receive shift register until the first stop bit of
a frame is received. The second stop bit will be ignored by the receiver.
When the first stop bit is received and a complete serial frame is present in the receive shift register, the
contents of the shift register will be moved into the two-level receive buffer. Then, the Receive Complete
interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set, and the optional
interrupt will be generated.
The received data can be read from the DATA register when the Receive Complete interrupt flag is set.
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Disabling the Receiver
Writing '0' to the Receiver Enable bit in the CTRLB register (CTRLB.RXEN) will disable the receiver, flush
the two-level receive buffer, and data from ongoing receptions will be lost.
Error Bits
The USART receiver has three error bits in the Status (STATUS) register: Frame Error (FERR), Buffer
Overflow (BUFOVF), and Parity Error (PERR). Once an error happens, the corresponding error bit will be
set until it is cleared by writing ‘1’ to it. These bits are also cleared automatically when the receiver is
disabled.
There are two methods for buffer overflow notification, selected by the Immediate Buffer Overflow
Notification bit in the Control A register (CTRLA.IBON):
When CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then
empty the receive FIFO by reading RxDATA, until the receiver complete interrupt flag (INTFLAG.RXC) is
cleared.
When CTRLA.IBON=0, the buffer overflow condition is attending data through the receive FIFO. After the
received data is read, STATUS.BUFOVF will be set along with INTFLAG.RXC.
Asynchronous Data Reception
The USART includes a clock recovery and data recovery unit for handling asynchronous data reception.
The clock recovery logic can synchronize the incoming asynchronous serial frames at the RxD pin to the
internally generated baud-rate clock.
The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving the
noise immunity of the receiver.
Asynchronous Operational Range
The operational range of the asynchronous reception depends on the accuracy of the internal baud-rate
clock, the rate of the incoming frames, and the frame size (in number of bits). In addition, the operational
range of the receiver is depending on the difference between the received bit rate and the internally
generated baud rate. If the baud rate of an external transmitter is too high or too low compared to the
internally generated baud rate, the receiver will not be able to synchronize the frames to the start bit.
There are two possible sources for a mismatch in baud rate: First, the reference clock will always have
some minor instability. Second, the baud-rate generator cannot always do an exact division of the
reference clock frequency to get the baud rate desired. In this case, the BAUD register value should be
set to give the lowest possible error. Refer to Clock Generation – Baud-Rate Generator for details.
Recommended maximum receiver baud-rate errors for various character sizes are shown in the table
below.
Table 32-3. Asynchronous Receiver Error for 16-fold Oversampling
D
RSLOW [%] RFAST [%] Max. total error [%] Recommended max. Rx error [%]
(Data bits+Parity)
5
94.12
107.69
+5.88/-7.69
±2.5
6
94.92
106.67
+5.08/-6.67
±2.0
7
95.52
105.88
+4.48/-5.88
±2.0
8
96.00
105.26
+4.00/-5.26
±2.0
9
96.39
104.76
+3.61/-4.76
±1.5
10
96.70
104.35
+3.30/-4.35
±1.5
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The following equations calculate the ratio of the incoming data rate and internal receiver baud rate:
�SLOW =
•
•
•
•
•
•
�+ 1 �
� − 1 + � ⋅ � + ��
�FAST =
,
�+ 2 �
� + 1 � + ��
RSLOW is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver
baud rate
RFAST is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver
baud rate
D is the sum of character size and parity size (D = 5 to 10 bits)
S is the number of samples per bit (S = 16, 8 or 3)
SF is the first sample number used for majority voting (SF = 7, 3, or 2) when CTRLA.SAMPA=0.
SM is the middle sample number used for majority voting (SM = 8, 4, or 2) when CTRLA.SAMPA=0.
The recommended maximum Rx Error assumes that the receiver and transmitter equally divide the
maximum total error. Its connection to the SERCOM Receiver error acceptance is depicted in this figure:
Figure 32-5. USART Rx Error Calculation
SERCOM Receiver error acceptance
from RSLOW and RFAST formulas
Error Max (%)
+
+ offset error
Baud Generator
depends on BAUD register value
Clock source error
+
Recommended max. Rx Error (%)
Baud Rate
Error Min (%)
The recommendation values in the table above accommodate errors of the clock source and the baud
generator. The following figure gives an example for a baud rate of 3Mbps:
Figure 32-6. USART Rx Error Calculation Example
SERCOM Receiver error acceptance
sampling = x16
data bits = 10
parity = 0
start bit = stop bit = 1
Error Max 3.3%
+
No baud generator offset error
+
Fbaud(3Mbps) = 48MHz *1(BAUD=0) /16
Error Max 3.3%
Accepted
+
Receiver
Error
+
DFLL source at 3MHz
Transmitter Error*
+/-0.3%
Error Max 3.0%
Baud Rate 3Mbps
Error Min -4.05%
Error Min -4.35%
Error Min -4.35%
security margin
*Transmitter Error depends on the external transmitter used in the application.
It is advised that it is within the Recommended max. Rx Error (+/-1.5% in this example).
Larger Transmitter Errors are acceptable but must lie within the Accepted Receiver Error.
Recommended
max. Rx Error +/-1.5%
(example)
Related Links
Clock Generation – Baud-Rate Generator on page 514
Asynchronous Arithmetic Mode BAUD Value Selection on page 515
32.6.3.
Additional Features
32.6.3.1. Parity
Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit field in the
Control A register (CTRLA.FORM).
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If even parity is selected (CTRLB.PMODE=0), the parity bit of an outgoing frame is '1' if the data contains
an odd number of bits that are '1', making the total number of '1' even.
If odd parity is selected (CTRLB.PMODE=1), the parity bit of an outgoing frame is '1' if the data contains
an even number of bits that are '0', making the total number of '1' odd.
When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming
frames and compares the result with the parity bit of the corresponding frame. If a parity error is detected,
the Parity Error bit in the Status register (STATUS.PERR) is set.
32.6.3.2. Hardware Handshaking
The USART features an out-of-band hardware handshaking flow control mechanism, implemented by
connecting the RTS and CTS pins with the remote device, as shown in the figure below.
Figure 32-7. Connection with a Remote Device for Hardware Handshaking
USART
Remote
Device
TXD
RXD
RXD
TXD
CTS
RTS
CTS
RTS
Hardware handshaking is only available in the following configuration:
•
•
•
USART with internal clock (CTRLA.MODE=1),
Asynchronous mode (CTRLA.CMODE=0),
and Flow control pinout (CTRLA.TXPO=2).
When the receiver is disabled or the receive FIFO is full, the receiver will drive the RTS pin high. This
notifies the remote device to stop transfer after the ongoing transmission. Enabling and disabling the
receiver by writing to CTRLB.RXEN will set/clear the RTS pin after a synchronization delay. When the
receive FIFO goes full, RTS will be set immediately and the frame being received will be stored in the
shift register until the receive FIFO is no longer full.
Figure 32-8. Receiver Behavior when Operating with Hardware Handshaking
RXD
RXEN
RTS
Rx FIFO Full
The current CTS Status is in the STATUS register (STATUS.CTS). Character transmission will start only if
STATUS.CTS=0. When CTS is set, the transmitter will complete the ongoing transmission and stop
transmitting.
Figure 32-9. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
32.6.3.3. IrDA Modulation and Demodulation
Transmission and reception can be encoded IrDA compliant up to 115.2 kb/s. IrDA modulation and
demodulation work in the following configuration:
•
•
IrDA encoding enabled (CTRLB.ENC=1),
Asynchronous mode (CTRLA.CMODE=0),
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•
and 16x sample rate (CTRLA.SAMPR[0]=0).
During transmission, each low bit is transmitted as a high pulse. The pulse width is 3/16 of the baud rate
period, as illustrated in the figure below.
Figure 32-10. IrDA Transmit Encoding
1 baud clock
TXD
IrDA encoded TXD
3/16 baud clock
The reception decoder has two main functions.
The first is to synchronize the incoming data to the IrDA baud rate counter. Synchronization is performed
at the start of each zero pulse.
The second main function is to decode incoming Rx data. If a pulse width meets the minimum length set
by configuration (RXPL.RXPL), it is accepted. When the baud rate counter reaches its middle value (1/2
bit length), it is transferred to the receiver.
Note: Note that the polarity of the transmitter and receiver are opposite: During transmission, a '0' bit is
transmitted as a '1' pulse. During reception, an accepted '0' pulse is received as a '0' bit.
Example: The figure below illustrates reception where RXPL.RXPL is set to 19. This
indicates that the pulse width should be at least 20 SE clock cycles. When using
BAUD=0xE666 or 160 SE cycles per bit, this corresponds to 2/16 baud clock as minimum
pulse width required. In this case the first bit is accepted as a '0', the second bit is a '1',
and the third bit is also a '1'. A low pulse is rejected since it does not meet the minimum
requirement of 2/16 baud clock.
Figure 32-11. IrDA Receive Decoding
Baud clock
0
0.5
1
1.5
2
2.5
IrDA encoded RXD
RXD
20 SE clock cycles
32.6.3.4. Break Character Detection and Auto-Baud
Break character detection and auto-baud are available in this configuration:
•
•
Auto-baud frame format (CTRLA.FORM = 0x04 or 0x05),
Asynchronous mode (CTRLA.CMODE = 0),
•
and 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1).
The auto-baud follows the LIN format. All LIN Frames start with a Break Field followed by a Sync Field.
The USART uses a break detection threshold of greater than 11 nominal bit times at the configured baud
rate. At any time, if more than 11 consecutive dominant bits are detected on the bus, the USART detects
a Break Field. When a Break Field has been detected, the Receive Break interrupt flag
(INTFLAG.RXBRK) is set and the USART expects the Sync Field character to be 0x55. This field is used
to update the actual baud rate in order to stay synchronized. If the received Sync character is not 0x55,
then the Inconsistent Sync Field error flag (STATUS.ISF) is set along with the Error interrupt flag
(INTFLAG.ERROR), and the baud rate is unchanged.
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Figure 32-12. LIN Break and Sync Fields
Break Field
Sync Field
8 bit times
After a break field is detected and the start bit of the Sync Field is detected, a counter is started. The
counter is then incremented for the next 8 bit times of the Sync Field. At the end of these 8 bit times, the
counter is stopped. At this moment, the 13 most significant bits of the counter (value divided by 8) give
the new clock divider (BAUD.BAUD), and the 3 least significant bits of this value (the remainder) give the
new Fractional Part (BAUD.FP).
When the Sync Field has been received, the clock divider (BAUD.BAUD) and the Fractional Part
(BAUD.FP) are updated after a synchronization delay. After the Break and Sync Fields are received,
multiple characters of data can be received.
32.6.3.5. RS485
RS485 is available with the following configuration:
•
USART frame format (CTRLA.FORM = 0x00 or 0x01)
•
RS485 pinout (CTRLA.TXPO=0x3).
The RS485 feature enables control of an external line driver as shown in the figure below. While
operating in RS485 mode, the transmit enable pin (TE) is driven high when the transmitter is active.
Figure 32-13. RS485 Bus Connection
USART
RXD
Differential
Bus
TXD
TE
The TE pin will remain high for the complete frame including stop bit(s). If a Guard Time is programmed in
the Control C register (CTRLC.GTIME), the line will remain driven after the last character completion. The
following figure shows a transfer with one stop bit and CTRLC.GTIME=3.
Figure 32-14. Example of TE Drive with Guard Time
Start
Data
Stop GTIME=3
TXD
TE
The Transmit Complete interrupt flag (INTFLAG.TXC) will be raised after the guard time is complete and
TE goes low.
32.6.3.6. Collision Detection
When the receiver and transmitter are connected either through pin configuration or externally, transmit
collision can be detected after selecting the Collision Detection Enable bit in the CTRLB register
(CTRLB.COLDEN=1). To detect collision, the receiver and transmitter must be enabled (CTRLB.RXEN=1
and CTRLB.TXEN=1).
Collision detection is performed for each bit transmitted by comparing the received value with the transmit
value, as shown in the figure below. While the transmitter is idle (no transmission in progress), characters
can be received on RxD without triggering a collision.
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Figure 32-15. Collision Checking
8-bit character, single stop bit
TXD
RXD
Collision checked
The next figure shows the conditions for a collision detection. In this case, the start bit and the first data
bit are received with the same value as transmitted. The second received data bit is found to be different
than the transmitted bit at the detection point, which indicates a collision.
Figure 32-16. Collision Detected
Collision checked and ok
Tri-state
TXD
RXD
TXEN
Collision detected
When a collision is detected, the USART follows this sequence:
1. Abort the current transfer.
2. Flush the transmit buffer.
3. Disable transmitter (CTRLB.TXEN=0)
– This is done after a synchronization delay. The CTRLB Synchronization Busy bit
(SYNCBUSY.CTRLB) will be set until this is complete.
– After disabling, the TxD pin will be tri-stated.
4. Set the Collision Detected bit (STATUS.COLL) along with the Error interrupt flag
(INTFLAG.ERROR).
5. Set the Transmit Complete interrupt flag (INTFLAG.TXC), since the transmit buffer no longer
contains data.
After a collision, software must manually enable the transmitter again before continuing, after assuring
that the CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not set.
32.6.3.7. Loop-Back Mode
For loop-back mode, configure the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout
(CTRLA.TXPO) to use the same data pins for transmit and receive. The loop-back is through the pad, so
the signal is also available externally.
32.6.3.8. Start-of-Frame Detection
The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep
mode, the internal fast startup oscillator must be selected as the GCLK_SERCOMx_CORE source.
When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART
clock is enabled. After startup, the rest of the data frame can be received, provided that the baud rate is
slow enough in relation to the fast startup internal oscillator start-up time. Refer to Electrical
Characteristics for details. The start-up time of this oscillator varies with supply voltage and temperature.
The USART start-of-frame detection works both in asynchronous and synchronous modes. It is enabled
by writing ‘1’ to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE).
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If the Receive Start Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the
Receive Start interrupt is generated immediately when a start is detected.
When using start-of-frame detection without the Receive Start interrupt, start detection will force the
8MHz Internal Oscillator and USART clock active while the frame is being received. In this case, the CPU
will not wake up until the Receive Complete interrupt is generated.
Related Links
Electrical Characteristics 85°C on page 900
32.6.3.9. Sample Adjustment
In asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value
based on majority voting. The three samples used for voting can be selected using the Sample
Adjustment bit field in Control A register (CTRLA.SAMPA). When CTRLA.SAMPA=0, samples 7-8-9 are
used for 16x oversampling, and samples 3-4-5 are used for 8x oversampling.
32.6.4.
DMA, Interrupts and Events
Table 32-4. Module Request for SERCOM USART
Condition
Request
DMA
Interrupt
Event
Data Register Empty (DRE)
Yes
(request cleared when data is written)
Yes
NA
Receive Complete (RXC)
Yes
(request cleared when data is read)
Yes
Transmit Complete (TXC)
NA
Yes
Receive Start (RXS)
NA
Yes
Clear to Send Input Change (CTSIC)
NA
Yes
Receive Break (RXBRK)
NA
Yes
Error (ERROR)
NA
Yes
32.6.4.1. DMA Operation
The USART generates the following DMA requests:
•
•
Data received (RX): The request is set when data is available in the receive FIFO. The request is
cleared when DATA is read.
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is
cleared when DATA is written.
32.6.4.2. Interrupts
The USART has the following interrupt sources. These are asynchronous interrupts, and can wake up the
device from any sleep mode:
•
•
•
•
•
Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
Receive Start (RXS)
Clear to Send Input Change (CTSIC)
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•
•
Received Break (RXBRK)
Error (ERROR)
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually
enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and
disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is
enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is
disabled, or the USART is reset. For details on clearing interrupt flags, refer to the INTFLAG register
description.
The USART has one common interrupt request line for all the interrupt sources. The value of INTFLAG
indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests.
Refer to Nested Vector Interrupt Controller for details.
Related Links
Nested Vector Interrupt Controller on page 43
32.6.4.3. Events
Not applicable.
32.6.5.
Sleep Mode Operation
The behavior in sleep mode is depending on the clock source and the Run In Standby bit in the Control A
register (CTRLA.RUNSTDBY):
•
Internal clocking, CTRLA.RUNSTDBY=1: GCLK_SERCOMx_CORE can be enabled in all sleep
modes. Any interrupt can wake up the device.
•
External clocking, CTRLA.RUNSTDBY=1: The Receive Start and the Receive Complete interrupt(s)
can wake up the device.
•
Internal clocking, CTRLA.RUNSTDBY=0: Internal clock will be disabled, after any ongoing transfer
was completed. The Receive Start and the Receive Complete interrupt(s) can wake up the device.
•
External clocking, CTRLA.RUNSTDBY=0: External clock will be disconnected, after any ongoing
transfer was completed. All reception will be dropped.
32.6.6.
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
•
•
•
•
Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
Transmitter Enable bit in the Control B register (CTRLB.TXEN)
Note: CTRLB.RXEN is write-synchronized somewhat differently. See also CTRLB for details.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
Related Links
Register Synchronization on page 123
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32.7.
Offset
Register Summary
Name
0x00
0x01
0x02
Bit Pos.
7:0
CTRLA
RUNSTDBY
15:8
MODE[2:0]
SAMPR[2:0]
23:16
SAMPA[1:0]
0x03
31:24
DORD
0x04
7:0
SBMODE
0x05
15:8
0x06
CTRLB
31:24
0x08
7:0
0x09
CTRLC
0x0B
0x0C
0x0D
0x0E
SWRST
IBON
RXPO[1:0]
CPOL
TXPO[1:0]
CMODE
FORM[3:0]
CHSIZE[2:0]
PMODE
ENC
23:16
0x07
0x0A
ENABLE
SFDE
COLDEN
RXEN
TXEN
GTIME[2:0]
15:8
HDRDLY[1:0]
BRKLEN[1:0]
23:16
31:24
BAUD
RXPL
7:0
BAUD[7:0]
15:8
BAUD[15:8]
7:0
RXPL[7:0]
0x0F
...
Reserved
0x13
0x14
INTENCLR
0x15
Reserved
0x16
INTENSET
0x17
Reserved
0x18
INTFLAG
0x19
Reserved
0x1A
0x1B
STATUS
7:0
ERROR
RXBRK
CTSIC
RXS
RXC
TXC
DRE
7:0
ERROR
RXBRK
CTSIC
RXS
RXC
TXC
DRE
7:0
ERROR
RXBRK
CTSIC
RXS
RXC
TXC
DRE
COLL
ISF
CTS
BUFOVF
FERR
PERR
CTRLB
ENABLE
SWRST
7:0
15:8
0x1C
7:0
0x1D
15:8
0x1E
SYNCBUSY
0x1F
TXE
23:16
31:24
0x20
...
Reserved
0x27
0x28
0x29
DATA
7:0
DATA[7:0]
15:8
DATA[8:8]
7:0
DBGSTOP
0x2A
...
Reserved
0x2F
0x30
32.8.
DBGCTRL
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
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Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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32.8.1.
Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
Access
30
29
28
DORD
CPOL
CMODE
R/W
R/W
0
0
22
21
Reset
Bit
23
SAMPA[1:0]
Access
27
26
25
24
R/W
R/W
R/W
0
R/W
R/W
0
0
0
0
20
19
18
17
FORM[3:0]
RXPO[1:0]
16
TXPO[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
SAMPR[2:0]
Access
Reset
Bit
R/W
R/W
R/W
R
0
0
0
0
7
6
5
4
3
RUNSTDBY
Access
Reset
8
IBON
2
MODE[2:0]
1
0
ENABLE
SWRST
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit 30 – DORD: Data Order
This bit selects the data order when a character is shifted out from the Data register.
This bit is not synchronized.
Value
Description
0
MSB is transmitted first.
1
LSB is transmitted first.
Bit 29 – CPOL: Clock Polarity
This bit selects the relationship between data output change and data input sampling in synchronous
mode.
This bit is not synchronized.
CPOL
TxD Change
RxD Sample
0x0
Rising XCK edge
Falling XCK edge
0x1
Falling XCK edge
Rising XCK edge
Bit 28 – CMODE: Communication Mode
This bit selects asynchronous or synchronous communication.
This bit is not synchronized.
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Value
Description
0
Asynchronous communication.
1
Synchronous communication.
Bits 27:24 – FORM[3:0]: Frame Format
These bits define the frame format.
These bits are not synchronized.
FORM[3:0]
Description
0x0
USART frame
0x1
USART frame with parity
0x2-0x3
Reserved
0x4
Auto-baud - break detection and auto-baud.
0x5
Auto-baud - break detection and auto-baud
with parity
0x6-0xF
Reserved
Bits 23:22 – SAMPA[1:0]: Sample Adjustment
These bits define the sample adjustment.
These bits are not synchronized.
SAMPA[1:0]
16x Over-sampling
(CTRLA.SAMPR=0 or 1)
8x Over-sampling
(CTRLA.SAMPR=2 or 3)
0x0
7-8-9
3-4-5
0x1
9-10-11
4-5-6
0x2
11-12-13
5-6-7
0x3
13-14-15
6-7-8
Bits 21:20 – RXPO[1:0]: Receive Data Pinout
These bits define the receive data (RxD) pin configuration.
These bits are not synchronized.
RXPO[1:0]
Name
Description
0x0
PAD[0]
SERCOM PAD[0] is used for data reception
0x1
PAD[1]
SERCOM PAD[1] is used for data reception
0x2
PAD[2]
SERCOM PAD[2] is used for data reception
0x3
PAD[3]
SERCOM PAD[3] is used for data reception
Bits 17:16 – TXPO[1:0]: Transmit Data Pinout
These bits define the transmit data (TxD) and XCK pin configurations.
This bit is not synchronized.
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Bits 15:13 – SAMPR[2:0]: Sample Rate
These bits select the sample rate.
These bits are not synchronized.
SAMPR[2:0]
Description
0x0
16x over-sampling using arithmetic baud rate generation.
0x1
16x over-sampling using fractional baud rate generation.
0x2
8x over-sampling using arithmetic baud rate generation.
0x3
8x over-sampling using fractional baud rate generation.
0x4
3x over-sampling using arithmetic baud rate generation.
0x5-0x7
Reserved
Bit 8 – IBON: Immediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer
overflow occurs.
Value
Description
0
STATUS.BUFOVF is asserted when it occurs in the data stream.
1
STATUS.BUFOVF is asserted immediately upon buffer overflow.
Bit 7 – RUNSTDBY: Run In Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
RUNSTDBY
External Clock
Internal Clock
0x0
External clock is disconnected when
ongoing transfer is finished. All
reception is dropped.
Generic clock is disabled when ongoing
transfer is finished. The device can wake up
on Receive Start or Transfer Complete
interrupt.
0x1
Wake on Receive Start or Receive
Complete interrupt.
Generic clock is enabled in all sleep modes.
Any interrupt can wake up the device.
Bits 4:2 – MODE[2:0]: Operating Mode
These bits select the USART serial communication interface of the SERCOM.
These bits are not synchronized.
Value
Description
0x0
USART with external clock
0x1
USART with internal clock
Bit 1 – ENABLE: Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable
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Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set.
SYNCBUSY.ENABLE is cleared when the operation is complete.
This bit is not enable-protected.
Value
Description
0
The peripheral is disabled or being disabled.
1
The peripheral is enabled or being enabled.
Bit 0 – SWRST: Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the
SERCOM will be disabled.
Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same writeoperation will be discarded. Any register write access during the ongoing reset will result in an APB error.
Reading any register will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
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32.8.2.
Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
23
22
21
20
19
18
25
24
Access
Reset
Bit
17
16
RXEN
TXEN
R/W
R/W
0
0
10
9
8
PMODE
ENC
SFDE
COLDEN
R/W
R/W
R/W
R/W
0
0
0
0
1
0
Access
Reset
Bit
15
14
Access
13
Reset
Bit
7
6
5
12
4
11
3
2
SBMODE
Access
Reset
CHSIZE[2:0]
R/W
R/W
R/W
R/W
0
0
0
0
Bit 17 – RXEN: Receiver Enable
Writing '0' to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer
and clear the FERR, PERR and BUFOVF bits in the STATUS register.
Writing '1' to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the
USART is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set
until the receiver is enabled. When the receiver is enabled, CTRLB.RXEN will read back as '1'.
Writing '1' to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain
set until the receiver is enabled, and CTRLB.RXEN will read back as '1'.
This bit is not enable-protected.
Value
Description
0
The receiver is disabled or being enabled.
1
The receiver is enabled or will be enabled when the USART is enabled.
Bit 16 – TXEN: Transmitter Enable
Writing '0' to this bit will disable the USART transmitter. Disabling the transmitter will not become effective
until ongoing and pending transmissions are completed.
Writing '1' to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the
USART is enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until
the transmitter is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as '1'.
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Writing '1' to CTRLB.TXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain
set until the receiver is enabled, and CTRLB.TXEN will read back as '1'.
This bit is not enable-protected.
Value
Description
0
The transmitter is disabled or being enabled.
1
The transmitter is enabled or will be enabled when the USART is enabled.
Bit 13 – PMODE: Parity Mode
This bit selects the type of parity used when parity is enabled (CTRLA.FORM is '1'). The transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The receiver
will generate a parity value for the incoming data and parity bit, compare it to the parity mode and, if a
mismatch is detected, STATUS.PERR will be set.
This bit is not synchronized.
Value
Description
0
Even parity.
1
Odd parity.
Bit 10 – ENC: Encoding Format
This bit selects the data encoding format.
This bit is not synchronized.
Value
Description
0
Data is not encoded.
1
Data is IrDA encoded.
Bit 9 – SFDE: Start of Frame Detection Enable
This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on
the RxD line.
This bit is not synchronized.
SFDE
INTENSET.RXS INTENSET.RXC Description
0
X
X
Start-of-frame detection disabled.
1
0
0
Reserved
1
0
1
Start-of-frame detection enabled. RXC wakes up the
device from all sleep modes.
1
1
0
Start-of-frame detection enabled. RXS wakes up the
device from all sleep modes.
1
1
1
Start-of-frame detection enabled. Both RXC and RXS
wake up the device from all sleep modes.
Bit 8 – COLDEN: Collision Detection Enable
This bit enables collision detection.
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This bit is not synchronized.
Value
Description
0
Collision detection is not enabled.
1
Collision detection is enabled.
Bit 6 – SBMODE: Stop Bit Mode
This bit selects the number of stop bits transmitted.
This bit is not synchronized.
Value
Description
0
One stop bit.
1
Two stop bits.
Bits 2:0 – CHSIZE[2:0]: Character Size
These bits select the number of bits in a character.
These bits are not synchronized.
CHSIZE[2:0]
Description
0x0
8 bits
0x1
9 bits
0x2-0x4
Reserved
0x5
5 bits
0x6
6 bits
0x7
7 bits
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32.8.3.
Control C
Name: CTRLC
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
HDRDLY[1:0]
Access
Reset
Bit
7
6
5
4
BRKLEN[1:0]
GTIME[2:0]
Access
Reset
R/W
R/W
R/W
0
0
0
Bits 11:10 – HDRDLY[1:0]: LIN Master Header Delay
These bits define the delay between break and sync transmission in addition to the delay between the
sync and identifier (ID) fields when in LIN master mode (CTRLA.FORM=0x2).
This field is only valid when using the LIN header command (CTRLB.LINCMD=0x2).
Value
Description
0x0
Delay between break and sync transmission is 1 bit time.
Delay between sync and ID transmission is 1 bit time.
0x1
Delay between break and sync transmission is 4 bit time.
Delay between sync and ID transmission is 4 bit time.
0x2
Delay between break and sync transmission is 8 bit time.
Delay between sync and ID transmission is 4 bit time.
0x3
Delay between break and sync transmission is 14 bit time.
Delay between sync and ID transmission is 4 bit time.
Bits 9:8 – BRKLEN[1:0]: LIN Master Break Length
These bits define the length of the break field transmitted when in LIN master mode (CTRLA.FORM=0x2).
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Value
Description
0x0
Break field transmission is 13 bit times
0x1
Break field transmission is 17 bit times
0x2
Break field transmission is 21 bit times
0x3
Break field transmission is 26 bit times
Bits 2:0 – GTIME[2:0]: Guard Time
These bits define the guard time when using RS485 mode (CTRLA.TXPO=0x3).
For RS485 mode, the guard time is programmable from 0-7 bit times and defines the time that the
transmit enable pin (TE) remains high after the last stop bit is transmitted and there is no remaining data
to be transmitted.
Value
Description
0
The receiver is disabled or being enabled.
1
The receiver is enabled or will be enabled when the USART is enabled.
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32.8.4.
Baud
Name: BAUD
Offset: 0x0C
Reset: 0x0000
Property: Enable-Protected, PAC Write-Protection
Bit
15
14
13
12
11
10
9
8
BAUD[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
BAUD[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 15:0 – BAUD[15:0]: Baud Value
Arithmetic Baud Rate Generation (CTRLA.SAMPR[0]=0):
These bits control the clock generation, as described in the SERCOM Baud Rate section.
If Fractional Baud Rate Generation (CTRLA.SAMPR[0]=1) bit positions 15 to 13 are replaced by FP[2:0]
Fractional Part:
•
Bits 15:13 - FP[2:0]: Fractional Part
•
These bits control the clock generation, as described in the SERCOM Clock Generation – BaudRate Generator section.
Bits 12:0 - BAUD[21:0]: Baud Value
These bits control the clock generation, as described in the SERCOM Clock Generation – BaudRate Generator section.
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32.8.5.
Receive Pulse Length Register
Name: RXPL
Offset: 0x0E
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
RXPL[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7:0 – RXPL[7:0]: Receive Pulse Length
When the encoding format is set to IrDA (CTRLB.ENC=1), these bits control the minimum pulse length
that is required for a pulse to be accepted by the IrDA receiver with regards to the serial engine clock
period �����.
����� ≥ RXPL + 2 ⋅ �����
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32.8.6.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
Bit
7
Access
Reset
6
5
4
3
2
1
0
ERROR
RXBRK
CTSIC
RXS
RXC
TXC
DRE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 7 – ERROR: Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 5 – RXBRK: Receive Break Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Break Interrupt Enable bit, which disables the Receive Break
interrupt.
Value
Description
0
Receive Break interrupt is disabled.
1
Receive Break interrupt is enabled.
Bit 4 – CTSIC: Clear to Send Input Change Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Clear To Send Input Change Interrupt Enable bit, which disables the
Clear To Send Input Change interrupt.
Value
Description
0
Clear To Send Input Change interrupt is disabled.
1
Clear To Send Input Change interrupt is enabled.
Bit 3 – RXS: Receive Start Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Start Interrupt Enable bit, which disables the Receive Start
interrupt.
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Value
Description
0
Receive Start interrupt is disabled.
1
Receive Start interrupt is enabled.
Bit 2 – RXC: Receive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive
Complete interrupt.
Value
Description
0
Receive Complete interrupt is disabled.
1
Receive Complete interrupt is enabled.
Bit 1 – TXC: Transmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disables the Receive
Complete interrupt.
Value
Description
0
Transmit Complete interrupt is disabled.
1
Transmit Complete interrupt is enabled.
Bit 0 – DRE: Data Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data
Register Empty interrupt.
Value
Description
0
Data Register Empty interrupt is disabled.
1
Data Register Empty interrupt is enabled.
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32.8.7.
Interrupt Enable Set
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
Bit
7
Access
Reset
6
5
4
3
2
1
0
ERROR
RXBRK
CTSIC
RXS
RXC
TXC
DRE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 7 – ERROR: Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 5 – RXBRK: Receive Break Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break
interrupt.
Value
Description
0
Receive Break interrupt is disabled.
1
Receive Break interrupt is enabled.
Bit 4 – CTSIC: Clear to Send Input Change Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear
To Send Input Change interrupt.
Value
Description
0
Clear To Send Input Change interrupt is disabled.
1
Clear To Send Input Change interrupt is enabled.
Bit 3 – RXS: Receive Start Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start
interrupt.
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Value
Description
0
Receive Start interrupt is disabled.
1
Receive Start interrupt is enabled.
Bit 2 – RXC: Receive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive
Complete interrupt.
Value
Description
0
Receive Complete interrupt is disabled.
1
Receive Complete interrupt is enabled.
Bit 1 – TXC: Transmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit
Complete interrupt.
Value
Description
0
Transmit Complete interrupt is disabled.
1
Transmit Complete interrupt is enabled.
Bit 0 – DRE: Data Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register
Empty interrupt.
Value
Description
0
Data Register Empty interrupt is disabled.
1
Data Register Empty interrupt is enabled.
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32.8.8.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: Bit
Access
Reset
5
4
3
2
1
0
ERROR
7
6
RXBRK
CTSIC
RXS
RXC
TXC
DRE
R/W
R/W
R/W
R/W
R
R/W
R
0
0
0
0
0
0
0
Bit 7 – ERROR: Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in
the STATUS register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.Writing '0' to
this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 5 – RXBRK: Receive Break
This flag is cleared by writing '1' to it.
This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 4 – CTSIC: Clear to Send Input Change
This flag is cleared by writing a '1' to it.
This flag is set when a change is detected on the CTS pin.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 3 – RXS: Receive Start
This flag is cleared by writing '1' to it.
This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled
(CTRLB.SFDE is '1').
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Start interrupt flag.
Bit 2 – RXC: Receive Complete
This flag is cleared by reading the Data register (DATA) or by disabling the receiver.
This flag is set when there are unread data in DATA.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
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Bit 1 – TXC: Transmit Complete
This flag is cleared by writing '1' to it or by writing new data to DATA.
This flag is set when the entire frame in the transmit shift register has been shifted out and there are no
new data in DATA.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 0 – DRE: Data Register Empty
This flag is cleared by writing new data to DATA.
This flag is set when DATA is empty and ready to be written.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
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32.8.9.
Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
7
6
5
4
3
2
1
0
TXE
COLL
ISF
CTS
BUFOVF
FERR
PERR
R/W
R/W
R/W
R
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 6 – TXE: Transmitter Empty
When CTRLA.FORM is set to LIN master mode, this bit is set when any ongoing transmission is complete
and TxDATA is empty. When CTRLA.FORM is not set to LIN master mode, this bit will always read back
as zero.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 5 – COLL: Collision Detected
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 4 – ISF: Inconsistent Sync Field
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to
0x55 is received.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 3 – CTS: Clear to Send
This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO).
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 2 – BUFOVF: Buffer Overflow
Reading this bit before reading the Data register will indicate the error status of the next character to be
read.
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This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive
buffer is full, there is a new character waiting in the receive shift register and a new start bit is detected.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 1 – FERR: Frame Error
Reading this bit before reading the Data register will indicate the error status of the next character to be
read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set if the received character had a frame error, i.e., when the first stop bit is zero.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 0 – PERR: Parity Error
Reading this bit before reading the Data register will indicate the error status of the next character to be
read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set if parity checking is enabled (CTRLA.FORM is 0x1, 0x5) and a parity error is detected.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
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32.8.10. Synchronization Busy
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
CTRLB
ENABLE
SWRST
Access
R
R
R
Reset
0
0
0
Bit 2 – CTRLB: CTRLB Synchronization Busy
Writing to the CTRLB register when the SERCOM is enabled requires synchronization. When writing to
CTRLB the SYNCBUSY.CTRLB bit will be set until synchronization is complete. If CTRLB is written while
SYNCBUSY.CTRLB is asserted, an APB error will be generated.
Value
Description
0
CTRLB synchronization is not busy.
1
CTRLB synchronization is busy.
Bit 1 – ENABLE: SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the
SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be
discarded and an APB error will be generated.
Value
Description
0
Enable synchronization is not busy.
1
Enable synchronization is busy.
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Bit 0 – SWRST: Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the
SYNCBUSY.SWRST bit will be set until synchronization is complete.
Writes to any register while synchronization is on-going will be discarded and an APB error will be
generated.
Value
Description
0
SWRST synchronization is not busy.
1
SWRST synchronization is busy.
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32.8.11. Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: Bit
15
14
13
12
11
10
9
8
DATA[8:8]
Access
R/W
Reset
Bit
0
7
6
5
4
3
2
1
0
DATA[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 8:0 – DATA[8:0]: Data
Reading these bits will return the contents of the Receive Data register. The register should be read only
when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register
(INTFLAG.RXC) is set. The status bits in STATUS should be read before reading the DATA value in order
to get any corresponding error.
Writing these bits will write the Transmit Data register. This register should be written only when the Data
Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set.
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32.8.12. Debug Control
Name: DBGCTRL
Offset: 0x30
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGSTOP
Access
R/W
Reset
0
Bit 0 – DBGSTOP: Debug Stop Mode
This bit controls the baud-rate generator functionality when the CPU is halted by an external debugger.
Value
Description
0
The baud-rate generator continues normal operation when the CPU is halted by an external
debugger.
1
The baud-rate generator is halted when the CPU is halted by an external debugger.
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33.
33.1.
SERCOM SPI – SERCOM Serial Peripheral Interface
Overview
The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface
(SERCOM).
The SPI uses the SERCOM transmitter and receiver configured as shown in Block Diagram. Each side,
master and slave, depicts a separate SPI containing a shift register, a transmit buffer and two receive
buffers. In addition, the SPI master uses the SERCOM baud-rate generator, while the SPI slave can use
the SERCOM address match logic. Labels in capital letters are synchronous to CLK_SERCOMx_APB
and accessible by the CPU, while labels in lowercase letters are synchronous to the SCK clock.
Related Links
SERCOM – Serial Communication Interface on page 510
33.2.
Features
SERCOM SPI includes the following features:
•
•
•
•
•
•
•
•
1.
Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
Single-buffered transmitter, double-buffered receiver
Supports all four SPI modes of operation
Single data direction operation allows alternate function on MISO or MOSI pin
Selectable LSB- or MSB-first data transfer
Can be used with DMA
Master operation:
– Serial clock speed, fSCK=1/tSCK(1)
– 8-bit clock generator
– Hardware controlled SS
Slave operation:
– Serial clock speed, fSCK=1/tSSCK(1)
– Optional 8-bit address match operation
– Operation in all sleep modes
– Wake on SS transition
For tSCK and tSSCK values, refer to SPI Timing Characteristics.
Related Links
SERCOM in SPI Mode Timing on page 926
SERCOM – Serial Communication Interface on page 510
Features on page 510
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33.3.
Block Diagram
Figure 33-1. Full-Duplex SPI Master Slave Interconnection
Master
BAUD
Slave
Tx DATA
Tx DATA
ADDR/ADDRMASK
SCK
_SS
baud rate generator
shift register
MISO
shift register
MOSI
33.4.
rx buffer
rx buffer
Rx DATA
Rx DATA
==
Address Match
Signal Description
Table 33-1. SERCOM SPI Signals
Signal Name
Type
Description
PAD[3:0]
Digital I/O
General SERCOM pins
One signal can be mapped to one of several pins.
Related Links
I/O Multiplexing and Considerations on page 28
33.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
33.5.1.
I/O Lines
In order to use the SERCOM’s I/O lines, the I/O pins must be configured using the IO Pin Controller
(PORT).
When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the
I/O pins according to the table below. Both PORT control bits PINCFGn.PULLEN and PINCFGn.DRVSTR
are still effective. If the receiver is disabled, the data input pin can be used for other purposes. In master
mode, the slave select line (SS) is hardware controlled when the Master Slave Select Enable bit in the
Control B register (CTRLB.MSSEN) is '1'.
Table 33-2. SPI Pin Configuration
Pin
Master SPI
Slave SPI
MOSI
Output
Input
MISO
Input
Output
SCK
Output
Input
SS
Output (CTRLB.MSSEN=1)
Input
The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the
Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the
table above.
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Related Links
PORT: IO Pin Controller on page 455
33.5.2.
Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The
interrupts can wake up the device from sleep modes.
Related Links
PM – Power Manager on page 177
33.5.3.
Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled
in the Main Clock.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured
and enabled in the Generic Clock Controller before using the SPI.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writes to certain
registers will require synchronization to the clock domains.
Related Links
GCLK - Generic Clock Controller on page 127
Peripheral Clock Masking on page 152
Synchronization on page 569
33.5.4.
DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
DMAC – Direct Memory Access Controller on page 346
33.5.5.
Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
Nested Vector Interrupt Controller on page 43
33.5.6.
Events
Not applicable.
33.5.7.
Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging refer to the Debug Control (DBGCTRL) register for details.
33.5.8.
Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
PAC Write-Protection is not available for the following registers:
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•
•
•
Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual
register description.
Write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
33.5.9.
Analog Connections
Not applicable.
33.6.
Functional Description
33.6.1.
Principle of Operation
The SPI is a high-speed synchronous data transfer interface It allows high-speed communication
between the device and peripheral devices.
The SPI can operate as master or slave. As master, the SPI initiates and controls all data transactions.
The SPI is single buffered for transmitting and double buffered for receiving.
When transmitting data, the Data register can be loaded with the next character to be transmitted during
the current transmission.
When receiving, the data is transferred to the two-level receive buffer, and the receiver is ready for a new
character.
The SPI transaction format is shown in SPI Transaction Format. Each transaction can contain one or
more characters. The character size is configurable, and can be either 8 or 9 bits.
Figure 33-2. SPI Transaction Format
Transaction
Character
MOSI/MISO
Character 0
Character 1
Character 2
_SS
The SPI master must pull the slave select line (SS) of the desired slave low to initiate a transaction. The
master and slave prepare data to send via their respective shift registers, and the master generates the
serial clock on the SCK line.
Data are always shifted from master to slave on the Master Output Slave Input line (MOSI); data is shifted
from slave to master on the Master Input Slave Output line (MISO).
Each time character is shifted out from the master, a character will be shifted out from the slave
simultaneously. To signal the end of a transaction, the master will pull the SS line high
33.6.2.
Basic Operation
33.6.2.1. Initialization
The following registers are enable-protected, meaning that they can only be written when the SPI is
disabled (CTRL.ENABLE=0):
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•
•
•
•
Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset
(CTRLA.SWRST)
Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN)
Baud register (BAUD)
Address register (ADDR)
When the SPI is enabled or is being enabled (CTRLA.ENABLE=1), any writing to these registers will be
discarded.
when the SPI is being disabled, writing to these registers will be completed after the disabling.
Enable-protection is denoted by the Enable-Protection property in the register description.
Initialize the SPI by following these steps:
1. Select SPI mode in master / slave operation in the Operating Mode bit group in the CTRLA register
(CTRLA.MODE= 0x2 or 0x3 ).
2. Select transfer mode for the Clock Polarity bit and the Clock Phase bit in the CTRLA register
(CTRLA.CPOL and CTRLA.CPHA) if desired.
3. Select the Frame Format value in the CTRLA register (CTRLA.FORM).
4. Configure the Data In Pinout field in the Control A register (CTRLA.DIPO) for SERCOM pads of the
receiver.
5. Configure the Data Out Pinout bit group in the Control A register (CTRLA.DOPO) for SERCOM
pads of the transmitter.
6. Select the Character Size value in the CTRLB register (CTRLB.CHSIZE).
7. Write the Data Order bit in the CTRLA register (CTRLA.DORD) for data direction.
8. If the SPI is used in master mode:
8.1.
Select the desired baud rate by writing to the Baud register (BAUD).
8.2.
If Hardware SS control is required, write '1' to the Master Slave Select Enable bit in CTRLB
register (CTRLB.MSSEN).
9. Enable the receiver by writing the Receiver Enable bit in the CTRLB register (CTRLB.RXEN=1).
33.6.2.2. Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and
disabled by writing '0' to it.
Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of
this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled.
Refer to the CTRLA register description for details.
33.6.2.3. Clock Generation
In SPI master operation (CTRLA.MODE=0x3), the serial clock (SCK) is generated internally by the
SERCOM baud-rate generator.
In SPI mode, the baud-rate generator is set to synchronous mode. The 8-bit Baud register (BAUD) value
is used for generating SCK and clocking the shift register. Refer to Clock Generation – Baud-Rate
Generator for more details.
In SPI slave operation (CTRLA.MODE is 0x2), the clock is provided by an external master on the SCK
pin. This clock is used to directly clock the SPI shift register.
Related Links
Clock Generation – Baud-Rate Generator on page 514
Asynchronous Arithmetic Mode BAUD Value Selection on page 515
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33.6.2.4. Data Register
The SPI Transmit Data register (TxDATA) and SPI Receive Data register (RxDATA) share the same I/O
address, referred to as the SPI Data register (DATA). Writing DATA register will update the Transmit Data
register. Reading the DATA register will return the contents of the Receive Data register.
33.6.2.5. SPI Transfer Modes
There are four combinations of SCK phase and polarity to transfer serial data. The SPI data transfer
modes are shown in SPI Transfer Modes (Table) and SPI Transfer Modes (Figure).
SCK phase is configured by the Clock Phase bit in the CTRLA register (CTRLA.CPHA). SCK polarity is
programmed by the Clock Polarity bit in the CTRLA register (CTRLA.CPOL). Data bits are shifted out and
latched in on opposite edges of the SCK signal. This ensures sufficient time for the data signals to
stabilize.
Table 33-3. SPI Transfer Modes
Mode
CPOL
CPHA
Leading Edge
Trailing Edge
0
0
0
Rising, sample
Falling, setup
1
0
1
Rising, setup
Falling, sample
2
1
0
Falling, sample
Rising, setup
3
1
1
Falling, setup
Rising, sample
Note: Leading edge is the first clock edge in a clock cycle.
Trailing edge is the second clock edge in a clock cycle.
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Figure 33-3. SPI Transfer Modes
Mode 0
Mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
Mode 1
Mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
33.6.2.6. Transferring Data
Master
In master mode (CTRLA.MODE=0x3), when Master Slave Enable Select (CTRLB.MSSEN) is ‘1’,
hardware will control the SS line.
When Master Slave Select Enable (CTRLB.MSSEN) is '0', the SS line must be configured as an output.
SS can be assigned to any general purpose I/O pin. When the SPI is ready for a data transaction,
software must pull the SS line low.
When writing a character to the Data register (DATA), the character will be transferred to the shift register.
Once the content of TxDATA has been transferred to the shift register, the Data Register Empty flag in the
Interrupt Flag Status and Clear register (INTFLAG.DRE) will be set. And a new character can be written
to DATA.
Each time one character is shifted out from the master, another character will be shifted in from the slave
simultaneously. If the receiver is enabled (CTRLA.RXEN=1), the contents of the shift register will be
transferred to the two-level receive buffer. The transfer takes place in the same clock cycle as the last
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data bit is shifted in. And the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG.RXC) will be set. The received data can be retrieved by reading DATA.
When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete
Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. When the
transaction is finished, the master must pull the SS line high to notify the slave. If Master Slave Select
Enable (CTRLB.MSSEN) is set to '0', the software must pull the SS line high.
Slave
In slave mode (CTRLA.MODE=0x2), the SPI interface will remain inactive with the MISO line tri-stated as
long as the SS pin is pulled high. Software may update the contents of DATA at any time as long as the
Data Register Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set.
When SS is pulled low and SCK is running, the slave will sample and shift out data according to the
transaction mode set. When the content of TxDATA has been loaded into the shift register, INTFLAG.DRE
will be set, and new data can be written to DATA.
Similar to the master, the slave will receive one character for each character transmitted. A character will
be transferred into the two-level receive buffer within the same clock cycle its last data bit is received. The
received character can be retrieved from DATA when the Receive Complete interrupt flag
(INTFLAG.RXC) is set.
When the master pulls the SS line high, the transaction is done and the Transmit Complete Interrupt flag
in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set.
After DATA is written it takes up to three SCK clock cycles until the content of DATA is ready to be loaded
into the shift register on the next character boundary. As a consequence, the first character transferred in
a SPI transaction will not be the content of DATA. This can be avoided by using the preloading feature.
Refer to Preloading of the Slave Shift Register.
When transmitting several characters in one SPI transaction, the data has to be written into DATA register
with at least three SCK clock cycles left in the current character transmission. If this criteria is not met, the
previously received character will be transmitted.
Once the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.
33.6.2.7. Receiver Error Bit
The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status
register (STATUS). Once an error happens, the bit will stay set until it is cleared by writing '1' to it. The bit
is also automatically cleared when the receiver is disabled.
There are two methods for buffer overflow notification, selected by the immediate buffer overflow
notification bit in the Control A register (CTRLA.IBON):
If CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then
empty the receive FIFO by reading RxDATA until the receiver complete interrupt flag in the Interrupt Flag
Status and Clear register (INTFLAG.RXC) goes low.
If CTRLA.IBON=0, the buffer overflow condition travels with data through the receive FIFO. After the
received data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC,
and RxDATA will be zero.
33.6.3.
Additional Features
33.6.3.1. Address Recognition
When the SPI is configured for slave operation (CTRLA.MODE=0x2) with address recognition
(CTRLA.FORM is 0x2), the SERCOM address recognition logic is enabled: the first character in a
transaction is checked for an address match.
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If there is a match, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.RXC) is set, the MISO output is enabled, and the transaction is processed. If the device is in
sleep mode, an address match can wake up the device in order to process the transaction.
If there is no match, the complete transaction is ignored.
If a 9-bit frame format is selected, only the lower 8 bits of the shift register are checked against the
Address register (ADDR).
Preload must be disabled (CTRLB.PLOADEN=0) in order to use this mode.
Related Links
Address Match and Mask on page 516
33.6.3.2. Preloading of the Slave Shift Register
When starting a transaction, the slave will first transmit the contents of the shift register before loading
new data from DATA. The first character sent can be either the reset value of the shift register (if this is
the first transmission since the last reset) or the last character in the previous transmission.
Preloading can be used to preload data into the shift register while SS is high: this eliminates sending a
dummy character when starting a transaction. If the shift register is not preloaded, the current contents of
the shift register will be shifted out.
Only one data character will be preloaded into the shift register while the synchronized SS signal is high.
If the next character is written to DATA before SS is pulled low, the second character will be stored in
DATA until transfer begins.
For proper preloading, sufficient time must elapse between SS going low and the first SCK sampling
edge, as in Timing Using Preloading. See also Electrical Characteristics for timing details.
Preloading is enabled by writing '1' to the Slave Data Preload Enable bit in the CTRLB register
(CTRLB.PLOADEN).
Figure 33-4. Timing Using Preloading
Required _SS-to-SCK time
using PRELOADEN
_SS
_SS synchronized
to system domain
SCK
Synchronization
to system domain
MISO to SCK
setup time
33.6.3.3. Master with Several Slaves
Master with multiple slaves in parallel is only available when Master Slave Select Enable
(CTRLB.MSSEN) is set to zero and hardware SS control is disabled. If the bus consists of several SPI
slaves, an SPI master can use general purpose I/O pins to control the SS line to each of the slaves on the
bus, as shown in Multiple Slaves in Parallel. In this configuration, the single selected SPI slave will drive
the tri-state MISO line.
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Figure 33-5. Multiple Slaves in Parallel
shift register
MOSI
MOSI
MISO
SCK
MISO
SCK
_SS[0]
_SS
shift register
SPI Slave 0
SPI Master
_SS[n-1]
MOSI
MISO
SCK
_SS
shift register
SPI Slave n-1
Another configuration is multiple slaves in series, as in Multiple Slaves in Series. In this configuration, all
n attached slaves are connected in series. A common SS line is provided to all slaves, enabling them
simultaneously. The master must shift n characters for a complete transaction. Depending on the Master
Slave Select Enable bit (CTRLB.MSSEN), the SS line can be controlled either by hardware or user
software and normal GPIO.
Figure 33-6. Multiple Slaves in Series
shift register
SPI Master
MOSI
MISO
SCK
_SS
MOSI
MISO
SCK
_SS
shift register
MOSI
shift register
MISO
SCK
_SS
SPI Slave 0
SPI Slave n-1
33.6.3.4. Loop-Back Mode
For loop-back mode, configure the Data In Pinout (CTRLA.DIPO) and Data Out Pinout (CTRLA.DOPO) to
use the same data pins for transmit and receive. The loop-back is through the pad, so the signal is also
available externally.
33.6.3.5. Hardware Controlled SS
In master mode, a single SS chip select can be controlled by hardware by writing the Master Slave Select
Enable (CTRLB.MSSEN) bit to '1'. In this mode, the SS pin is driven low for a minimum of one baud cycle
before transmission begins, and stays low for a minimum of one baud cycle after transmission completes.
If back-to-back frames are transmitted, the SS pin will always be driven high for a minimum of one baud
cycle between frames.
In Hardware Controlled SS, the time T is between one and two baud cycles depending on the SPI
transfer mode.
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Figure 33-7. Hardware Controlled SS
T
T
T
T
T
_SS
SCK
T = 1 to 2 baud cycles
When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO.
33.6.3.6. Slave Select Low Detection
In slave mode, the SPI can wake the CPU when the slave select (SS) goes low. When the Slave Select
Low Detect is enabled (CTRLB.SSDE=1), a high-to-low transition will set the Slave Select Low interrupt
flag (INTFLAG.SSL) and the device will wake up if applicable.
33.6.4.
DMA, Interrupts, and Events
Table 33-4. Module Request for SERCOM SPI
Condition
Request
DMA
Interrupt
Event
Yes
(request cleared when
data is written)
Yes
NA
Receive Complete (RXC) Yes
(request cleared when
data is read)
Yes
Transmit Complete (TXC) NA
Yes
Slave Select low (SSL)
NA
Yes
Error (ERROR)
NA
Yes
Data Register Empty
(DRE)
33.6.4.1. DMA Operation
The SPI generates the following DMA requests:
•
•
Data received (RX): The request is set when data is available in the receive FIFO. The request is
cleared when DATA is read.
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is
cleared when DATA is written.
33.6.4.2. Interrupts
The SPI has the following interrupt sources. These are asynchronous interrupts, and can wake up the
device from any sleep mode:
•
•
•
•
•
Data Register Empty (DRE)
Receive Complete (RXC)
Transmit Complete (TXC)
Slave Select Low (SSL)
Error (ERROR)
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Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually
enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and
disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is
enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is
disabled, or the SPI is reset. For details on clearing interrupt flags, refer to the INTFLAG register
description.
The SPI has one common interrupt request line for all the interrupt sources. The value of INTFLAG
indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests.
Refer to Nested Vector Interrupt Controller for details.
Related Links
Nested Vector Interrupt Controller on page 43
33.6.4.3. Events
Not applicable.
33.6.5.
Sleep Mode Operation
The behavior in sleep mode is depending on the master/slave configuration and the Run In Standby bit in
the Control A register (CTRLA.RUNSTDBY):
•
•
•
•
33.6.6.
Master operation, CTRLA.RUNSTDBY=1: The peripheral clock GCLK_SERCOM_CORE will
continue to run in idle sleep mode and in standby sleep mode. Any interrupt can wake up the
device.
Master operation, CTRLA.RUNSTDBY=0: GLK_SERCOMx_CORE will be disabled after the
ongoing transaction is finished. Any interrupt can wake up the device.
Slave operation, CTRLA.RUNSTDBY=1: The Receive Complete interrupt can wake up the device.
Slave operation, CTRLA.RUNSTDBY=0: All reception will be dropped, including the ongoing
transaction.
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
•
•
•
Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
Note: CTRLB.RXEN is write-synchronized somewhat differently. See also CTRLB for details.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
Related Links
Register Synchronization on page 123
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33.7.
Offset
Register Summary
Name
0x00
0x01
0x02
Bit Pos.
7:0
CTRLA
RUNSTDBY
MODE[2:0]
15:8
DIPO[1:0]
31:24
DORD
0x04
7:0
PLOADEN
0x05
15:8
0x06
0x07
SWRST
IBON
23:16
0x03
CTRLB
ENABLE
AMODE[1:0]
CPOL
DOPO[1:0]
CPHA
FORM[3:0]
CHSIZE[2:0]
MSSEN
SSDE
23:16
RXEN
31:24
0x08
...
Reserved
0x0B
0x0C
BAUD
7:0
BAUD[7:0]
0x0D
...
Reserved
0x13
0x14
INTENCLR
0x15
Reserved
0x16
INTENSET
0x17
Reserved
0x18
INTFLAG
0x19
Reserved
0x1A
0x1B
STATUS
7:0
ERROR
SSL
RXC
TXC
DRE
7:0
ERROR
SSL
RXC
TXC
DRE
7:0
ERROR
SSL
RXC
TXC
DRE
ENABLE
SWRST
7:0
0x1C
7:0
0x1D
15:8
0x1E
SYNCBUSY
0x1F
BUFOVF
15:8
CTRLB
23:16
31:24
0x20
...
Reserved
0x23
0x24
7:0
0x25
15:8
0x26
ADDR
0x27
0x28
0x29
23:16
ADDR[7:0]
ADDRMASK[7:0]
31:24
DATA
7:0
DATA[7:0]
15:8
DATA[8:8]
7:0
DBGSTOP
0x2A
...
Reserved
0x2F
0x30
DBGCTRL
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33.8.
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Refer to Synchronization
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
Refer to Register Access Protection.
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33.8.1.
Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
Access
Reset
Bit
23
30
29
28
DORD
CPOL
CPHA
27
R/W
R/W
R/W
R/W
0
0
0
0
22
21
20
19
26
25
24
R/W
R/W
R/W
0
0
0
18
17
FORM[3:0]
DIPO[1:0]
Access
Reset
Bit
15
14
16
DOPO[1:0]
R/W
R/W
R/W
R/W
0
0
0
0
13
12
9
8
11
10
IBON
Access
R/W
Reset
0
Bit
7
6
5
4
3
RUNSTDBY
Access
Reset
2
MODE[2:0]
1
0
ENABLE
SWRST
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit 30 – DORD: Data Order
This bit selects the data order when a character is shifted out from the shift register.
This bit is not synchronized.
Value
Description
0
MSB is transferred first.
1
LSB is transferred first.
Bit 29 – CPOL: Clock Polarity
In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode.
This bit is not synchronized.
Value
Description
0
SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing
edge is a falling edge.
1
SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing
edge is a rising edge.
Bit 28 – CPHA: Clock Phase
In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode.
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This bit is not synchronized.
Mode
CPOL
CPHA
Leading Edge
Trailing Edge
0x0
0
0
Rising, sample
Falling, change
0x1
0
1
Rising, change
Falling, sample
0x2
1
0
Falling, sample
Rising, change
0x3
1
1
Falling, change
Rising, sample
Value
Description
0
The data is sampled on a leading SCK edge and changed on a trailing SCK edge.
1
The data is sampled on a trailing SCK edge and changed on a leading SCK edge.
Bits 27:24 – FORM[3:0]: Frame Format
This bit field selects the various frame formats supported by the SPI in slave mode. When the 'SPI frame
with address' format is selected, the first byte received is checked against the ADDR register.
FORM[3:0]
Name
Description
0x0
SPI
SPI frame
0x1
-
Reserved
0x2
SPI_ADDR
SPI frame with address
0x3-0xF
-
Reserved
Bits 21:20 – DIPO[1:0]: Data In Pinout
These bits define the data in (DI) pad configurations.
In master operation, DI is MISO.
In slave operation, DI is MOSI.
These bits are not synchronized.
DIPO[1:0]
Name
Description
0x0
PAD[0]
SERCOM PAD[0] is used as data input
0x1
PAD[1]
SERCOM PAD[1] is used as data input
0x2
PAD[2]
SERCOM PAD[2] is used as data input
0x3
PAD[3]
SERCOM PAD[3] is used as data input
Bits 17:16 – DOPO[1:0]: Data Out Pinout
This bit defines the available pad configurations for data out (DO) and the serial clock (SCK). In slave
operation, the slave select line (SS) is controlled by DOPO, while in master operation the SS line is
controlled by the port configuration.
In master operation, DO is MOSI.
In slave operation, DO is MISO.
These bits are not synchronized.
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DOPO
DO
SCK
Slave SS
Master SS
0x0
PAD[0]
PAD[1]
PAD[2]
System configuration
0x2
PAD[3]
PAD[1]
PAD[2]
System configuration
Bit 8 – IBON: Immediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow
occurs.
This bit is not synchronized.
Value
Description
0
STATUS.BUFOVF is set when it occurs in the data stream.
1
STATUS.BUFOVF is set immediately upon buffer overflow.
Bit 7 – RUNSTDBY: Run In Standby
This bit defines the functionality in standby sleep mode.
These bits are not synchronized.
RUNSTDBY Slave
Master
0x0
Disabled. All reception is dropped,
including the ongoing transaction.
Generic clock is disabled when ongoing
transaction is finished. All interrupts can wake
up the device.
0x1
Ongoing transaction continues, wake on
Receive Complete interrupt.
Generic clock is enabled while in sleep modes.
All interrupts can wake up the device.
Bits 4:2 – MODE[2:0]: Operating Mode
These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the
SERCOM.
0x2: SPI slave operation
0x3: SPI master operation
These bits are not synchronized.
Bit 1 – ENABLE: Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable
Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is
cleared when the operation is complete.
This bit is not enable-protected.
Value
Description
0
The peripheral is disabled or being disabled.
1
The peripheral is enabled or being enabled.
Bit 0 – SWRST: Software Reset
Writing '0' to this bit has no effect.
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Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the
SERCOM will be disabled.
Writing ''1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same writeoperation will be discarded. Any register write access during the ongoing reset will result in an APB error.
Reading any register will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST and SYNCBUSY. SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
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33.8.2.
Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
23
22
21
20
19
18
25
24
17
16
Access
Reset
Bit
RXEN
Access
R/W
Reset
0
Bit
15
14
AMODE[1:0]
13
12
11
10
9
MSSEN
SSDE
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
7
6
5
Access
4
3
2
PLOADEN
Access
Reset
1
8
0
CHSIZE[2:0]
R/W
R/W
R/W
R/W
0
0
0
0
Bit 17 – RXEN: Receiver Enable
Writing '0' to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from
ongoing receptions will be lost and STATUS.BUFOVF will be cleared.
Writing '1' to CTRLB.RXEN when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is
enabled, CTRLB.RXEN will be cleared, SYNCBUSY.CTRLB will be set and remain set until the receiver is
enabled. When the receiver is enabled CTRLB.RXEN will read back as '1'.
Writing '1' to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set
until the receiver is enabled, and CTRLB.RXEN will read back as '1'.
This bit is not enable-protected.
Value
Description
0
The receiver is disabled or being enabled.
1
The receiver is enabled or it will be enabled when SPI is enabled.
Bits 15:14 – AMODE[1:0]: Address Mode
These bits set the slave addressing mode when the frame format (CTRLA.FORM) with address is used.
They are unused in master mode.
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AMODE[1:0] Name
Description
0x0
MASK
ADDRMASK is used as a mask to the ADDR register
0x1
2_ADDRS The slave responds to the two unique addresses in ADDR and ADDRMASK
0x2
RANGE
The slave responds to the range of addresses between and including ADDR
and ADDRMASK. ADDR is the upper limit
0x3
-
Reserved
Bit 13 – MSSEN: Master Slave Select Enable
This bit enables hardware slave select (SS) control.
Value
Description
0
Hardware SS control is disabled.
1
Hardware SS control is enabled.
Bit 9 – SSDE: Slave Select Low Detect Enable
This bit enables wake up when the slave select (SS) pin transitions from high to low.
Value
Description
0
SS low detector is disabled.
1
SS low detector is enabled.
Bit 6 – PLOADEN: Slave Data Preload Enable
Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. If the
SS line is high when DATA is written, it will be transferred immediately to the shift register.
Bits 2:0 – CHSIZE[2:0]: Character Size
CHSIZE[2:0]
Name
Description
0x0
8BIT
8 bits
0x1
9BIT
9 bits
0x2-0x7
-
Reserved
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33.8.3.
Baud Rate
Name: BAUD
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit
7
6
5
4
3
2
1
0
BAUD[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7:0 – BAUD[7:0]: Baud Register
These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate
Generator.
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33.8.4.
Interrupt Enable Clear
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
Bit
7
Access
Reset
3
2
1
0
ERROR
6
5
4
SSL
RXC
TXC
DRE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit 7 – ERROR: Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 3 – SSL: Slave Select Low Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Slave Select Low Interrupt Enable bit, which disables the Slave Select
Low interrupt.
Value
Description
0
Slave Select Low interrupt is disabled.
1
Slave Select Low interrupt is enabled.
Bit 2 – RXC: Receive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive
Complete interrupt.
Value
Description
0
Receive Complete interrupt is disabled.
1
Receive Complete interrupt is enabled.
Bit 1 – TXC: Transmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Transmit Complete Interrupt Enable bit, which disable the Transmit
Complete interrupt.
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Value
Description
0
Transmit Complete interrupt is disabled.
1
Transmit Complete interrupt is enabled.
Bit 0 – DRE: Data Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data
Register Empty interrupt.
Value
Description
0
Data Register Empty interrupt is disabled.
1
Data Register Empty interrupt is enabled.
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33.8.5.
Interrupt Enable Set
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
Bit
7
Access
Reset
3
2
1
0
ERROR
6
5
4
SSL
RXC
TXC
DRE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit 7 – ERROR: Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 3 – SSL: Slave Select Low Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Slave Select Low Interrupt Enable bit, which enables the Slave Select Low
interrupt.
Value
Description
0
Slave Select Low interrupt is disabled.
1
Slave Select Low interrupt is enabled.
Bit 2 – RXC: Receive Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive
Complete interrupt.
Value
Description
0
Receive Complete interrupt is disabled.
1
Receive Complete interrupt is enabled.
Bit 1 – TXC: Transmit Complete Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit
Complete interrupt.
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Value
Description
0
Transmit Complete interrupt is disabled.
1
Transmit Complete interrupt is enabled.
Bit 0 – DRE: Data Register Empty Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register
Empty interrupt.
Value
Description
0
Data Register Empty interrupt is disabled.
1
Data Register Empty interrupt is enabled.
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33.8.6.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: Bit
Access
Reset
3
2
1
0
ERROR
7
6
5
4
SSL
RXC
TXC
DRE
R/W
R/W
R
R/W
R
0
0
0
0
0
Bit 7 – ERROR: Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in
the STATUS register. The BUFOVF error will set this interrupt flag.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 3 – SSL: Slave Select Low
This flag is cleared by writing '1' to it.
This bit is set when a high to low transition is detected on the _SS pin in slave mode and Slave Select
Low Detect (CTRLB.SSDE) is enabled.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 2 – RXC: Receive Complete
This flag is cleared by reading the Data (DATA) register or by disabling the receiver.
This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first
data received in a transaction will be an address.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 1 – TXC: Transmit Complete
This flag is cleared by writing '1' to it or by writing new data to DATA.
In master mode, this flag is set when the data have been shifted out and there are no new data in DATA.
In slave mode, this flag is set when the _SS pin is pulled high. If address matching is enabled, this flag is
only set if the transaction was initiated with an address match.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 0 – DRE: Data Register Empty
This flag is cleared by writing new data to DATA.
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This flag is set when DATA is empty and ready for new data to transmit.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
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33.8.7.
Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: –
Bit
15
14
13
12
11
7
6
5
4
3
10
9
8
2
1
0
Access
Reset
Bit
BUFOVF
Access
R/W
Reset
0
Bit 2 – BUFOVF: Buffer Overflow
Reading this bit before reading DATA will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. See also CTRLA.IBON for overflow handling.
When set, the corresponding RxDATA will be zero.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Value
Description
0
No Buffer Overflow has occurred.
1
A Buffer Overflow has occurred.
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33.8.8.
Synchronization Busy
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property: Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
CTRLB
ENABLE
SWRST
Access
R
R
R
Reset
0
0
0
Bit 2 – CTRLB: CTRLB Synchronization Busy
Writing to the CTRLB when the SERCOM is enabled requires synchronization. Ongoing synchronization
is indicated by SYNCBUSY.CTRLB=1 until synchronization is complete. If CTRLB is written while
SYNCBUSY.CTRLB=1, an APB error will be generated.
Value
Description
0
CTRLB synchronization is not busy.
1
CTRLB synchronization is busy.
Bit 1 – ENABLE: SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. Ongoing
synchronization is indicated by SYNCBUSY.ENABLE=1 until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be
discarded and an APB error will be generated.
Value
Description
0
Enable synchronization is not busy.
1
Enable synchronization is busy.
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Bit 0 – SWRST: Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. Ongoing synchronization is indicated
by SYNCBUSY.SWRST=1 until synchronization is complete.
Writes to any register while synchronization is on-going will be discarded and an APB error will be
generated.
Value
Description
0
SWRST synchronization is not busy.
1
SWRST synchronization is busy.
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33.8.9.
Address
Name: ADDR
Offset: 0x24
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
Reset
Bit
ADDRMASK[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
Bit
ADDR[7:0]
Access
Reset
Bits 23:16 – ADDRMASK[7:0]: Address Mask
These bits hold the address mask when the transaction format with address is used (CTRLA.FORM,
CTRLB.AMODE).
Bits 7:0 – ADDR[7:0]: Address
These bits hold the address when the transaction format with address is used (CTRLA.FORM,
CTRLB.AMODE).
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33.8.10. Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: –
Bit
15
14
13
12
11
10
9
8
DATA[8:8]
Access
R/W
Reset
Bit
0
7
6
5
4
3
2
1
0
DATA[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 8:0 – DATA[8:0]: Data
Reading these bits will return the contents of the receive data buffer. The register should be read only
when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register
(INTFLAG.RXC) is set.
Writing these bits will write the transmit data buffer. This register should be written only when the Data
Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set.
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33.8.11. Debug Control
Name: DBGCTRL
Offset: 0x30
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGSTOP
Access
R/W
Reset
0
Bit 0 – DBGSTOP: Debug Stop Mode
This bit controls the functionality when the CPU is halted by an external debugger.
Value
Description
0
The baud-rate generator continues normal operation when the CPU is halted by an external
debugger.
1
The baud-rate generator is halted when the CPU is halted by an external debugger.
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34.
SERCOM I2C – SERCOM Inter-Integrated Circuit
34.1.
Overview
The inter-integrated circuit ( I2C) interface is one of the available modes in the serial communication
interface (SERCOM).
The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 34-1 I2C
Single-Master Single-Slave Interconnection. Labels in capital letters are registers accessible by the CPU,
while lowercase labels are internal to the SERCOM. Each master and slave have a separate I2C interface
containing a shift register, a transmit buffer and a receive buffer. In addition, the I2C master uses the
SERCOM baud-rate generator, while the I2C slave uses the SERCOM address match logic.
Related Links
SERCOM – Serial Communication Interface on page 510
34.2.
Features
SERCOM I2C includes the following features:
•
•
•
•
•
•
•
•
Master or slave operation
Can be used with DMA
Philips I2C compatible
SMBus™ compatible
PMBus compatible
Support of 100kHz and 400kHz, 1MHz and 3.4MHz I2C mode low system clock frequencies
Physical interface includes:
– Slew-rate limited outputs
– Filtered inputs
Slave operation:
– Operation in all sleep modes
– Wake-up on address match
– 7-bit and 10-bit Address match in hardware for:
–
• Unique address and/or 7-bit general call address
• Address range
• Two unique addresses can be used with DMA
Related Links
Features on page 510
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34.3.
Block Diagram
Figure 34-1. I2C Single-Master Single-Slave Interconnection
Master
BAUD
TxDATA
0
baud rate generator
Slave
TxDATA
SCL
SCL hold low
0
SCL hold low
shift register
shift register
0
SDA
0
RxDATA
34.4.
ADDR/ADDRMASK
RxDATA
==
Signal Description
Signal Name
Type
Description
PAD[0]
Digital I/O
SDA
PAD[1]
Digital I/O
SCL
PAD[2]
Digital I/O
SDA_OUT (4-wire)
PAD[3]
Digital I/O
SDC_OUT (4-wire)
One signal can be mapped on several pins.
Not all the pins are I2C pins.
Related Links
I/O Multiplexing and Considerations on page 28
34.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
34.5.1.
I/O Lines
In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller
(PORT).
When the SERCOM is used in I2C mode, the SERCOM controls the direction and value of the I/O pins.
Both PORT control bits PINCFGn.PULLEN and PINCFGn.DRVSTR are still effective. If the receiver or
transmitter is disabled, these pins can be used for other purposes.
Related Links
PORT: IO Pin Controller on page 455
34.5.2.
Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The
interrupts can wake up the device from sleep modes.
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Related Links
PM – Power Manager on page 177
34.5.3.
Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled
in the Main Clock Controller and the Power Manager.
Two generic clocks ared used by SERCOM, GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW.
The core clock (GCLK_SERCOMx_CORE) can clock the I2C when working as a master. The slow clock
(GCLK_SERCOM_SLOW) is required only for certain functions, e.g. SMBus timing. These clocks must
be configured and enabled in the Generic Clock Controller (GCLK) before using the I2C.
These generic clocks are asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this
asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to
Synchronization for further details.
Related Links
GCLK - Generic Clock Controller on page 127
Peripheral Clock Masking on page 152
PM – Power Manager on page 177
34.5.4.
DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
DMAC – Direct Memory Access Controller on page 346
34.5.5.
Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
Nested Vector Interrupt Controller on page 43
34.5.6.
Events
Not applicable.
34.5.7.
Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging refer to the Debug Control (DBGCTRL) register for details.
Refer to the DBGCTRL register for details.
34.5.8.
Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
PAC Write-Protection is not available for the following registers:
•
Interrupt Flag Clear and Status register (INTFLAG)
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•
•
•
Status register (STATUS)
Data register (DATA)
Address register (ADDR)
Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual
register description.
Write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller on page 48
34.5.9.
Analog Connections
Not applicable.
34.6.
Functional Description
34.6.1.
Principle of Operation
The I2C interface uses two physical lines for communication:
•
Serial Data Line (SDA) for packet transfer
•
Serial Clock Line (SCL) for the bus clock
A transaction starts with the I2C master sending the start condition, followed by a 7-bit address and a
direction bit (read or write to/from the slave).
The addressed I2C slave will then acknowledge (ACK) the address, and data packet transactions can
begin. Every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the
data was acknowledged or not.
If a data packet is not acknowledged (NACK), whether by the I2C slave or master, the I2C master takes
action by either terminating the transaction by sending the stop condition, or by sending a repeated start
to transfer more data.
The figure below illustrates the possible transaction formats and Transaction Diagram Symbols explains
the transaction symbols. These symbols will be used in the following descriptions.
Figure 34-2. Basic I2C Transaction Diagram
SDA
SCL
6..0
S
ADDRESS
S
ADDRESS
7..0
R/W
R/W
ACK
DATA
A
DATA
7..0
ACK
A
DATA
ACK/NACK
DATA
A/A
P
P
Direction
Address Packet
Data Packet #0
Data Packet #1
Transaction
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Transaction Diagram Symbols
Bus Driver
Master driving bus
S
START condition
Slave driving bus
Sr
repeated START condition
Either Master or Slave driving bus
P
STOP condition
Data Package Direction
R
Master Read
Master Write
A
Acknowledge (ACK)
A
Not Acknowledge (NACK)
'1'
'0'
34.6.2.
Acknowledge
'0'
'1'
W
Special Bus Conditions
Basic Operation
34.6.2.1. Initialization
The following registers are enable-protected, meaning they can be written only when the I2C interface is
disabled (CTRLA.ENABLE is ‘0’):
•
Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset
(CTRLA.SWRST) bits
•
Control B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command
(CTRLB.CMD) bits
•
Baud register (BAUD)
•
Address register (ADDR) in slave operation.
When the I2C is enabled or is being enabled (CTRLA.ENABLE=1), writing to these registers will be
discarded. If the I2C is being disabled, writing to these registers will be completed after the disabling.
Enable-protection is denoted by the "Enable-Protection" property in the register description.
Before the I2C is enabled it must be configured as outlined by the following steps:
1. Select I2C Master or Slave mode by writing 0x4 or 0x5 to the Operating Mode bits in the CTRLA
register (CTRLA.MODE).
2. If desired, select the SDA Hold Time value in the CTRLA register (CTRLA.SDAHOLD).
3. If desired, enable smart operation by setting the Smart Mode Enable bit in the CTRLB register
(CTRLB.SMEN).
4. If desired, enable SCL low time-out by setting the SCL Low Time-Out bit in the Control A register
(CTRLA.LOWTOUT).
5. In Master mode:
5.1.
Select the inactive bus time-out in the Inactive Time-Out bit group in the CTRLA register
(CTRLA.INACTOUT).
5.2.
Write the Baud Rate register (BAUD) to generate the desired baud rate.
In Slave mode:
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5.1.
5.2.
Configure the address match configuration by writing the Address Mode value in the
CTRLB register (CTRLB.AMODE).
Set the Address and Address Mask value in the Address register (ADDR.ADDR and
ADDR.ADDRMASK) according to the address configuration.
34.6.2.2. Enabling, Disabling, and Resetting
This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and
disabled by writing '0' to it.
Refer to CTRLA for details.
34.6.2.3. I2C Bus State Logic
The bus state logic includes several logic blocks that continuously monitor the activity on the I2C bus lines
in all sleep modes. The start and stop detectors and the bit counter are all essential in the process of
determining the current bus state. The bus state is determined according to Bus State Diagram. Software
can get the current bus state by reading the Master Bus State bits in the Status register
(STATUS.BUSSTATE). The value of STATUS.BUSSTATE in the figure is shown in binary.
Figure 34-3. Bus State Diagram
RESET
UNKNOWN
(0b00)
Timeout or Stop Condition
Start Condition
IDLE
(0b01)
Timeout or Stop Condition
BUSY
(0b11)
Write ADDR to generate
Start Condition
OWNER
(0b10)
Lost Arbitration
Repeated
Start Condition
Stop Condition
Write ADDR to generate
Repeated Start Condition
The bus state machine is active when the I2C master is enabled.
After the I2C master has been enabled, the bus state is UNKNOWN (0b00). From the UNKNOWN state,
the bus will transition to IDLE (0b01) by either:
•
Forcing by by writing 0b01 to STATUS.BUSSTATE
•
A stop condition is detected on the bus
•
If the inactive bus time-out is configured for SMBus compatibility (CTRLA.INACTOUT) and a timeout occurs.
Note: Once a known bus state is established, the bus state logic will not re-enter the UNKNOWN state.
When the bus is IDLE it is ready for a new transaction. If a start condition is issued on the bus by another
I2C master in a multi-master setup, the bus becomes BUSY (0b11). The bus will re-enter IDLE either
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when a stop condition is detected, or when a time-out occurs (inactive bus time-out needs to be
configured).
If a start condition is generated internally by writing the Address bit group in the Address register
(ADDR.ADDR) while IDLE, the OWNER state (0b10) is entered. If the complete transaction was
performed without interference, i.e., arbitration was not lost, the I2C master can issue a stop condition,
which will change the bus state back to IDLE.
However, if a packet collision is detected while in OWNER state, the arbitration is assumed lost and the
bus state becomes BUSY until a stop condition is detected. A repeated start condition will change the bus
state only if arbitration is lost while issuing a repeated start.
Regardless of winning or losing arbitration, the entire address will be sent. If arbitration is lost, only 'ones'
are transmitted from the point of losing arbitration and the rest of the address length.
Note: Violating the protocol may cause the I2C to hang. If this happens it is possible to recover from this
state by a software reset (CTRLA.SWRST='1').
Related Links
CTRLA on page 635
34.6.2.4. I2C Master Operation
The I2C master is byte-oriented and interrupt based. The number of interrupts generated is kept at a
minimum by automatic handling of most events. The software driver complexity and code size are
reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart
Mode Enable bit in the Control A register (CTRLA.SMEN).
The I2C master has two interrupt strategies.
When SCL Stretch Mode (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit . In
this mode the I2C master operates according to Master Behavioral Diagram (SCLSM=0). The circles
labelled "Mn" (M1, M2..) indicate the nodes the bus logic can jump to, based on software or hardware
interaction.
This diagram is used as reference for the description of the I2C master operation throughout the
document.
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Figure 34-4. I2C Master Behavioral Diagram (SCLSM=0)
APPLICATION
MB INTERRUPT + SCL HOLD
M1
M2
BUSY
P
M3
IDLE
S
M4
ADDRESS
Wait for
IDLE
SW
R/W BUSY
SW
R/W A
SW
P
SW
Sr
W
A
M1
BUSY
M2
IDLE
M3
BUSY
DATA
SW
A/A
SB INTERRUPT + SCL HOLD
SW
Software interaction
SW
The master provides data on the bus
A
A/A
Addressed slave provides data on the bus
BUSY
P
A/A Sr
IDLE
M4
M2
M3
A/A
R
A
DATA
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit, as in Master
Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA
before acknowledging.
Note: I2C High-speed (Hs) mode requires CTRLA.SCLSM=1.
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M4
Figure 34-5. I2C Master Behavioral Diagram (SCLSM=1)
APPLICATION
MB INTERRUPT + SCL HOLD
M1
M2
BUSY
P
M3
IDLE
S
M4
ADDRESS
Wait for
IDLE
SW
R/W BUSY
SW
R/W A
SW
P
SW
Sr
W
A
M1
BUSY
M2
IDLE
M3
BUSY
DATA
SW
A/A
SB INTERRUPT + SCL HOLD
SW
Software interaction
SW
BUSY
The master provides data on the bus
P
IDLE
M4
M2
Addressed slave provides data on the bus
Sr
R
A
M3
DATA
A/A
Master Clock Generation
The SERCOM peripheral supports several I2C bi-directional modes:
•
Standard mode (Sm) up to 100kHz
•
Fast mode (Fm) up to 400kHz
•
Fast mode Plus (Fm+) up to 1MHz
•
High-speed mode (Hs) up to 3.4MHz
The Master clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode,
Fast-Mode, and Fast-Mode Plus). For Hs, refer to Master Clock Generation (High-Speed Mode).
Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
In I2C Sm, Fm, and Fm+ mode, the Master clock (SCL) frequency is determined as described in this
section:
The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise
(TRISE) and fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the
bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH
until a high state has been detected.
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M4
Figure 34-6. SCL Timing
TLOW
P
S
Sr
TLOW
SCL
THIGH
TFALL
TBUF
SDA
TSU;STO
THD;STA
TSU;STA
The following parameters are timed using the SCL low time period TLOW. This comes from the Master
Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or
the Master Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it.
•
TLOW – Low period of SCL clock
•
TSU;STO – Set-up time for stop condition
•
•
•
•
•
•
TBUF – Bus free time between stop and start conditions
THD;STA – Hold time (repeated) start condition
TSU;STA – Set-up time for repeated start condition
THIGH is timed using the SCL high time count from BAUD.BAUD
TRISE is determined by the bus impedance; for internal pull-ups. Refer to Electrical Characteristics.
TFALL is determined by the open-drain current limit and bus impedance; can typically be regarded
as zero. Refer to Electrical Characteristics for details.
The SCL frequency is given by:
�SCL =
1
�LOW + �HIGH + �RISE
�SCL =
�GCLK
10 + 2���� +�GCLK ⋅ �RISE
�SCL =
�GCLK
10 + ���� + ������� +�GCLK ⋅ �RISE
When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In
this case the following formula will give the SCL frequency:
When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency:
The following formulas can determine the SCL TLOW and THIGH times:
�LOW =
�HIGH =
������� + 5
�GCLK
���� + 5
�GCLK
Note: The I2C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and
BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be nonzero.
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Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when
the DATA register is written in smart mode. If a greater startup time is required due to long rise times, the
time between DATA write and IF clear must be controlled by software.
Note: When timing is controlled by user, the Smart Mode cannot be enabled.
Related Links
Electrical Characteristics 85°C on page 900
Master Clock Generation (High-Speed Mode)
For I2C Hs transfers, there is no SCL synchronization. Instead, the SCL frequency is determined by the
GCLK_SERCOMx_CORE frequency (fGCLK) and the High-Speed Baud setting in the Baud register
(BAUD.HSBAUD). When BAUD.HSBAUDLOW=0, the HSBAUD value will determine both SCL high and
SCL low. In this case the following formula determines the SCL frequency.
�SCL =
�GCLK
2 + 2 ⋅ �� ����
�SCL =
�GCLK
2 + �� ���� + ���������
When HSBAUDLOW is non-zero, the following formula determines the SCL frequency.
Note: The I2C standard Hs (High-speed) requires a nominal high to low SCL ratio of 1:2, and HSBAUD
should be set accordingly. At a minimum, BAUD.HSBAUD and/or BAUD.HSBAUDLOW must be nonzero.
Transmitting Address Packets
The I2C master starts a bus transaction by writing the I2C slave address to ADDR.ADDR and the direction
bit, as described in Principle of Operation. If the bus is busy, the I2C master will wait until the bus
becomes idle before continuing the operation. When the bus is idle, the I2C master will issue a start
condition on the bus. The I2C master will then transmit an address packet using the address written to
ADDR.ADDR. After the address packet has been transmitted by the I2C master, one of four cases will
arise according to arbitration and transfer direction.
Case 1: Arbitration lost or bus error during address packet transmission
If arbitration was lost during transmission of the address packet, the Master on Bus bit in the Interrupt
Flag Status and Clear register (INTFLAG.MB) and the Arbitration Lost bit in the Status register
(STATUS.ARBLOST) are both set. Serial data output to SDA is disabled, and the SCL is released, which
disables clock stretching. In effect the I2C master is no longer allowed to execute any operation on the
bus until the bus is idle again. A bus error will behave similarly to the arbitration lost condition. In this
case, the MB interrupt flag and Master Bus Error bit in the Status register (STATUS.BUSERR) are both
set in addition to STATUS.ARBLOST.
The Master Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain
the last successfully received acknowledge or not acknowledge indication.
In this case, software will typically inform the application code of the condition and then clear the interrupt
flag before exiting the interrupt routine. No other flags have to be cleared at this moment, because all
flags will be cleared automatically the next time the ADDR.ADDR register is written.
Case 2: Address packet transmit complete – No ACK received
If there is no I2C slave device responding to the address packet, then the INTFLAG.MB interrupt flag and
STATUS.RXNACK will be set. The clock hold is active at this point, preventing further activity on the bus.
The missing ACK response can indicate that the I2C slave is busy with other tasks or sleeping. Therefore,
it is not able to respond. In this event, the next step can be either issuing a stop condition (recommended)
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or resending the address packet by a repeated start condition. When using SMBus logic, the slave must
ACK the address. If there is no response, it means that the slave is not available on the bus.
Case 3: Address packet transmit complete – Write packet, Master on Bus set
If the I2C master receives an acknowledge response from the I2C slave, INTFLAG.MB will be set and
STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the
bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can
enable the I2C operation to continue:
•
•
•
Initiate a data transmit operation by writing the data byte to be transmitted into DATA.DATA.
Transmit a new address packet by writing ADDR.ADDR. A repeated start condition will
automatically be inserted before the address packet.
Issue a stop condition, consequently terminating the transaction.
Case 4: Address packet transmit complete – Read packet, Slave on Bus set
If the I2C master receives an ACK from the I2C slave, the I2C master proceeds to receive the next byte of
data from the I2C slave. When the first data byte is received, the Slave on Bus bit in the Interrupt Flag
register (INTFLAG.SB) will be set and STATUS.RXNACK will be cleared. The clock hold is active at this
point, preventing further activity on the bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can
enable the I2C operation to continue:
•
Let the I2C master continue to read data by acknowledging the data received. ACK can be sent by
software, or automatically in smart mode.
•
Transmit a new address packet.
•
Terminate the transaction by issuing a stop condition.
Note: An ACK or NACK will be automatically transmitted if smart mode is enabled. The Acknowledge
Action bit in the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent.
Transmitting Data Packets
When an address packet with direction Master Write (see Figure 34-2 Basic I2C Transaction Diagram)
was transmitted successfully , INTFLAG.MB will be set. The I2C master will start transmitting data via the
I2C bus by writing to DATA.DATA, and monitor continuously for packet collisions. I
If a collision is detected, the I2C master will lose arbitration and STATUS.ARBLOST will be set. If the
transmit was successful, the I2C master will receive an ACK bit from the I2C slave, and STATUS.RXNACK
will be cleared. INTFLAG.MB will be set in both cases, regardless of arbitration outcome.
It is recommended to read STATUS.ARBLOST and handle the arbitration lost condition in the beginning
of the I2C Master on Bus interrupt. This can be done as there is no difference between handling address
and data packet arbitration.
STATUS.RXNACK must be checked for each data packet transmitted before the next data packet
transmission can commence. The I2C master is not allowed to continue transmitting data packets if a
NACK is received from the I2C slave.
Receiving Data Packets (SCLSM=0)
When INTFLAG.SB is set, the I2C master will already have received one data packet. The I2C master
must respond by sending either an ACK or NACK. Sending a NACK may be unsuccessful when
arbitration is lost during the transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB.
Instead, INTFLAG.MB will indicate a change in arbitration. Handling of lost arbitration is the same as for
data bit transmission.
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Receiving Data Packets (SCLSM=1)
When INTFLAG.SB is set, the I2C master will already have received one data packet and transmitted an
ACK or NACK, depending on CTRLB.ACKACT. At this point, CTRLB.ACKACT must be set to the correct
value for the next ACK bit, and the transaction can continue by reading DATA and issuing a command if
not in the smart mode.
High-Speed Mode
High-speed transfers are a multi-step process, see High Speed Transfer.
First, a master code (0b00001nnn, where 'nnn' is a unique master code) is transmitted in Full-speed
mode, followed by a NACK since no slaveshould acknowledge. Arbitration is performed only during the
Full-speed Master Code phase. The master code is transmitted by writing the master code to the address
register (ADDR.ADDR) and writing the high-speed bit (ADDR.HS) to '0'.
After the master code and NACK have been transmitted, the master write interrupt will be asserted. In the
meanwhile, the slave address can be written to the ADDR.ADDR register together with ADDR.HS=1. Now
in High-speed mode, the master will generate a repeated start, followed by the slave address with RWdirection. The bus will remain in High-speed mode until a stop is generated. If a repeated start is desired,
the ADDR.HS bit must again be written to '1', along with the new address ADDR.ADDR to be transmitted.
Figure 34-7. High Speed Transfer
F/S-mode
S
Master Code
Hs-mode
A
R/W A
ADDRESS
Sr
F/S-mode
DATA
A/A
P
Hs-mode continues
N Data Packets
Sr
ADDRESS
Transmitting in High-speed mode requires the I2C master to be configured in High-speed mode
(CTRLA.SPEED=0x2) and the SCL clock stretch mode (CTRLA.SCLSM) bit set to '1'.
10-Bit Addressing
When 10-bit addressing is enabled by the Ten Bit Addressing Enable bit in the Address register
(ADDR.TENBITEN=1) and the Address bit field ADDR.ADDR is written, the two address bytes will be
transmitted, see 10-bit Address Transmission for a Read Transaction. The addressed slave
acknowledges the two address bytes, and the transaction continues. Regardless of whether the
transaction is a read or write, the master must start by sending the 10-bit address with the direction bit
(ADDR.ADDR[0]) being zero.
If the master receives a NACK after the first byte, the write interrupt flag will be raised and the
STATUS.RXNACK bit will be set. If the first byte is acknowledged by one or more slaves, then the master
will proceed to transmit the second address byte and the master will first see the write interrupt flag after
the second byte is transmitted. If the transaction direction is read-from-slave, the 10-bit address
transmission must be followed by a repeated start and the first 7 bits of the address with the read/write bit
equal to '1'.
Figure 34-8. 10-bit Address Transmission for a Read Transaction
MB INTERRUPT
1
S 11110 addr[9:8]
W
A
addr[7:0]
A
S
W
Sr 11110 addr[9:8]
R
A
This implies the following procedure for a 10-bit read operation:
1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit
(ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR).
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2.
3.
Once the Master on Bus interrupt is asserted, Write ADDR[7:0] register to '11110 address[9:8]
1'. ADDR.TENBITEN must be cleared (can be written simultaneously with ADDR).
Proceed to transmit data.
34.6.2.5. I2C Slave Operation
The I2C slave is byte-oriented and interrupt-based. The number of interrupts generated is kept at a
minimum by automatic handling of most events. The software driver complexity and code size are
reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart
Mode Enable bit in the Control A register (CTRLA.SMEN).
The I2C slave has two interrupt strategies.
When SCL Stretch Mode bit (CTRLA.SCLSM) is '0', SCL is stretched before or after the acknowledge bit.
In this mode, the I2C slave operates according to I2C Slave Behavioral Diagram (SCLSM=0). The circles
labelled "Sn" (S1, S2..) indicate the nodes the bus logic can jump to, based on software or hardware
interaction.
This diagram is used as reference for the description of the I2C slave operation throughout the document.
Figure 34-9. I2C Slave Behavioral Diagram (SCLSM=0)
AMATCH INTERRUPT
S1
S3
S2
S
DRDY INTERRUPT
A
ADDRESS
R
S
W
S1
S2
Sr
S3
S
W
A
A
P
S1
P
S2
Sr
S3
DATA
A/A
PREC INTERRUPT
W
Interrupt on STOP
Condition Enabled
S
W
S
W
A
DATA
S
W
A/A
S
W
Software interaction
The master provides data
on the bus
Addressed slave provides
data on the bus
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit is sent as shown in
Slave Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check
DATA before acknowledging. For master reads, an address and data interrupt will be issued
simultaneously after the address acknowledge. However, for master writes, the first data interrupt will be
seen after the first data byte has been received by the slave and the acknowledge bit has been sent to
the master.
Note: For I2C High-speed mode (Hs), SCLSM=1 is required.
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Figure 34-10. I2C Slave Behavioral Diagram (SCLSM=1)
AMATCH INTERRUPT (+ DRDY INTERRUPT in Master Read mode)
S1
S3
S2
S
ADDRESS
R
A/A
DRDY INTERRUPT
S
W
P
S2
Sr
S3
DATA
P
S2
Sr
S3
A/A
PREC INTERRUPT
W
Interrupt on STOP
Condition Enabled
S
W
A/A
S
W
DATA
A/A
S
W
S
W
Software interaction
The master provides data
on the bus
Addressed slave provides
data on the bus
Receiving Address Packets (SCLSM=0)
When CTRLA.SCLSM=0, the I2C slave stretches the SCL line according to Figure 34-9 I2C Slave
Behavioral Diagram (SCLSM=0). When the I2C slave is properly configured, it will wait for a start
condition.
When a start condition is detected, the successive address packet will be received and checked by the
address match logic. If the received address is not a match, the packet will be rejected, and the I2C slave
will wait for a new start condition. If the received address is a match, the Address Match bit in the
Interrupt Flag register (INTFLAG.AMATCH) will be set.
SCL will be stretched until the I2C slave clears INTFLAG.AMATCH. As the I2C slave holds the clock by
forcing SCL low, the software has unlimited time to respond.
The direction of a transaction is determined by reading the Read / Write Direction bit in the Status register
(STATUS.DIR). This bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, this indicates that the last packet
addressed to the I2C slave had a packet collision. A collision causes the SDA and SCL lines to be
released without any notification to software. Therefore, the next AMATCH interrupt is the first indication
of the previous packet’s collision. Collisions are intended to follow the SMBus Address Resolution
Protocol (ARP).
After the address packet has been received from the I2C master, one of two cases will arise based on
transfer direction.
Case 1: Address packet accepted – Read flag set
The STATUS.DIR bit is ‘1’, indicating an I2C master read operation. The SCL line is forced low, stretching
the bus clock. If an ACK is sent, I2C slave hardware will set the Data Ready bit in the Interrupt Flag
register (INTFLAG.DRDY), indicating data are needed for transmit. If a NACK is sent, the I2C slave will
wait for a new start condition and address match.
Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The
I2C slave Command bit field in the Control B register (CTRLB.CMD) can be written to '0x3' for both read
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and write operations as the command execution is dependent on the STATUS.DIR bit. Writing ‘1’ to
INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
Case 2: Address packet accepted – Write flag set
The STATUS.DIR bit is cleared, indicating an I2C master write operation. The SCL line is forced low,
stretching the bus clock. If an ACK is sent, the I2C slave will wait for data to be received. Data, repeated
start or stop can be received.
If a NACK is sent, the I2C slave will wait for a new start condition and address match. Typically, software
will immediately acknowledge the address packet by sending an ACK/NACK. The I2C slave command
CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent
on STATUS.DIR.
Writing ‘1’ to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the
CTRLB.ACKACT bit.
Receiving Address Packets (SCLSM=1)
When SCLSM=1, the I2C slave will stretch the SCL line only after an ACK, see Slave Behavioral Diagram
(SCLSM=1). When the I2C slave is properly configured, it will wait for a start condition to be detected.
When a start condition is detected, the successive address packet will be received and checked by the
address match logic.
If the received address is not a match, the packet will be rejected and the I2C slave will wait for a new
start condition.
If the address matches, the acknowledge action as configured by the Acknowledge Action bit Control B
register (CTRLB.ACKACT) will be sent and the Address Match bit in the Interrupt Flag register
(INTFLAG.AMATCH) is set. SCL will be stretched until the I2C slave clears INTFLAG.AMATCH. As the
I2C slave holds the clock by forcing SCL low, the software is given unlimited time to respond to the
address.
The direction of a transaction is determined by reading the Read/Write Direction bit in the Status register
(STATUS.DIR). This bit will be updated only when a valid address packet is received.
If the Transmit Collision bit in the Status register (STATUS.COLL) is set, the last packet addressed to the
I2C slave had a packet collision. A collision causes the SDA and SCL lines to be released without any
notification to software. The next AMATCH interrupt is, therefore, the first indication of the previous
packet’s collision. Collisions are intended to follow the SMBus Address Resolution Protocol (ARP).
After the address packet has been received from the I2C master, INTFLAG.AMATCH be set to ‘1’ to clear
it.
Receiving and Transmitting Data Packets
After the I2C slave has received an address packet, it will respond according to the direction either by
waiting for the data packet to be received or by starting to send a data packet by writing to DATA.DATA.
When a data packet is received or sent, INTFLAG.DRDY will be set. After receiving data, the I2C slave
will send an acknowledge according to CTRLB.ACKACT.
Case 1: Data received
INTFLAG.DRDY is set, and SCL is held low, pending for SW interaction.
Case 2: Data sent
When a byte transmission is successfully completed, the INTFLAG.DRDY interrupt flag is set. If NACK is
received, indicated by STATUS.RXNACK=1, the I2C slave must expect a stop or a repeated start to be
received. The I2C slave must release the data line to allow the I2C master to generate a stop or repeated
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start. Upon detecting a stop condition, the Stop Received bit in the Interrupt Flag register
(INTFLAG.PREC) will be set and the I2C slave will return to IDLE state.
High-Speed Mode
When the I2C slave is configured in High-speed mode (Hs, CTRLA.SPEED=0x2) and CTRLA.SCLSM=1,
switching between Full-speed and High-speed modes is automatic. When the slave recognizes a START
followed by a master code transmission and a NACK, it automatically switches to High-speed mode and
sets the High-speed status bit (STATUS.HS). The slave will then remain in High-speed mode until a
STOP is received.
10-Bit Addressing
When 10-bit addressing is enabled (ADDR.TENBITEN=1), the two address bytes following a START will
be checked against the 10-bit slave address recognition. The first byte of the address will always be
acknowledged, and the second byte will raise the address interrupt flag, see 10-bit Addressing.
If the transaction is a write, then the 10-bit address will be followed by N data bytes.
If the operation is a read, the 10-bit address will be followed by a repeated START and reception of '11110
ADDR[9:8] 1', and the second address interrupt will be received with the DIR bit set. The slave matches
on the second address as it it was addressed by the previous 10-bit address.
Figure 34-11. 10-bit Addressing
AMATCH INTERRUPT
S 11110 addr[9:8]
W
A
addr[7:0]
S
W
AMATCH INTERRUPT
A
Sr 11110 addr[9:8]
R
S
W
PMBus Group Command
When the PMBus Group Command bit in the CTRLB register is set (CTRLB.GCMD=1) and 7-bit
addressing is used, INTFLAG.PREC will be set when a STOP condition is detected on the bus. When
CTRLB.GCMD=0, a STOP condition without address match will not be set INTFLAG.PREC.
The group command protocol is used to send commands to more than one device. The commands are
sent in one continuous transmission with a single STOP condition at the end. When the STOP condition is
detected by the slaves addressed during the group command, they all begin executing the command they
received.
PMBus Group Command Example shows an example where this slave, bearing ADDRESS 1, is
addressed after a repeated START condition. There can be multiple slaves addressed before and after
this slave. Eventually, at the end of the group command, a single STOP is generated by the master. At
this point a STOP interrupt is asserted.
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Figure 34-12. PMBus Group Command Example
Command/Data
S
ADDRESS 0
W
n Bytes
A
A
AMATCH INTERRUPT
DRDY INTERRUPT
Command/Data
Sr
ADDRESS 1
(this slave)
S
W
W
A
34.6.3.
ADDRESS 2
W
A
n Bytes
A
PREC INTERRUPT
Command/Data
Sr
S
W
n Bytes
A
P
S
W
Additional Features
34.6.3.1. SMBus
The I2C includes three hardware SCL low time-outs which allow a time-out to occur for SMBus SCL low
time-out, master extend time-out, and slave extend time-out. This allows for SMBus functionality These
time-outs are driven by the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to
accurately time the time-out and must be configured to use a 32KHz oscillator. The I2C interface also
allows for a SMBus compatible SDA hold time.
•
•
•
TTIMEOUT: SCL low time of 25..35ms – Measured for a single SCL low period. It is enabled by
CTRLA.LOWTOUTEN.
TLOW:SEXT: Cumulative clock low extend time of 25 ms – Measured as the cumulative SCL low
extend time by a slave device in a single message from the initial START to the STOP. It is enabled
by CTRLA.SEXTTOEN.
TLOW:MEXT: Cumulative clock low extend time of 10 ms – Measured as the cumulative SCL low
extend time by the master device within a single byte from START-to-ACK, ACK-to-ACK, or ACKto-STOP. It is enabled by CTRLA.MEXTTOEN.
34.6.3.2. Smart Mode
The I2C interface has a smart mode that simplifies application code and minimizes the user interaction
needed to adhere to the I2C protocol. The smart mode accomplishes this by automatically issuing an ACK
or NACK (based on the content of CTRLB.ACKACT) as soon as DATA.DATA is read.
34.6.3.3. 4-Wire Mode
Writing a '1' to the Pin Usage bit in the Control A register (CTRLA.PINOUT) will enable 4-wire mode
operation. In this mode, the internal I2C tri-state drivers are bypassed, and an external I2C compliant tristate driver is needed when connecting to an I2C bus.
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Figure 34-13. I2C Pad Interface
SCL_OUT/
SDA_OUT
SCL_OUT/
SDA_OUT
pad
PINOUT
I2C
Driver
SCL/SDA
pad
SCL_IN/
SDA_IN
PINOUT
34.6.3.4. Quick Command
Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command.
When quick command is enabled, the corresponding interrupt flag (INTFLAG.SB or INTFLAG.MB) is set
immediately after the slave acknowledges the address. At this point, the software can either issue a stop
command or a repeated start by writing CTRLB.CMD or ADDR.ADDR.
34.6.4.
DMA, Interrupts and Events
Table 34-1. Module Request for SERCOM I2C Slave
Condition
Request
DMA
Interrupt
Data needed for transmit
(TX) (Slave transmit
mode)
Yes
(request cleared when
data is written)
Data received (RX)
(Slave receive mode)
Yes
(request cleared when
data is read)
Event
NA
Data Ready (DRDY)
Yes
Address Match
(AMATCH)
Yes
Stop received (PREC)
Yes
Error (ERROR)
Yes
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Table 34-2. Module Request for SERCOM I2C Master
Condition
Request
DMA
Interrupt
Data needed for transmit
(TX) (Master transmit
mode)
Yes
(request cleared when
data is written)
Data needed for transmit
(RX) (Master transmit
mode)
Yes
(request cleared when
data is read)
Event
NA
Master on Bus (MB)
Yes
Stop received (SB)
Yes
Error (ERROR)
Yes
34.6.4.1. DMA Operation
Smart mode must be enabled for DMA operation in the Control B register by writing CTRLB.SMEN=1.
Slave DMA
When using the I2C slave with DMA, an address match will cause the address interrupt flag
(INTFLAG.ADDRMATCH) to be raised. After the interrupt has been serviced, data transfer will be
performed through DMA.
The I2C slave generates the following requests:
•
•
Write data received (RX): The request is set when master write data is received. The request is
cleared when DATA is read.
Read data needed for transmit (TX): The request is set when data is needed for a master read
operation. The request is cleared when DATA is written.
Master DMA
When using the I2C master with DMA, the ADDR register must be written with the desired address
(ADDR.ADDR), transaction length (ADDR.LEN), and transaction length enable (ADDR.LENEN). When
ADDR.LENEN is written to 1 along with ADDR.ADDR, ADDR.LEN determines the number of data bytes
in the transaction from 0 to 255. DMA is then used to transfer ADDR.LEN bytes followed by an
automatically generated NACK (for master reads) and a STOP.
If a NACK is received by the slave for a master write transaction before ADDR.LEN bytes, a STOP will be
automatically generated and the length error (STATUS.LENERR) will be raised along with the
INTFLAG.ERROR interrupt.
The I2C master generates the following requests:
•
•
Read data received (RX): The request is set when master read data is received. The request is
cleared when DATA is read.
Write data needed for transmit (TX): The request is set when data is needed for a master write
operation. The request is cleared when DATA is written.
34.6.4.2. Interrupts
The I2C slave has the following interrupt sources. These are asynchronous interrupts. They can wake-up
the device from any sleep mode:
•
Error (ERROR)
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•
•
•
Data Ready (DRDY)
Address Match (AMATCH)
Stop Received (PREC)
The I2C master has the following interrupt sources. These are asynchronous interrupts. They can wakeup the device from any sleep mode:
•
•
•
Error (ERROR)
Slave on Bus (SB)
Master on Bus (MB)
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) will be set when the interrupt condition is meet. Each interrupt can be individually
enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and
disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An
interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request active until the interrupt flag is cleared, the interrupt is disabled or the I2C is reset.
See INTFLAG register for details on how to clear interrupt flags.
The I2C has one common interrupt request line for all the interrupt sources. The value of INTFLAG
indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests.
Refer to Nested Vector Interrupt Controller for details.
Related Links
Nested Vector Interrupt Controller on page 43
34.6.4.3. Events
Not applicable.
34.6.5.
Sleep Mode Operation
I2C Master Operation
The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In
Standby bit in the Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run
in standby sleep mode. Any interrupt can wake up the device.
If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is
finished. Any interrupt can wake up the device.
I2C Slave Operation
Writing CTRLA.RUNSTDBY=1 will allow the Address Match interrupt to wake up the device.
When CTRLA.RUNSTDBY=0, all receptions will be dropped.
34.6.6.
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
•
•
•
•
Software Reset bit in the CTRLA register (CTRLA.SWRST)
Enable bit in the CTRLA register (CTRLA.ENABLE)
Write to Bus State bits in the Status register (STATUS.BUSSTATE)
Address bits in the Address register (ADDR.ADDR) when in master operation.
The following registers are synchronized when written:
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•
Data (DATA) when in master operation
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
Related Links
Register Synchronization on page 123
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34.7.
Offset
Register Summary - I2C Slave
Name
0x00
0x01
0x02
Bit Pos.
7:0
CTRLA
31:24
0x04
7:0
0x06
CTRLB
0x07
MODE[2:0]
ENABLE
SWRST
15:8
23:16
0x03
0x05
RUNSTDBY
15:8
SEXTTOEN
SDAHOLD[1:0]
PINOUT
LOWTOUT
SCLSM
AMODE[1:0]
SPEED[1:0]
AACKEN
23:16
ACKACT
GCMD
SMEN
CMD[1:0]
31:24
0x08
...
Reserved
0x13
0x14
INTENCLR
0x15
Reserved
0x16
INTENSET
0x17
Reserved
0x18
INTFLAG
0x19
Reserved
0x1A
0x1B
STATUS
0x1C
0x1D
0x1E
7:0
ERROR
DRDY
AMATCH
PREC
7:0
ERROR
DRDY
AMATCH
PREC
7:0
ERROR
DRDY
AMATCH
PREC
7:0
CLKHOLD
RXNACK
COLL
BUSERR
LENERR
SEXTTOUT
LOWTOUT
SR
DIR
15:8
7:0
SYNCBUSY
0x1F
ENABLE
SWRST
15:8
23:16
31:24
0x20
...
Reserved
0x23
0x24
7:0
0x25
15:8
0x26
ADDR
23:16
0x27
31:24
0x28
7:0
0x29
34.8.
DATA
ADDR[6:0]
GENCEN
TENBITEN
ADDR[9:7]
ADDRMASK[6:0]
ADDRMASK[9:7]
DATA[7:0]
15:8
Register Description - I2C Slave
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "WriteSynchronized" or the "Read-Synchronized" property in each individual register description. For details,
refer to Synchronization.
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Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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34.8.1.
Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
Access
Reset
Bit
23
30
29
27
26
25
24
SCLSM
R/W
R/W
R/W
R/W
0
0
0
0
17
16
22
21
SEXTTOEN
Access
28
LOWTOUT
20
SPEED[1:0]
19
18
SDAHOLD[1:0]
PINOUT
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
15
14
13
12
7
6
5
4
11
10
3
2
9
8
Access
Reset
Bit
RUNSTDBY
Access
Reset
MODE[2:0]
1
0
ENABLE
SWRST
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit 30 – LOWTOUT: SCL Low Time-Out
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the slave will release its clock
hold, if enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will
remain set.
Value
Description
0
Time-out disabled.
1
Time-out enabled.
Bit 27 – SCLSM: SCL Clock Stretch Mode
This bit controls when SCL will be stretched for software interaction.
This bit is not synchronized.
Value
Description
0
SCL stretch according to Figure 34-9 I2C Slave Behavioral Diagram (SCLSM=0)
1
SCL stretch only after ACK bit according to Figure 34-10 I2C Slave Behavioral Diagram
(SCLSM=1)
Bits 25:24 – SPEED[1:0]: Transfer Speed
These bits define bus speed.
These bits are not synchronized.
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Value
Description
0x0
Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1
Fast-mode Plus (Fm+) up to 1 MHz
0x2
High-speed mode (Hs-mode) up to 3.4 MHz
0x3
Reserved
Bit 23 – SEXTTOEN: Slave SCL Low Extend Time-Out
This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms
from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal
state machine. Any interrupt flags set at the time of time-out will remain set. If the address was
recognized, PREC will be set when a STOP is received.
This bit is not synchronized.
Value
Description
0
Time-out disabled
1
Time-out enabled
Bits 21:20 – SDAHOLD[1:0]: SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
These bits are not synchronized.
Value
Name
Description
0x0
DIS
Disabled
0x1
75
50-100ns hold time
0x2
450
300-600ns hold time
0x3
600
400-800ns hold time
Bit 16 – PINOUT: Pin Usage
This bit sets the pin usage to either two- or four-wire operation:
This bit is not synchronized.
Value
Description
0
4-wire operation disabled
1
4-wire operation enabled
Bit 7 – RUNSTDBY: Run in Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
Value
Description
0
Disabled – All reception is dropped.
1
Wake on address match, if enabled.
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Bits 4:2 – MODE[2:0]: Operating Mode
These bits must be written to 0x04 to select the I2C slave serial communication interface of the SERCOM.
These bits are not synchronized.
Bit 1 – ENABLE: Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization
Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE
will be cleared when the operation is complete.
This bit is not enable-protected.
Value
Description
0
The peripheral is disabled or being disabled.
1
The peripheral is enabled.
Bit 0 – SWRST: Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the
SERCOM will be disabled.
Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same writeoperation will be discarded. Any register write access during the ongoing reset will result in an APB error.
Reading any register will return the reset value of the register.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
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34.8.2.
Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
30
29
28
27
23
22
21
20
19
26
25
18
17
24
Access
Reset
Bit
ACKACT
Access
Reset
Bit
15
14
13
12
11
AMODE[1:0]
16
CMD[1:0]
R/W
R/W
R/W
0
0
0
10
9
8
AACKEN
GCMD
SMEN
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
7
6
2
1
0
Access
5
4
3
Access
Reset
Bit 18 – ACKACT: Acknowledge Action
This bit defines the slave's acknowledge behavior after an address or data byte is received from the
master. The acknowledge action is executed when a command is written to the CMD bits. If smart mode
is enabled (CTRLB.SMEN=1), the acknowledge action is performed when the DATA register is read.
This bit is not enable-protected.
Value
Description
0
Send ACK
1
Send NACK
Bits 17:16 – CMD[1:0]: Command
This bit field triggers the slave operation as the below. The CMD bits are strobe bits, and always read as
zero. The operation is dependent on the slave interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH,
in addition to STATUS.DIR.
All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared
when a command is given.
This bit is not enable-protected.
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Table 34-3. Command Description
CMD[1:0] DIR
Action
0x0
X
(No action)
0x1
X
(Reserved)
0x2
Used to complete a transaction in response to a data interrupt (DRDY)
0 (Master write) Execute acknowledge action succeeded by waiting for any start (S/Sr)
condition
1 (Master read) Wait for any start (S/Sr) condition
0x3
Used in response to an address interrupt (AMATCH)
0 (Master write) Execute acknowledge action succeeded by reception of next byte
1 (Master read) Execute acknowledge action succeeded by slave data interrupt
Used in response to a data interrupt (DRDY)
0 (Master write) Execute acknowledge action succeeded by reception of next byte
1 (Master read) Execute a byte read operation followed by ACK/NACK reception
Bits 15:14 – AMODE[1:0]: Address Mode
These bits set the addressing mode.
These bits are not write-synchronized.
Value
Name
Description
0x0
MASK
The slave responds to the address written in ADDR.ADDR masked by the value
in ADDR.ADDRMASK.
See SERCOM – Serial Communication Interface for additional information.
0x1
2_ADDRS The slave responds to the two unique addresses in ADDR.ADDR and
ADDR.ADDRMASK.
0x2
RANGE
The slave responds to the range of addresses between and including
ADDR.ADDR and ADDR.ADDRMASK. ADDR.ADDR is the upper limit.
0x3
-
Reserved.
Bit 10 – AACKEN: Automatic Acknowledge Enable
This bit enables the address to be automatically acknowledged if there is an address match.
This bit is not write-synchronized.
Value
Description
0
Automatic acknowledge is disabled.
1
Automatic acknowledge is enabled.
Bit 9 – GCMD: PMBus Group Command
This bit enables PMBus group command support. When enabled, the Stop Recived interrupt flag
(INTFLAG.PREC) will be set when a STOP condition is detected if the slave has been addressed since
the last STOP condition on the bus.
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This bit is not write-synchronized.
Value
Description
0
Group command is disabled.
1
Group command is enabled.
Bit 8 – SMEN: Smart Mode Enable
When smart mode is enabled, data is acknowledged automatically when DATA.DATA is read.
This bit is not write-synchronized.
Value
Description
0
Smart mode is disabled.
1
Smart mode is enabled.
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34.8.3.
Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
Bit
7
Access
Reset
6
5
4
3
2
1
0
ERROR
DRDY
AMATCH
PREC
R/W
R/W
R/W
R/W
0
0
0
0
Bit 7 – ERROR: Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 2 – DRDY: Data Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Ready bit, which disables the Data Ready interrupt.
Value
Description
0
The Data Ready interrupt is disabled.
1
The Data Ready interrupt is enabled.
Bit 1 – AMATCH: Address Match Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match
interrupt.
Value
Description
0
The Address Match interrupt is disabled.
1
The Address Match interrupt is enabled.
Bit 0 – PREC: Stop Received Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received
interrupt.
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Value
Description
0
The Stop Received interrupt is disabled.
1
The Stop Received interrupt is enabled.
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34.8.4.
Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
Bit
7
Access
Reset
6
5
4
3
2
1
0
ERROR
DRDY
AMATCH
PREC
R/W
R/W
R/W
R/W
0
0
0
0
Bit 7 – ERROR: Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 2 – DRDY: Data Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Data Ready bit, which enables the Data Ready interrupt.
Value
Description
0
The Data Ready interrupt is disabled.
1
The Data Ready interrupt is enabled.
Bit 1 – AMATCH: Address Match Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match
interrupt.
Value
Description
0
The Address Match interrupt is disabled.
1
The Address Match interrupt is enabled.
Bit 0 – PREC: Stop Received Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received
interrupt.
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Value
Description
0
The Stop Received interrupt is disabled.
1
The Stop Received interrupt is enabled.
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34.8.5.
Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: Bit
7
Access
Reset
2
1
0
ERROR
6
5
4
3
DRDY
AMATCH
PREC
R/W
R/W
R/W
R/W
0
0
0
0
Bit 7 – ERROR: Error
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in
the STATUS register. The corresponding bits in STATUS are SEXTTOUT, LOWTOUT, COLL, and
BUSERR.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 2 – DRDY: Data Ready
This flag is set when a I2C slave byte transmission is successfully completed.
The flag is cleared by hardware when either:
•
•
•
Writing to the DATA register.
Reading the DATA register with smart mode enabled.
Writing a valid command to the CMD register.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Ready interrupt flag.
Bit 1 – AMATCH: Address Match
This flag is set when the I2C slave address match logic detects that a valid address has been received.
The flag is cleared by hardware when CTRL.CMD is written.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Address Match interrupt flag. When cleared, an ACK/NACK will be sent
according to CTRLB.ACKACT.
Bit 0 – PREC: Stop Received
This flag is set when a stop condition is detected for a transaction being processed. A stop condition
detected between a bus master and another slave will not set this flag, unless the PMBus Group
Command is enabled in the Control B register (CTRLB.GCMD=1).
This flag is cleared by hardware after a command is issued on the next address match.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Stop Received interrupt flag.
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34.8.6.
Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: Bit
15
14
13
12
11
Access
Reset
Bit
5
10
9
LENERR
SEXTTOUT
R/W
R/W
0
0
8
7
6
4
3
2
1
0
CLKHOLD
LOWTOUT
SR
DIR
RXNACK
COLL
BUSERR
Access
R
R/W
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit 10 – LENERR: Transaction Length Error
This bit is set when the length counter is enabled (LENGTH.LENEN) and a STOP or repeated START is
received before or after the length in LENGTH.LEN is reached.
This bit is cleared automatically when responding to a new start condition with ACK or NACK
(CTRLB.CMD=0x3) or when INTFLAG.AMATCH is cleared.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status.
Bit 10 – HS: High-speed
This bit is set if the slave detects a START followed by a Master Code transmission.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status. However, this flag is automatically cleared when a STOP is
received.
Bit 9 – SEXTTOUT: Slave SCL Low Extend Time-Out
This bit is set if a slave SCL low extend time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to
CTRLB.CMD) or when INTFLAG.AMATCH is cleared.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status.
Value
Description
0
No SCL low extend time-out has occurred.
1
SCL low extend time-out has occurred.
Bit 7 – CLKHOLD: Clock Hold
The slave Clock Hold bit (STATUS.CLKHOLD) is set when the slave is holding the SCL line low,
stretching the I2C clock. Software should consider this bit a read-only status flag that is set when
INTFLAG.DRDY or INTFLAG.AMATCH is set.
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This bit is automatically cleared when the corresponding interrupt is also cleared.
Bit 6 – LOWTOUT: SCL Low Time-out
This bit is set if an SCL low time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to
CTRLB.CMD) or when INTFLAG.AMATCH is cleared.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status.
Value
Description
0
No SCL low time-out has occurred.
1
SCL low time-out has occurred.
Bit 4 – SR: Repeated Start
When INTFLAG.AMATCH is raised due to an address match, SR indicates a repeated start or start
condition.
This flag is only valid while the INTFLAG.AMATCH flag is one.
Value
Description
0
Start condition on last address match
1
Repeated start condition on last address match
Bit 3 – DIR: Read / Write Direction
The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from
a master.
Value
Description
0
Master write operation is in progress.
1
Master read operation is in progress.
Bit 2 – RXNACK: Received Not Acknowledge
This bit indicates whether the last data packet sent was acknowledged or not.
Value
Description
0
Master responded with ACK.
1
Master responded with NACK.
Bit 1 – COLL: Transmit Collision
If set, the I2C slave was not able to transmit a high data or NACK bit, the I2C slave will immediately
release the SDA and SCL lines and wait for the next packet addressed to it.
This flag is intended for the SMBus address resolution protocol (ARP). A detected collision in non-ARP
situations indicates that there has been a protocol violation, and should be treated as a bus error.
Note that this status will not trigger any interrupt, and should be checked by software to verify that the
data were sent correctly. This bit is cleared automatically if responding to an address match with an ACK
or a NACK (writing 0x3 to CTRLB.CMD), or INTFLAG.AMATCH is cleared.
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Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status.
Value
Description
0
No collision detected on last data byte sent.
1
Collision detected on last data byte sent.
Bit 0 – BUSERR: Bus Error
The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus,
regardless of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start
or stop is detected on the I2C bus lines. A start condition directly followed by a stop condition is one
example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol
violation, and will set STATUS.BUSERR.
This bit is cleared automatically if responding to an address match with an ACK or a NACK (writing 0x3 to
CTRLB.CMD) or INTFLAG.AMATCH is cleared.
Writing a '1' to this bit will clear the status.
Writing a '0' to this bit has no effect.
Value
Description
0
No bus error detected.
1
Bus error detected.
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34.8.7.
Synchronization Busy
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property:
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
ENABLE
SWRST
Access
R
R
Reset
0
0
Bit 1 – ENABLE: SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the
SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be
discarded and an APB error will be generated.
Value
Description
0
Enable synchronization is not busy.
1
Enable synchronization is busy.
Bit 0 – SWRST: Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the
SYNCBUSY.SWRST bit will be set until synchronization is complete.
Writes to any register while synchronization is on-going will be discarded and an APB error will be
generated.
Value
Description
0
SWRST synchronization is not busy.
1
SWRST synchronization is busy.
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34.8.8.
Address
Name: ADDR
Offset: 0x24
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
ADDRMASK[9:7]
Access
R/W
R/W
R/W
0
0
0
19
18
17
16
Reset
Bit
23
22
21
20
ADDRMASK[6:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
TENBITEN
Access
8
ADDR[9:7]
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
7
2
1
6
5
4
3
ADDR[6:0]
Access
Reset
0
GENCEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 26:17 – ADDRMASK[9:0]: Address Mask
These bits act as a second address match register, an address mask register or the lower limit of an
address range, depending on the CTRLB.AMODE setting.
Bit 15 – TENBITEN: Ten Bit Addressing Enable
Value
Description
0
10-bit address recognition disabled.
1
10-bit address recognition enabled.
Bits 10:1 – ADDR[9:0]: Address
These bits contain the I2C slave address used by the slave address match logic to determine if a master
has addressed the slave.
When using 7-bit addressing, the slave address is represented by ADDR[6:0].
When using 10-bit addressing (ADDR.TENBITEN=1), the slave address is represented by ADDR[9:0]
When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to
indicate whether it is a read or a write transaction.
Bit 0 – GENCEN: General Call Address Enable
A general call address is an address consisting of all-zeroes, including the direction bit (master write).
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Value
Description
0
General call address recognition disabled.
1
General call address recognition enabled.
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34.8.9.
Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: Write-Synchronized, Read-Synchronized
Bit
15
14
13
12
7
6
5
4
11
10
9
8
3
2
1
0
Access
Reset
Bit
DATA[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7:0 – DATA[7:0]: Data
The slave data register I/O location (DATA.DATA) provides access to the master transmit and receive
data buffers. Reading valid data or writing data to be transmitted can be successfully done only when
SCL is held low by the slave (STATUS.CLKHOLD is set). An exception occurs when reading the last data
byte after the stop condition has been received.
Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state
of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).
Writing or reading DATA.DATA when not in smart mode does not require synchronization.
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34.9.
Offset
Register Summary - I2C Master
Name
0x00
0x01
0x02
Bit Pos.
7:0
CTRLA
31:24
0x04
7:0
0x06
CTRLB
0x07
MODE[2:0]
ENABLE
SWRST
15:8
23:16
0x03
0x05
RUNSTDBY
SEXTTOEN
MEXTTOEN
SDAHOLD[1:0]
LOWTOUT
INACTOUT[1:0]
PINOUT
SCLSM
SPEED[1:0]
15:8
QCEN
23:16
ACKACT
SMEN
CMD[1:0]
31:24
0x08
...
Reserved
0x0B
0x0C
0x0D
0x0E
BAUD
0x0F
7:0
BAUD[7:0]
15:8
BAUDLOW[7:0]
23:16
HSBAUD[7:0]
31:24
HSBAUDLOW[7:0]
0x10
...
Reserved
0x13
0x14
INTENCLR
0x15
Reserved
0x16
INTENSET
0x17
Reserved
0x18
INTFLAG
0x18
0x19
0x1A
0x1B
DATA
STATUS
7:0
ERROR
SB
MB
7:0
ERROR
SB
MB
7:0
ERROR
SB
MB
RXNACK
ARBLOST
BUSERR
7:0
DATA[7:0]
15:8
7:0
CLKHOLD
LOWTOUT
BUSSTATE[1:0]
15:8
LENERR
SEXTTOUT
MEXTTOUT
0x1C
7:0
SYSOP
ENABLE
SWRST
0x1D
15:8
0x1E
SYNCBUSY
0x1F
23:16
31:24
0x21
...
Reserved
0x23
0x24
0x25
0x26
7:0
ADDR
0x27
15:8
23:16
TENBITEN
HS
LENEN
ADDR[2:0]
LEN[7:0]
31:24
0x28
...
Reserved
0x2F
0x30
DBGCTRL
7:0
DBGSTOP
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34.10. Register Description - I2C Master
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "WriteSynchronized" or the "Read-Synchronized" property in each individual register description. For details,
refer to Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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34.10.1. Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
30
29
LOWTOUT
Access
Reset
Bit
27
26
25
SCLSM
24
SPEED[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
21
20
19
23
22
SEXTTOEN
MEXTTOEN
Access
28
INACTOUT[1:0]
18
17
SDAHOLD[1:0]
16
PINOUT
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
15
14
13
12
7
6
5
4
11
10
3
2
9
8
Access
Reset
Bit
RUNSTDBY
Access
Reset
MODE[2:0]
1
0
ENABLE
SWRST
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit 30 – LOWTOUT: SCL Low Time-Out
This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the master will release its clock
hold, if enabled, and complete the current transaction. A stop condition will automatically be transmitted.
INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The
STATUS.LOWTOUT and STATUS.BUSERR status bits will be set.
This bit is not synchronized.
Value
Description
0
Time-out disabled.
1
Time-out enabled.
Bits 29:28 – INACTOUT[1:0]: Inactive Time-Out
If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus
state logic will be set to idle. An inactive bus arise when either an I2C master or slave is holding the SCL
low.
Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up.
Calculated time-out periods are based on a 100kHz baud rate.
These bits are not synchronized.
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Value
Name
Description
0x0
DIS
Disabled
0x1
55US
5-6 SCL cycle time-out (50-60µs)
0x2
105US
10-11 SCL cycle time-out (100-110µs)
0x3
205US
20-21 SCL cycle time-out (200-210µs)
Bit 27 – SCLSM: SCL Clock Stretch Mode
This bit controls when SCL will be stretched for software interaction.
This bit is not synchronized.
Value
Description
0
SCL stretch according to Figure 34-4 I2C Master Behavioral Diagram (SCLSM=0).
1
SCL stretch only after ACK bit, Figure 34-5 I2C Master Behavioral Diagram (SCLSM=1).
Bits 25:24 – SPEED[1:0]: Transfer Speed
These bits define bus speed.
These bits are not synchronized.
Value
Description
0x0
Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1
Fast-mode Plus (Fm+) up to 1 MHz
0x2
High-speed mode (Hs-mode) up to 3.4 MHz
0x3
Reserved
Bit 23 – SEXTTOEN: Slave SCL Low Extend Time-Out
This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms
from the initial START to a STOP, the master will release its clock hold if enabled, and complete the
current transaction. A STOP will automatically be transmitted.
SB or MB will be set as normal, but CLKHOLD will be release. The MEXTTOUT and BUSERR status bits
will be set.
This bit is not synchronized.
Value
Description
0
Time-out disabled
1
Time-out enabled
Bit 22 – MEXTTOEN: Master SCL Low Extend Time-Out
This bit enables the master SCL low extend time-out. If SCL is cumulatively held low for greater than
10ms from START-to-ACK, ACK-to-ACK, or ACK-to-STOP the master will release its clock hold if
enabled, and complete the current transaction. A STOP will automatically be transmitted.
SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status
bits will be set.
This bit is not synchronized.
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Value
Description
0
Time-out disabled
1
Time-out enabled
Bits 21:20 – SDAHOLD[1:0]: SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
These bits are not synchronized.
Value
Name
Description
0x0
DIS
Disabled
0x1
75NS
50-100ns hold time
0x2
450NS
300-600ns hold time
0x3
600NS
400-800ns hold time
Bit 16 – PINOUT: Pin Usage
This bit set the pin usage to either two- or four-wire operation:
This bit is not synchronized.
Value
Description
0
4-wire operation disabled.
1
4-wire operation enabled.
Bit 7 – RUNSTDBY: Run in Standby
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
Value
Description
0
GCLK_SERCOMx_CORE is disabled and the I2C master will not operate in standby sleep
mode.
1
GCLK_SERCOMx_CORE is enabled in all sleep modes.
Bits 4:2 – MODE[2:0]: Operating Mode
These bits must be written to 0x5 to select the I2C master serial communication interface of the
SERCOM.
These bits are not synchronized.
Bit 1 – ENABLE: Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable
Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE
will be cleared when the operation is complete.
This bit is not enable-protected.
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Value
Description
0
The peripheral is disabled or being disabled.
1
The peripheral is enabled.
Bit 0 – SWRST: Software Reset
Writing '0' to this bit has no effect.
Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the
SERCOM will be disabled.
Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same writeoperation will be discarded. Any register write access during the ongoing reset will result in an APB error.
Reading any register will return the reset value of the register.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is not enable-protected.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
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34.10.2. Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
30
29
28
27
23
22
21
20
19
26
25
18
17
24
Access
Reset
Bit
ACKACT
Access
Reset
Bit
15
14
13
12
11
16
CMD[1:0]
R/W
R/W
R/W
0
0
0
10
9
8
QCEN
SMEN
Access
R
R/W
Reset
0
0
1
0
Bit
7
6
5
4
3
2
Access
Reset
Bit 18 – ACKACT: Acknowledge Action
This bit defines the I2C master's acknowledge behavior after a data byte is received from the I2C slave.
The acknowledge action is executed when a command is written to CTRLB.CMD, or if smart mode is
enabled (CTRLB.SMEN is written to one), when DATA.DATA is read.
This bit is not enable-protected.
This bit is not write-synchronized.
Value
Description
0
Send ACK.
1
Send NACK.
Bits 17:16 – CMD[1:0]: Command
Writing these bits triggers a master operation as described below. The CMD bits are strobe bits, and
always read as zero. The acknowledge action is only valid in master read mode. In master write mode, a
command will only result in a repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits
can be written at the same time, and then the acknowledge action will be updated before the command is
triggered.
Commands can only be issued when either the Slave on Bus interrupt flag (INTFLAG.SB) or Master on
Bus interrupt flag (INTFLAG.MB) is '1'.
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If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address
in ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits.
This will trigger a repeated start followed by transmission of the new address.
Issuing a command will set the System Operation bit in the Synchronization Busy register
(SYNCBUSY.SYSOP).
Table 34-4. Command Description
CMD[1:0]
Direction
Action
0x0
X
(No action)
0x1
X
Execute acknowledge action succeeded by repeated Start
0x2
0 (Write)
No operation
1 (Read)
Execute acknowledge action succeeded by a byte read operation
X
Execute acknowledge action succeeded by issuing a stop condition
0x3
These bits are not enable-protected.
Bit 9 – QCEN: Quick Command Enable
This bit is not write-synchronized.
Value
Description
0
Quick Command is disabled.
1
Quick Command is enabled.
Bit 8 – SMEN: Smart Mode Enable
When smart mode is enabled, acknowledge action is sent when DATA.DATA is read.
This bit is not write-synchronized.
Value
Description
0
Smart mode is disabled.
1
Smart mode is enabled.
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34.10.3. Baud Rate
Name: BAUD
Offset: 0x0C
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
HSBAUDLOW[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
HSBAUD[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
BAUDLOW[7:0]
Access
BAUD[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:24 – HSBAUDLOW[7:0]: High Speed Master Baud Rate Low
HSBAUDLOW non-zero: HSBAUDLOW indicates the SCL low time in High-speed mode according to
HSBAUDLOW = �GCLK ⋅ �LOW − 1
HSBAUDLOW equal to zero: The HSBAUD register is used to time TLOW, THIGH, TSU;STO, THD;STA and
TSU;STA.. TBUF is timed by the BAUD register.
Bits 23:16 – HSBAUD[7:0]: High Speed Master Baud Rate
This bit field indicates the SCL high time in High-speed mode according to the following formula. When
HSBAUDLOW is zero, TLOW, THIGH, TSU;STO, THD;STA and TSU;STA are derived using this formula. TBUF is
timed by the BAUD register.
HSBAUD = �GCLK ⋅ �HIGH − 1
Bits 15:8 – BAUDLOW[7:0]: Master Baud Rate Low
If this bit field is non-zero, the SCL low time will be described by the value written.
For more information on how to calculate the frequency, see SERCOM Clock Generation – Baud-Rate
Generator.
Bits 7:0 – BAUD[7:0]: Master Baud Rate
This bit field is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If BAUD.BAUDLOW is
zero, BAUD will be used to generate both high and low periods of the SCL.
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For more information on how to calculate the frequency, see SERCOM Clock Generation – Baud-Rate
Generator.
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34.10.4. Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
Bit
7
Access
Reset
6
5
4
3
2
1
0
ERROR
SB
MB
R/W
R/W
R/W
0
0
0
Bit 7 – ERROR: Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 1 – SB: Slave on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Slave on Bus Interrupt Enable bit, which disables the Slave on Bus
interrupt.
Value
Description
0
The Slave on Bus interrupt is disabled.
1
The Slave on Bus interrupt is enabled.
Bit 0 – MB: Master on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Master on Bus Interrupt Enable bit, which disables the Master on Bus
interrupt.
Value
Description
0
The Master on Bus interrupt is disabled.
1
The Master on Bus interrupt is enabled.
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34.10.5. Interrupt Enable Clear
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
Bit
7
Access
Reset
6
5
4
3
2
1
0
ERROR
SB
MB
R/W
R/W
R/W
0
0
0
Bit 7 – ERROR: Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.
Value
Description
0
Error interrupt is disabled.
1
Error interrupt is enabled.
Bit 1 – SB: Slave on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Slave on Bus Interrupt Enable bit, which enables the Slave on Bus
interrupt.
Value
Description
0
The Slave on Bus interrupt is disabled.
1
The Slave on Bus interrupt is enabled.
Bit 0 – MB: Master on Bus Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Master on Bus Interrupt Enable bit, which enables the Master on Bus
interrupt.
Value
Description
0
The Master on Bus interrupt is disabled.
1
The Master on Bus interrupt is enabled.
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34.10.6. Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: Bit
7
Access
Reset
1
0
ERROR
6
5
4
3
2
SB
MB
R/W
R/W
R/W
0
0
0
Bit 7 – ERROR: Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status bits in the
STATUS register. These status bits are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and
BUSERR.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 1 – SB: Slave on Bus
The Slave on Bus flag (SB) is set when a byte is successfully received in master read mode, i.e., no
arbitration lost or bus error occurred during the operation. When this flag is set, the master forces the SCL
line low, stretching the I2C clock period. The SCL line will be released and SB will be cleared on one of
the following actions:
•
•
•
•
Writing to ADDR.ADDR
Writing to DATA.DATA
Reading DATA.DATA when smart mode is enabled (CTRLB.SMEN)
Writing a valid command to CTRLB.CMD
Writing '1' to this bit location will clear the SB flag. The transaction will not continue or be terminated until
one of the above actions is performed.
Writing '0' to this bit has no effect.
Bit 0 – MB: Master on Bus
This flag is set when a byte is transmitted in master write mode. The flag is set regardless of the
occurrence of a bus error or an arbitration lost condition. MB is also set when arbitration is lost during
sending of NACK in master read mode, or when issuing a start condition if the bus state is unknown.
When this flag is set and arbitration is not lost, the master forces the SCL line low, stretching the I2C clock
period. The SCL line will be released and MB will be cleared on one of the following actions:
•
•
•
•
Writing to ADDR.ADDR
Writing to DATA.DATA
Reading DATA.DATA when smart mode is enabled (CTRLB.SMEN)
Writing a valid command to CTRLB.CMD
Writing '1' to this bit location will clear the MB flag. The transaction will not continue or be terminated until
one of the above actions is performed.
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Writing '0' to this bit has no effect.
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34.10.7. Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: Write-Synchronized
Bit
15
14
13
12
11
Access
Reset
Bit
7
6
CLKHOLD
LOWTOUT
5
Access
R
R/W
R
Reset
0
0
0
4
3
10
9
8
LENERR
SEXTTOUT
MEXTTOUT
R/W
R/W
R/W
0
0
0
2
1
0
RXNACK
ARBLOST
BUSERR
R
R
R/W
R/W
0
0
0
0
BUSSTATE[1:0]
Bit 10 – LENERR: Transaction Length Error
This bit is set when automatic length is used for a DMA transaction and the slave sends a NACK before
ADDR.LEN bytes have been written by the master.
Writing '1' to this bit location will clear STATUS.LENERR. This flag is automatically cleared when writing
to the ADDR register.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bit 9 – SEXTTOUT: Slave SCL Low Extend Time-Out
This bit is set if a slave SCL low extend time-out occurs.
This bit is automatically cleared when writing to the ADDR register.
Writing '1' to this bit location will clear SEXTTOUT. Normal use of the I2C interface does not require the
SEXTTOUT flag to be cleared by this method.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bit 8 – MEXTTOUT: Master SCL Low Extend Time-Out
This bit is set if a master SCL low time-out occurs.
Writing '1' to this bit location will clear STATUS.MEXTTOUT. This flag is automatically cleared when
writing to the ADDR register.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bit 7 – CLKHOLD: Clock Hold
This bit is set when the master is holding the SCL line low, stretching the I2C clock. Software should
consider this bit when INTFLAG.SB or INTFLAG.MB is set.
This bit is cleared when the corresponding interrupt flag is cleared and the next operation is given.
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Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
This bit is not write-synchronized.
Bit 6 – LOWTOUT: SCL Low Time-Out
This bit is set if an SCL low time-out occurs.
Writing '1' to this bit location will clear this bit. This flag is automatically cleared when writing to the ADDR
register.
Writing '0' to this bit has no effect.
This bit is not write-synchronized.
Bits 5:4 – BUSSTATE[1:0]: Bus State
These bits indicate the current I2C bus state.
When in UNKNOWN state, writing 0x1 to BUSSTATE forces the bus state into the IDLE state. The bus
state cannot be forced into any other state.
Writing BUSSTATE to idle will set SYNCBUSY.SYSOP.
Value
Name
Description
0x0
UNKNOWN The bus state is unknown to the I2C master and will wait for a stop condition to
be detected or wait to be forced into an idle state by software
0x1
IDLE
The bus state is waiting for a transaction to be initialized
0x2
OWNER
The I2C master is the current owner of the bus
0x3
BUSY
Some other I2C master owns the bus
Bit 2 – RXNACK: Received Not Acknowledge
This bit indicates whether the last address or data packet sent was acknowledged or not.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
This bit is not write-synchronized.
Value
Description
0
Slave responded with ACK.
1
Slave responded with NACK.
Bit 1 – ARBLOST: Arbitration Lost
This bit is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a start or
repeated start condition on the bus. The Master on Bus interrupt flag (INTFLAG.MB) will be set when
STATUS.ARBLOST is set.
Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
This bit is not write-synchronized.
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Bit 0 – BUSERR: Bus Error
This bit indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An
illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C
bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a
time-out occurs during a frame, this is also considered a protocol violation, and will set BUSERR.
If the I2C master is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB
will be set in addition to BUSERR.
Writing the ADDR.ADDR register will automatically clear the BUSERR flag.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
This bit is not write-synchronized.
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34.10.8. Synchronization Busy
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property:
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
SYSOP
ENABLE
SWRST
Access
R
R
R
Reset
0
0
0
Bit 2 – SYSOP: System Operation Synchronization Busy
Writing CTRLB.CMD, STATUS.BUSSTATE, ADDR, or DATA when the SERCOM is enabled requires
synchronization. When written, the SYNCBUSY.SYSOP bit will be set until synchronization is complete.
Value
Description
0
System operation synchronization is not busy.
1
System operation synchronization is busy.
Bit 1 – ENABLE: SERCOM Enable Synchronization Busy
Enabling and disabling the SERCOM (CTRLA.ENABLE) requires synchronization. When written, the
SYNCBUSY.ENABLE bit will be set until synchronization is complete.
Writes to any register (except for CTRLA.SWRST) while enable synchronization is on-going will be
discarded and an APB error will be generated.
Value
Description
0
Enable synchronization is not busy.
1
Enable synchronization is busy.
Bit 0 – SWRST: Software Reset Synchronization Busy
Resetting the SERCOM (CTRLA.SWRST) requires synchronization. When written, the
SYNCBUSY.SWRST bit will be set until synchronization is complete.
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Writes to any register while synchronization is on-going will be discarded and an APB error will be
generated.
Value
Description
0
SWRST synchronization is not busy.
1
SWRST synchronization is busy.
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34.10.9. Address
Name: ADDR
Offset: 0x24
Reset: 0x0000
Property: Write-Synchronized
Bit
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
Access
Reset
Bit
LEN[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
TENBITEN
HS
LENEN
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
Bit
7
6
5
2
1
0
Access
ADDR[2:0]
4
3
Access
Reset
Bits 23:16 – LEN[7:0]: Transaction Length
These bits define the transaction length of a DMA transaction from 0 to 255 bytes. The Transfer Length
Enable (LENEN) bit must be written to '1' in order to use DMA.
Bit 15 – TENBITEN: Ten Bit Addressing Enable
This bit enables 10-bit addressing. This bit can be written simultaneously with ADDR to indicate a 10-bit
or 7-bit address transmission.
Value
Description
0
10-bit addressing disabled.
1
10-bit addressing enabled.
Bit 14 – HS: High Speed
This bit enables High-speed mode for the current transfer from repeated START to STOP. This bit can be
written simultaneously with ADDR for a high speed transfer.
Value
Description
0
High-speed transfer disabled.
1
High-speed transfer enabled.
Bit 13 – LENEN: Transfer Length Enable
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Value
Description
0
Automatic transfer length disabled.
1
Automatic transfer length enabled.
Bits 10:8 – ADDR[2:0]: Address
When ADDR is written, the consecutive operation will depend on the bus state:
UNKNOWN: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated.
BUSY: The I2C master will await further operation until the bus becomes IDLE.
IDLE: The I2C master will issue a start condition followed by the address written in ADDR. If the address
is acknowledged, SCL is forced and held low, and STATUS.CLKHOLD and INTFLAG.MB are set.
OWNER: A repeated start sequence will be performed. If the previous transaction was a read, the
acknowledge action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to
issue a repeated start is performed while INTFLAG.MB or INTFLAG.SB is set.
STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB will be cleared when ADDR is
written.
The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access
does not trigger the master logic to perform any bus protocol related operations.
The I2C master control logic uses bit 0 of ADDR as the bus protocol’s read/write flag (R/W); 0 for write
and 1 for read.
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34.10.10. Data
Name: DATA
Offset: 0x18
Reset: 0x0000
Property: Write-Synchronized, Read-Synchronized
Bit
15
14
13
12
7
6
5
4
11
10
9
8
3
2
1
0
Access
Reset
Bit
DATA[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7:0 – DATA[7:0]: Data
The master data register I/O location (DATA) provides access to the master transmit and receive data
buffers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is
held low by the master (STATUS.CLKHOLD is set). An exception is reading the last data byte after the
stop condition has been sent.
Accessing DATA.DATA auto-triggers I2C bus operations. The operation performed depends on the state
of CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).
Writing or reading DATA.DATA when not in smart mode does not require synchronization.
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34.10.11. Debug Control
Name: DBGCTRL
Offset: 0x30
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
DBGSTOP
Access
R/W
Reset
0
Bit 0 – DBGSTOP: Debug Stop Mode
This bit controls functionality when the CPU is halted by an external debugger.
Value
Description
0
The baud-rate generator continues normal operation when the CPU is halted by an external
debugger.
1
The baud-rate generator is halted when the CPU is halted by an external debugger.
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35.
TC – Timer/Counter
35.1.
Overview
There are up to five TC peripheral instances.
Each TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can
be set to count events, or clock pulses. The counter, together with the compare/capture channels, can be
configured to timestamp input events or IO pin edges, allowing for capturing of frequency and/or pulse
width.
A TC can also perform waveform generation, such as frequency generation and pulse-width modulation.
35.2.
Features
•
•
•
•
•
•
•
•
Selectable configuration
– 8-, 16- or 32-bit TC operation, with compare/capture channels
2 compare/capture channels (CC) with:
– Double buffered timer period setting (in 8-bit mode only)
– Double buffered compare channel
Waveform generation
– Frequency generation
– Single-slope pulse-width modulation
Input capture
– Event / IO pin edge capture
– Frequency capture
– Pulse-width capture
– Time-stamp capture
One input event
Interrupts/output events on:
– Counter overflow/underflow
– Compare match or capture
Internal prescaler
DMA support
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35.3.
Block Diagram
Figure 35-1. Timer/Counter Block Diagram
Base Counter
BUFV
PERBUF
Prescaler
PER
"count"
Counter
OVF (INT/Event/DMA Req.)
"clear"
"load"
COUNT
ERR (INT Req.)
Control Logic
"direction"
"TCE"
Event
System
"event"
BOTTOM
=0
UPDATE
TOP
=
Compare/Capture
(Unit x = {0,1}
BUFV
"capture"
CCBUFx
Control Logic
WO[1]
Waveform
Generation
CCx
"match"
=
35.4.
WO[0]
MCx (INT/Event/DMA Req.)
Signal Description
Table 35-1. Signal Description for TC.
Signal Name
Type
Description
WO[1:0]
Digital output
Waveform output
Digital input
Capture input
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
Related Links
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I/O Multiplexing and Considerations on page 28
35.5.
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
35.5.1.
I/O Lines
In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller
(PORT).
Related Links
PORT: IO Pin Controller on page 455
35.5.2.
Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The
interrupts can wake up the device from sleep modes. Events connected to the event system can trigger
other operations in the system without exiting sleep modes.
Related Links
PM – Power Manager on page 177
35.5.3.
Clocks
The TC bus clocks (CLK_TCx_APB) can be enabled and disabled in the Main Clock Module. The default
state of CLK_TCx_APB can be found in the Peripheral Clock Masking.
The generic clocks (GCLK_TCx) are asynchronous to the user interface clock (CLK_TCx_APB). Due to
this asynchronicity, accessing certain registers will require synchronization between the clock domains.
Refer to Synchronization for further details.
Note that TC0 and TC1 share a peripheral clock channel, as do TC2 and TC3. For this reason they
cannot be set to different clock frequencies.
Related Links
Peripheral Clock Masking on page 152
35.5.4.
DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for
details.
Related Links
DMAC – Direct Memory Access Controller on page 346
35.5.5.
Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
Nested Vector Interrupt Controller on page 43
35.5.6.
Events
The events of this peripheral are connected to the Event System.
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Related Links
EVSYS – Event System on page 487
35.5.7.
Debug Operation
When the CPU is halted in debug mode, this peripheral will halt normal operation. This peripheral can be
forced to continue operation during debugging - refer to the Debug Control (DBGCTRL) register for
details.
35.5.8.
Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except the following:
•
•
•
•
•
Interrupt Flag Status and Clear register (INTFLAG)
Status register (STATUS)
Count register (COUNT)
Period and Period Buffer registers (PER, PERBUF)
Compare/Capture Value registers and Compare/Capture Value Buffer registers (CCx, CCBUFx)
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection
does not apply for accesses through an external debugger.
35.5.9.
Analog Connections
Not applicable.
35.6.
Functional Description
35.6.1.
Principle of Operation
The following definitions are used throughout the documentation:
Table 35-2. Timer/Counter Definitions
Name
Description
TOP
The counter reaches TOP when it becomes equal to the highest value in
the count sequence. The TOP value can be the same as Period (PER)
or the Compare Channel 0 (CC0) register value depending on the
waveform generator mode in Waveform Output Operations.
ZERO
The counter is ZERO when it contains all zeroes
MAX
The counter reaches MAX when it contains all ones
UPDATE
The timer/counter signals an update when it reaches ZERO or TOP,
depending on the direction settings.
Timer
The timer/counter clock control is handled by an internal source
Counter
The clock control is handled externally (e.g. counting external events)
CC
For compare operations, the CC are referred to as “compare channels”
For capture operations, the CC are referred to as “capture channels.”
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Each TC instance has up to two compare/capture channels (CC0 and CC1).
The counter in the TC can either count events from the Event System, or clock ticks of the GCLK_TCx
clock, which may be divided by the prescaler.
The counter value is passed to the CCx where it can be either compared to user-defined values or
captured.
The Counter register (COUNT), compare and capture registers with buffers (CCx and CCBUFx) can be
configured as 8-, 16- or 32-bit registers, with according MAX values. Mode settings determine the
maximum range of the counter. Each buffer register has a buffer valid (BUFV) flag that indicates when the
buffer contains a new value.
In 8-bit mode, Period Value (PER) and Period Buffer Value (PERBUF) registers are also available. The
counter range and the operating frequency determine the maximum time resolution achievable with the
TC peripheral.
The TC can be set to count up or down. Under normal operation, the counter value is continuously
compared to the TOP or ZERO value to determine whether the counter has reached that value. On a
comparison match the TC can request DMA transactions, or generate interrupts or events for the Event
System.
In compare operation, the counter value is continuously compared to the values in the CCx registers. In
case of a match the TC can request DMA transactions, or generate interrupts or events for the Event
System. In waveform generator mode, these comparisons are used to set the waveform period or pulse
width.
Capture operation can be enabled to perform input signal period and pulse width measurements, or to
capture selectable edges from an IO pin or internal event from Event System.
35.6.2.
Basic Operation
35.6.2.1. Initialization
The following registers are enable-protected, meaning that they can only be written when the TC is
disabled (CTRLA.ENABLE =0):
•
•
•
•
Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits
Drive Control register (DRVCTRL)
Wave register (WAVE)
Event Control register (EVCTRL)
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is
written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted
by the "Enable-Protected" property in the register description.
Before enabling the TC, the peripheral must be configured by the following steps:
1. Enable the TC bus clock (CLK_TCx_APB).
2. Select 8-, 16- or 32-bit counter mode via the TC Mode bit group in the Control A register
(CTRLA.MODE). The default mode is 16-bit.
3. Select one wave generation operation in the Waveform Generation Operation bit group in the
WAVE register (WAVE.WAVEGEN).
4. If desired, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control A
register (CTRLA.PRESCALER).
– If the prescaler is used, select a prescaler synchronization operation via the Prescaler and
Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC).
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5.
6.
7.
8.
If desired, select one-shot operation by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT).
If desired, configure the counting direction 'down' (starting from the TOP value) by writing a '1' to
the Counter Direction bit in the Control B register (CTRLBSET.DIR).
For capture operation, enable the individual channels to capture in the Capture Channel x Enable
bit group in the Control A register (CTRLA.CAPTEN).
If desired, enable inversion of the waveform output or IO pin input signal for individual channels via
the Invert Enable bit group in the Drive Control register (DRVCTRL.INVEN).
35.6.2.2. Enabling, Disabling, and Resetting
The TC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The TC is
disbled by writing a zero to CTRLA.ENABLE.
The TC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All
registers in the TC, except DBGCTRL, will be reset to their initial state. Refer to the CTRLA register for
details.
The TC should be disabled before the TC is reset in order to avoid undefined behavior.
35.6.2.3. Prescaler Selection
The GCLK_TCx is fed into the internal prescaler.
The prescaler consists of a counter that counts up to the selected prescaler value, whereupon the output
of the prescaler toggles.
If the prescaler value is higher than one, the counter update condition can be optionally executed on the
next GCLK_TCx clock pulse or the next prescaled clock pulse. For further details, refer to Prescaler
(CTRLA.PRESCALER) and Counter Synchronization (CTRLA.PRESYNC) description.
Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see
the register description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
Note: When counting events, the prescaler is bypassed.
The joint stream of prescaler ticks and event action ticks is called CLK_TC_CNT.
Figure 35-2. Prescaler
PRESCALER
GCLK_TC
Prescaler
EVACT
GCLK_TC /
{1,2,4,8,64,256,1024}
CLK_TC_CNT
COUNT
EVENT
35.6.2.4. Counter Mode
The counter mode is selected by the Mode bit group in the Control A register (CTRLA.MODE). By default,
the counter is enabled in the 16-bit counter resolution. Three counter resolutions are available:
•
COUNT8: The 8-bit TC has its own Period Value and Period Buffer Value registers (PER and
PERBUF).
•
COUNT16: 16-bit is the default counter mode. There is no dedicated period register in this mode.
•
COUNT32: This mode is achieved by pairing two 16-bit TC peripherals. TC0 is paired with TC1,
and TC2 is paired with TC3. TC4 does not support 32-bit resolution.
When paired, the TC peripherals are configured using the registers of the even-numbered TC (TC0
or TC2 respectively). The odd-numbered partner (TC1 or TC3 respectively) will act as slave, and
the Slave bit in the Status register (STATUS.SLAVE) will be set. The register values of a slave will
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not reflect the registers of the 32-bit counter. Writing to any of the slave registers will not affect the
32-bit counter. Normal access to the slave COUNT and CCx registers is not allowed.
35.6.2.5. Counter Operations
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at
each TC clock input (CLK_TC_CNT). A counter clear or reload marks the end of the current counter cycle
and the start of a new one.
The counting direction is set by the Direction bit in the Control B register (CTRLB.DIR). If this bit is zero
the counter is counting up, and counting down if CTRLB.DIR=1. The counter will count up or down for
each tick (clock or event) until it reaches TOP or ZERO. When it is counting up and TOP is reached, the
counter will be set to zero at the next tick (overflow) and the Overflow Interrupt Flag in the Interrupt Flag
Status and Clear register (INTFLAG.OVF) will be set. When it is counting down, the counter is reloaded
with the TOP value when ZERO is reached (underflow), and INTFLAG.OVF is set.
INTFLAG.OVF can be used to trigger an interrupt, a DMA request, or an event. An overflow/underflow
occurrence (i.e. a compare match with TOP/ZERO) will stop counting if the One-Shot bit in the Control B
register is set (CTRLBSET.ONESHOT).
It is possible to change the counter value (by writing directly in the COUNT register) even when the
counter is running. When starting the TC, the COUNT value will be either ZERO or TOP (depending on
the counting direction set by CTRLBSET.DIR or CTRLBCLR.DIR), unless a different value has been
written to it, or the TC has been stopped at a value other than ZERO. The write access has higher priority
than count, clear, or reload. The direction of the counter can also be changed during normal operation.
See also the figure below.
Figure 35-3. Counter Operation
Period (T)
Direction Change
COUNT written
MAX
"reload" update
"clear" update
COUNT
TOP
ZERO
DIR
Due to asynchronous clock domains, the internal counter settings are written when the synchronization is
complete. Normal operation must be used when using the counter as timer base for the capture channels.
Stop Command and Event Action
A Stop command can be issued from software by using Command bits in the Control B Set register
(CTRLBSET.CMD = 0x2, STOP). When a Stop is detected while the counter is running, the counter will
be loaded with the starting value (ZERO or TOP, depending on direction set by CTRLBSET.DIR or
CTRLBCLR.DIR). All waveforms are cleared and the Stop bit in the Status register is set
(STATUS.STOP).
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Re-Trigger Command and Event Action
A re-trigger command can be issued from software by writing the Command bits in the Control B Set
register (CTRLBSET.CMD = 0x1, RETRIGGER), or from event when a re-trigger event action is
configured in the Event Control register (EVCTRL.EVACT = 0x1, RETRIGGER).
When the command is detected during counting operation, the counter will be reloaded or cleared,
depending on the counting direction (CTRLBSET.DIR or CTRLBCLR.DIR). When the re-trigger command
is detected while the counter is stopped, the counter will resume counting from the current value in the
COUNT register.
Note: When a re-trigger event action is configured in the Event Action bits in the Event Control register
(EVCTRL.EVACT=0x1, RETRIGGER), enabling the counter will not start the counter. The counter will
start on the next incoming event and restart on corresponding following event.
Count Event Action
The TC can count events. When an event is received, the counter increases or decreases the value,
depending on direction settings (CTRLBSET.DIR or CTRLBCLR.DIR). The count event action can be
selected by the Event Action bit group in the Event Control register (EVCTRL.EVACT=0x2, COUNT).
Start Event Action
The TC can start counting operation on an event when previously stopped. In this configuration, the event
has no effect if the counter is already counting. When the peripheral is enabled, the counter operation
starts when the event is received or when a re-trigger software command is applied.
The Start TC on Event action can be selected by the Event Action bit group in the Event Control register
(EVCTRL.EVACT=0x3, START).
35.6.2.6. Compare Operations
By default, the Compare/Capture channel is configured for compare operations.
When using the TC and the Compare/Capture Value registers (CCx) for compare operations, the counter
value is continuously compared to the values in the CCx registers. This can be used for timer or for
waveform operation.
The Channel x Compare Buffer (CCBUFx) registers provide double buffer capability. The double buffering
synchronizes the update of the CCx register with the buffer value at the UPDATE condition or a forced
update command (CTRLBSET.CMD=UPDATE). For further details, refer to Double Buffering. The
synchronization prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free
output.
Waveform Output Operations
The compare channels can be used for waveform generation on output port pins. To make the waveform
available on the connected pin, the following requirements must be fulfilled:
1. Choose a waveform generation mode in the Waveform Generation Operation bit in Waveform
register (WAVE.WAVEGEN).
2. Optionally invert the waveform output WO[x] by writing the corresponding Output Waveform x Invert
Enable bit in the Driver Control register (DRVCTRL.INVENx).
3. Configure the pins with the I/O Pin Controller. Refer to PORT - I/O Pin Controller for details.
The counter value is continuously compared with each CCx value. On a comparison match, the Match or
Capture Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the
next zero-to-one transition of CLK_TC_CNT (see Normal Frequency Operation). An interrupt/and or event
can be generated on comparison match if enabled. The same condition generates a DMA request.
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There are four waveform configurations for the Waveform Generation Operation bit group in the
Waveform register (WAVE.WAVEGEN). This will influence how the waveform is generated and impose
restrictions on the top value. The configurations are:
•
Normal frequency (NFRQ)
•
Match frequency (MFRQ)
•
Normal pulse-width modulation (NPWM)
•
Match pulse-width modulation (MPWM)
When using NPWM or NFRQ configuration, the TOP will be determined by the counter resolution. In 8-bit
counter mode, the Period register (PER) is used as TOP, and the TOP can be changed by writing to the
PER register. In 16- and 32-bit counter mode, TOP is fixed to the maximum (MAX) value of the counter.
Normal Frequency Generation (NFRQ)
For Normal Frequency Generation, the period time (T) is controlled by the period register (PER) for 8-bit
counter mode and MAX for 16- and 32-bit mode. The waveform generation output (WO[x]) is toggled on
each compare match between COUNT and CCx, and the corresponding Match or Capture Channel x
Interrupt Flag (INTFLAG.MCx) will be set.
Figure 35-4. Normal Frequency Operation
Period (T)
Direction Change
COUNT Written
MAX
COUNT
"reload" update
"clear" update
"match"
TOP
CCx
ZERO
WO[x]
Match Frequency Generation (MFRQ)
For Match Frequency Generation, the period time (T) is controlled by the CC0 register instead of PER or
MAX. WO[0] toggles on each update condition.
Figure 35-5. Match Frequency Operation
Period (T)
Direction Change
COUNT Written
MAX
"reload" update
"clear" update
COUNT
CC0
ZERO
WO[0]
Normal Pulse-Width Modulation Operation (NPWM)
NPWM uses single-slope PWM generation.
For single-slope PWM generation, the period time (T) is controlled by the TOP value, and CCx controls
the duty cycle of the generated waveform output. When up-counting, the WO[x] is set at start or compare
match between the COUNT and TOP values, and cleared on compare match between COUNT and CCx
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register values. When down-counting, the WO[x] is cleared at start or compare match between the
COUNT and ZERO values, and set on compare match between COUNT and CCx register values.
The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform:
�PWM_SS =
log(TOP+1)
log(2)
�PWM_SS =
�GCLK_TC
N(TOP+1)
The PWM frequency (fPWM_SS) depends on TOP value and the peripheral clock frequency (fGCLK_TCC),
and can be calculated by the following equation:
Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).
Match Pulse-Width Modulation Operation (MPWM)
In MPWM, the output of WO[1] is depending on CC1 as shown in the figure below. On on every overflow/
underflow, a one-TC-clock-cycle negative pulse is put out on WO[0] (not shown in the figure).
Figure 35-6. Match PWM Operation
Period(T)
CCx= Zero
CCx= TOP
" clear" update
" match"
MAX
CC0
COUNT
CC1
ZERO
WO[1]
The table below shows the update counter and overflow event/interrupt generation conditions in different
operation modes.
Table 35-3. Counter Update and Overflow Event/interrupt Conditions in TC
Name
Operation
TOP
Update
Output Waveform
OVFIF/Event
On Match
On Update Up
Down
NFRQ
Normal
Frequency
PER
TOP/
ZERO
Toggle
Stable
TOP
ZERO
MFRQ
Match
Frequency
CC0
TOP/
ZERO
Toggle
Stable
TOP
ZERO
NPWM
SinglePER
slope PWM
TOP/
ZERO
See description above.
TOP
ZERO
MPWM
SingleCC0
slope PWM
TOP/
ZERO
Toggle
TOP
ZERO
Toggle
Related Links
PORT: IO Pin Controller on page 455
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35.6.2.7. Double Buffering
The Compare Channels (CCx) registers, and the Period (PER) register in 8-bit mode are double buffered.
Each buffer register has a buffer valid bit (CCBUFVx or PERBUFV) in the STATUS register, which
indicates that the buffer register contains a new valid value that can be copied into the corresponding
register. As long as the respective buffer valid status flag (PERBUFV or CCBUFVx) are set to '1', related
syncbusy bits are set (SYNCBUSY.PER or SYNCBUSY.CCx), a write to the respective PER/PERBUF or
CCx/CCBUFx registers will generate a PAC error, and access to the respective PER or CCx register is
invalid.
When the buffer valid flag bit in the STATUS register is '1' and the Lock Update bit in the CTRLB register
is set to '0', (writing CTRLBCLR.LUPD to '1'), double buffering is enabled: the data from buffer registers
will be copied into the corresponding register under hardware UPDATE conditions, then the buffer valid
flags bit in the STATUS register are automatically cleared by hardware.
Note: The software update command (CTRLBSET.CMD=0x3) is acting independently of the LUPD
value.
A compare register is double buffered as in the following figure.
Figure 35-7. Compare Channel Double Buffering
"write enable"
CCBUFVx
UPDATE
"data write"
EN
CCBUFx
EN
CCx
COUNT
=
"match"
Both the registers (PER/CCx) and corresponding buffer registers (PERBUF/CCBUFx) are available in the
I/O register map, and the double buffering feature is not mandatory. The double buffering is disabled by
writing a '1' to CTRLBSET.LUPD.
Note: In NFRQ, MFRQ or PWM down-counting counter mode (CTRLBSET.DIR=1), when double buffering
is enabled (CTRLBCLR.LUPD=1), PERBUF register is continously copied into the PER independently of
update conditions.
Changing the Period
The counter period can be changed by writing a new TOP value to the Period register (PER or CC0,
depending on the waveform generation mode), any period update on registers (PER or CCx) is effective
after the synchronization delay, whatever double buffering enabling is.
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Figure 35-8. Unbuffered Single-Slope Up-Counting Operation
Counter Wraparound
MAX
"clear" update
"write"
COUNT
ZERO
New TOP written to
PER that is higher
than current COUNT
New TOP written to
PER that is lower
than current COUNT
A counter wraparound can occur in any operation mode when up-counting without buffering, see Figure
35-8 Unbuffered Single-Slope Up-Counting Operation.
COUNT and TOP are continuously compared, so when a new TOP value that is lower than current
COUNT is written to TOP, COUNT will wrap before a compare match.
Figure 35-9. Unbuffered Single-Slope Down-Counting Operation
MAX
"reload" update
"write"
COUNT
ZERO
New TOP written to
PER that is higher
than current COUNT
New TOP written to
PER that is lower
than current COUNT
When double buffering is used, the buffer can be written at any time and the counter will still maintain
correct operation. The period register is always updated on the update condition, as shown in Figure
35-10 Changing the Period Using Buffering. This prevents wraparound and the generation of odd
waveforms.
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Figure 35-10. Changing the Period Using Buffering
MAX
" clear" update
" write"
COUNT
ZERO
New TOP written to
PER that is higher
than currentCOUNT
New TOP written to
PER that is lower
than currentCOUNT
35.6.2.8. Capture Operations
To enable and use capture operations, the corresponding Capture Channel x Enable bit in the Control A
register (CTRLA.CAPTENx) must be written to '1'.
A capture trigger can be provided by input event line TC_EV or by asynchronous IO pin WO[x] for each
capture channel or by a TC event. To enable the capture from input event line, Event Input Enable bit in
the Event Control register (EVCTRL.TCEI) must be written to '1'. To enable the capture from the IO pin,
the Capture On Pin x Enable bit in CTRLA register (CTRLA.COPENx) must be written to '1'.
Note: The RETRIGGER, COUNT and START event actions are available only on an event from the
Event System.
By default, a capture operation is done when a rising edge is detected on the input signal. Capture on
falling edge is available, its activation is depending on the input source:
•
When the channel is used with a IO pin, write a '1' to the corresponding Invert Enable bit in the
Drive Control register (DRVCTRL.INVENx).
•
When the channel is counting events from the Event System, write a '1' to the TC Event Input Invert
Enable bit in Event Control register (EVCTRL.TCINV).
For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or
read, any content in CCBUFx is transferred to CCx. The buffer valid flag is passed to set the CCx
interrupt flag (IF) and generate the optional interrupt, event or DMA request. CCBUFx register value can't
be read, all captured data must be read from CCx register.
Figure 35-11. Capture Double Buffering
"capture"
COUNT
BV
EN
CCBx
IF
EN
CCx
"INT/DMA
request"
data read
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For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or
read, any content in CCBUFx is transferred to CCx. The buffer valid flag is passed to set the CCx
interrupt flag (IF) and generate the optional interrupt, event or DMA request. CCBUFx register value can't
be read, all captured data must be read from CCx register.
Event Capture Action
The compare/capture channels can be used as input capture channels to capture events from the Event
System or from the corresponding IO pin, and give them a timestamp. The following figure shows four
capture events for one capture channel.
Figure 35-12. Input Capture Timing
events
TOP
COUNT
ZERO
Capture 0
Capture 1
Capture 2
Capture 3
The TC can detect capture overflow of the input capture channels: When a new capture event is detected
while the Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and
INTFLAG.ERR will be set.
Period and Pulse-Width (PPW) Capture Action
The TC can perform two input captures and restart the counter on one of the edges. This enables the TC
to measure the pulse width and period and to characterize the frequency f and duty cycle of an input
signal:
�=
1
�
dutyCycle =
��
�
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Figure 35-13. PWP Capture
Period (T)
external signal
Pulsewitdh (tp)
events
MAX
"capture"
COUNT
ZERO
CC0
CC1
CC0
CC1
Selecting PWP in the Event Action bit group in the Event Control register (EVCTRL.EVACT) enables the
TC to perform one capture action on the rising edge and the other one on the falling edge. The period T
will be captured into CC1 and the pulse width tp in CC0. EVCTRL.EVACT=PPW (period and pulsewidth)offers identical functionality, but will capture T into CC0 and tp into CC1.
The TC Event Input Invert Enable bit in the Event Control register (EVCTRL.TCINV) is used to select
whether the wraparound should occur on the rising edge or the falling edge. If EVCTRL.TCINV=1, the
wraparound will happen on the falling edge. This also be for DRVCTRL.INVENx if pin capture is enabled.
The TC can detect capture overflow of the input capture channels: When a new capture event is detected
while the Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and
INTFLAG.ERR will be set.
Note: The corresponding capture is working only if the channel is enabled in capture mode
(CTRLA.CAPTENx=1). If not, the capture action is ignored and the channel is enabled in compare mode
of operation. Consequently, both channels must be enabled in order to fully characterize the input.
Pulse-Width Capture Action
The TC performs the input capture on the falling edge of the input signal. When the edge is detected, the
counter value is cleared and the TC stops counting. When a rising edge is detected on the input signal,
the counter restarts the counting operation. To enable the operation on opposite edges, the input signal to
capture must be inverted (refer to DRVCTRL.INVEN or EVCTRL.TCEINV).
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Figure 35-14. Pulse-Width Capture on Channel 0
external signal
Pulsewitdh (tp)
events
MAX
"capture"
"restart"
COUNT
ZERO
CC0
CC0
The TC can detect capture overflow of the input capture channels: When a new capture event is detected
while the Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and
INTFLAG.ERR will be set.
35.6.3.
Additional Features
35.6.3.1. One-Shot Operation
When one-shot is enabled, the counter automatically stops on the next counter overflow or underflow
condition. When the counter is stopped, the Stop bit in the Status register (STATUS.STOP) is
automatically set and the waveform outputs are set to zero.
One-shot operation is enabled by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT), and disabled by writing a '1' to CTRLBCLR.ONESHOT. When enabled, the TC
will count until an overflow or underflow occurs and stops counting operation. The one-shot operation can
be restarted by a re-trigger software command, a re-trigger event, or a start event. When the counter
restarts its operation, STATUS.STOP is automatically cleared.
35.6.3.2. Time-Stamp Capture
This feature is enabled when the Capture Time Stamp (STAMP) Event Action in Event Control register
(EVCTRL.EVACT) is selected. The counter TOP value must be smaller than MAX.
When a capture event is detected, the COUNT value is copied into the corresponding Channel x
Compare/Capture Value (CCx) register. In case of an overflow, the MAX value is copied into the
corresponding CCx register.
When a valid captured value is present in the capture channel register, the corresponding Capture
Channel x Interrupt Flag (INTFLAG.MCx) is set.
The timer/counter can detect capture overflow of the input capture channels: When a new capture event
is detected while the Capture Channel interrupt flag (INTFLAG.MCx) is still set, the new time-stamp will
not be stored and INTFLAG.ERR will be set.
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Figure 35-15. Time-Stamp
Capture Events
MAX
TOP
"capture"
"overflow"
COUNT
ZERO
CCx Value
35.6.4.
COUNT
COUNT
TOP
COUNT
MAX
DMA Operation
The TC can generate the following DMA requests:
•
Overflow (OVF): the request is set when an update condition (overflow, underflow or re-trigger) is
detected, the request is cleared by hardware on DMA acknowledge.
•
Match or Capture Channel x (MCx): for a compare channel, the request is set on each compare
match detection, the request is cleared by hardware on DMA acknowledge. For a capture channel,
the request is set when valid data is present in the CCx register, and cleared when CCx register is
read.
35.6.5.
Interrupts
The TC has the following interrupt sources:
•
•
•
Overflow/Underflow (OVF)
Match or Capture Channel x (MCx)
Capture Overflow Error (ERR)
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG) is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable
Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable
Clear register (INTENCLR).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or
the TC is reset. See INTFLAG for details on how to clear interrupt flags.
The TC has one common interrupt request line for all the interrupt sources. The user must read the
INTFLAG register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested
Vector Interrupt Controller for details.
Related Links
Nested Vector Interrupt Controller on page 43
35.6.6.
Events
The TC can generate the following output events:
•
•
Overflow/Underflow (OVF)
Match or Capture Channel x (MCx)
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Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.MCEOx) enables the
corresponding output event. The output event is disabled by writing EVCTRL.MCEOx=0.
One of the following event actions can be selected by the Event Action bit group in the Event Control
register (EVCTRL.EVACT):
•
Disable event action (OFF)
•
Start TC (START)
•
Re-trigger TC (RETRIGGER)
•
Count on event (COUNT)
•
•
•
Capture time stamp (STAMP)
Capture Period (PPW and PWP)
Capture Pulse Width (PW)
Writing a '1' to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events
to the TC. Writing a '0' to this bit disables input events to the TC. The TC requires only asynchronous
event inputs. For further details on how configuring the asynchronous events, refer to EVSYS - Event
System.
Related Links
EVSYS – Event System on page 487
35.6.7.
Sleep Mode Operation
The TC can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit
in the Control A register (CTRLA.RUNSTDBY) must be '1'. This peripheral can wake up the device from
any sleep mode using interrupts or perform actions through the Event System.
If the On Demand bit in the Control A register (CTRLA.ONDEMAND) is written to '1', the module stops
requesting its peripheral clock when the STOP bit in STATUS register (STATUS.STOP) is set to '1'. When
a re-trigger or start condition is detected, the TC requests the clock before the operation starts.
35.6.8.
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
•
•
Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE)
Capture Channel Buffer Valid bit in STATUS register (STATUS.CCBUFVx)
The following registers are synchronized when written:
•
•
•
•
Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
Count Value register (COUNT)
Period Value and Period Buffer Value registers (PER and PERBUF)
Channel x Compare/Capture Value and Channel x Compare/Capture Buffer Value registers (CCx
and CCBUFx)
The following registers are synchronized when read:
•
Count Value register (COUNT): synchronization is done on demand through READSYNC command
(CTRLBSET.CMD).
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
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Required read-synchronization is denoted by the "Read-Synchronized" property in the register
description.
35.7.
Register Summary
Table 35-4. Register Summary – 8-bit Mode
Offset
Name
Bit Pos.
0x00
7:0
0x01
15:8
0x02
CTRLA
0x03
ONDEMAND RUNSTDBY
23:16
COPEN1
ENABLE
SWRST
PRESCALER[2:0]
COPEN0
CAPTEN1
CAPTEN0
LUPD
DIR
LUPD
DIR
31:24
CTRLBCLR
7:0
CMD[2:0]
0x05
CTRLBSET
7:0
CMD[2:0]
0x07
MODE[1:0]
ALOCK
0x04
0x06
PRESCSYNC[1:0]
EVCTRL
ONESHOT
ONESHOT
7:0
TCEI
TCINV
EVACT[2:0]
15:8
MCEO1
MCEO0
OVFEO
0x08
INTENCLR
7:0
MC1
MC0
ERR
OVF
0x09
INTENSET
7:0
MC1
MC0
ERR
OVF
0x0A
INTFLAG
7:0
MC1
MC0
ERR
OVF
CCBUFV1
CCBUFV0
SLAVE
STOP
0x0B
STATUS
7:0
0x0C
WAVE
7:0
0x0D
DRVCTRL
7:0
0x0E
Reserved
0x0F
DBGCTRL
7:0
0x11
15:8
SYNCBUSY
0x13
WAVEGEN[1:0]
INVEN1
7:0
0x10
0x12
PERBUFV
INVEN0
DBGRUN
CC1
CC0
PER
COUNT
STATUS
CTRLB
ENABLE
SWRST
23:16
31:24
0x14
COUNT
7:0
COUNT[7:0]
0x15
Reserved
0x16
Reserved
0x17
Reserved
0x18
Reserved
0x19
Reserved
0x1A
Reserved
0x1B
PER
7:0
PER[7:0]
0x1C
CC0
7:0
CC[7:0]
0x1D
CC1
7:0
CC[7:0]
0x1E
Reserved
0x1F
Reserved
0x20
Reserved
0x21
Reserved
0x22
Reserved
0x23
Reserved
0x24
Reserved
0x25
Reserved
0x26
Reserved
0x27
Reserved
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Offset
Name
0x28
Reserved
0x29
Reserved
0x2A
Reserved
Bit Pos.
0x2B
Reserved
0x2C
Reserved
0x2D
Reserved
0x2E
Reserved
0x2F
PERBUF
7:0
PERBUF[7:0]
0x30
CCBUF0
7:0
CCBUF[7:0]
0x31
CCBUF1
7:0
CCBUF[7:0]
0x32
Reserved
0x33
Reserved
Table 35-5. Register Summary – 16-bit Mode
Offset
Name
0x00
0x01
0x02
Bit Pos.
7:0
CTRLA
0x03
ONDEMAND RUNSTDBY
PRESCSYNC[1:0]
MODE[1:0]
15:8
ALOCK
23:16
COPEN1
ENABLE
SWRST
PRESCALER[2:0]
COPEN0
CAPTEN1
CAPTEN0
31:24
0x04
CTRLBCLR
7:0
CMD[2:0]
ONESHOT
LUPD
DIR
0x05
CTRLBSET
7:0
CMD[2:0]
ONESHOT
LUPD
DIR
0x06
0x07
EVCTRL
7:0
TCEI
TCINV
15:8
MCEO1
MCEO0
EVACT[2:0]
OVFEO
0x08
INTENCLR
7:0
MC1
MC0
ERR
OVF
OVF
0x09
INTENSET
7:0
MC1
MC0
ERR
0x0A
INTFLAG
7:0
MC1
MC0
ERR
OVF
0x0B
STATUS
7:0
CCBUFV1
CCBUFV0
SLAVE
STOP
0x0C
WAVE
0x0D
DRVCTRL
0x0E
Reserved
0x0F
DBGCTRL
0x10
0x11
0x12
SYNCBUSY
0x15
COUNT
0x16
Reserved
Reserved
0x18
Reserved
0x19
Reserved
0x1A
Reserved
0x1B
Reserved
0x1C
0x1E
0x1F
INVEN0
DBGRUN
CC1
CC0
COUNT
STATUS
CTRLB
ENABLE
SWRST
15:8
23:16
31:24
0x17
0x1D
INVEN1
7:0
7:0
0x13
0x14
WAVEGEN[1:0]
7:0
CC0
CC1
7:0
COUNT[7:0]
15:8
COUNT[15:8]
7:0
CC[7:0]
15:8
CC[15:8]
7:0
CC[7:0]
15:8
CC[5:8]
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Offset
Name
0x20
Reserved
0x21
Reserved
0x22
Reserved
0x23
Reserved
0x24
Reserved
0x25
Reserved
0x26
Reserved
0x27
Reserved
0x28
Reserved
0x29
Reserved
0x2A
Reserved
0x2B
Reserved
0x2C
Reserved
0x2D
Reserved
0x2E
Reserved
0x2F
Reserved
0x30
0x31
0x32
0x33
CCBUF0
CCBUF1
0x34
Reserved
0x35
Reserved
0x36
Reserved
0x37
Reserved
Bit Pos.
7:0
CCBUF[7:0]
15:8
CCBUF[15:8]
7:0
CCBUF[7:0]
15:8
CCBUF[5:8]
Table 35-6. Register Summary – 32-bit Mode
Offset
Name
Bit Pos.
0x00
7:0
0x01
15:8
0x02
CTRLA
0x03
ONDEMAND RUNSTDBY
23:16
COPEN1
ENABLE
SWRST
PRESCALER[2:0]
COPEN0
CAPTEN1
CAPTEN0
LUPD
DIR
LUPD
DIR
31:24
CTRLBCLR
7:0
CMD[2:0]
0x05
CTRLBSET
7:0
CMD[2:0]
0x07
MODE[1:0]
ALOCK
0x04
0x06
PRESCSYNC[1:0]
EVCTRL
ONESHOT
ONESHOT
7:0
TCEI
TCINV
15:8
MCEO1
MCEO0
EVACT[2:0]
OVFEO
0x08
INTENCLR
7:0
MC1
MC0
ERR
OVF
0x09
INTENSET
7:0
MC1
MC0
ERR
OVF
0x0A
INTFLAG
7:0
MC1
MC0
ERR
OVF
0x0B
STATUS
7:0
CCBUFV1
CCBUFV0
SLAVE
STOP
0x0C
WAVE
7:0
0x0D
DRVCTRL
7:0
0x0E
Reserved
0x0F
DBGCTRL
7:0
0x11
15:8
0x13
SYNCBUSY
INVEN1
7:0
0x10
0x12
WAVEGEN[1:0]
INVEN0
DBGRUN
CC1
CC0
COUNT
STATUS
CTRLB
ENABLE
SWRST
23:16
31:24
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Offset
Name
Bit Pos.
0x14
7:0
COUNT[7:0]
0x15
15:8
COUNT[15:8]
23:16
COUNT[23:16]
31:24
COUNT[31:24]
0x16
COUNT
0x17
0x18
Reserved
0x19
Reserved
0x1A
Reserved
0x1B
Reserved
0x1C
7:0
CC[7:0]
0x1D
15:8
CC[15:8]
23:16
CC[23:16]
0x1F
31:24
CC[31:24]
0x20
7:0
CC[7:0]
0x1E
0x21
0x22
CC0
CC1
0x23
0x24
Reserved
0x25
Reserved
0x26
Reserved
0x27
Reserved
0x28
Reserved
0x29
Reserved
0x2A
Reserved
0x2B
Reserved
0x2C
Reserved
0x2D
Reserved
0x2E
Reserved
0x2F
Reserved
0x30
0x31
0x32
CCBUF0
0x33
15:8
CC[15:8]
23:16
CC[23:16]
31:24
CC[31:24]
7:0
CCBUF[7:0]
15:8
CCBUF[15:8]
23:16
CCBUF[23:16]
31:24
CCBUF[31:24]
0x34
7:0
CCBUF[7:0]
0x35
15:8
CCBUF[15:8]
23:16
CCBUF[23:16]
31:24
CCBUF[31:24]
0x36
CCBUF1
0x37
0x38
Reserved
0x39
Reserved
0x3A
Reserved
0x3B
Reserved
0x3C
Reserved
0x3D
Reserved
0x3E
Reserved
0x3F
Reserved
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35.8.
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "WriteSynchronized" or the "Read-Synchronized" property in each individual register description. For details,
refer to Synchronization.
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
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35.8.1.
Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized, Enable-Protected
Bit
31
30
23
22
29
28
27
26
19
18
25
24
Access
Reset
Bit
Access
Reset
Bit
15
14
21
20
17
16
COPEN1
COPEN0
CAPTEN1
CAPTEN0
R/W
R/W
R/W
R/W
0
0
0
0
13
12
9
8
11
10
ALOCK
Access
R/W
R/W
R/W
0
0
0
0
Reset
Bit
7
6
ONDEMAND
RUNSTDBY
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Access
Reset
5
PRESCALER[2:0]
R/W
4
3
PRESCSYNC[1:0]
2
1
0
ENABLE
SWRST
R/W
R/W
R/W
0
0
0
MODE[1:0]
Bit 11 – ALOCK: Auto Lock
When this bit is set, Lock bit update (LUPD) is set to '1' on each overflow/underflow or re-trigger event.
This bit is not synchronized.
Value
Description
0
The LUPD bit is not affected on overflow/underflow, and re-trigger event.
1
The LUPD bit is set on each overflow/underflow or re-trigger event.
Bits 10:8 – PRESCALER[2:0]: Prescaler
These bits select the counter prescaler factor.
These bits are not synchronized.
Value
Name
Description
0x0
DIV1
Prescaler: GCLK_TC
0x1
DIV2
Prescaler: GCLK_TC/2
0x2
DIV4
Prescaler: GCLK_TC/4
0x3
DIV8
Prescaler: GCLK_TC/8
0x4
DIV16
Prescaler: GCLK_TC/16
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Value
Name
Description
0x5
DIV64
Prescaler: GCLK_TC/64
0x6
DIV256
Prescaler: GCLK_TC/256
0x7
DIV1024
Prescaler: GCLK_TC/1024
Bit 7 – ONDEMAND: Clock On Demand
This bit selects the clock requirements when the TC is stopped.
In standby mode, if the Run in Standby bit (CTRLA.RUNSTDBY) is '0', ONDEMAND is forced to '0'.
This bit is not synchronized.
Value
Description
0
The On Demand is disabled. If On Demand is disabled, the TC will continue to request the
clock when its operation is stopped (STATUS.STOP=1).
1
The On Demand is enabled. When On Demand is enabled, the stopped TC will not request
the clock. The clock is requested when a software re-trigger command is applied or when an
event with start/re-trigger action is detected.
Bit 6 – RUNSTDBY: Run in Standby
This bit is used to keep the TC running in standby mode.
This bit is not synchronized.
Value
Description
0
The TC is halted in standby.
1
The TC continues to run in standby.
Bits 5:4 – PRESCSYNC[1:0]: Prescaler and Counter Synchronization
These bits select whether the counter should wrap around on the next GCLK_TCx clock or the next
prescaled GCLK_TCx clock. It also makes it possible to reset the prescaler.
These bits are not synchronized.
Value
Name
Description
0x0
GCLK
Reload or reset the counter on next generic clock
0x1
PRESC
Reload or reset the counter on next prescaler clock
0x2
RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter
0x3
-
Reserved
Bits 3:2 – MODE[1:0]: Timer Counter Mode
These bits select the counter mode.
These bits are not synchronized.
Value
Name
Description
0x0
COUNT16
Counter in 16-bit mode
0x1
COUNT8
Counter in 8-bit mode
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Value
Name
Description
0x2
COUNT32
Counter in 32-bit mode
0x3
-
Reserved
Bit 1 – ENABLE: Enable
Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately, and the ENABLE
Synchronization Busy bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set.
SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value
Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST: Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will
be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation
will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
Bits 20, 21 – COPEN0, COPEN1: Capture On Pin x Enable [x = 1..0]
This bit selects the trigger source for capture operation, either events or I/O pin input.
Value
Description
0
Event from Event System is selected as trigger source for capture operation on channel x.
1
I/O pin is selected as trigger source for capture operation on channel x.
Bits 16, 17 – CAPTEN0, CAPTEN1: Capture Channel x Enable [x = 1..0]
These bits are used to select whether channel x is a capture or a compare channel.
These bits are not synchronized.
Value
Description
0
CAPTENx disables capture on channel x.
1
CAPTENx enables capture on channel x.
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35.8.2.
Control B Clear
This register allows the user to clear bits in the CTRLB register without doing a read-modify-write
operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET).
Name: CTRLBCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
Bit
7
6
5
4
3
CMD[2:0]
Access
Reset
2
1
0
ONESHOT
LUPD
DIR
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 7:5 – CMD[2:0]: Command
These bits are used for software control of the TC. The commands are executed on the next prescaled
GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as
zero.
Writing 0x0 to these bits has no effect.
Writing a '1' to any of these bits will clear the pending command.
Bit 2 – ONESHOT: One-Shot on Counter
This bit controls one-shot operation of the TC.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable one-shot operation.
Value
Description
0
The TC will wrap around and continue counting on an overflow/underflow condition.
1
The TC will wrap around and stop on the next underflow/overflow condition.
Bit 1 – LUPD: Lock Update
This bit controls the update operation of the TC buffered registers.
When CTRLB.LUPD is set, no update of the buffered registers is performed, even though an UPDATE
condition has occurred. Locking the update ensures that all buffer registers are valid before an update is
performed.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the LUPD bit.
Value
Description
0
The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on
counter update condition.
1
The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER
registers.
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Bit 0 – DIR: Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
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35.8.3.
Control B Set
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation.
Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Name: CTRLBSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection, Read-synchronized, Write-Synchronized
Bit
7
6
5
4
3
CMD[2:0]
Access
Reset
2
1
0
ONESHOT
LUPD
DIR
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 7:5 – CMD[2:0]: Command
These bits are used for software control of the TC. The commands are executed on the next prescaled
GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as
zero.
Writing 0x0 to these bits has no effect.
Writing a value different from 0x0 to these bits will issue a command for execution.
Value