AT91SAM9G20-EK Evaluation Board .................................................................................................................... User Guide 6413C–ATARM–18-Feb-09 1-2 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide Table of Contents Section 1 Overview .................................................................................................................... 1-1 1.1 Scope................................................................................................................................. 1-1 1.2 Deliverables ....................................................................................................................... 1-1 1.3 AT91SAM9G20-EK Evaluation Board ............................................................................... 1-1 Section 2 Setting Up the AT91SAM9G20-EK Board.................................................................. 2-1 2.1 Electrostatic Warning ......................................................................................................... 2-1 2.2 Requirements..................................................................................................................... 2-1 2.3 Layout ................................................................................................................................ 2-2 2.4 Powering Up the Board...................................................................................................... 2-4 2.5 Backup Power Supply........................................................................................................ 2-4 2.6 Getting Started................................................................................................................... 2-4 2.7 AT91SAM9G20-EK Block Diagram ................................................................................... 2-5 Section 3 Board Description....................................................................................................... 3-1 3.1 AT91SAM9G20 Microcontroller ......................................................................................... 3-1 3.2 AT91SAM9G20 Block Diagram ......................................................................................... 3-4 3.3 Microcontroller ................................................................................................................... 3-5 3.4 Memory .............................................................................................................................. 3-5 3.5 Clock Circuitry.................................................................................................................... 3-5 3.6 Reset Circuitry ................................................................................................................... 3-5 3.7 Shutdown Controller .......................................................................................................... 3-5 3.8 Power Supply Circuitry....................................................................................................... 3-5 3.9 Remote Communication .................................................................................................... 3-5 3.10 Audio Stereo Interface ....................................................................................................... 3-6 3.11 User Interface .................................................................................................................... 3-6 3.12 Debug Interface ................................................................................................................. 3-6 3.13 Expansion Slot ................................................................................................................... 3-6 3.14 PIO Usage ......................................................................................................................... 3-7 Section 4 Configuration .............................................................................................................. 4-1 4.1 Jumpers ............................................................................................................................. 4-1 4.2 JTAG/ICE........................................................................................................................... 4-2 AT91SAM9G20-EK Evaluation Board User Guide i 6413C–ATARM–18-Feb-09 Table of Contents (Continued) 4.3 Microcontroller Clock ......................................................................................................... 4-2 4.4 Memory .............................................................................................................................. 4-2 4.5 Ethernet ............................................................................................................................. 4-3 4.6 Miscellaneous .................................................................................................................... 4-3 Section 5 Schematics................................................................................................................. 5-1 5.1 Schematics ........................................................................................................................ 5-1 Section 6 Errata.......................................................................................................................... 6-1 6.1 Wrong Silkscreen of BB and 1.0V on the Board ................................................................ 6-1 6.2 Choice of an Oscillator Capacitance.................................................................................. 6-1 6.3 SD Card Slots and Booting Capability ............................................................................... 6-1 Section 7 Revision History ......................................................................................................... 7-1 7.1 ii 6413C–ATARM–18-Feb-09 Revision History ................................................................................................................. 7-1 AT91SAM9G20-EK Evaluation Board User Guide Section 1 Overview 1.1 Scope The AT91SAM9G20-EK Evaluation Kit enables the evaluation of and code development for applications running on an AT91SAM9G20 device. This guide focuses on the AT91SAM9G20-EK board as an evaluation platform. The board supports the AT91SAM9G20 in a 217-ball LFBGA RoHS-compliant Package. 1.2 Deliverables The AT91SAM9G20-EK package contains the following items: 1.3 an AT91SAM9G20-EK board a universal input AC/DC power supply with US and Europe plug adapter one A/B-type USB cable one serial RS232 cable one RJ45 crossed Ethernet cable one CD-ROM that allows the user to begin evaluating the AT91 ARM® Thumb® 32-bit microcontroller quickly one 3V Lithium battery AT91SAM9G20-EK Evaluation Board The board is equipped with an AT91SAM9G20 microcontroller together with the following: 64 Mbytes of SDRAM memory 256 Mbytes of NAND Flash memory one Atmel® serial DataFlash® one Atmel TWI serial EEPROM one USB Device port interface two USB Host port interfaces one DBGU serial communication port one complete MODEM serial communication port one additional serial communication port with RTS/CTS handshake control JTAG/ICE debug interface one PHY Ethernet 100-base TX with three status LEDs one on-board Audio DAC one Power LED and one general-purpose LED AT91SAM9G20-EK Evaluation Board User Guide 1-1 6413C–ATARM–18-Feb-09 Overview two user-input push buttons one Wakeup-input push button one reset push button two DataFlash SD/MMC card slots four expansion connectors (PIOA, PIOB, PIOC, IMAGE SENSOR) one BGA-like EBI expansion footprint connector one Lithium Coin Cell Battery Retainer for 12 mm cell size 1-2 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide Section 2 Setting Up the AT91SAM9G20-EK Board 2.1 Electrostatic Warning The AT91SAM9G20-EK evaluation board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element. 2.2 Requirements In order to set up the AT91SAM9G20-EK evaluation board, the following items are needed: the AT91SAM9G20-EK evaluation board itself, AC/DC power adapter (5V at 2A), 2.1 mm by 5.5 mm. AT91SAM9G20-EK Evaluation Board User Guide 2-1 6413C–ATARM–18-Feb-09 C4 J2 C2 MN1 J16 J19 C3 C1 R70 R71 R77 R78 J3 R10 DS1 R81 R84 R25 C110 C111 C112 C113 R5 R7 K C11 J11 D1 C12 R163 R164 MN10 MN15 Q1 BP2 MN3 R11 R169 R9 Q2 C15 C14 R3 BP1 R167 R64 Q3 J28 C85 R168 R46 R156 R155 R47 R42 MN9 C82 J26 C105 5 MN12 C104 S5 R37 J23 1 J33 R158 C107 TP2 MN5 C47 J7 S2 C146 MN2 C16 J10 J9 R151 R150 C17 R15 C42 Y3 J4 BP3 C87 C25 R49 Y2 C99 TP6 TP5 C26 L3 C101 CR1 TP1 R165 R57 DS5 R108 J15 RR6 RR10 BP4 RR11 MN4 R56 J12 RR20 C90 R62 C94 R50 S8 C93 RR1 R166 J14 RR17 R28 J5 C123 C124 R87 C119 C103 R157 R160 C106 R154 R159 R94 R95 R104 C74 C71 C79 R32 C80 C77 RR21 R39 C83 C78 C81 C72 R31 C127 MN6B1 MN6A1 MN7 MN8 C122 MN14 1 C73 R38 R98 RR19 J34 Y1 J6 J8 R103 C70 L5 R105 L2 J20 R106 RR4 C24 R20 R18 C23 R43 R21 R45 R22 DS2 DS3 DS4 5 R96 J1 R26 C95 R153 R44 L4 C102 R124 R119 R120 R101 2-2 R107 6413C–ATARM–18-Feb-09 C121 TP3 5 C69 C68 C76 C75 C118 C84 J24 C117 C148 C114 MN13 C115 J18 R171 R170 TP7 1 TP4 J25 J31 Figure 2-1. C116 2.3 R86 R83 R85 R88 J17 Setting Up the AT91SAM9G20-EK Board Layout Top View AT91SAM9G20-EK Evaluation Board User Guide C134 C135 CR2 J35 R29 R35 R33 R41 R34 S6 R30 R176 R172 C125 R175 RR14 R174 R92 C49 C48 C31 C30 RR16 C39 C36 C22 S4 R59 C51 C50 RR18 C38 R27 C21 C27 C28 R60 R121 R134 C98 R51 R122 C37 RR9 C33 C46 MN11 R52 R54 C45 R130 C40 C43 RR8 R132 RR7 R118 C32 C44 S7 R133 C91 C92 R53 R58 C96 R61 R126 C88 C89 R65 R137 R24 R23 R109 R125 Y4 R136 R48 C139 C137 C18 C143 C142 R2 R128 C136 R12 L1 C145 C140 R68 R8 R6 R75 R72 R73 J13 C131 C132 R14 C86 R16 R63 R123 RR13 RR12 RR15 R55 R127 R135 R93 R173 R129 C41 C97 R131 C35 C34 R91 RR5 RR3 RR2 C138 R17 R19 C141 C144 AT91SAM9G20-EK Evaluation Board User Guide C133 R13 R162 R161 C147 C5 R4 R1 S3 C6 R82 F2 C109 R89 R90 R76 R74 R67 R66 F1 S1 C120 C108 Figure 2-2. C130 C126 Setting Up the AT91SAM9G20-EK Board Bottom View 6413C–ATARM–18-Feb-09 2-3 R69 R79 R80 Setting Up the AT91SAM9G20-EK Board 2.4 Powering Up the Board The AT91SAM9G20-EK requires 5V DC (±5%). DC power is supplied to the board via the 2.1 mm by 5.5 mm socket J1. Coaxial plug center positive standard. 2.5 Backup Power Supply The user can plug in a battery (3V Lithium Battery CR1225 or equivalent) in order to permanently power the backup part of the device. In this case, J10 configuration must be set in position 1, 2. Refer to Section 4.1 ”Jumpers”. 2.6 Getting Started The AT91SAM9G20-EK evaluation board is delivered with a CD-ROM containing all necessary information and step-by-step procedures for working with the most common development tools. 2-4 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide Setting Up the AT91SAM9G20-EK Board AT91SAM9G20-EK Block Diagram 2.7 AT91SAM9G20-EK Block Diagram Figure 2-3. POWER SUPPLY WM8731 01 - POWER SUPPLY DBGU SERIAL INTERFACES COM0 SHEET 2 PB9 SHDN PC1 PB18 PB17 PB16 PA23 PA24 PB3 SHEET 6 PB15 PB14 PB4 PB5 PB26 PB27 PB24 PB22 PB23 PB25 PC5 DDM DDP COM1 DEVICE HDMA HDPA PB6 PB7 PB28 PB29 HOST A HDMB HDPB NRST PA20 PA21 PB0 PA29 PA28 PA22 PA18 PA27 PA17 PA26 PA25 PA15 PA14 PA11 PA10 PA13 PA12 PA16 PA19 SHEET 5 HOST B 05 - COMMUNICATION RMII_MII ETHERNET 03 - RMII_MII ETHERNET PB9 PC1 PB18 PB17 PB16 PA23 PA24 PB3 PB15 PB14 PB4 PB5 PB26 PB27 PB24 PB22 PB23 PB25 PB6 PB7 PB28 PB29 PC5 PB[0..31] PIO PC[0..15] PB[0..31] PCK0 TD0 TF0 TK0 PA23/TWD PA24/TWCK SPI1_NPCS0 PB[0..31] DBGU_TXD DBGU_RXD PC[0..15] PIO DDM DDP HDMA HDPA ETXCK/REFCLK HDMB HDPB PA19 ETX3 ETX2 ETX1 ETX0 ETXEN PA[0..31] PA11 PA10 PA13 PA12 PA16 ERX3 ERX2 ERX1 ERX0 ERXCK ERXDV PA26 PA25 PA15 PA14 PA27 PA17 ETXER ERXER ECOL ECRS PA22 PA18 PA29 PA28 EMDC EMDIO PIO PB[0..31] PA20 PA21 PB0 NRST AT91SAM9G20-CU SHDN DDM DDP HDMA HDPA HDMB HDPB 02 - AT91SAM9G20-CU D[0..31] A[0..22] RAS CAS SDA10 SDW E SDCS_NCS1 SDCK SDCKE CFIOR_NBS1_NW R1 CFIOW _NBS3_NW R3 NANDOE NANDW E CFOE_NRD CFW E_NW E_NW R0 NCS0 NRST PA[0..31] PB[0..31] PC[0..15] VREFP AVDD AGND D[0..31] A[0..22] NCS0 NRST PA[0..31] PB[0..31] PC[0..15] PIO PIO MCDA0 MCDA1 MCDA2 MCDA3 MCCK MCCDA SPI0_MISO MCDB0 MCDB1 MCDB2 SPI0_NPCS0 MCDB3 MCCK SPI0_MOSI MCCDB SPI0_SPCK SPI0_NPCS1 TWCK TWD CFWE_NWE_NWR0 CFOE_NRD A[0..14] RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE A16 A17 NBS1 NBS3 PA8 D[0..15] A22 A21 NANDOE NANDWE PC14 PC13 PA6 PA9 PA10 PA11 PA8 PA7 PC2 PA0 PA5 PA4 PA3 PA1 PC9 PA2 PC11 NRST PA24 PA23 MEMORY A[0..14] D[0..31] RAS CAS SDA10 SDW E SDCS_NCS1 SDCK SDCKE CFIOR_NBS1_NW R1 CFIOW _NBS3_NW R3 A16 A17 CARD READER CARD READER (BOOT) A22 A21 NANDOE NANDW E PC14 PC13 D[0..15] PA6 PA9 PA10 PA11 PA8 PA7 PC2 PA0 PA5 PA4 PA3 PA8 PA1 PC9 PA2 PC11 NRST PA24 PA23 NCS0 NANDOE NANDW E CFW E_NW E_NW R0 CFIOR_NBS1_NW R1 CFIOW _NBS3_NW R3 CFOE_NRD SDCK SDCKE RAS CAS SDA10 SDW E SDCS_NCS1 A[0..22] D[0..31] 03 - MEMORY EXPANSION_Users Interfaces RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE NBS1 NBS3 NANDOE NANDWE NRST PA[0..31] PB[0..31] PC[0..15] VREFP AVDD AGND SHEET 7 06 - EXPANSION CONNECTORS 2-5 AT91SAM9G20-EK Evaluation Board User Guide SDRAM MCIA DATAFLASH NANFLASH MCIB DATAFLASH SERIAL SERIAL EEPROM DATAFLASH 5VDC DAC RS232 USB 10/100 Mbps FAST ETHERNET 6413C–ATARM–18-Feb-09 Setting Up the AT91SAM9G20-EK Board 2-6 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide Section 3 Board Description 3.1 AT91SAM9G20 Microcontroller • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor • • • • • • • • • • – DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration – 32-KByte Data Cache, 32-KByte Instruction Cache, Write Buffer – CPU Frequency 400 MHz – Memory Management Unit – EmbeddedICE™, Debug Communication Channel Support Additional Embedded Memories – One 64-KByte Internal ROM, Single-cycle Access at Maximum Matrix Speed – Two 16-KByte Internal SRAM, Single-cycle Access at Maximum Matrix Speed External Bus Interface (EBI) – Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash® USB 2.0 Full Speed (12 Mbits per second) Device Port – On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM USB 2.0 Full Speed (12 Mbits per second) Host and Double Port – Single or Dual On-chip Transceivers – Integrated FIFOs and Dedicated DMA Channels Ethernet MAC 10/100 Base T – Media Independent Interface or Reduced Media Independent Interface – 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Image Sensor Interface – ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate – 12-bit Data Interface for Support of High Sensibility Sensors – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format Bus Matrix – Six 32-bit-layer Matrix – Boot Mode Select Option, Remap Command Fully-featured System Controller, including – Reset Controller, Shutdown Controller – Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-time Timer Reset Controller (RSTC) – Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control Clock Generator (CKGR) – Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 3 to 20 MHz On-chip Oscillator, One up to 800 MHz PLL and One up to 100 MHz PLL AT91SAM9G20-EK Evaluation Board User Guide 3-1 6413C–ATARM–18-Feb-09 Board Description • Power Management Controller (PMC) • • • • • • • • • • • • • • • 3-2 6413C–ATARM–18-Feb-09 – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Two Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) – Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-time Timer (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler One 4-channel 10-bit Analog-to-Digital Converter Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC) – 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output – All I/O Lines are Schmitt Trigger Inputs Peripheral DMA Controller Channels (PDC) One Two-slot MultiMedia Card Interface (MCI) – SDCard/SDIO and MultiMediaCard™ Compliant – Automatic Protocol Control and Fast Automatic Data Transfers with PDC One Synchronous Serial Controller (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support – Full Modem Signal Control on USART0 Two 2-wire UARTs Two Master/Slave Serial Peripheral Interfaces (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects – Synchronous Communications Two Three-channel 16-bit Timer/Counters (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability – High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2 One Two-wire Interface (TWI) – Compatible with Standard Two-wire Serial Memories – One, Two or Three Bytes for Slave Address – Sequential Read/Write Operations – Master, Multi-master and Slave Mode Operation – Bit Rate: Up to 400 Kbits – General Call Supported in Slave Mode – Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode AT91SAM9G20-EK Evaluation Board User Guide Board Description • IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins • Required Power Supplies – 0.9V to 1.1V for VDDBU, VDDCORE, VDDPLL – 1.65 to 3.6V for VDDOSC – 1.65V to 3.6V for VDDIOP (Peripheral I/Os) – 3.0V to 3.6V for VDDUSB – 3.0V to 3.6V VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os) • Available in a 217-ball LFBGA RoHS-compliant Package AT91SAM9G20-EK Evaluation Board User Guide 3-3 6413C–ATARM–18-Feb-09 PIT RSTC SHDC RTT 4GPREG MCI PDC POR VDDCORE NRST POR OSC RC WDT OSC PLLB PLLA PMC PDC DBGU AIC System Controller SLAVE SHDN WKUP VDDBU OSCSEL XIN32 XOUT32 XIN XOUT DRXD DTXD PCK0-PCK1 FIQ IRQ0-IRQ2 TST Filter Filter M C D B0 -M CD M M B3 C C D A0 CD M B C M DA CC 3 D M A CC K 3-4 TWI PDC PIOA PIOC PIOB PDC USART0 USART1 USART2 USART3 USART4 USART5 TD TDI TMO T S C RTK CK JT AG SE L MMU TC0 TC1 TC2 Fast SRAM 16 Kbytes Bus Interface PDC SPI0 SPI1 ROM 64 Kbytes I ICache 32K bytes D TC3 TC4 TC5 Fast SRAM 16 Kbytes DCache 32K bytes ARM926EJ-S Processor In-Circuit Emulator JTAG Selection and Boundary Scan APB TW C TW D T CK R S0 T SC S0 CT S R K0 -RT 3 X - S TXD0- SCK3 D RX 2 0 -T D5 D XD5 S DCR0 D0 R DT I0 R0 6413C–ATARM–18-Feb-09 FIFO DMA FIFO PDC 4-channel 10-bit ADC PDC Peripheral Bridge SPI0_, SPI1_ USB Device DPRAM DMA Image Sensor Interface Transceiver 24-channel Peripheral DMA 6-layer Matrix 6 x 100M x 32-bit words BM S SSC ET E XC T K ECXE -E R N ERRS -E XC T ERXE -EC XE K R O ET X0 -E L R R M X0 ER XD D - X M C ETX 3 V D 3 F1 IO 00 10/100 Ethernet MAC Transc. HD P HD B M B ECC Controller Static Memory Controller SDRAM Controller CompactFlash NAND Flash EBI DMA USB OHCI Transc. IS I _M IS CK I_ IS PC I_ K IS DO I _V -I IS SY SI_ I_ N D7 H SY C NC HD HD PA M A NP NPCS NPCS3 NPCS2 C 1 SP S0 M CK O T M SI C IS L O TI K0 O -T TI A0- CL O T K TC B0 IOA2 L -T 2 TI K3 IOB O TI A3 TC 2 O -T LK B3 IO 5 -T A I O 5 B5 TK TF TD RD RF RK AD 0AD AD 3 TR IG AD VR EF VD DA N A ND AN A D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21/NANDALE, A22/NANDCLE D16-D31 NWAIT A23-A24 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1-CFCE2 NCS2, NCS6, NCS7 NCS3/NANDCS Figure 3-1. G 3.2 DD DDM P MASTER Board Description AT91SAM9G20 Block Diagram Block Diagram AT91SAM9G20-EK Evaluation Board User Guide Board Description 3.3 Microcontroller 3.4 3.5 3.6 3.7 3.8 3.9 One 217-ball LFBGA fitted on board Memory 32 Kbytes of Internal ROM Two 4-KByte Internal SRAMs Atmel serial DataFlash 64 Mbytes of SDRAM memory (32-bit bus width) 256 Mbytes of NAND Flash memory (8-bit bus width) TWI serial EEPROM Clock Circuitry 18.432 MHz standard crystal for the embedded oscillator Selectable 32,768Hz Low-power external standard crystal Oscillator or Internal Low Power RC Oscillator Reset Circuitry Internal reset controller with bi-directional reset pin External reset pushbutton Shutdown Controller Programmable shutdown and Wake-Up Wake-up push button Power Supply Circuitry On-board 1.0V High Efficiency step-down charge pump regulator with shutdown control On-board 3.3V linear regulator with shutdown control On-board power sequencer Remote Communication One serial interface (DBGU COM Port) via RS-232 DB9 male socket One complete modem serial interface (COM Port 0) via RS-232 DB9 male socket One additional serial interface (COM Port 1) with RTS/CTS handshake control via RS-232 DB9 male socket USB V2.0 full-speed compliant, 12 Mbits per second (UDP) Two USB Host ports V2.0 full-speed compliant, 12 Mbits per second (UHP) AT91SAM9G20-EK Evaluation Board User Guide 3-5 6413C–ATARM–18-Feb-09 Board Description 3.10 3.11 3.12 3.13 One Ethernet 100-base TX with three status LEDs Audio Stereo Interface Stereo Audio Codec with Integrated Headphone Driver (50 mW on 16W @ 3.3V) One Headset output (J4) with master volume and mute controls User Interface Two user input push buttons One user green LED One yellow power LED (can be also software controlled) Debug Interface All I/Os of the AT91SAM9G20 are routed to peripheral extension connectors All I/Os of the AT91SAM9G20 Image Sensor Interface are routed to peripheral extension connectors All EBI Signals of the AT91SAM9G20 are routed to extension footprint connectors (J25) Debug Interface 20-pin JTAG/ICE interface connector DBGU COM port Expansion Slot One on-board DataFlash device Two SD/MMC card slots, the system can boot from slot J35 All I/Os of the AT91SAM9G20 are routed to peripheral extension connectors All I/Os of the AT91SAM9G20 Image Sensor Interface are routed to peripheral extension connectors All EBI Signals of the AT91SAM9G20 are routed to extension footprint connectors (J25) This allows the developer to check the integrity of the components and to extend the features of the board by adding external hardware components or boards. 3-6 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide Board Description 3.14 PIO Usage Table 3-1. I/O Peripheral Controller A I/O Line Peripheral A Peripheral B Comments Function PA0 SPI0_MISO MCDB0 SPI DataFlash, SPI/MCI SD/MMC/DataFlash Slot PA1 SPI0_MOSI MCCDB (PA0..PA5) PA2 SPI0_SPCK PA3 SPI0_NPCS0 MCDB3 PA4 RTS2 MCDB2 PA5 CTS2 MCDB1 PA6 MCDA0 Boot SD Card Slot (DAT0) PA7 MCCDA Boot SD Card Slot (CMD) PA8 MCCK MCI SD/MMC/DataFlash Slot (CLK) PA9 MCDA1 Boot SD Card Slot (DAT1) PA10 MCDA2 ETX2 1- Boot SD Card Slot (DAT2), 2- ETHERNET DM9161A MII Interface (disconnected by default, see R120) PA11 MCDA3 ETX3 1- Boot SD Card Slot (DAT3), 2- ETHERNET DM9161A MII Interface (disconnected by default, see R119) PA12 ETX0 PA13 ETX1 PA14 ERX0 PA15 ERX1 PA16 ETXEN PA17 ERXDV PA18 ERXER PA19 ETXCK PA20 EMDC PA21 EMDIO PA22 ADTRG ETXER ETHERNET DM9161A MII Interface PA23 TWD ETX2 SERIAL EEPROM (SDA), WM8731 audio DAC PA24 TWCK ETX3 SERIAL EEPROM (SCL), WM8731 audio DAC PA25 TCLK0 ERX2 ETHERNET DM9161A MII Interface (PA25..PA29) PA26 TIOA0 ERX3 High-Drive PA27 TIOA1 ERXCK High-Drive PA28 TIOA2 ECRS High-Drive PA29 SCK1 ECOL PA30 SCK2 RXD4 (BP3) User's interface Push Button PA31 SCK0 TXD4 (BP4) User's interface Push Button ETHERNET DM9161A RMII Interface (PA12..PA19) ETHERNET DM9161A MII/RMII Interface (PA20..PA21) AT91SAM9G20-EK Evaluation Board User Guide 3-7 6413C–ATARM–18-Feb-09 Board Description Table 3-2. I/O Peripheral Controller B I/O Line Peripheral A Peripheral B PB0 SPI1_MISO TIOA3 ETHERNET DM9161A MII/RMII (IRQ) PB1 SPI1_MOSI TIOB3 Audio DAC WM8731 (MOSI) PB2 SPI1_SPCK TIOA4 Audio DAC WM8731 (SPCK) PB3 SPI1_NPCS0 TIOB4 Audio DAC WM8731 (Chip Select) PB4 TXD0 COM PORT 0 (TXD) PB5 RXD0 COM PORT 0 (RXD) PB6 TXD1 TCLK1 COM PORT 1 (TXD) PB7 RXD1 TCLK2 COM PORT 1 (RXD) PB8 TXD2 User LED PB9 RXD2 Power LED PB10 TXD3 ISI_D8 PB11 RXD3 ISI_D9 PB12 TXD5 ISI_D10 PB13 RXD5 ISI_D11 PB14 DRXD SERIAL DEBUG PORT(RXD) PB15 DTXD SERIAL DEBUG PORT(TXD) PB16 TK0 TCLK3 Audio DAC WM8731 (BCLK) PB17 TF0 TCLK4 Audio DAC WM8731 (LRFS) PB18 TD0 TIOB4 Audio DAC WM8731 (SDIN) PB19 RD0 TIOB5 (J28) IMAGE SENSOR CONNECTOR (CTRL2) PB20 RK0 ISI_D0 (J28) IMAGE SENSOR CONNECTOR (PB20..PB31) PB21 RF0 ISI_D1 PB22 DSR0 ISI_D2 PB23 DCD0 ISI_D3 PB24 DTR0 ISI_D4 PB25 RI0 ISI_D5 PB26 RTS0 ISI_D6 PB27 CTS0 ISI_D7 PB28 RTS1 ISI_PCK PB29 CTS1 ISI_VSYNC PB30 PCK0 ISI_HSYNC PB31 PCK1 ISI_MCK 3-8 6413C–ATARM–18-Feb-09 Comments Function (J28) IMAGE SENSOR CONNECTOR (PB10..PB13) Warning: Shared with COM PORT 0 (PB22..PB27) Warning: Shared with COM PORT 1 (PB28..PB29) AT91SAM9G20-EK Evaluation Board User Guide Board Description Table 3-3. I/o Peripheral Controller C I/O Line Peripheral A Peripheral B PC0 AD0 SCK3 PC1 AD1 PCK0 PC2 AD2 PCK1 PC3 AD3 SPI1_NPCS3 PC4 A23 SPI1_NPCS2 (J28) IMAGE SENSOR CONNECTOR (CTRL1) PC5 A24 SPI1_NPCS1 USB_CNX (VBUS DETECT) PC6 TIOB2 CFCE1 PC7 TIOB1 CFCE2 PC8 NCS4/CFCS0 RTS3 PC9 NCS5/CFCS1 TIOB0 PC10 A25/CFRNW CTS3 PC11 NCS2 SPI0_NPCS1 PC12 IRQ0 NCS7 PC13 FIQ NCS6 NAND Flash (RDYBSY) PC14 NCS3/NANDCS IRQ2 NAND Flash (NANDCS) PC15 NWAIT IRQ1 PC16 D16 SPI0_NPCS2 PC17 D17 SPI0_NPCS3 PC18 D18 SPI1_NPCS1 PC19 D19 SPI1_NPCS2 PC20 D20 SPI1_NPCS3 PC21 D21 EF100 PC22 D22 TCLK5 PC23 D23 PC24 D24 PC25 D25 PC26 D26 PC27 D27 PC28 D28 PC29 D29 PC30 D30 PC31 D31 AT91SAM9G20-EK Evaluation Board User Guide Comments Function Audio DAC WM8731 (MCLK) SPI DataFlash memory (Chip Select) EBI Data Bus (PC16..PC31) 3-9 6413C–ATARM–18-Feb-09 Board Description 3-10 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide Section 4 Configuration 4.1 Jumpers Table 4-1. Jumpers Configuration Designation Default Setting Feature J2 Closed 3.3V Jumper(1) J3 Closed Forces power on. To use the software shutdown control: • J3 must be opened, • 3V battery backup must be present, • J10 jumper set in position 1-2 J6 Closed VDDPLL Jumper(1) Open Enables boot on the internal ROM Closed Enables boot on the NCS0 2-3 Slow Clock OSCSEL 1-2: Internal RC Oscillator 2-3: External Crystal Oscillator J10 2-3 VDDBU Jumper select(1) 1-2: Lithium 3V Battery 2-3: 1.0V from VDDCORE J12 Closed VDDCORE Jumper(1) J15 Closed Enables Ethernet Auto MDIX control J33 Closed Serial DataFlash chip select enable J34 Closed NAND Flash chip select enable J7 J9 Note: 1. These jumpers are provided for power consumption measurement. By default, they are closed. To use this feature, the user has to open the strap and insert an ampere meter. AT91SAM9G20-EK Evaluation Board User Guide 4-1 6413C–ATARM–18-Feb-09 Configuration 4.2 JTAG/ICE Table 4-2. JTAG/ICE Configuration Designation 4.3 Default Setting Feature S1 Opened Disables the ICE NTRST input S2 Opened Selects ICE Debug Mode or JTAG Boundary Scan Mode S3 Opened Disables TCK <-> RTCK local loop. If S3 is closed, R13 must be unsoldered. R13 Soldered Enables the ICE RTCK return. S3 must be opened R14 Soldered Enables the ICE RTCK return. S3 must be opened Microcontroller Clock Table 4-3. Microcontroller Clock Configuration Designation Default Setting Feature R18/R20 Soldered S4 Opened Enables the use of 18.432MHz crystal. If external clock is used, R18/R20 must be unsoldered and S4 closed. Slow Clock Setting. See Table 4-1. J9 4.4 Memory Table 4-4. Memory Configuration Designation Default Setting Feature Soldered Soldered Enables MN7 Chip select access Enables MN8 Chip select access SDRAM R31 R32 NAND Flash (MN6+x) J34 R34 S6 Closed Soldered Opened Enables the use of NAND Flash (MN6x) Enables the use of Ready Busy signal Disables write protect SERIAL DataFlash (MN9) J33 S5 Soldered Opened Enable the use of the Serial DataFlash®(MN9) Disables write protect TWI SERIAL EEPROM (MN10) R46 R47 4-2 6413C–ATARM–18-Feb-09 Soldered Soldered Enables SCL access Enables SDA access AT91SAM9G20-EK Evaluation Board User Guide Configuration 4.5 Ethernet RMII is the factory default mode. To evaluate the MII mode, the user has to unsolder R49, R50, R127 and close S7 and S8. When the RMII mode is used, the user can use the specific MII signals as PIO, but the following resistors must be unsoldered (R119 to R126). Note that, by default, resistors R112 and R120 are not populated in order to avoid contention between the MII signals and the SD Card slot J35. If the Ethernet MII mode is implemented on the board, then you must not insert any card into slot J35. Otherwise, signal conflicts could occur and damage both the Ethernet controller and the SD Card. 4.6 Miscellaneous Refer to “Board Layout - Top View” in Section 5.1 ”Schematics” for the PIO Usage. AT91SAM9G20-EK Evaluation Board User Guide 4-3 6413C–ATARM–18-Feb-09 Configuration 4-4 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide Section 5 Schematics 5.1 Schematics This section contains the following schematics: Board Layout - Top View Power Supply and Audio AT91SAM9G20-CU Memory Ethernet Serial Interface Expansion and User Interface AT91SAM9G20-EK Evaluation Board User Guide 5-1 6413C–ATARM–18-Feb-09 4 3 2 SHEET 3 D[0..31] A[0..22] POWER SUPPLY PB9 5VDC DAC D PB9 PIO SHDN SDCK SDCKE PA23 PA24 PB3 PA23 PA24 PB3 NANDOE NANDW E PA23/TWD PA24/TWCK SPI1_NPCS0 PIO PIO A16 A17 A22 A21 NANDOE NANDWE PC14 PC13 A22 A21 NANDOE NANDW E PC14 PC13 D[0..15] 01 - POWER SUPPLY PB[0..31] RS232 SERIAL INTERFACES MCDA0 MCDA1 MCDA2 MCDA3 MCCK MCCDA SHEET 6 DBGU PB15 PB14 COM0 PB4 PB5 PB26 PB27 PB24 PB22 PB23 PB25 C PB6 PB7 PB28 PB29 COM1 DBGU_TXD DBGU_RXD PB15 PB14 PB4 PB5 PB26 PB27 PB24 PB22 PB23 PB25 SPI0_MISO MCDB0 MCDB1 MCDB2 SPI0_NPCS0 MCDB3 MCCK SPI0_MOSI MCCDB PB6 PB7 PB28 PB29 SPI0_SPCK SPI0_NPCS1 PC[0..15] USB DEVICE HOST A HOST B PC5 DDM DDP PIO PC5 05 - COMMUNICATION 10/100 Mbps FAST ETHERNET PA11 PA10 PA13 PA12 PA16 PA26 PA25 PA15 PA14 PA27 PA17 PA22 PA18 PA29 PA28 PA20 PA21 PB0 NRST PA19 ETXCK/REFCLK PA11 PA10 PA13 PA12 PA16 ETX3 ETX2 ETX1 ETX0 ETXEN PA26 PA25 PA15 PA14 ERX3 ERX2 ERX1 ERX0 PA27 PA17 ERXCK ERXDV PA22 PA18 ETXER ERXER PA29 PA28 ECOL ECRS PA20 PA21 PB0 EMDC EMDIO PIO A 7 NRST PA24 PA23 PA24 PA23 CFWE_NWE_NWR0 CFOE_NRD CFOE_NRD NBS1 NBS3 NANDOE NANDWE NCS0 NRST PA[0..31] PB[0..31] PC[0..15] PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 6 USAGE TX_EN RX_DV RX_ER TX_CLK MDC MDIO TX_ER SDA/ DIN/ TW D SCL/CLK/TW CK RXD2 RXD3 RX_CLK CRS COL BP3 BP4 PIOB PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 USAGE MDINTR --CS TXD0 RXD0 TXD1 RXD1 USER LED POW ERLED ISI_DATA[8] ISI_DATA[9] ISI_DATA[10] ISI_DATA[11] DRXD DTXD 5 RAS CAS SDA10 SDW E SDCS_NCS1 SDCK SDCKE B CFW E_NW E_NW R0 CFIOR_NBS1_NW R1 CFIOW _NBS3_NW R3 CFOE_NRD NANDOE NANDW E NCS0 NRST NRST PA[0..31] PA[0..31] PB[0..31] PB[0..31] PC[0..15] PC[0..15] VREFP AVDD AGND 06 - EXPANSION CONNECTORS PIO MUXING PIOA NCS0 VREFP AVDD AGND 02 - AT91SAM9G20-CU USAGE SHEET 7 A[0..22] SDCK SDCKE DAT0_B/MISO CMD_B/MOSI SCK DAT3_B DAT2_B DAT1_B DAT0_A CMD_A CLK_B/CLK_A DAT1_A DAT2_A/ TXD2 DAT3_A/ TXD3 TXD0 TXD1 RXD0 RXD1 C D[0..31] RAS CAS SDA10 SDWE SDCS_NCS1 03 - RMII_MII ETHERNET PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA2 PC11 HDMB HDPB PB[0..31] PIOA PA2 PC11 CARD READER 03 - MEMORY EXPANSION_Users Interfaces CFW E_NW E_NW R0 NRST CARD READER (BOOT) PA0 PA5 PA4 PA3 PA8 PA1 PC9 PA8 HDMA HDPA SHEET 5 PA19 8 TWCK TWD DDM DDP PA[0..31] RMII_MII ETHERNET B DDM DDP HDMB HDPB HDMB HDPB PA1 PC9 PA6 PA9 PA10 PA11 PA8 PA7 PC2 NRST HDMA HDPA HDMA HDPA D[0..15] PA6 PA9 PA10 PA11 PA8 PA7 PC2 PA0 PA5 PA4 PA3 D CFIOR_NBS1_NW R1 CFIOW _NBS3_NW R3 A16 A17 PB[0..31] WM8731 RAS CAS SDA10 SDW E SDCS_NCS1 SDCK SDCKE NBS1 NBS3 CFIOR_NBS1_NW R1 CFIOW _NBS3_NW R3 PCK0 TD0 TF0 TK0 PC1 PB18 PB17 PB16 A[0..14] RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE SHDN PC[0..15] PC1 PB18 PB17 PB16 D[0..31] A[0..14] RAS CAS SDA10 SDW E SDCS_NCS1 PB[0..31] SHEET 2 D[0..31] A[0..22] 1 SHEET 4 MEMORY SDRAM 5 AT91SAM9G20-CU MCIA DATAFLASH NANFLASH 6 MCIB DATAFLASH 7 SERIAL SERIAL EEPROM DATAFLASH 8 PIOB PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 USAGE BCLK LRFS SDIN PIO_CNTRL2 ISI_DATA[0] ISI_DATA[1] DSR0/ ISI_DATA[2] DCD0/ ISI_DATA[3] DTR0/ ISI_DATA[4] RI0/ ISI_DATA[5] RTS0/ ISI_DATA[6] CTS0/ ISI_DATA[7] RTS1/ ISI_PCK CTS1/ ISI_VSYNC ISI_HSYNC ISI_MCK 4 PIOC USAGE PIOC PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 -MCLK CD_A -PIO_CNTRL1/ A23 USBCNX/ A24 CFCE1 CFCE2 CFCS0_NCS4 CD_B/ CFCS1_NCS5 A25_CFRNW CS/ NCS2 NCS7 RDYBSY/ NCS6 NANDCS_NCS3 NW AIT PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 USAGE D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A D C B A INIT EDIT REV MODIF. AT91SAM9G20-EK DIAGRAM SCALE PP PP PP TVT DES. 06/03/09 07/10/08 02/07/08 15/04/08 DATE 1/1 2 DATE REV. SHEET D This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 3 VER. 1 1 7 7 6 5 10 SQUARE CM COPPER AREA FOR HEAT SINKING WITH NO SOLDER MASK MN1 LT1963AEQ-3.3 D 3 C1 330µF VIN + CR1 5V R168 3V3 CURRENT MEASURE 6 GND 3V3 J2 VOUT SD GND FB 1 3 5 1 IRLML6402 2 4 3 Q3 C3 10µF C4 10µF D R163 10K 5V R161 82K R164 1K PA24 1 2 J1 C2 10µF 10V 2 R3 100K 2 NOT POPULATED PB3 5V 3 1 REGULATED 5V ONLY 4 PA23 8 CLK 4 C147 100NF R6 0R R2 R128 0R C5 1µF C136 10µF C6 1µF GND_DAC SHDN 8 R167 10K C1P C2M VIN C2P VOUT C140 10µF 1V0 7 C11 R7 22µF 30K C15 4.7µF TPS60500 FB EN GND MN3 PG C141 100NF 15 17 GND_DAC 10 19 18 R11 120K 2 20 AVDD 24 21 11 VMID C139 10µF C138 100NF GND_DAC AGND HP VOL /MUTE DRIVER MICBIAS RLINEIN VOL MICIN MUTE MUTE ADC DAC MUX ROUT LOUT ADC J4 MUTE DIGITAL FILTER MUTE MUTE VOL R136 47K 10 GND_DAC MUX 0db/20db LLINEIN RHPOUT C GND_DAC MUTE ATTEN /MUTE DAC 220µF 10V 13 12 220µF 10V MUTE 9 HP VOL /MUTE DRIVER LM293 LHPOUT C16 C17 3 1 4 2 3.5 PHONEJACK STEREO R137 47K 9 ATTEN /MUTE MUTE GND_DAC DCVDD 27 BCLK ADCLRC 7 DACLRC DIGITAL AUDIO INTERFACE 3 26 B 25 XTO XTI/MCLK MMSD4148 CLOCK DIVIDER DACDAT CLOCK DIVIDER 5 OSC 4 D1 CLKOUT + R166 10K - 3 MN15A 1 4 C12 10PF 1 2 3 16 HPVDD HPGND CONTROL INTERFACE DGND 5V 5V C1M 5 6 14 DBVDD 5V C137 100NF 8 B WM8731SEDS 28 C VCC_DAC MODE R169 NOT POPULATED SCLK R10 10K CSB MN2 R9 10K R165 15K 22 100K 3 2 2 SDIN VCC_DAC 1 C14 15PF 23 3V3 FORCE POWER ON + J3 + R162 15K 1 4 ADCDAT 5 AUDIO DAC INTERFACE 5V LM293 6 Q2 6 Si1563EDH MN15B 7 - CS 6 + DIN 8 5 R151100K BCLK SDIN LRFS R150100K R8 47R 3V3 3V3 MCLK 3V3 TP3 TP4 C143 10µF C144 100NF C145 10µF PB16 TP2 PB18 TP1 PC1 GND TEST POINT POWER LED PB17 R1 120R C142 100NF R4 470K DS1 YELLOW 3 VCC_DAC A Q1 IRLML2402 1 R5 0R 3V3 L1 POWERLED PB9 10uH 150mA 2 C146 100NF A ADHESIVE FEET R15 0R R12 1R Z3 Z4 11.1 11.1 Z5 Z6 11.1 11.1 D C B A INIT EDIT GND_DAC C18 4.7µF GND_DAC GND_DAC REV MODIF. AT91SAM9G20-EK SCALE PP PP PP TVT DES. 06/03/09 07/10/08 02/07/08 15/04/08 DATE 1/1 7 6 5 4 3 2 DATE REV. SHEET D POW ER SUPPLY & AUDIO This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 VER. 1 2 7 8 7 6 5 4 3 C HDPB HDMB S1 1V0 S2 S3 NTRST H16 R1 T1 L5 C49 100NF P2 C22 100NF U1 C48 4.7µF R18 0R C23 10PF Y1 18.432MHz R20 0R XIN N1 C24 10PF S4 OUT GND C47 100NF RD31 RD30 RD29 RD28 RD27 RD26 RD25 RD24 RD23 RD22 RD21 RD20 RD19 RD18 RD17 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 T3 T4 U3 U4 A17 A15 A16 B11 B16 C11 B12 B14 C12 B13 B15 G1 J4 2 J2 3 H11 J1 4 K21 K42 M44 N33 K14 L3 3 L2 1 N42 P43 R32 P34 M21 RD16 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 C37 10µF WKUP BP2 C32 100NF SHDN C33 C35 100NF 100NF C34 C36 100NF 100NF R27 0R J12 1V0 3V3 C44 100NF C42 C45 10µF 100NF 10V VDDCORE CURRENT MEASURE VDDOSC RD15 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 RA13 RA14 RA15 RA16 RA17 RA18 RA19 RA20 RA21 RA22 R-RAS R-CAS R-SDWE R-SDA10 R-SDCKE R-SDCK R-CFWE R-FIOR R-FIOW R-NANDOE C46 100NF C51 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 1 2 4 3 1 2 3 3 4 1 2 1 3 2 4 2 3 4 2 1 1 3 4 8A0 7A1 5A2 6A3 8A4 7A5 6A6 6A7 5A8 8A9 7A10 8A11 6A12 7A13 5A14 7A15 6A16 5A17 7A18 8A19 8A20 6A21 5A22 RR17A RR17B RR18D RR16C RR16A RR16B RR17C RR18C RR17D RR18A RR18B RR10A RR9C RR10B RR9D RR9B RR10C RR10D RR11B RR9A RR11A RR11C RR11D 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 27R 3 1 6 8 RR19C RR19A 27R 27R 2 4 1 2 7 5 8 7 RR19B RR16D RR21A RR21B 27R 27R 27R 27R RR19D RR20D 27R 27R 4 4 5 5 3 6 RR20B RR21C RR21D 2 3 4 RR20A 1 R-NCS0 R-CFOE_NRD RR2B RR2A RR2C RR3B RR2D RR3A RR3C RR3D RR4D RR4C RR4B RR5A RR5C RR4A RR5B RR5D RR20C R-SDCS_NCS1 27R SDWE SDA10 SDCKE SDCK SDCS_NCS1 NCS0 CFWE_NWE_NWR0 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 8 R153 100K 1K BOOT MODE SELECT 10uH VREFP 0R 7 6 5 4 3 RESET VREFP AVDD C28 100NF 3V3 L2 C30 100NF R45 1R C31 4.7µF 10uH 150mA 0R R22 R28 0R 3V3 AGND AGND A 150mA D C B A INIT EDIT REV MODIF. AT91SAM9G20-EK AT91SAM9G20-CU SCALE PP PP PP TVT DES. 06/03/09 07/10/08 02/07/08 15/04/08 DATE 1/1 2 VER. DATE REV. SHEET D This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 B NRST OPENED : EMBEDDED ROM CLOSED : EBI_NCS0 AVDD R2 27R 27R BP1 3V3 BMS J7 TST R19 R16 1K 27R 27R NANDOE NANDWE 27R C 3V3 CFOE_NRD 7 6 5 C50 100NF 4.7µF RAS CAS R-NANDWE C27 100NF R44 1R C39 C41 100NF 100NF C40 100NF RD14 L4 VDDOSC C38 10µF RD13 7D0 8D1 6D2 7D3 5D4 8D5 6D6 5D7 5D8 6D9 7D10 8D11 6D12 8D13 7D14 5D15 R4 L4 VDDIOP P8 VDDIOP U17 VDDIOM VDDIOM VDDIOM J3 G4 D11 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDDUSB D8 G14 L1 T7 T15 D6 F4 M3 H8 H9 H10 J8 J9 J10 K8 K9 K10 K16 R7 C43 100NF RD12 R21 GNDANA 3V3 VDDIOM R26 100K WAKE UP C16 GNDUSB GNDUSB VDDCORE VDDCORE 3V3 RD11 2 1 3 2 4 1 3 4 4 3 2 1 3 1 2 4 U2 VDDANA D10 D12 T13 R24 NOT POPULATED VDDBU VDDCORE OSCSEL M1 3 + 1K 3 2 1 XIN32 RD10 F17 ADVREF VDDCORE 4 1V0 J10 R23 10K 3V CR1225 R25 D17 1 J11 VDD MN5 R1100D101C Z11 2 A 3 2 1 XIN32 OSCSELF14 VDDBU J9 XOUT32 RD9 R17 TST XIN RD8 F15 BMS Y2 32.768 kHz C26 10PF NOT POPULATED XOUT32 E17 1 C25 10PF XOUT RD7 G15 NRST GNDPLL RD6 C10 B10 NANDOE NANDW E H14 1 3 5 J8 2 4 XOUTP1 RD5 A12 B2 A1 CFW E/NW E/NW R0 CFIOR/NBS1/NW R1 CFIOW /NBS3/NW R3 VDDPLL RD4 A13 CFOE/NRD VDDCORE D9 R43 1R RD3 B3 A14 SDCS/NCS1 NCS0 N.C4 N2 VDDPLL C21 100NF T2 GNDPLL 1V0 10uH 150mA N.C1 A[0..22] D RD2 F2 B4 G3 B1 D[0..31] 27R 27R 27R 27R 27R 27R 27R 27R TP5 TP6 RD1 D3 C3 SDW E SDA10 SDCKE SDCK GNDBU J6 B NTRST RR13D RR13C RR13A RR13B RR12C RR12B RR12D RR12A RD0 A2 A3 C4 B5 C5 D5 A4 B6 A5 C6 D7 A6 B7 A7 C7 B8 A8 C8 A9 C9 B9 A10 A11 RAS CAS VDDBU NRST E16 R14 0R 0R TDI TMS TCK RTCK TDO JTAGSEL SHDN R13 J16 G17 H15 G16 J14 F16 D16 ICE_RTCK TDI TMS TCK RTCK TDO JTAGSEL HDPB HDMB D4 C2 D2 E3 E4 E2 F3 G2 C1 D1 E1 H4 H3 F1 H2 K3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 1 27R 27R 27R 27R 27R 27R 27R 27R D15 C15 N.C2 N.C3 NBS0/A0 NW R2/NBS2/A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BA0/A16 BA1/A17 A18 A19 A20 A21 A22 AT91SAM9G20B-CU HDPA HDMA WKUP ICE_NTRST D14 C14 DDP DDM B17 1 3 5 7 9 11 13 15 ICE_NRST 17 19 E14 E15 HDPA HDMA ICE INTERFACE 4 3 2 1 2 4 6 8 10 12 14 16 18 20 C13 D13 DDP DDM RR1 100K C17 5 6 7 8 3V3 PA0/SPI0_MISO/MCDB0 PA1/SPI0_MOSI/MCCDB PA2/SPI0_SPCK PA3/SPI0_NPCS0/MCDB3 PA4/RTS2/MCDB2 PA5/CTS2/MCDB1 PA6/MCDA0 PA7/MCCDA PA8/MCCK PA9/MCDA1 PA10/MCDA2/ETX2 PA11/MCDA3/ETX3 PA12/ETX0 PA13/ETX1 PA14/ERX0 PA15/ERX1 PA16/ETXEN PA17/ERXDV PA18/ERXER PA19/ETXCK PA20/EMDC PA21/EMDIO PA22/ADTRG/ETXER PA23/TW D/ETX2 PA24/TW CK/ETX3 PA25/TCLK0/ERX2 PA26/TIOA0/ERX3 PA27/TIOA1/ERXCK PA28/TIOA2/ECRS PA29/SCK1/ECOL PA30/SCK2/RXD4 PA31/SCK0/TXD4 SCK3/AD0/PC0 PCK0/AD1/PC1 PCK1/AD2/PC2 SPI1_NPCS3/AD3/PC3 SPI1_NPCS2/A23/PC4 SPI1_NPCS1/A24/PC5 CFCE1/TIOB2/PC6 CFCE2/TIOB1/PC7 RTS3/NCS4_CFCS0/PC8 TIOB0/NCS5_CFCS1/PC9 CTS3/A25_CFRNW/PC10 SPI0_NPCS1/NCS2/PC11 NCS7/IRQ0/PC12 NCS6/FIQ/PC13 IRQ2/NCS3_NANDCS/PC14 IRQ1/NWAIT/PC15 SPI0_NPCS2/D16/PC16 SPI0_NPCS3/D17/PC17 SPI1_NPCS1/D18/PC18 SPI1_NPCS2/D19/PC19 SPI1_NPCS3/D20/PC20 EF100/D21/PC21 TCLK5/D22/PC22 D23/PC23 D24/PC24 D25/PC25 D26/PC26 D27/PC27 D28/PC28 D29/PC29 D30/PC30 D31/PC31 R10 P11 T9 P12 R11 R12 T10 P13 T11 P14 R13 T12 U9 U10 U11 U12 U15 U14 U16 U13 T14 R14 T16 R15 R16 P16 P15 T17 L14 R17 N15 N14 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 D TIOA3/SPI1_MISO/PB0 TIOB3/SPI1_MOSI/PB1 TIOA4/SPI1_SPCK/PB2 TIOA5/SPI1_NPCS0/PB3 TXD0/PB4 RXD0//PB5 TCLK1/TXD1/PB6 TCLK2/RXD1/PB7 TXD2/PB8 RXD2/PB9 ISI_D8/TXD3/PB10 ISI_D9/RXD3/PB11 ISI_D10/TXD5/PB12 ISI_D11/RXD5/PB13 DRXD/PB14 DTXD/PB15 TCLK3/TK0/PB16 TCLK4/TF0/PB17 TIOB4/TD0/PB18 TIOB5/RD0/PB19 ISI_D0/RK0/PB20 ISI_D1/RF0/PB21 ISI_D2/DSR0/PB22 ISI_D3/DCD0/PB23 ISI_D4/DTR0/PB24 ISI_D5/RI0/PB25 ISI_D6/RTS0/PB26 ISI_D7/CTS0/PB27 ISI_PCK/RTS1/PB28 ISI_VSYNC/CTS1/PB29 ISI_HSYNC/PCK0/PB30 ISI_MCK/PCK1/PB31 MN4 PA[0..31] N16 M14 M15 M16 K14 P17 N17 M17 L16 L15 T5 P5 R5 P6 L17 K17 J17 K15 H17 J15 U5 U6 T6 R6 P7 U7 R8 U8 R9 T8 P9 P10 PB[0..31] J5 RR15B RR15C RR15A RR15D RR14A RR14B RR14D RR14C 7D16 6D17 8D18 5D19 8D20 7D21 5D22 6D23 5D24 6D25 8D26 7D27 6D28 7D29 5D30 8D31 PC[0..15] 2 1 3 7 8 7 6 5 4 3 2 1 SDRAM A[0..14] D[0..31] A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 D A13 23 24 25 26 29 30 31 32 33 34 22 35 SDA10 SDA10 20 21 BA0 BA1 A16 A17 36 40 A14 SDCKE SDCK A0 SDCKE 37 SDCK 38 NBS0 15 39 CFIOR_NBS1_NW R1 CAS RAS 3V3 SDW E R29 470K C R31 SDCS_NCS1 CAS RAS 17 18 SDW E 16 19 MN7 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C1 VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 20 21 BA0 BA1 36 40 A14 A1 SDCKE 37 SDCK 38 NBS2 15 39 CAS RAS 17 18 SDW E 16 19 CFIOW _NBS3_NW R3 28 41 54 6 12 46 52 C68 C70 C72 C74 100NF 100NF 100NF 100NF C69 C71 C73 100NF 100NF 100NF 3V3 256 Mbits 0R SDA10 A13 3V3 1 14 27 3 9 43 49 23 24 25 26 29 30 31 32 33 34 22 35 MN8 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C1 VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D 3V3 C75 C77 C79 C81 100NF 100NF 100NF 100NF C76 C78 C80 100NF 100NF 100NF 256 Mbits R30 470K R32 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 C 0R 3V3 NANDFLASH D[0..15] RDYBSY 3V3 3V3 B R33 R34 R35 R41 A22 CLE A21 ALE nRE nW E nCE 470K 0R RnB 1K WP 470K 0R 0R S6 16 17 8 18 9 7 19 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 CLE ALE RE WE CE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 R/B WP N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 N.C15 N.C16 N.C17 N.C18 PRE N.C19 VCC VCC VSS VSS VSS 26 28 30 32 40 42 44 46 27 29 31 33 41 43 45 47 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A22 A21 nRE nW E nCE RnB 7 WP 19 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 39 38 36 3V3 37 12 48 25 13 C84 100NF C83 100NF NOT POPULATED 16 17 8 18 9 MN6B1 8-bit bus width CLE ALE RE WE CE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 R/B WP N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 N.C15 N.C16 N.C17 N.C18 N.C19 N.C20 N.C21 N.C22 N.C23 PRE N.C24 N.C25 N.C26 N.C27 N.C28 VCC VCC VSS VSS 29 30 31 32 41 42 43 44 D0 D1 D2 D3 D4 D5 D6 D7 PA2 PC11 SCK CS J33 3 NRST MN9 SO SI SCK CS VCC GND RESET WP 6 7 C82 100NF 5 S5 48 47 46 45 40 39 38 35 34 33 28 27 37 12 3V3 8 1 2 4 W RITE PROTECT NORMALLY OPEN 3V3 68K 68K 68K 68K 10K PC13 NANDCS J34 R38 R39 16-bit bus width B R42 NOT POPULATED PA5 PA0 3V3 PA8 PA1 PA3 PA4 36 13 J13 R160 R159 R158 R157 R154 A22 A21 NANDOE NANDW E PC14 MN6A1 SERIAL DATAFLASH R37 470K DUAL FOOTPRINT DAT1_B DAT0_B CLK_B 3V3 CMD_B DAT3_B DAT2_B C85 100NF K9F2G08U0A-PCB0T 3V3 FPS009 8 7 6 5 4 3 2 1 9 12 11 10 CD_B PC9 SD CARD / MMCB CARD DATAFLASH CARD INTERFACE 3V3 10K PA24 PA23 R46 SCL SDA R47 0R 0R PA9 PA6 R155 10K 6 5 3V3 C86 100NF 8 4 PA8 MN10 SCL SDA VCC GND A0 A1 NC WP 1 2 3 PA7 PA11 PA10 R170 R171 R172 R173 R174 68K 68K 68K 68K R156 10K A DAT1_A DAT0_A CLK_A 3V3 CMD_A DAT3_A R175 DAT2_A R176 0R 0R C148 100NF 7 SERIAL EEPROM 8 7 6 5 4 J35 8 7 6 5 4 3 2 1 9 FPS009 12 11 10 CD_A A PC2 SD CARD / MMCA CARD DATAFLASH CARD INTERFACE (BOOTABLE) 3 D C B A INIT EDIT REV MODIF. AT91SAM9G20-EK MEMORY PP PP PP TVT DES. 06/03/09 07/10/08 02/07/08 15/04/08 DATE 1/1 SCALE DATE REV. SHEET D This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 2 VER. 1 4 7 8 7 6 D 5 4 3 2 1 D 3V3 10K 4 C87 100NF C88 22PF SG-8002JC-50.0000M-PCB PA19 TX_CLK R50 PA15 PA25 PA14 PA27 PA17 PA22 PA18 R134 PA29 PA28 1,5K 3V3 PA21 MDIO S8 R60 RXD3 R121 10K RXD2 R122 RXD1 RXD0 0R PA26 RX_CLK RX_DV TX_ER RX_ER R133 COL CRS 10K 3V3 MDC PA20 MDINTR PB0 3V3 42 0R 17 18 19 20 21 22 R119 NOT POPULATED R120 NOT POPULATED R129 C 10K 0R TXD3 TXD2 TXD1 TXD0 TX_EN PA11 PA10 PA13 PA12 PA16 R130 R49 S7 R55 R56 0R 10K R57 10K 10K 0R R131 R123 10K 0R R132 R124 10K 0R R127 R125 R126 R135 10K 0R 0R 10K 26 27 28 29 34 37 16 38 36 35 24 25 32 39 3V3 J15 C96 100NF 41 C97 100NF 30 C98 100NF 23 15 33 44 B R62 0R 10 40 NRST C89 22PF Y4 25MHz 1 2 C90 MN11 REF_CLK/XT2 XT1 TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK/ISOLATE RXD3/PHYAD3 RXD2/PHYAD2 RXD1/PHYAD1 RXD0/PHYAD0 COL/RMII CRS/PHYAD4 TX- RX- AVDDR DM9161AEP AVDDT AGND AGND AGND DVDD 8 3 BGRESG 4 TX+ 1 2 TD- TX- 2 3 RD+ RX+ 3 RX- 6 C BGRES LEDMODE LED0/OP0 LED1/OP1 LED2/OP2 CABLESTS/LINKSTS RESET N.C 6 RD- 1 L3 742792093 C91 100NF C92 100NF 2 VCCA 9 C101 10µF 10V R53 49R9 1% R54 49R9 1% C102 100NF GND_ETH 75 75 1nF 4 7 8 J00-0061NL GND_ETH RR6 10K 75 8 3V3 R58 6,80K 1% RJ45 ETHERNET CONNECTOR 3V3 DS2 DS3 DS4 45 75 7 NC 5 GND_ETH C95 100NF 47 48 31 11 12 13 14 VCCA C93 10V 10µF C94 100NF 5 6 46 DVDD PW RDW N J14 1 TD+ 7 5 CT AVDDR DISMDIX DGND DGND DGND R52 49R9 1% 4 CT RX+ TX_ER/TXD4 RX_ER/RXD4/RPTR DVDD R51 49R9 1% GND_ETH VCCA RX_CLK/10BTSER RX_DV/TESTMODE MDC MDIO MDINTR TX+ 43 100NF 16 Y3 15 VDD 50 MHz 2 VSS OUT 3 8 7 6 5 1 OE 1 2 3 4 R48 YELLOW GREEN GREEN 1K 1K 1K R59 FULL DUPLEX R61 SPEED 100 R63 LINK&ACT B 3V3 C99 10µF 10V R64 0R R65 0R GND_ETH A A D C B A INIT EDIT REV MODIF. AT91SAM9G20-EK SCALE PP PP PP TVT DES. 06/03/09 07/10/08 02/07/08 15/04/08 DATE 1/1 7 6 5 4 3 2 DATE REV. SHEET D ETHERNET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 VER. 1 5 7 5 4 3 5V J16 CCUSBA-32002-30X B1 B2 B3 B4 F2 500 mA USB HOST INTERFACE A1 A2 A3 A4 D 1211 109 R66 R67 C110 47pF C111 47pF R70 3V3 DTXD NOT POPULATED DRXD PB14 R74 R76 27R 27R R72 0R R73 0R V+ C2- 11 V- SERIAL DEBUG PORT C105 100NF MALE RIGHT ANGLED C107 100NF 6 1 6 2 7 3 8 4 9 5 RXD TXD 13 R 9 2 7 T 12 15 C104 100NF 14 T 10 HDMB HDPB C113 47pF R77 R75 0R 8 R D J17 R78 R80 100K R82 C 0R PC5 R84 22K 3V3 TXD1 PB6 RTS1 PB28 RXD1 PB7 R87 NOT POPULATED C119 NOT POPULATED J19 PB29 0R R86 0R R88 0R C1C2+ 5 0R R85 GND 2 R89 27R 4 3 R90 27R V- 15 RS232 COM PORT 1 C115 100NF MALE RIGHT ANGLED 2 C116 100NF 6 1 6 2 7 3 8 4 9 5 RXD RTS TXD CTS C118 100NF 7 T 12 16 14 T 10 C 13 R 9 8 R J18 ADM3202ARN DDM DDP C123 15PF V+ C2- 11 USB DEVICE INTERFACE 1 5 CTS1 R83 VCC 3V3 10 15K R81 C1+ 3 4 C117 100NF R79 100K MN13 1 C114 100NF 3V3 NOT POPULATED 6 GND 16 ADM3202ARN C112 47pF C120 100NF VCC C1C2+ 5 R69 0R R68 100K R71 C1+ 3 4 C106 100NF HDMA HDPA PB15 C109 100NF C108 100NF 27R 27R 3V3 MN12 1 C103 100NF 1 11 F1 500 mA 2 11 6 10 7 3V3 C124 15PF C121 100NF R92 100K C127 100NF R91 100K RTS0 PB26 TXD0 PB4 B DTR0 0R R95 0R R96 0R MN14 C1+ VCC 26 GND 25 24 1 C1C2+ V+ 27 2 C2- V- 3 14 T1IN T1OUT 9 13 T2IN T2OUT 10 12 T3IN T3OUT 11 T T T 3V3 RS232 COM PORT 0 C122 100NF MALE RIGHT ANGLED C125 100NF 1 6 2 7 3 8 4 9 5 DCD DSR RXD RTS TXD CTS DTR RI C126 100NF B 10 PB24 R94 R93 100K 28 21 R J20 20 DCD0 PB23 DSR0 PB22 RXD0 PB5 CTS0 PB27 RI0 PB25 R98 0R R101 0R R103 0R R104 0R R105 0R R106 0R 11 8 R 19 R1OUT 18 R2OUT 17 R3OUT 16 R4OUT 15 R5OUT 23 EN R R R R R R1IN 4 R2IN 5 R3IN 6 R4IN 7 R5IN 8 SHDN 22 3V3 MAX3241E A A R107 100K D C B A INIT EDIT REV MODIF. AT91SAM9G20-EK SCALE PP PP PP TVT DES. 06/03/09 07/10/08 02/07/08 15/04/08 DATE 1/1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 7 6 5 4 3 2 DATE REV. SHEET D SERIAL INTERFACES 8 VER. 1 6 7 8 7 6 5 4 3 2 1 J25 Interposer 100 TOP PA[0..31] PB[0..31] PC[0..15] J23 D RR8-2 RR8-4 RR7-2 RR7-4 0R 0R 0R 0R PA1 PA3 PA5 PA7 PA9 PA11 PA13 PA15 PA17 PA19 PA21 PA23 PA25 PA27 PA29 PA31 2 4 2 4 7 5 7 5 3V3 J26 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 8 6 8 6 1 3 1 3 PA0 PA2 PA4 PA6 PA8 PA10 PA12 PA14 PA16 PA18 PA20 PA22 PA24 PA26 PA28 PA30 RR8-1 RR8-3 RR7-1 RR7-3 0R 0R 0R 0R 3V3 PB1 PB3 PB5 PB7 PB9 PB11 PB13 PB15 PB17 PB19 PB21 PB23 PB25 PB27 PB29 PB31 3V3 PIO A 3V3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB0 PB2 PB4 PB6 PB8 PB10 PB12 PB14 PB16 PB18 PB20 PB22 PB24 PB26 PB28 PB30 A24 CFCE2 CFCS1_NCS5 NCS2 NCS6 NWAIT PC1 PC3 PC5 PC7 PC9 PC11 PC13 PC15 D17 D19 D21 D23 D25 D27 D29 D31 PC5 PC7 PC9 PC11 PC13 PC15 3V3 3V3 AVDD AGND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PC0 PC2 PC4 PC6 PC8 PC10 PC12 PC14 D16 D18 D20 D22 D24 D26 D28 D30 3V3 PC4 PC6 PC8 PC10 PC12 PC14 A23 CFCE1 CFCS0_NCS4 A25_CFRNW NCS7 NANDCS_NCS3 VREFP PIO C & ADC C133 100NF C C131 10V 10µF D[0..31] J24 PIO B 1V0 C130 100NF A[0..22] A0 NBS0_A0 A1 NWR2_NBS2_A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 C132 10V 10µF J28 R108 PC4 PA24 PIO_CNTRL1 TWCK PB21 PB23 PB25 PB27 PB11 PB13 ISI_DATA[1] ISI_DATA[3] ISI_DATA[5] ISI_DATA[7] ISI_DATA[9] ISI_DATA[11] 0R 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 R109 0R PB19 PA23 PB31 PB29 PB30 PB28 PB20 PB22 PB24 PB26 PB10 PB12 CFIOW _NBS3_NW R3 CFOE_NRD SDW E SDCKE CAS RAS PIO_CNTRL2 TWD ISI_MCK ISI_VSYNC ISI_HSYNC ISI_PCK ISI_DATA[0] ISI_DATA[2] ISI_DATA[4] ISI_DATA[6] ISI_DATA[8] ISI_DATA[10] D0 D1 D2 D5 D6 D7 D10 D11 D12 D15 D16 D17 D20 D21 D22 D25 D26 D27 D30 D31 A0 A3 A4 A5 A8 A9 A10 A13 A14 A15 A18 A19 A20 PC4 PC5 PC10 PC11 PC14 PC8 PC9 PC7 PC12 NANDOE NANDW E SPARE2 IMAGE SENSOR CONNECTOR PB19 PB20 PB21 NBS0_A0 A23 A24 A25_CFRNW NCS2 NANDCS_NCS3 CFCS0_NCS4 CFCS1_NCS5 CFCE2 NCS7 A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C4 A5 B5 C5 A6 B6 C6 A7 B7 C7 A8 B8 C8 A9 B9 C9 A10 B10 C10 A11 B11 C11 A12 B12 C12 A13 B13 C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 A17 B17 C17 A18 B18 C18 A19 B19 C19 A20 B20 C20 E1 D1 E2 D2 D4 D3 E3 D3 D9 D8 E4 D4 D14 D13 E5 D5 D19 D18 E6 D6 D24 D23 E7 D7 D29 D28 E8 D8 A2 A1 NWR2_NBS2_A1 E9 D9 A7 A6 D E10 A12 D10 A11 E11 A17 D11 A16 E12 A22 D12 A21 C E13 D13 SDCS_NCS1 NCS0 E14 D14 CFW E_NW E_NW R0 CFIOR_NBS1_NW R1 E15 D15 SDA10 SDCK E16 PC13 D16 PC15 NCS6 NWAIT E17 PC6 D17 CFCE1 E18 D18 E19 PB30 D19 SPARE1 SPARE0 E20 D20 NRST B B EBI CONNECTORS NOT POPULATED 3V3 Z15 J31-1 C134 47 uF 6V3 USER INTERFACE J31-2 3V3 NOT POPULATED C135 100NF GREEN R118 220R PB8 PA30 J31-3 CR2 3.3V BP3 DS5 A A PA31 D C B A INIT EDIT BP4 REV MODIF. AT91SAM9G20-EK EXPANSION_UI PP PP PP TVT DES. 06/03/09 07/10/08 02/07/08 15/04/08 DATE 1/1 SCALE 7 6 5 4 3 2 DATE REV. SHEET D This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 VER. 1 7 7 Section 6 Errata 6.1 Wrong Silkscreen of BB and 1.0V on the Board There is a silkscreen reversion on the board, for the selection of the VDDBU source: On J10 position 1-2, the marking should be ‘BB’ for Battery Backup instead of ‘1.0V’ On J10 position 2-3, the marking should be ‘1.0V’ instead of ‘BB’. This erratum is not applicable for AT91SAM9G20-EK Rev. C and later versions. 6.2 Choice of an Oscillator Capacitance For many reasons at the manufacturing level, Atmel does not specify any crystal references at the board design stage. Because of that, the user can find an inconsistency in the value of the used capacitance of the 18.432 MHz crystal on each pin (C23, C24), and the nominal load capacitance of the crystal. As a reminder, here is the way to select these values.The electrical parameter allows you to fit the right values provided by the crystal manufacturer - and not by Atmel. They are called "Load Capacitance" of the crystal. You have to take stray capacitances (package, socket, trace) into account in order to be close enough to the equivalent nominal Load Capacitance. With the on-board HCM49-18.432MABJT crystal reference, 10 pF capacitances have been fitted on the 18.432 MHz crystal for a nominal 27 pF load capacitance. 6.3 SD Card Slots and Booting Capability On the board, Slot J13 is incorrectly marked with a “bootable” mention (solder side). This should be applied to J35 instead. However, the schematic entitled ” Memory” attached to this User Guide, in Section 5.1 ”Schematics” does represent the correct location and marking. AT91SAM9G20-EK Evaluation Board User Guide 6-1 6413C–ATARM–18-Feb-09 Errata 6-2 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide Section 7 Revision History 7.1 Revision History Table 7-1. Document Comments Change Request Ref 6413C Section 6.3 ”SD Card Slots and Booting Capability”, added to errata 6874 6413B Errata section created with Section 6.1 ”Wrong Silkscreen of BB and 1.0V on the Board” 5413 Section 6.2 ”Choice of an Oscillator Capacitance” added to errata 6392 New schematics pdf file (at91sam9g20-ek revc.pdf) attached to Section 5.1 ”Schematics” 5936 - Section 1.2 ”Deliverables” on page 1-1, last bullet added - Section 3.8 ”Power Supply Circuitry” on page 3-5, last bullet added - PA23-24 rows edited in Table 3-1 on page 3-7 - 2 rows (J33-34) added to Table 4-1 on page 4-1 5851 - Section 1.3 ”AT91SAM9G20-EK Evaluation Board” on page 1-1: ‘one’ DataFlash changed to ‘two’ - 3 figures changed: Figure 2-1 on page 2-2, Figure 2-2 on page 2-3, and Figure 2-3 on page 2-5 - Typo in Section 2.6 ”Getting Started” on page 2-4: ‘tools’ instead of ‘tool’ - 4 bullets removed from Section 3.11 ”User Interface” on page 3-6 - 2 bullets edited in Section 3.13 ”Expansion Slot” on page 3-6 - PA6 to PA11 rows edited in Table 3-1 on page 3-7 - PB0 and PB8-9 rows edited in Table 3-2 on page 3-8 - A paragraph added at the end of Section 4.5 ”Ethernet” on page 4-3 RFO 6413A First Issue AT91SAM9G20-EK Evaluation Board User Guide 7-1 6413C–ATARM–18-Feb-09 Revision History 7-2 6413C–ATARM–18-Feb-09 AT91SAM9G20-EK Evaluation Board User Guide Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support AT91SAM Support Atmel techincal support Sales Contacts www.atmel.com/contacts/ Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, DataFlash ® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM ®, Thumb ®, the ARMPowered® logo and others are registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. 6413C–ATARM–18-Feb-09