NOIP1SN5000A D

NOIP1SN5000A,
NOIP1SN2000A
PYTHON 5.0/2.0 MegaPixels
Global Shutter CMOS Image
Sensors
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Features
• 5 MegaPixels: 2592 x 2048 Active Pixels
2 MegaPixels: 1920 x 1200 Active Pixels
• 4.8 mm x 4.8 mm Low Noise Global Shutter Pixels with
In-pixel CDS
• Monochrome (SN), Color (SE) and NIR (FN)
• Zero ROT Mode Enabling Higher Frame Rate
• Frame Rate at Full Resolution/HD (LVDS)
♦ 100/85 frames per second @ 5 MP (Zero ROT/Non−Zero ROT)
♦ 230/180 frames per second @ 2 MP (Zero ROT/Non−Zero ROT)
♦ 250/200 frames per second @ Full HD (Zero ROT/Non−Zero ROT)
• On-chip 10-bit Analog-to-Digital Converter (ADC)
• 8-bit or 10-bit Output Mode
• Eight Low Voltage Differential Signaling (LVDS) High
Speed Serial Outputs
Figure 1. PYTHON 5000
• Random Programmable Region of Interest (ROI)
Readout
• Pipelined and Triggered Global Shutter
• LVDS Channel Multiplexing
• On-chip Fixed Pattern Noise (FPN) Correction
• Serial Peripheral Interface (SPI)
• Automatic Exposure Control (AEC)
The sensor has on-chip programmable gain amplifiers and
• Phase Locked Loop (PLL)
10-bit A/D converters. The integration time and gain
• High Dynamic Range (HDR)
parameters can be reconfigured without any visible image
artifact. Optionally the on-chip automatic exposure control
• Dual Power Supply (3.3 V and 1.8 V)
loop (AEC) controls these parameters dynamically. The
• −40°C to +85°C Operational Temperature Range
image’s black level is either calibrated automatically or can
• 84-pin LCC
be adjusted by adding a user programmable offset.
• 1.5 W Power Dissipation
A high level of programmability using a four wire serial
• These Devices are Pb−Free and are RoHS Compliant
peripheral interface enables the user to read out specific
Applications
regions of interest. Up to sixteen regions can be
programmed, achieving even higher frame rates.
• Machine Vision
The image data interface part consists of eight LVDS
• Motion Monitoring
lanes,
facilitating frame rates up to 100 frames per second in
• Security
Zero
ROT
mode. Each channel runs at 720 Mbps. A separate
• Intelligent Traffic Systems (ITS)
synchronization channel containing payload information is
Description
provided to facilitate the image reconstruction at the
The PYTHON’s high sensitivity 4.8 mm x 4.8 mm pixels
receiving end.
support low noise “pipelined” and “triggered” global shutter
The PYTHON medium resolution family is packaged in
readout modes. In global shutter mode, the sensor supports
a 84-pin LCC package and is available in a monochrome and
correlated double sampling (CDS) readout, reducing noise
color version. For more information, please contact your
and increasing dynamic range.
local distributor or email us at [email protected].
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 0
1
Publication Order Number:
NOIP1SN5000A/D
NOIP1SN5000A, NOIP1SN2000A
ORDERING INFORMATION
Part Number
Family
NOIP1SN5000A−QDI
PYTHON 5000
Description
5 MegaPixel, LVDS color micro lens
NOIP1FN5000A−QDI
5 MegaPixel, LVDS mono micro lens, NIR Spectrum
PYTHON 2000
Product Status
84−pin LCC
Production:
Q1, 2015
5 MegaPixel, LVDS mono micro lens
NOIP1SE5000A−QDI
NOIP1SN2000A−QDI
Package
2 MegaPixel, LVDS mono micro lens
NOIP1SE2000A−QDI
2 MegaPixel, LVDS color micro lens
NOIP1FN2000A−QDI
2 MegaPixel, LVDS mono micro lens, NIR Spectrum
The P1−SN/SE base part is used to reference the mono, color and NIR enhanced versions of the LVDS interface. More details
on the part number coding can be found at http://www.onsemi.com/pub_link/Collateral/TND310−D.PDF
Package Mark
Line 1: NOI P1xx RRRRA where xx denotes mono micro lens (SN) or color micro lens (SE) option or NIR micro lens (FN),
RRRR is the resolution (5000), (2000)
Line 2: −QDI
Line 3: AWLYYWW where AWL is PRODUCTION lot traceability, YYWW is the 4−digit date code
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NOIP1SN5000A, NOIP1SN2000A
SPECIFICATIONS
Key Specifications
Table 2. NOMINAL ELECTRO−OPTICAL
SPECIFICATIONS
Table 1. GENERAL SPECIFICATIONS (Note 1)
Parameter
Specification
Parameter
Specification
Pixel Type
Global shutter pixel architecture
Shutter Type
Pipelined and triggered global shutter
Active Pixels
5 MegaPixels: 2592 (H) x 2048 (V)
2 MegaPixels: 1984 (H) x 1264 (V)
Frame Rate
at Full Resolution
100 frames per second @ 5 MegaPixels
230 frames per second @ 2 MegaPixels
250 frames per second @ Full HD
Pixel Size
4.8 mm x 4.8 mm
Conversion Gain
0.107 LSB10/e-, 143 mV/e-
Temporal Noise
< 10.7 e- (Non−Zero ROT, 1x gain)
< 9.4 e- (Non−Zero ROT, 2x gain)
Responsivity at 550 nm
7.5 V/lux.s
Parasitic Light
Sensitivity (PLS)
<1/5000
Full Well Charge
10000 e-
Master Clock
72 MHz when PLL is used,
360 MHz (10-bit) / 288 MHz (8-bit) when PLL
is not used
Windowing
16 Randomly programmable windows.
Normal, sub-sampled and binned readout
modes
ADC Resolution
(Note 1)
10-bit, 8-bit
LVDS Outputs
8 data + sync + clock
Quantum Efficiency
(QE x FF)
57%
Data Rate
8 x 720 Mbps (10-bit) /
8 x 576 Mbps (8-bit)
Pixel FPN
< 1.25 (Non−Zero ROT)
< 1.35 (Zero−ROT)
Power Dissipation
1.5 W in 10-bit mode
PRNU
< 10 LSB10
Package Type
84-pin LCC
MTF
63% @ 535 nm − X-dir & Y-dir
63% @ 535 nm − X-dir & Y-dir (NIR)
PSNL @ 20°C
(t_int = 30 ms)
300 LSB10/s, 2800 e-/s
Dark Signal @ 20°C
9.3 e-/s, 1.0 LSB10/s
Dynamic Range
60 dB
Signal to Noise Ratio
(SNR max)
40 dB
Table 3. RECOMMENDED OPERATING RATINGS (Note 2)
Symbol
TJ
Description
Operating temperature range
Min
Max
Unit
−40
85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. ABSOLUTE MAXIMUM RATINGS (Notes 3 and 4)
Min
Max
Unit
ABS (1.8 V supply group)
Symbol
ABS rating for 1.8 V supply group
–0.5
2.2
V
ABS (3.3 V supply group)
ABS rating for 3.3 V supply group
–0.5
4.3
V
ABS storage temperature range
−40
+150
°C
85
%RH
TS
Parameter
ABS storage humidity range at 85°C
Electrostatic discharge (ESD)
LU
Human Body Model (HBM): JS−001−2012
2000
Charged Device Model (CDM): EIA/JESD22−C101, Class C1
500
Latch−up: JESD−78
100
V
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The ADC is 11−bit, down−scaled to 10−bit. The PYTHON uses a larger word−length internally to provide 10−bit on the output.
2. Operating ratings are conditions in which operation of the device is intended to be functional.
3. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer
to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.
4. Caution needs to be taken to avoid dried stains on the underside of the glass due to condensation. The glass lid glue is permeable and can
absorb moisture if the sensor is placed in a high % RH environment.
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NOIP1SN5000A, NOIP1SN2000A
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6, 7, 8 and 9)
Parameter
Description
Min
Typ
Max
3.3
3.6
Unit
Power Supply Parameters − P1−SN/SE LVDS
(Note: All ground pins (gnd_18, gnd_33 and gnd_colpc) should be connected to an external 0 V ground reference.)
vdd_33
Supply voltage, 3.3 V
Idd_33
Current consumption 3.3 V supply
vdd_18
Supply voltage, 1.8 V
Idd_18
Current consumption 1.8 V supply
vdd_pix
Supply voltage, pixel
Idd_pix
Current consumption pixel supply
35
Ptot
Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
1.5
Pstby_lp
Power consumption in low power standby mode
Popt
Power consumption at lower pixel rates
3.0
345
1.8
1.6
2.0
140
3.3
3.25
V
mA
V
mA
3.35
V
mA
W
50
mW
Configurable
I/O − P1−SN/SE LVDS (EIA/TIA−644): Conforming to standard/additional specifications and deviations listed
fserdata
Data rate on data channels
DDR signaling − 4 data channels, 1 synchronization channel
720
Mbps
fserclock
Clock rate of output clock
Clock output for mesochronous signaling
360
MHz
Vicm
LVDS input common mode level
Tccsk
Channel to channel skew (Training pattern should be used to correct
per channel skew)
0.3
1.25
1.8
V
50
ps
72
MHz
360
MHz
Electrical Interface − P1−SN/SE LVDS
fin
Input clock rate when PLL used
fin
Input clock when LVDS input used
tidc
Input clock duty cycle when PLL used
tj
fspi
45
50
55
%
Input clock jitter
20
ps
SPI clock rate when PLL used at fin = 72 MHz
10
MHz
Max
Units
Frame Specifications − P1−SN/SE−LVDS
Typical
Non−Zero ROT
Zero ROT
fps_roi1
Xres x Yres = 2592 x 2048
85
100
fps
fps_roi2
Xres x Yres = 2048 x 2048
100
130
fps
fps_roi3
Xres x Yres = 1920 x 1200
180
230
fps
fps_roi4
Xres x Yres = 1920 x 1080
200
250
fps
fps_roi5
Xres x Yres = 1600 x 1200
205
275
fps
fps_roi6
Xres x Yres = 1024 x 1024
320
480
fps
fps_roi7
Xres x Yres = 1280 x 720
390
550
fps
fps_roi8
Xres x Yres = 800 x 600
615
985
fps
fps_roi9
Xres x Yres = 640 x 480
845
1450
fps
fps_roi10
Xres x Yres = 512 x 512
880
1555
fps
fps_roi11
Xres x Yres = 256 x 256
2035
2790
fps
fps_roi12
Xres x Yres = 544 x 20
7925
10400
fpix
Pixel rate (8 channels at 72 Mpix/s)
fps
576
Mpix/s
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All parameters are characterized for DC conditions after thermal equilibrium is established.
6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is
recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high
impedance circuit.
7. Minimum and maximum limits are guaranteed through test and design.
8. Refer to ACSPYTHON5000 available at CISP extranet for detailed acceptance criteria specifications.
9. For power supply management recommendations, please refer to Application Note AND9158.
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4
NOIP1SN5000A, NOIP1SN2000A
Color Filter Array
The PYTHON color sensors are processed with a Bayer RGB color pattern as shown in Figure 2. Pixel (0,0) has a red filter
situated to the bottom left.
Y
X
pixel (0;0)
Figure 2. Color Filter Array for the Pixel Array
Spectral Response Curve
6000
Red
Green1
Green2
Blue
Mono
Response [V/s/W/m2]
5000
4000
3000
2000
1000
0
300
400
500
600
700
800
900
Wavelength [nm]
Figure 3. Spectral Response Curve for Mono and Color
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5
1000
1100
NOIP1SN5000A, NOIP1SN2000A
7000
NIR
STANDARD
6000
Response [V/s/W/m2]
5000
4000
3000
2000
1000
0
300
400
500
600
700
800
900
1000
1100
Wavelength [nm]
Figure 4. Spectral Response Curve for Standard and NIR Mono
Ray Angle and Microlens Array Information
versus photodiode position will cause a tilted angle of peak
photoresponse, here denoted Chief Ray Angle (CRA).
Microlenses and photodiodes are aligned with 0 shift and
CRA in the center of the array, while the shift and CRA
increases radially towards its edges, as illustrated by
Figure 7.
The purpose of the shifted microlenses is to improve the
uniformity of photoresponse when camera lenses with
a finite exit pupil distance are used. In the standard version
of Python 5000, the CRA varies nearly linearly with distance
from the center as illustrated in Figure 8, with a corner CRA
of approximately 5.4 degrees. This edge CRA is matching
a lens with exit pupil distance of ~80 mm.
An array of microlenses is placed over the CMOS pixel
array in order to improve the absolute responsivity of the
photodiodes. The combined microlens array and pixel array
has two important properties:
Angular Dependency of Photoresponse of a Pixel
The photoresponse of a pixel with microlens in the center
of the array to a fixed optical power with varied incidence
angle is as plotted in Figure 5, where definitions of angles
fx and fy are as described by Figure 6.
Microlens Shift across Array and CRA
The microlens array is fabricated with a slightly smaller
pitch than the array of photodiodes. This difference in pitch
creates a varying degree of shift of a pixel’s microlens with
regards to its photodiode. A shift in microlens position
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NOIP1SN5000A, NOIP1SN2000A
Figure 5. Center Pixel Photoresponse to a Fixed Optical Power with Incidence Angle Varied along fx and fy.
Note that the Photoresponse Peaks near Normal Incidence for Center Pixels
Figure 6. Definition of Angles Used in Figure 5
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NOIP1SN5000A, NOIP1SN2000A
Figure 7. Principle of Microlens Shift. The Center Axes of the Microlens and the Photodiode Coincide
for the Center Pixels. For the Edge Pixels, there is a Shift between the Axes of the Microlens and the Photodiode
Causing a Peak Response Incidence Angle (CRA) that Deviates from the Normal of the Pixel Array
Figure 8. Variation of Peak Responsivity Angle (CRA) as a Function of Distance from the Center of the Array
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NOIP1SN5000A, NOIP1SN2000A
OVERVIEW
Figures 9 gives an overview of the major functional blocks of the PYTHON sensor.
Image Core
Row Dec od er
Image Core Bias
Pixel Array
Column Structure
Automatic
Exposure
Control
(AEC)
16 Analog channels
Analog Front End (AFE)
16 x 10 bit
Digital channels
Control &
Registers
Clock
Distribution
Data Formatting
8 x 10 bit
Digital channels
Re set
LVDS Clock
Input
SPI Interface
CMOS Clock
Input
Serializers & LVDS Interface
LVDS
Receiver
External Trigger s
PLL
8/4/2/1 LVDS Channels
1 LVDS Sync Channel
1 LVDS Clock Channel
Figure 9. Block Diagram
Image Core
LVDS Clock Receiver
The image core consists of:
• Pixel Array
• Address Decoders and Row Drivers
• Pixel Biasing
The PYTHON 5000 pixel array contains 2592 (H) x
2048 (V) readable pixels with a pixel pitch of 4.8 mm. Four
dummy pixel rows and columns are placed at every side of
the pixel array to eliminate possible edge effects. The sensor
uses in−pixel CDS architecture, which makes it possible to
achieve a low noise read out of the pixel array in global
shutter mode with CDS.
The PYTHON 2000 image array contains 1984 (H) x
1264 (V) readable pixels, inclusive of 32 pixels on each side
to allow for reprocessing or color reconstruction.
The function of the row drivers is to access the image array
to reset or read the pixel data. The row drivers are controlled
by the on−chip sequencer and can access the pixel array.
The pixel biasing block guarantees that the data on a pixel
is transferred properly to the column multiplexer when the
row drivers select a pixel line for readout.
The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Typical input clock frequency is 360 MHz in 10−bit mode
and 288 MHz in 8−bit mode. The clock input needs to be
terminated with a 100 W resistor.
Column Multiplexer
All pixels of one image row are stored in the column
sample−and−hold (S/H) stages. These stages store both the
reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 16 parallel differential outputs operating at a
frequency of 36 MHz. At this stage, the reset signal and
integrated signal values are transferred into an
FPN−corrected differential signal. A programmable gain of
1x, 2x, or 4x can be applied to the signal. The column
multiplexer
also
supports
read−1−skip−1
and
read−2−skip−2 mode. Enabling this mode increases the
frame rate, with a decrease in resolution.
Bias Generator
The bias generator generates all required reference
voltages and bias currents used on chip. An external resistor
of 47 kW, connected between pin IBIAS_MASTER and
gnd_33, is required for the bias generator to operate
properly.
Phase Locked Loop
The PLL accepts a (low speed) clock and generates the
required high speed clock. Optionally this PLL can be
bypassed. Typical input clock frequency is 72 MHz.
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NOIP1SN5000A, NOIP1SN2000A
Analog Front End
In addition to the LVDS data outputs, two extra LVDS
outputs are available. One of these outputs carries the output
clock, which is skew aligned to the output data channels. The
second LVDS output contains frame format synchronization
codes to serve system−level image reconstruction.
The AFE contains 16 channels, each containing a PGA
and a 10−bit ADC.
For each of the 16 channels, a pipelined 10−bit ADC is
used to convert the analog image data into a digital signal,
which is delivered to the data formatting block. A black
calibration loop is implemented to ensure that the black level
is mapped to match the correct ADC input level.
Channel Multiplexer
The LVDS channel multiplexer provides a 8:4, 8:2 and 8:1
feature, in addition to utilizing all 8 output channels.
Data Formatting
The data block receives data from two ADCs and
multiplexes this data to one data stream. A cyclic
redundancy check (CRC) code is calculated on the passing
data.
A frame synchronization data block transmits
synchronization codes such as frame start, line start, frame
end, and line end indications.
The data block calculates a CRC once per line for every
channel. This CRC code can be used for error detection at the
receiving end.
Sequencer
Serializer and LVDS Interface
•
The sequencer:
• Controls the image core. Starts and stops integration
•
•
•
The serializer and LVDS interface block receives the
formatted (10−bit or 8−bit) data from the data formatting
block. This data is serialized and transmitted by the LVDS
output driver.
In 10−bit mode, the maximum output data rate is
720 Mbps per channel. In 8−bit mode, the maximum output
data rate is 576 Mbps per channel.
and control pixel readout.
Operates the sensor in master or slave mode.
Applies the window settings. Organizes readouts so that
only the configured windows are read.
Controls the column multiplexer and analog core.
Applies gain settings and subsampling modes at the
correct time, without corrupting image data.
Starts up the sensor correctly when leaving standby
mode.
Automatic Exposure Control
The AEC block implements a control system to modulate
the exposure of an image. Both integration time and gains
are controlled by this block to target a predefined
illumination level.
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NOIP1SN5000A, NOIP1SN2000A
OPERATING MODES
Global Shutter Mode
The PYTHON operates in pipelined or triggered global
shutter modes. In this mode, light integration takes place on
all pixels in parallel, although subsequent readout is
sequential. Figure 10 shows the integration and readout
sequence for the global shutter mode. All pixels are light
sensitive at the same period of time. The whole pixel core is
reset simultaneously and after the integration time all pixel
values are sampled together on the storage node inside each
pixel. The pixel core is read out line by line after integration.
Note that the integration and readout can occur in parallel or
sequentially. The integration starts at a certain period,
relative to the frame start.
Figure 10. Global Shutter Operation
Pipelined Global Shutter Mode
Overhead Time (ROT). Figure 11 shows the exposure and
readout time line in pipelined global shutter mode.
In pipelined global shutter mode, the integration and
readout are done in parallel. Images are continuously read
and integration of frame N is ongoing during readout of the
previous frame N−1. The readout of every frame starts with
a Frame Overhead Time (FOT), during which the analog
value on the pixel diode is transferred to the pixel memory
element. After the FOT, the sensor is read out line per line
and the readout of each line is preceded by the Row
Reset
N
Integration Time
Handling
Readout
Handling
Master Mode
In this mode, the integration time is set through the
register interface and the sensor integrates and reads out the
images autonomously. The sensor acquires images without
any user interaction.
Exposure Time N
FOT
Reset
N+1
Exposure Time N+1
FOT
ÉÉÉÉ
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É
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ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
É
FOT
ROT
Readout Frame N-1
FOT
Readout Frame N
FOT
Line Readout
Figure 11. Pipelined Shutter Operation in Master Mode
of reset and integration starts. The integration continues
until the user or system deasserts the external pin. Upon a
falling edge of the trigger input, the image is sampled and the
readout begins. Figure 12 shows the relation between the
external trigger signal and the exposure/readout timing.
Slave Mode
The slave mode adds more manual control to the sensor.
The integration time registers are ignored in this mode and
the integration time is instead controlled by an external pin.
As soon as the control pin is asserted, the pixel array goes out
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NOIP1SN5000A, NOIP1SN2000A
External Trigger
Integration Time
Handling
Readout
Handling
Reset
N
FOT
Exposure Time N
FOT
Readout N−1
Reset
N+1
FOT
Exposure T im e N+1
Readout N
FOT
FOT
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
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É
É
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É
É
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É
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É
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ÉÉÉ
ÉÉÉ
ÉÉ
ROT
Line Readout
Figure 12. Pipelined Shutter Operation in Slave Mode
Triggered Global Shutter Mode
The triggered global shutter mode can also be controlled
in a master or in a slave mode.
Master Mode
In this mode, a rising edge on the synchronization pin is
used to trigger the start of integration and readout. The
integration time is defined by a register setting. The sensor
autonomously integrates during this predefined time, after
which the FOT starts and the image array is readout
sequentially. A falling edge on the synchronization pin does
not have any impact on the readout or integration and
subsequent frames are started again for each rising edge.
Figure 13 shows the relation between the external trigger
signal and the exposure/readout timing.
If a rising edge is applied on the external trigger before the
exposure time and FOT of the previous frame is complete,
it is ignored by the sensor.
In this mode, manual intervention is required to control
both the integration time and the start of readout. After the
integration time, indicated by a user controlled pin, the
image core is read out. After this sequence, the sensor goes
to an idle mode until a new user action is detected.
The three main differences with the pipelined global
shutter mode are:
• Upon user action, one single image is read.
• Normally, integration and readout are done
sequentially. However, the user can control the sensor
in such a way that two consecutive batches are
overlapping, that is, having concurrent integration and
readout.
• Integration and readout is under user control through an
external pin.
This mode requires manual intervention for every frame.
The pixel array is kept in reset state until requested.
No effect on falling edge
External Trigger
Integration Time
Handling
Reset
N
Exposure Time N
FOT
Reset
N+1
Exposure Time N+1
FOT
Readout N
FOT
Register Controlled
Readout
Handling
FOT
Readout N-1
FOT
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É
ÉÉ
É
ÉÉ
É
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É
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É
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É
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É
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É
É
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É
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ÉÉÉ
ÉÉÉÉ
ÉÉÉ
É
ROT
Line Readout
Figure 13. Triggered Shutter Operation in Master Mode
FOT starts. The analog value on the pixel diode is
transferred to the pixel memory element and the image
readout can start. A request for a new frame is started when
the synchronization pin is asserted again.
Slave Mode
Integration time control is identical to the pipelined
shutter slave mode. An external synchronization pin
controls the start of integration. When it is de−asserted, the
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12
NOIP1SN5000A, NOIP1SN2000A
Non−Zero and Zero Row Overhead Time (ROT) Modes
This operation mode can be used for two reasons:
In pipelined global shutter mode, the integration and
readout are done in parallel. Images are continuously read
out and integration of frame N is ongoing during readout of
the previous frame N−1. The readout of every frame starts
with a Frame Overhead Time (FOT), during which the
analog value of the pixel diode is transferred to the pixel
memory element. After the FOT, the sensor is read out line
by line and the readout of each line is preceded by a Row
Overhead Time (ROT) as shown in Figure 14.
In Reduced/Zero ROT operation mode (refer to
Figure 15), the row blanking and kernel readout occur in
parallel. This mode is called reduced ROT as a part of the
ROT is done while the image row is readout. The actual ROT
can thus be longer, however the perceived ROT will be
shorter (‘overhead’ spent per line is reduced).
(
FOT
)
ROT
ys
Readout
ys
• Reduced total line time.
• Lower power due to reduced clock−rate.
ROT
ys+1
Readout
ys
ROT
ye
Readout
ye
Valid Data
Figure 14. Integration and Readout Sequence of the Sensor Operating in Pipelined Global Shutter Mode with
Non−Zero ROT Readout.
(
FOT
)
ROT
ys
(blanked out)
ROT
ys+1
Readout
ys
ROT
ye
Readout
ye−1
ROT
dummy
Readout
ye
Valid Data
Figure 15. Integration and Readout Sequence of the Sensor operating in Pipelined Global Shutter Mode with
Zero ROT Readout.
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13
NOIP1SN5000A, NOIP1SN2000A
SENSOR OPERATION
Flowchart
Figure 16 shows the sensor operation flowchart. The sensor has six different ‘states’. Every state is indicated with the oval
circle. These states are Power off, Low power standby, Standby (1), Standby (2), Idle, Running.
Power Off
Power Down
Sequence
Power Up Sequence
Low-Power Standby
Disable Clock Management
Part 1
Poll Lock Indication
(only when PLL is enabled)
Standby (1)
Enable Clock Management - Part 2
(First Pass after Hard Reset)
Intermediate Standby
Required Register
Upload
Standby (2)
Sensor (re-)configuration
(optional)
Soft Power-Down
Soft Power-Up
Sensor (re-)configuration
(optional)
Idle
Disable Sequencer
Enable Sequencer
Running
Sensor (re-)configuration
(optional)
Figure 16. Sensor Operation Flowchart
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14
Assertion of reset_n Pin
Enable Clock Management - Part 2
(Not First Pass after Hard Reset)
Disable Clock Management
Part 2
Enable Clock Management - Part 1
NOIP1SN5000A, NOIP1SN2000A
Sensor States
power up sequence is finished and the first SPI upload can
be initiated.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
Low Power Standby
In low power standby state, all power supplies are on, but
internally every block is disabled. No internal clock is
running (PLL / LVDS clock receiver is disabled).
All register settings are set to their default values (see
Table 35).
Only a subset of the SPI registers is active for read/write
in order to be able to configure clock settings and leave the
low power standby state. The only SPI registers that should
be touched are the ones required for the ‘Enable Clock
Management’ action described in Enable Clock
Management − Part 1 on page 16
clock input
reset_n
vdd_18
vdd_33
Standby (1)
In standby state, the PLL/LVDS clock receiver is running,
but the derived logic clock signal is not enabled.
vdd_pix
SPI Upload
Standby (2)
> 10us
In standby state, the derived logic clock signal is running.
All SPI registers are active, meaning that all SPI registers
can be accessed for read or write operations. All other blocks
are disabled.
> 10us
> 10us
> 10us
> 10us
Figure 17. Power Up Sequence
Enable Clock Management − Part 1
The ‘Enable Clock Management’ action configures the
clock management blocks and activates the clock generation
and distribution circuits in a pre−defined way. First, a set of
clock settings must be uploaded through the SPI register.
These settings are dependent on the desired operation mode
of the sensor.
Table 6 shows the SPI uploads to be executed to configure
the sensor for P1−SN/SE 8−bit and 10−bit serial, with and
without the PLL.
If the PLL is not used, the LVDS clock input must be
running.
It is important to follow the upload sequence listed in
Table 6.
Idle
In the idle state, all internal blocks are enabled, except the
sequencer block. The sensor is ready to start grabbing
images as soon as the sequencer block is enabled.
Running
In running state, the sensor is enabled and grabbing
images. The sensor can be operated in global master/slave
modes.
User Actions: Power Up Functional Mode Sequences
Power Up Sequence
Figure 17 shows the power up sequence of the sensor. The
figure indicates that the first supply to ramp−up is the
vdd_18 supply, followed by vdd_33 and vdd_pix
respectively. It is important to comply with the described
sequence. Any other supply ramping sequence may lead to
high current peaks and, as consequence, a failure of the
sensor power up.
The clock input should start running when all supplies are
stabilized. When the clock frequency is stable, the reset_n
signal can be de−asserted. After a wait period of 10 ms, the
Use of Phase Locked Loop
If PLL is used, the PLL is started after the upload of the
SPI registers. The PLL requires (dependent on the settings)
some time to generate a stable output clock. A lock detect
circuit detects if the clock is stable. When complete, this is
flagged in a status register.
Check the PLL_lock flag 24[0] by reading the SPI
register. When the flag is set, the ‘Enable Clock
Management− Part 2’ action can be continued. When PLL
is not used, this step can be bypassed as shown in Figure 16
on page 14.
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15
NOIP1SN5000A, NOIP1SN2000A
Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #
Address
Data
Description
P1−SN/SE 8−bit mode with PLL
1
2
0x000C
Monochrome sensor
0x000D
Color sensor
2
32
0x000C
Configure clock management
3
20
0x0000
Configure clock management
4
17
0x210F
Configure PLL
5
26
0x1180
Configure PLL lock detector
6
27
0xCCBC
Configure PLL lock detector
7
8
0x0000
Release PLL soft reset
8
16
0x0003
Enable PLL
0x000C
Monochrome sensor
0x000D
Color sensor
P1−SN/SE 8−bit mode without PLL
1
2
2
32
0x0008
Configure clock management
3
20
0x0001
Enable LVDS clock input
P1−SN/SE 10−bit mode with PLL
1
2
0x000C
Monochrome sensor
0x000D
Color sensor
2
32
0x0004
Configure clock management
3
20
0x0000
Configure clock management
4
17
0x2113
Configure PLL
5
26
0x2280
Configure PLL lock detector
6
27
0x3D2D
Configure PLL lock detector
7
8
0x0000
Release PLL soft reset
8
16
0x0003
Enable PLL
P1−SN/SE 10−bit mode without PLL
1
2
2
32
3
20
0x000C
Monochrome sensor
0x000D
Color sensor
0x0000
Configure clock management
0x0001
Enable LVDS clock input
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NOIP1SN5000A, NOIP1SN2000A
Enable Clock Management − Part 2
The next step to configure the clock management consists of SPI uploads which enables all internal clock distribution. The
required uploads are listed in Table 7. Note that it is important to follow the upload sequence listed in Table 7.
Table 7. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #
Address
Data
Description
P1−SN/SE 8−bit mode with PLL
1
9
0x0000
Release clock generator soft reset
2
32
0x000E
Enable logic clock
3
34
0x0001
Enable logic blocks
P1−SN/SE 8−bit mode without PLL
1
9
0x0000
Release clock generator soft reset
2
32
0x000A
Enable logic clock
3
34
0x0001
Enable logic blocks
P1−SN/SE 10−bit mode with PLL
1
9
0x0000
Release clock generator soft reset
2
32
0x0006
Enable logic clock
3
34
0x0001
Enable logic block
P1−SN/SE 10−bit mode without PLL
1
9
0x0000
Release clock generator soft reset
2
32
0x0002
Enable logic clock
3
34
0x0001
Enable logic blocks
Required Register Upload
In this phase, the ‘reserved’ register settings are uploaded through the SPI register. Different settings are not allowed and
may cause the sensor to malfunction.
Table 8. REQUIRED REGISTER UPLOADS FOR
10−BIT, ZERO−ROT, PIPELINED GLOBAL SHUTTER
MASTER MODE
Upload #
Address
Data (Zero ROT)
1
41
0x0855
2
42
0x0003
3
43
0x0008
4
65
0xF8CB
5
66
0x53C8
6
67
0x8788
7
69
0x0888
8
70
0x4111
9
71
0x9788
10
72
0x3337
11
81
0x86A5
12
128
0x4714
13
129**
0x0001
14
171
0x1001
15
176
0x00F1
16
192
0x000C
17
193*
0x0800
Upload #
Address
Data (Zero ROT)
18
194
0x0224
19
197
0x0104
20
204
0x01E1
21
211
0x0E49
22
215
0x111F
23
216
0x7F00
24
219
0x0020
25
220
0x2434
26
224
0x3E07
27
227
0x0000
28
250
0x1081
29
384
0xC800
30
385
0xFB1F
31
386
0xFB1F
32
387
0xFB12
33
388
0xF912
34
389
0xF902
35
390
0xF804
36
391
0xF008
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NOIP1SN5000A, NOIP1SN2000A
Upload #
Address
Data (Zero ROT)
Upload #
Address
Data (Zero ROT)
37
38
392
0xF102
69
424
0x107F
393
0xF30F
70
425
0x1079
39
394
0xF30F
71
426
0x0071
40
395
0xF30F
72
427
0x0031
41
396
0xF30F
73
428
0x01B4
42
397
0xF30F
74
429
0x21B9
43
398
0xF30F
75
430
0x20B1
44
399
0xF102
76
431
0x00B1
45
400
0xF008
77
432
0x10BF
46
401
0xF24A
78
433
0x10B9
47
402
0xF264
79
434
0x00B1
48
403
0xF226
80
435
0x0030
49
404
0xF021
81
436
0x0030
50
405
0xF002
82
437
0x2079
51
406
0xF40A
83
438
0x2071
52
407
0xF005
84
439
0x0071
53
408
0xF20F
85
440
0x107F
54
409
0xF20F
86
441
0x1079
55
410
0xF20F
87
442
0x0071
56
411
0xF20F
88
443
0x0031
57
412
0xF005
89
444
0x01B4
58
413
0xEC05
90
445
0x21B9
59
414
0xC801
91
446
0x20B1
60
415
0xC800
92
447
0x00B1
61
416
0xC800
93
448
0x10BF
62
417
0xCC0A
94
449
0x10B9
63
418
0xC806
95
450
0x00B1
64
419
0xC800
96
451
0x0030
65
420
0x0030
Upload #
Address
Data (Non−Zero ROT)
66
421
0x2179
15
193*
0x5000
67
422
0x2071
Upload #
Address
Data (8−bit mode)
68
423
0x0071
13
129**
0x2001
*Required Uploads for Non−Zero ROT / 8−bit mode are the same as
for Zero ROT 10−bit mode with the exceptions noted.
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NOIP1SN5000A, NOIP1SN2000A
Soft Power Up
During the soft power up action, the internal blocks are enabled and prepared to start processing the image data stream. This
action exists of a set of SPI uploads. The soft power up uploads are listed in Table 9.
Table 9. SOFT POWER UP REGISTER UPLOADS
Upload #
Address
Data
Description
P1−SN/SE 8−bit mode with PLL
1
10
0x0000
Release soft reset state
2
32
0x000F
Enable analogue clock
3
64
0x0001
Enable biasing clock
4
40
0x0003
Enable column multiplexer
5
48
0x0001
Enable AFE
6
68
0x0085
Enable LVDS bias
7
72
0x3337
Enable charge pump
8
112
0x0007
Enable LVDS transmitters
P1−SN/SE 8−bit mode without PLL
1
10
0x0000
Release soft reset state
2
32
0x000B
Enable analogue clock
3
64
0x0001
Enable biasing clock
4
40
0x0003
Enable column multiplexer
5
48
0x0001
Enable AFE
6
68
0x0085
Enable LVDS bias
7
72
0x3337
Enable charge pump
8
112
0x0007
Enable LVDS transmitters
P1−SN/SE 10−bit mode with PLL
1
10
0x0000
Release soft reset state
2
32
0x0007
Enable analogue clock
3
64
0x0001
Enable biasing clock
4
40
0x0003
Enable column multiplexer
5
48
0x0001
Enable AFE
6
68
0x0085
Enable LVDS bias
7
72
0x3337
Enable charge pump
8
112
0x0007
Enable LVDS transmitters
P1−SN/SE 10−bit mode without PLL
1
10
0x0000
Release soft reset state
2
32
0x0003
Enable analogue clock
3
64
0x0001
Enable biasing clock
4
40
0x0003
Enable column multiplexer
5
48
0x0001
Enable AFE
6
68
0x0085
Enable LVDS bias
7
72
0x3337
Enable charge pump
8
112
0x0007
Enable LVDS transmitters
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NOIP1SN5000A, NOIP1SN2000A
Enable Sequencer
During the ‘Enable Sequencer’ action, the frame grabbing sequencer is enabled. The sensor starts grabbing images in the
configured operation mode. Refer to Sensor States on page 15.
The ‘Enable Sequencer’ action consists of a set of register uploads. The required uploads are listed in Table 10.
Table 10. ENABLE SEQUENCER REGISTER UPLOADS
Upload #
Address
Data
1
192
0x000D
User Actions: Functional Modes to Power Down Sequences
Disable Sequencer
During the ‘Disable Sequencer’ action, the frame grabbing sequencer is stopped. The sensor stops grabbing images and
returns to the idle mode.
The ‘Disable Sequencer’ action consists of a set of register uploads. as listed in Table 11.
Table 11. DISABLE SEQUENCER REGISTER UPLOAD
Upload #
Address
Data
1
192
0x000C
Soft Power Down
During the soft power down action, the internal blocks are disabled and the sensor is put in standby state to reduce the current
dissipation. This action exists of a set of SPI uploads. The soft power down uploads are listed in Table 12.
Table 12. SOFT POWER DOWN REGISTER UPLOADS
Upload #
Address
Data
Description
P1−SN/SE 8−bit mode with PLL
1
112
0x0000
Disable LVDS transmitters
2
72
0x3330
Disable charge pump
3
48
0x0000
Disable AFE
4
40
0x0000
Disable column multiplexer
5
64
0x0000
Disable biasing clock
6
32
0x000E
Disable analogue clock
7
10
0x0999
Soft reset
P1−SN/SE 8−bit mode without PLL
1
112
0x0000
Disable LVDS transmitters
2
72
0x3330
Disable charge pump
3
48
0x0000
Disable AFE
4
40
0x0000
Disable column multiplexer
5
64
0x0000
Disable biasing clock
6
32
0x000A
Disable analogue clock
7
10
0x0999
Soft reset
P1−SN/SE 10−bit mode with PLL
1
112
0x0000
Disable LVDS transmitters
2
72
0x3330
Disable charge pump
3
48
0x0000
Disable AFE
4
40
0x0000
Disable column multiplexer
5
64
0x0000
Disable biasing clock
6
32
0x0006
Disable analogue clock
7
10
0x0999
Soft reset
P1−SN/SE 10−bit mode without PLL
1
112
0x0000
Disable LVDS transmitters
2
72
0x3330
Disable charge pump
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NOIP1SN5000A, NOIP1SN2000A
Table 12. SOFT POWER DOWN REGISTER UPLOADS
Upload #
Address
Data
3
48
0x0000
Disable AFE
Description
4
40
0x0000
Disable column multiplexer
5
64
0x0000
Disable biasing clock
6
32
0x0002
Disable analogue clock
7
10
0x0999
Soft reset
Disable Clock Management − Part 2
The ‘Disable Clock Management’ action stops the internal clocking to further decrease the power dissipation. This action
can be implemented with the SPI uploads as shown in Table 13.
Table 13. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #
Address
Data
Description
P1−SN/SE 8−bit mode with PLL
1
32
0x000C
Disable logic clock
2
34
0x0000
Disable logic blocks
3
9
0x0009
Soft reset clock generator
P1−SN/SE 8−bit mode without PLL
1
32
0x0008
Disable logic clock
2
34
0x0000
Disable logic blocks
3
9
0x0009
Soft reset clock generator
P1−SN/SE 10−bit mode with PLL
1
32
0x0004
Disable logic clock
2
34
0x0000
Disable logic blocks
3
9
0x0009
Soft reset clock generator
P1−SN/SE 10−bit mode without PLL
1
32
0x0000
Disable logic clock
2
34
0x0000
Disable logic blocks
3
9
0x0009
Soft reset clock generator
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NOIP1SN5000A, NOIP1SN2000A
Disable Clock Management − Part 1
The ‘Disable Clock Management’ action stops the internal clocking to further decrease the power dissipation. This action
can be implemented with the SPI uploads as shown in Table 14.
Table 14. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #
Address
Data
Description
P1−SN/SE 8−bit mode with PLL
1
8
0x0099
Soft reset PLL
2
16
0x0000
Disable PLL
0x0000
Configure clock management
P1−SN/SE 8−bit mode without PLL
1
20
P1−SN/SE 10−bit mode with PLL
1
8
0x0099
Soft reset PLL
2
16
0x0000
Disable PLL
0x0000
Configure clock management
P1−SN/SE 10−bit mode without PLL
1
20
Power Down Sequence
Figure 18 illustrates the timing diagram of the preferred
power down sequence. It is important that the sensor is in
reset before the clock input stops running. Otherwise, the
internal PLL becomes unstable and the sensor gets into an
unknown state. This can cause high peak currents.
The same applies for the ramp down of the power
supplies. The preferred order to ramp down the supplies is
first vdd_pix, second vdd_33, and finally vdd_18. Any other
sequence can cause high peak currents.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
clock input
reset_n
vdd_18
vdd_33
vdd_pix
> 10us
> 10us
> 10us
> 10us
Figure 18. Power Down Sequence
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NOIP1SN5000A, NOIP1SN2000A
Sensor reconfiguration
Sensor Configuration
During the standby, idle, or running state several sensor
parameters can be reconfigured.
• Frame Rate and Exposure Time: Frame rate and
exposure time changes can occur during standby, idle,
and running states by modifying registers 199 to 203.
Refer to page 30−32 for more information.
• Signal Path Gain: Signal path gain changes can occur
during standby, idle, and running states by modifying
registers 204/205. Refer to page 37 for more
information.
• Windowing: Changes with respect to windowing can
occur during standby, idle, and running states. Refer to
Multiple Window Readout on page 31 for more
information.
• Subsampling: Changes of the subsampling mode can
occur during standby, idle, and running states by
modifying register 192. Refer to Subsampling on
page 32 for more information.
• Shutter Mode: The shutter mode can only be changed
during standby or idle mode by modifying register 192.
Reconfiguring the shutter mode during running state is
not supported.
This device contains multiple configuration registers.
Some of these registers can only be configured while the
sensor is not acquiring images (while register 192[0] = 0),
while others can be configured while the sensor is acquiring
images. For the latter category of registers, it is possible to
distinguish the register set that can cause corrupted images
(limited number of images containing visible artifacts) from
the set of registers that are not causing corrupted images.
These three categories are described here.
Static Readout Parameters
Some registers are only modified when the sensor is not
acquiring images. reconfiguration of these registers while
images are acquired can cause corrupted frames or even
interrupt the image acquisition. Therefore, it is
recommended to modify these static configurations while
the sequencer is disabled (register 192[0] = 0). The registers
shown in Table 15 should not be reconfigured during image
acquisition. A specific configuration sequence applies for
these registers. Refer to the operation flow and startup
description.
Table 15. STATIC READOUT PARAMETERS
Group
Addresses
Description
Clock generator
32
Configure according to recommendation
Image core
40
Configure according to recommendation
AFE
48
Configure according to recommendation
Bias
64–71
Configure according to recommendation
Charge Pump
72
Configure according to recommendation
LVDS
112
Configure according to recommendation
192 [6:1]
Operation modes are: • triggered_mode
• slave_mode
Sequencer mode selection
All reserved registers
Keep reserved registers to their default state, unless otherwise described in the recommendation
Dynamic Configuration Potentially Causing Image
Artifacts
image containing visible artifacts. A typical example of a
corrupted image is an image which is not uniformly
exposed.
The effect is transient in nature and the new configuration
is applied after the transient effect.
The category of registers as shown in Table 16 consists of
configurations that do not interrupt the image acquisition
process, but may lead to one or more corrupted images
during and after the reconfiguration. A corrupted image is an
Table 16. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS
Group
Addresses
Description
Black level configuration
128–129
197[12:8]
Reconfiguration of these registers may have an impact on the black−level
calibration algorithm. The effect is a transient number of images with incorrect black level compensation.
Sync codes
129[13]
116–126
Incorrect sync codes may be generated during the frame in which these registers are modified.
Datablock test configurations
144, 146–150
Modification of these registers may generate incorrect test patterns during
a transient frame.
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NOIP1SN5000A, NOIP1SN2000A
Dynamic Readout Parameters
shown in Table 17. Some reconfiguration may lead to one
frame being blanked. This happens when the modification
requires more than one frame to settle. The image is blanked
out and training patterns are transmitted on the data and sync
channels.
It is possible to reconfigure the sensor while it is acquiring
images. Frame related parameters are internally
resynchronized to frame boundaries, such that the modified
parameter does not affect a frame that has already started.
However, there can be restrictions to some registers as
Table 17. DYNAMIC READOUT PARAMETERS
Group
Addresses
Subsampling/binning
192[7]
192[8]
Description
Subsampling or binning is synchronized to a new frame start.
ROI configuration
195
256–303
A ROI switch is only detected when a new window is selected as the active window
(reconfiguration of register 195). reconfiguration of the ROI dimension of the active window does not
lead to a frame blank and can cause a corrupted image.
Exposure
reconfiguration
199−203
Exposure reconfiguration does not cause artifact. However, a latency of one frame is observed unless
reg_seq_exposure_sync_mode is set to ‘1’ in triggered global mode (master).
204
Gains are synchronized at the start of a new frame. Optionally, one frame latency can be incorporated
to align the gain updates to the exposure updates
(refer to register 204[13] − gain_lat_comp).
Gain reconfiguration
Freezing Active Configurations
them for the coming frames. The freezing of the active set
of registers can be programmed in the sync_configuration
registers, which can be found at the SPI address 206.
Figure 19 shows a reconfiguration that does not use the
sync_configuration option. As depicted, new SPI
configurations are synchronized to frame boundaries.
Figure 20 shows the usage of the sync_configuration
settings. Before uploading a set of registers, the
corresponding sync_configuration is de−asserted. After the
upload is completed, the sync_configuration is asserted
again and the sensor resynchronizes its set of registers to the
coming frame boundaries. As seen in the figure, this ensures
that the uploads performed at the end of frame N+2 and the
start of frame N+3 become active in the same frame (frame
N+4).
Though the readout parameters are synchronized to frame
boundaries, an update of multiple registers can still lead to
a transient effect in the subsequent images, as some
configurations require multiple register uploads. For
example, to reconfigure the exposure time in master global
mode, both the fr_length and exposure registers need to be
updated. Internally, the sensor synchronizes these
configurations to frame boundaries, but it is still possible
that the reconfiguration of multiple registers spans over two
or even more frames. To avoid inconsistent combinations,
freeze the active settings while altering the SPI registers by
disabling synchronization for the corresponding
functionality before reconfiguration. When all registers are
uploaded, re−enable the synchronization. The sensor’s
sequencer then updates its active set of registers and uses
Time Line
Frame NFrame N+1 Frame N+2 Frame N+3
Frame N+4
SPI Registers
Active Registers
Figure 19. Frame Synchronization of Configurations (no freezing)
Time Line
Frame NFrame N+1 Frame N+2 Frame N+3 Frame N+4
sync_configuration
This configuration is not taken into
account as sync_register is inactive.
SPI Registers
Active Registers
Figure 20. reconfiguration Using Sync_configuration
NOTE: SPI updates are not taken into account while sync_configuration is inactive. The active configuration is frozen
for the sensor. Table 18 lists the several sync_configuration possibilities along with the respective registers being
frozen.
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NOIP1SN5000A, NOIP1SN2000A
Table 18. ALTERNATE SYNC CONFIGURATIONS
Group
Affected Registers
Description
sync_black_lines
black_lines
Update of black line configuration is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
sync_exposure
mult_timer
fr_length
exposure
Update of exposure configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
sync_gain
mux_gainsw
afe_gain
Update of gain configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
sync_roi
roi_active0[15:0]
subsampling
binning
Update of active ROI configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
Note: The window configurations themselves are not frozen. reconfiguration of
active windows is not gated by this setting.
Window Configuration
Global Shutter Mode
Black Calibration
Up to 16 windows can be defined in global shutter mode
(pipelined or triggered). The windows are defined by
registers 256 to 303. Each window can be activated or
deactivated separately using register 195. It is possible to
reconfigure the inactive windows while the sensor is
acquiring images.
Switching between predefined windows is achieved by
activation of the respective windows. This way a minimum
number of registers need to be uploaded when it is necessary
to switch between two or more sets of windows. As an
example of this, scanning the scene at higher frame rates
using multiple windows and switching to full frame capture
when the object is tracked. Switching between the two
modes only requires an upload of one register.
The sensor automatically calibrates the black level for
each frame. Therefore, the device generates a configurable
number of electrical black lines at the start of each frame.
The desired black level in the resulting output interface can
be configured and is not necessarily targeted to ‘0’.
Configuring the target to a higher level yields some
information on the left side of the black level distribution,
while the other end of the distribution tail is clipped to ‘0’
when setting the black level target to ‘0’.
The black level is calibrated for the 16 columns contained
in one kernel. This implies 16 black level offsets are
generated and applied to the corresponding columns.
Configurable parameters for the black−level algorithm are
listed in Table 19.
Table 19. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Address
Register Name
Description
Black Line Generation
197[7:0]
black_lines
This register configures the number of black lines that are generated at the start of a frame. At least one
black line must be generated. The maximum number is 255.
Note: When the automatic black−level calibration algorithm is enabled, make sure that this register is
configured properly to produce sufficient black pixels for the black−level filtering.
The number of black pixels generated per line is dependent on the operation mode and window configurations:
Each black line contains 162 kernels.
197[12:8]
gate_first_line
A number of black lines are blanked out when a value different from 0 is configured. These blanked out
lines are not used for black calibration. It is recommended to enable this functionality, because the first
line can have a different behavior caused by boundary effects. When enabling, the number of black
lines must be set to at least two in order to have valid black samples for the calibration algorithm.
129[0]
auto_blackcal_enable
Internal black−level calibration functionality is enabled when set to ‘1’. Required black level offset compensation is calculated on the black samples and applied to all image pixels.
When set to ‘0’, the automatic black−level calibration functionality is disabled. It is possible to apply an
offset compensation to the image pixels, which is defined by the registers 129[10:1].
Note: Black sample pixels are not compensated; the raw data is sent out to provide
external statistics and, optionally, calibrations.
129[9:1]
blackcal_offset
Black calibration offset that is added or subtracted to each regular pixel value when auto_blackcal_enable is set to ‘0’. The sign of the offset is determined by register 129[10] (blackcal_offset_dec).
Note: All channels use the same offset compensation when automatic black calibration is disabled.
129[10]
blackcal_offset_dec
Sign of blackcal_offset. If set to ‘0’, the black calibration offset is added to each pixel. If set to ‘1’, the
black calibration offset is subtracted from each pixel.
This register is not used when auto_blackcal_enable is set to ‘1’.
Black Value Filtering
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NOIP1SN5000A, NOIP1SN2000A
Table 19. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Address
Register Name
Description
Black Line Generation
128[10:8]
black_samples
The black samples are low−pass filtered before being used for black level calculation. The more samples are taken into account, the more accurate the calibration, but more samples require more black
lines, which in turn affects the frame rate.
The effective number of samples taken into account for filtering is 2^ black_samples.
Note: An error is reported by the device if more samples than available are requested (refer to register
136).
Black Level Filtering Monitoring
136
blackcal_error0
An error is reported by the device if there are requests for more samples than are available (each bit
corresponding to one data path). The black level is not compensated correctly if one of the channels
indicates an error. There are three possible methods to overcome this situation and to perform a correct
offset compensation:
• Increase the number of black lines such that enough samples are generated at the cost of increasing frame time (refer to register 197).
• Relax the black calibration filtering at the cost of less accurate black level determination (refer to
register 128).
• Disable automatic black level calibration and provide the offset via SPI register upload. Note that
the black level can drift in function of the temperature. It is thus recommended to perform the offset
calibration periodically to avoid this drift.
NOTE: The maximum number of samples taken into account for black level statistics is half the number of kernels.
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NOIP1SN5000A, NOIP1SN2000A
Serial Peripheral Interface
as indicated in Figure 21. The sensor samples this
address data on a rising edge of the sck clock
(mosi needs to be driven by the system on the
falling edge of the sck clock).
3. The tenth bit sent by the master indicates the type
of transfer: high for a write command, low for a
read command.
4. Data transmission:
- For write commands, the master continues
sending the 16−bit data, most significant bit first.
- For read commands, the sensor returns the data on
the requested address on the miso pin, most
significant bit first. The miso pin must be sampled
by the system on the falling edge of sck (assuming
nominal system clock frequency and maximum
10 MHz SPI frequency).
5. When data transmission is complete, the system
deselects the sensor one clock period after the last
bit transmission by pulling ss_n high.
Maximum frequency for the SPI depends on the input
clock and type of sensor. The frequency is 1/6th of the PLL
input clock or 1/30th (in 10−bit mode) and 1/24th (in 8−bit
mode) of the LVDS input clock frequency.
At nominal input frequency, the maximum frequency for
the SPI is 10 MHz. Consecutive SPI commands can be
issued by leaving at least two SPI clock periods between two
register uploads. Deselect the chip between the SPI uploads
by pulling the ss_n pin high.
The sensor configuration registers are accessed through
an SPI. The SPI consists of four wires:
• sck: Serial Clock
• ss_n: Active Low Slave Select
• mosi: Master Out, Slave In, or Serial Data In
• miso: Master In, Slave Out, or Serial Data Out
The SPI is synchronous to the clock provided by the
master (sck) and asynchronous to the sensor’s system clock.
When the master wants to write or read a sensor’s register,
it selects the chip by pulling down the Slave Select line
(ss_n). When selected, data is sent serially and synchronous
to the SPI clock (sck).
Figure 21 shows the communication protocol for read and
write accesses of the SPI registers. The PYTHON sensor
uses 9−bit addresses and 16−bit data words.
Data driven by the system is colored blue in Figure 16,
while data driven by the sensor is colored yellow. The data
in grey indicates high−Z periods on the miso interface. Red
markers indicate sampling points for the sensor (mosi
sampling); green markers indicate sampling points for the
system (miso sampling during read operations).
The access sequence is:
1. Select the sensor for read or write by pulling down
the ss_n line.
2. One SPI clock cycle after selecting the sensor, the
9−bit address is transferred, most significant bit
first. The sck clock is passed through to the sensor
SPI − WRITE
ss_n
t_sckss
tsck
t_sssck
sck
ts _mos i
mosi
A8
th_mosi
A7
..
..
..
A1
A0
`1'
D15
D14
..
..
..
..
D1
D0
miso
SPI − READ
ss_n
t_sssck
t_sckss
tsck
sck
ts_mosi
mosi
A8
th_mosi
A7
..
..
..
A1
A0
`0'
th_miso
ts _miso
miso
D15
D14
..
..
Figure 21. SPI Read and Write Timing Diagram
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27
..
..
D1
D0
NOIP1SN5000A, NOIP1SN2000A
Table 20. SPI TIMING REQUIREMENTS
Group
Addresses
Description
100
(*)
Units
tsck
sck clock period
ns
tsssck
ss_n low to sck rising edge
tsck
ns
tsckss
sck falling edge to ss_n high
tsck
ns
ts_mosi
Required setup time for mosi
20
ns
th_mosi
Required hold time for mosi
20
ns
ts_miso
Setup time for miso
tsck/2−10
ns
th_miso
Hold time for miso
tsck/2−20
ns
tspi
Minimal time between two consecutive SPI accesses (not shown in figure)
2 x tsck
ns
*Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock).
tsck is defined as 1/fSPI. See text for more information on SPI clock frequency restrictions.
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NOIP1SN5000A, NOIP1SN2000A
IMAGE SENSOR TIMING AND READOUT
abandoned. This indicates the start of the integration or
exposure time. The length of the exposure time is defined by
the registers exposure and mult_timer.
NOTE: The start of the exposure time is synchronized to
the start of a new line (during ROT) if the
exposure period starts during a frame readout.
As a consequence, the effective time during
which the image core is in a reset state is
extended to the start of a new line.
• Make sure that the sum of the reset time and exposure
time exceeds the time required to readout all lines. If
this is not the case, the exposure time is extended until
all (active) lines are read out.
• Alternatively, it is possible to specify the frame time
and exposure time. The sensor automatically calculates
the required reset time. This mode is enabled by the
fr_mode register. The frame time is specified in the
register fr_length.
The following sections describe the configurations for
single slope reset mechanism. Dual and triple slope handling
during global shutter operation is similar to the single slope
operation. Extra integration time registers are available.
Global Shutter Mode
Pipelined Global Shutter (Master)
The integration time is controlled by the registers
fr_length[15:0] and exposure[15:0]. The mult_timer
configuration defines the granularity of the registers
reset_length and exposure and is read as number of system
clock cycles.
The exposure control for (Pipelined) Global Master mode
is depicted in Figure 22.
The pixel values are transferred to the storage node during
FOT, after which all photo diodes are reset. The reset state
remains active for a certain time, defined by the reset_length
and mult_timer registers, as shown in the figure. Note that
meanwhile the image array is read out line by line. After this
reset period, the global photodiode reset condition is
Frame N
Exposure State
FOT
Readout
FOT
Reset
Frame N+1
Integrating
FOT
Reset
Integrating
FOT
FOT
FOT
Image Array Global Reset
reset_length
x
mult_timer
exposure
x
mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 22. Integration Control for (Pipelined) Global Shutter Mode (Master)
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NOIP1SN5000A, NOIP1SN2000A
Triggered Global Shutter (Master)
exposure and mult_timer, as in the master pipelined global
mode. The fr_length configuration is not used. This
operation is graphically shown in Figure 23.
In master triggered global mode, the start of integration
time is controlled by a rising edge on the trigger0 pin. The
exposure or integration time is defined by the registers
Frame N
Exposure State
FOT
Reset
Integrating
FOT
Reset
Integrating
FOT
(No effect on falling edge)
trigger0
Readout
Frame N+1
FOT
FOT
FOT
Image Array Global Reset
exposure x mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 23. Exposure Time Control in Triggered Shutter Mode (Master)
the pixel storage node and readout of the image array. In
other words, the high time of the trigger pin indicates the
integration time, the period of the trigger pin indicates the
frame time.
The use of the trigger during slave mode is shown in
Figure 24.
Notes:
• The falling edge on the trigger pin does not have any
impact. Note however the trigger must be asserted for
at least 100 ns.
• The start of the exposure time is synchronized to the
start of a new line (during ROT) if the exposure period
starts during a frame readout. As a consequence, the
effective time during which the image core is in a reset
state is extended to the start of a new line.
• If the exposure timer expires before the end of readout,
the exposure time is extended until the end of the last
active line.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Notes:
• The registers exposure, fr_length, and mult_timer are
•
•
•
Triggered Global Shutter (Slave)
Exposure or integration time is fully controlled by means
of the trigger pin in slave mode. The registers fr_length,
exposure and mult_timer are ignored by the sensor.
A rising edge on the trigger pin indicates the start of the
exposure time, while a falling edge initiates the transfer to
not used in this mode.
The start of exposure time is synchronized to the start
of a new line (during ROT) if the exposure period starts
during a frame readout. As a consequence, the effective
time during which the image core is in a reset state is
extended to the start of a new line.
If the trigger is de−asserted before the end of readout,
the exposure time is extended until the end of the last
active line.
The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Frame N
Exposure State
FOT
Reset
Frame N+1
Integrating
FOT
Reset
Integrating
FOT
trigger0
Readout
FOT
FOT
FOT
Image Array Global Reset
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 24. Exposure Time Control in Global−Slave Mode
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NOIP1SN5000A, NOIP1SN2000A
ADDITIONAL FEATURES
Multiple Window Readout
The PYTHON sensor supports multiple window readout,
which means that only the user−selected Regions Of Interest
(ROI) are read out. This allows limiting data output for every
frame, which in turn allows increasing the frame rate. In
global shutter mode, up to eight ROIs can be configured.
y1_end
ROI 1
y0_end
y1_start
ROI 0
Window Configuration
Figure 25 shows the four parameters defining a region of
interest (ROI).
y0_start
y-end
x0_start
x0_end
x1_start
ROI 0
x1_end
Figure 26. Overlapping Multiple Window
Configuration
y-start
The sequencer analyses each line that needs to be read out
for multiple windows.
Restrictions
The following restrictions for each line are assumed for
the user configuration:
• Windows are ordered from left to right, based on their
x−start address:
x-start x-end
Figure 25. Region of Interest Configuration
x_start_roi(i) v x_start_roi(j) AND
• x−start[7:0]
x−start defines the x−starting point of the desired window.
The sensor reads out 16 pixels in one single clock cycle. As
a consequence, the granularity for configuring the x−start
position is also 16 pixels for no sub sampling. The value
configured in the x−start register is multiplied by 16 to find
the corresponding column in the pixel array.
• x−end[7:0]
This register defines the window end point on the x−axis.
Similar to x−start, the granularity for this configuration is
one kernel. x−end needs to be larger than x−start.
• y−start[9:0]
The starting line of the readout window. The granularity
of this setting is one line, except with color sensors where it
needs to be an even number.
• y−end[9:0]
The end line of the readout window. y−end must be
configured larger than y−start. This setting has the same
granularity as the y−start configuration.
Up to eight windows can be defined, possibly (partially)
overlapping, as illustrated in Figure 26.
x_end_roi(i) vx_end_roi(j)
Where j > i
Processing Multiple Windows
The sequencer control block houses two sets of counters
to construct the image frame. As previously described, the
y−counter indicates the line that needs to be read out and is
incremented at the end of each line. For the start of the frame,
it is initialized to the y−start address of the first window and
it runs until the y−end address of the last window to be read
out. The last window is configured by the configuration
registers and it is not necessarily window #15.
The x−counter starts counting from the x−start address of
the window with the lowest ID which is active on the
addressed line. Only windows for which the current
y−address is enclosed are taken into account for scanning.
Other windows are skipped.
Figure 27 illustrates a practical example of a
configuration with five windows. The current position of the
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NOIP1SN5000A, NOIP1SN2000A
read pointer (ys) is indicated by a red line crossing the image
array. For this position of the read pointer, three windows
need to be read out. The initial start position for the x−kernel
pointer is the x−start configuration of ROI1. Kernels are
scanned up to the ROI3 x−end position. From there, the
x−pointer jumps to the next window, which is ROI4 in this
illustration. When reaching ROI4’s x−end position, the read
pointer is incremented to the next line and xs is reinitialized
to the starting position of ROI1.
Notes:
• The starting point for the readout pointer at the start of
a frame is the y−start position of the first active
window.
• The read pointer is not necessarily incremented by one,
but depending on the configuration, it can jump in
y−direction. In Figure 27, this is the case when reaching
the end of ROI0 where the read pointer jumps to the
y−start position of ROI1
• The x−pointer starting position is equal to the x−start
configuration of the first active window on the current
line addressed. This window is not necessarily window
#0.
• The x−pointer is not necessarily incremented by one
each cycle. At the end of a window it can jump to the
start of the next window.
• Each window can be activated separately. There is no
restriction on which window and how many of the 16
windows are active.
ROI 2
ys
ROI 3
ROI 4
ROI 1
ROI 0
Figure 27. Scanning the Image Array with Five
Windows
Subsampling
Subsampling is used to reduce the image resolution. This
allows increasing the frame rate. Two subsampling modes
are supported:
Monochrome Sensors
For monochrome sensors, the read−1−skip−1
subsampling scheme is used. Subsampling occurs both in x−
and y− direction.
Color Sensors
For color sensors, the read−2−skip−2 subsampling
scheme is used. Subsampling occurs both in x− and y−
direction. Figure 28 shows which pixels are read and which
ones are skipped.
Figure 28. Subsampling Scheme for Monochrome and Color Sensors
Binning
binning and to 0x1 for 2x1 binning (binning in x
direction only).
2. Binning in y-direction cannot be used in
combination with pipelined integration and
readout. The integration time and readout time
should be separated in time (do not coincide).
Pixel binning is a technique in which different pixels
belonging to a rectangular bin are averaged in the analog
domain. Two−by−two pixel binning is available with the
PYTHON monochrome sensor. This implies that two
adjacent pixels are averaged both in column and row.
Binning is configurable using a register setting. Pixel
binning is not supported on PYTHON color option and in
Zero ROT mode.
NOTES:
1. Pixel binning can be configured independently in x
and y. Configure binning_mode to 0x0 for 2x2
Reverse Readout in Y−direction
Reverse readout in y−direction can be done by asserting
reverse_y (reg 194[8]). The reference for y_start and y_stop
pointers is reversed.
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NOIP1SN5000A, NOIP1SN2000A
Down−Multiplexing
Enabling the down−multiplexing is done through register
32[5:4]. The default value of 0 disables all
down−multiplexing. Higher values sets higher degree of
down−multiplexing, The channels that are used per degree
of multiplexing are shown in Table 21. The unused data
channels are powered down and will not send any data.
The PYTHON sensor contains a function for
down−multiplexing the output channels. Using this
function, one may for instance use the PYTHON 5000 with
sync+clock+4 data channels instead of sync+clock+8 data
channels.
Table 21. ILLUSTRATION OF WHICH CHANNELS THAT ARE USED DEPENDING ON DEGREE OF DOWN
MULTIPLEXING
Multiplex Mode
PYTHON 5000/2000 − 8 LVDS Channels
8 channels
Ch 0
4 channels
Ch 0
2 channels
Ch 0
1 channel
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 2
Ch 5
Ch 4
Ch 6
Ch 7
Ch 6
Ch 4
Multiple Slope Integration
To increase the dynamic range of the sensor, a second
slope is applied in the dual slope mode (green curve). The
sensor has the same responsivity in the black as for a single
slope, but from ‘knee point 1’ on, the sensor is less
responsive to incoming light. The result is that the saturation
point is at a higher light power level.
To further increase the dynamic range, a third slope can be
applied, resulting in a second knee point.
Refer to section Global Shutter Mode on page 29 for
general notes applicable to the global shutter operation and
more particular to the use of the trigger0 pin.
‘Multiple Slope Integration’ is a method to increase the
dynamic range of the sensor. The PYTHON supports up to
three slopes.
Figure 29 shows the sensor response to light when the
sensor is used with one slope, two slopes, and three slopes.
The X−axis represents the light power; the Y−axis shows the
sensor output signal. The kneepoint of the multiple slope
curves are adjustable in both position and voltage level.
It is clear that when using only one slope (red curve), the
sensor has the same responsivity over the entire range, until
the output saturates at the point indicated with ‘single slope
saturation point’.
output
1023
slope 3
`kneepoint 2'
slope 1 slope 2
`kneepoint 1'
0
single slope
saturation point
dual slope
saturation point
Figure 29. Multiple Slope Operation
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33
light
triple slope
saturation point
NOIP1SN5000A, NOIP1SN2000A
Kneepoint Configuration (Multiple Slope Reset Levels)
dual_slope_enable and triple_slope_enable and their values
are defined by the registers exposure_ds and exposure_ts.
NOTE: Dual and triple slope sequences must start after
readout of the previous frame is fully completed.
Figure 30 shows the frame timing for pipelined master
mode with dual and triple slope integration and
fr_mode = ‘0’ (fr_length representing the reset length).
In triggered master mode, the start of integration is
initiated by a rising edge on trigger0, while the falling edge
does not have any relevance. Exposure duration and
dual/triple slope points are defined by the registers.
The kneepoint reset levels are configured by means of
DAC configurations in the image core. The dual slope
kneepoint is configured with the dac_ds configuration,
while the triple slope kneepoint is configured with the
dac_ts register setting. Both are located on address 41.
Multiple Slope Integration in “Master Mode” (Pipelined
or Triggered)
In master mode, the time stamps for the double and triple
slope resets are configured in a similar way as the exposure
time. They are enabled through the registers
Figure 30. Multiple Slope Operation in Master Mode for fr_mode = ‘0’ (Pipelined)
Slave Mode
initiates the triple slope reset sequence. Rising edges on
trigger1 and trigger2 do not have any impact.
NOTE: Dual and triple slope sequences must start after
readout of the previous frame is fully completed.
In slave mode, the register settings for integration control
are ignored. The user has full control through the trigger0,
trigger1 and trigger2 pins. A falling edge on trigger1
initiates the dual slope reset while a falling edge on trigger2
Figure 31. Multiple Slope Operation in Slave Mode
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NOIP1SN5000A, NOIP1SN2000A
Black Reference
active window number, which is 0. Black reference data is
classified by a BL code.
The sensor reads out one or more black lines at the start of
every new frame. The number of black lines to be generated
is programmable and is minimal equal to 1. The length of the
black lines depends on the operation mode. The sensor
always reads out the entire line (162 kernels), independent
of window configurations.
The black references are used to perform black calibration
and offset compensation in the data channels. The raw black
pixel data is transmitted over the usual output interface,
while the regular image data is compensated (can be
bypassed).
On the output interface, black lines can be seen as a
separate window, however without Frame Start and Ends
(only Line Start/End). The Sync code following the Line
Start and Line End indications (“window ID”) contains the
Signal Path Gain
Analog Gain Stages
Referring to Table 22, two gain settings are available in
the analog data path to apply gain to the analog signal before
it is digitized.
The moment a gain reconfiguration is applied and
becomes valid can be controlled by the gain_lat_comp
configuration.
With ‘gain_lat_comp’ set to ‘0’, the new gain
configurations are applied from the very next frame.
With ‘gain_lat_comp’ set to ‘1’, the new gain settings are
postponed by one extra frame. This feature is useful when
exposure time and gain are reconfigured together, as an
exposure time update always has one frame latency.
Table 22. SIGNAL PATH GAIN STAGES
(Analog Gain Stages − register 204)
gain_stage1
(mux_gainsw0)
Gain Stage 1
gain_stage2 (afe_gain0)
Gain Stage 2
GAIN Total
0x1
1.00
0xF
1.00
1.00
0x4
1.88
0xF
1.00
1.88
Digital Gain Stage
The digital gain stage allows fine gain adjustments on the digitized samples. The gain configuration is an absolute 5.7
unsigned number (5 digits before and 7 digits after the decimal point).
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NOIP1SN5000A, NOIP1SN2000A
Automatic Exposure Control
AEC
Statistics
Requested Illumination Level
(Target)
Total Gain
Requested Gain
Changes
The exposure control mechanism has the shape of a general feedback control system. Figure 32 shows the high level block
diagram of the exposure control loop.
AEC
Filter
AEC
Enforcer
Integration Time
Analog Gain (Coarse Steps)
Digital Gain (Fine Steps)
Image Capture
Figure 32. Automatic Exposure Control Loop
Three main blocks can be distinguished:
• The statistics block compares the average of the
current image’s samples to the configured target value
for the average illumination of all pixels
• The relative gain change request from the statistics
block is filtered through the AEC Filter block in the
time domain (low pass filter) before being integrated.
The output of the filter is the total requested gain in the
complete signal path.
• The enforcer block accepts the total requested gain and
distributes this gain over the integration time and gain
stages (both analog and digital)
calculated illumination and the target illumination the
statistics block requests a relative gain change.
Statistics Subsampling and Windowing
For average calculation, the statistics block will
sub−sample the current image or windows by taking every
fourth sample into account. Note that only the pixels read out
through the active windows are visible for the AEC. In the
case where multiple windows are active, the samples will be
selected from the total samples. Samples contained in a
region covered by multiple (overlapping) window will be
taking into account only once.
It is possible to define an AEC specific sub−window on
which the AEC will calculate it’s average. For instance, the
sensor can be configured to read out a larger frame, while the
illumination is measured on a smaller region of interest, e.g.
center weighted as shown in Table 23.
The automatic exposure control loop is enabled by
asserting the aec_enable configuration in register 160.
NOTE: Dual and Triple slope integration is not
supported in conjunction with the AEC.
AEC Statistics Block
The statistics block calculates the average illumination of
the current image. Based on the difference between the
Table 23. AEC SAMPLE SELECTION
Register
Name
Description
192[10]
roi_aec_enable
When 0x0, all active windows are selected for statistics calculation.
When 0x1, the AEC samples are selected from the active pixels contained in the region of interest defined by roi_aec
253−255
roi_aec
These registers define a window from which the AEC samples will be selected when roi_aec_enable is asserted.
Configuration is similar to the regular region of interests.
The intersection of this window with the active windows define the selected pixels. It is important that this window at least
overlaps with one or more active windows.
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36
NOIP1SN5000A, NOIP1SN2000A
AEC Filter Block
Target Illumination
The target illumination value is configured by means of
register desired_intensity as shown in Table 24.
The filter block low−pass filters the gain change requests
received from the statistics block.
The filter can be restarted by asserting the restart_filter
configuration of register 160.
Table 24. AEC TARGET ILLUMINATION
CONFIGURATION
Register
161[9:0]
Name
desired_intensity
AEC Enforcer Block
Description
The enforcer block calculates the four different gain
parameters, based on the required total gain, thereby
respecting a specific hierarchy in those configurations.
Some (digital) hysteresis is added so that the (analog) sensor
settings don’t need to change too often.
Exposure Control Parameters
The several gain parameters are described below, in the
order in which these are controlled by the AEC for large
adjustments. Small adjustments are regulated by digital gain
only.
• Exposure Time
The exposure is the time between the global image array
reset de−assertion and the pixel charge transfer. The
granularity of the integration time steps is configured by the
mult_timer register.
NOTE: The exposure_time register is ignored when the
AEC is enabled. The register fr_length defines
the frame time and needs to be configured
accordingly.
• Analog Gain
The sensor has two analog gain settings. Typically the
AEC shall only regulate the first stage.
• Digital Gain
The last gain stage is a gain applied on the digitized
samples. The digital gain is represented by a 5.7 unsigned
number (i.e. 7 bits after the decimal point). While the analog
gain steps are coarse, the digital gain stage makes it possible
to achieve very fine adjustments.
Target intensity value, on 10−bit scale.
For 8−bit mode, target value is configured
on desired_intensity[9:2]
Color Sensor
The weight of each color can be configured for color
sensors by means of scale factors. Note these scale factor are
only used to calculate the statistics in order to compensate
for (off−chip) white balancing and/or color matrices. The
pixel values itself are not modified.
The scale factors are configured as 3.7 unsigned numbers
(0x80 = unity). Refer to Table 25 for color scale factors. For
mono sensors, configure these factors to their default value.
Table 25. COLOR SCALE FACTORS
Register
Name
Description
162[9:0]
red_scale_factor
Red scale factor for AEC statistics
163[9:0]
green1_scale_factor
Green1 scale factor for AEC
statistics
164[9:0]
green2_scale_factor
Green2 scale factor for AEC
statistics
165[9:0]
blue_scale_factor
Blue scale factor for AEC statistics
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NOIP1SN5000A, NOIP1SN2000A
AEC Control Range
AEC Update Frequency
The control range for each of the exposure parameters can
be pre−programmed in the sensor. Table 26 lists the relevant
registers.
As an integration time update has a latency of one frame,
the exposure control parameters are evaluated and updated
every other frame.
Note: The gain update latency must be postpone to match
the integration time latency. This is done by asserting the
gain_lat_comp register on address 204[13].
Table 26. MINIMUM AND MAXIMUM EXPOSURE
CONTROL PARAMETERS
Register
Name
Description
Exposure Control Status Registers
168[15:0]
min_exposure
Lower bound for the integration time
applied by the AEC
169[1:0]
min_mux_gain
Lower bound for the first stage
analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x0 = 1x
0x1 = 2x
169[3:2]
min_afe_gain
Lower bound for the second stage
analog amplifier.
This stage has only one
configuration with the following
approximative gain:
0x0 = 1.00x
169[15:4]
min_digital_gain
max_exposure
Upper bound for the integration time
applied by the AEC
171[1:0]
max_mux_gain
Upper bound for the first stage analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x0 = 1x
0x1 = 2x
171[15:4]
max_afe_gain
max_digital_
gain
Table 27. EXPOSURE CONTROL STATUS REGISTERS
Lower bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
unsigned format
170[15:0]
171[3:2]
Configured integration and gain parameters are reported
to the user by means of status registers. The sensor provides
two levels of reporting: the status registers reported in the
AEC address space are updated once the parameters are
recalculated and requested to the internal sequencer. The
status registers residing in the sequencer’s address space on
the other hand are updated once these parameters are taking
effect on the image readout. Refer to Table 27 reflecting the
AEC and Sequencer Status registers.
Register
Name
Description
AEC Status Registers
Upper bound for the second stage
analog amplifier
This stage has only one
configuration with the following
approximative gain:
0x0 = 1.00x
Upper bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
unsigned format
184[15:0]
total_pixels
Total number of pixels taken into account
for the AEC statistics.
186[9:0]
average
Calculated average illumination
level for the current frame.
187[15:0]
exposure
AEC calculated exposure.
Note: this parameter is updated at the
frame end.
188[1:0]
mux_gain
AEC calculated analog gain
(1st stage)
Note: this parameter is updated at the
frame end.
188[3:2]
afe_gain
AEC calculated analog gain
(2st stage)
Note: this parameter is updated at the
frame end.
188[15:4]
digital_gain
AEC calculated digital gain
(5.7 unsigned format)
Note: this parameter is updated at the
frame end.
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38
NOIP1SN5000A, NOIP1SN2000A
temperature. The Tsensor output is a 8−bit digital count
between 0 and 255, proportional to the temperature of the
silicon substrate. This reading can be translated directly to
a temperature reading in °C by calibrating the 8−bit readout
at 0°C and 85°C to achieve an output accuracy of ±2°C. The
Tsensor output can also be calibrated using a single
temperature point (example: room temperature or the
ambient temperature of the application), to achieve an
output accuracy of ±5°C.
Note that any process variation will result in an offset in
the bit count and that offset will remain within ±5°C over the
temperature range of 0°C and 85°C. Tsensor output digital
code can be read out through the SPI interface.
Table 27. EXPOSURE CONTROL STATUS REGISTERS
Register
Name
Description
Sequencer Status Registers
242[15:0]
mult_timer
mult_timer for current frame
Note: this parameter is updated once it
takes effect on the image.
243[15:0]
reset_length
Image array reset length for the
current frame.
Note: this parameter is updated once it
takes effect on the image.
244[15:0]
exposure
Exposure for the current frame.
Note: this parameter is updated once it
takes effect on the image.
245[15:0]
exposure_ds
Dual slope exposure for the current
frame. Note this parameter is not controlled by the AEC.
Note: this parameter is updated once it
takes effect on the image.
Output of the temperature sensor to the SPI:
Triple slope exposure for the
current frame. Note this parameter is not
controlled by the AEC.
Note: this parameter is updated once it
takes effect on the image.
Input from the SPI:
246[15:0]
exposure_ts
247[4:0]
mux_gainsw
1st
247[12:5]
afe_gain
2st stage analog gain for the current
frame.
Note: this parameter is updated once it
takes effect on the image.
db_gain
Digital gain configuration for the current
frame (5.7 unsigned
format).
Note: this parameter is updated once it
takes effect on the image.
248[12]
dual_slope
Dual slope configuration for the
current frame
Note 1: this parameter is updated once it
takes effect on the image.
Note 2: This parameter is not
controlled by the AEC.
triple_slope
The reg_tempd_enable is a global enable and this enables
or disables the temperature sensor when logic high or logic
low respectively. The temperature sensor is reset or disabled
when the input reg_tempd_enable is set to a digital low state.
stage analog gain for the current
frame.
Note: this parameter is updated once it
takes effect on the image.
248[11:0]
248[13]
tempd_reg_temp<7:0>: This is the 8−bit N count readout
proportional to temperature.
Calibration using one temperature point
The temperature sensor resolution is fixed for a given type
of package for the operating range of 0°C to +85°C and
hence devices can be calibrated at any ambient temperature
of the application, with the device configured in the mode of
operation.
Interpreting the actual temperature for the digital code
readout:
The formula used is
TJ = R (Nread − Ncalib) + Tcalib
TJ = junction die temperature
R = resolution in degrees/LSB (typical 0.75 deg/LSB)
Nread = Tsensor output (LSB count between 0 and 255)
Tcalib = Tsensor calibration temperature
Ncalib = Tsensor output reading at Tcalib
Triple slope configuration for the current
frame.
Note 1: this parameter is updated once it
takes effect on the image.
Note 2: This parameter is not
controlled by the AEC.
Temperature Sensor
The PYTHON has an on−chip temperature sensor which
returns a digital code (Tsensor) of the silicon junction
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39
NOIP1SN5000A, NOIP1SN2000A
Monitor Pins
The internal sequencer has two monitor outputs (monitor0 and monitor1) that can be used to communicate the internal states
from the sequencer. A three−bit register configures the assignment of the pins as shown in Table 28.
Table 28. REGISTER SETTING FOR THE MONITOR SELECT PIN
monitor_select [2:0]
192 [13:11]
monitor pin
0x0
monitor0
monitor1
‘0’
‘0’
0x1
monitor0
monitor1
Integration Time
ROT Indication (‘1’ during ROT, ‘0’ outside)
0x2
monitor0
monitor1
Integration Time
Dual/Triple Slope Integration (asserted during DS/TS FOT sequence)
0x3
monitor0
monitor1
Start of x−Readout Indication
Black Line Indication (‘1’ during black lines, ‘0’ outside)
0x4
monitor0
monitor1
Frame Start Indication
Start of ROT Indication
0x5
monitor0
monitor1
First Line Indication (‘1’ during first line, ‘0’ for all others)
Start of ROT Indication
0x6
monitor0
monitor1
ROT Indication (‘1’ during ROT, ‘0’ outside)
Start of X−Readout Indication
0x7
monitor0
monitor1
Start of X−readout Indication for Black Lines
Start of X−readout Indication for Image Lines
Description
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40
NOIP1SN5000A, NOIP1SN2000A
DATA OUTPUT FORMAT
P1−SN/SE: LVDS Interface Version
Figure 33 indicates that, after the FOT is completed, the
sensor reads out a number of black lines for black calibration
purposes. After these black lines, the windows are
processed. First a number of lines which only includes
information of ‘ROI 0’ are sent out, starting at position
y0_start. When the line at position y1_start is reached, a
number of lines containing data of ‘ROI 0’ and ‘ROI 1’ are
sent out, until the line position of y0_end is reached. From
there on, only data of ‘ROI 1’ appears on the data output
channels until line position y1_end is reached
During read out of the image data over the data channels,
the sync channel sends out frame synchronization codes
which give information related to the image data that is sent
over the four data output channels.
Each line of a window starts with a Line Start (LS)
indication and ends with a Line End (LE) indication. The
line start of the first line is replaced by a Frame Start (FS);
the line end of the last line is replaced with a Frame End
indication (FE). Each such frame synchronization code is
followed by a window ID (range 0 to 7). For overlapping
windows, the line synchronization codes of the overlapping
windows with lower IDs are not sent out (as shown in the
illustration: no LE/FE is transmitted for the overlapping part
of window 0).
NOTES: In Figure 33, only Frame Start and Frame End
Sync words are indicated in (b). CRC codes are
also omitted from the figure.
The P1−SN/SE has eight LVDS output channels, together
with an LVDS clock and an LVDS synchronization output
channel.
LVDS Output Channels
The image data output occurs through eight LVDS data
channels where a synchronization LVDS channel and an
LVDS output clock signal synchronizes the data.
The eight data channels are used to output the image data
only. The sync channel transmits information about the data
sent over these data channels (includes codes indicating
black pixels, normal pixels, and CRC codes).
8−bit / 10−bit Mode
The sensor can be used in 8−bit or 10−bit mode.
In 10−bit mode, the words on data and sync channel have
a 10−bit length. The output data rate is 720 Mbps.
In 8−bit mode, the words on data and sync channel have
an 8−bit length, the output data rate is 576 Mbps.
Note that the 8−bit mode can only be used to limit the data
rate at the consequence of image data word depth. It is not
supported to operate the sensor in 8−bit mode at a higher
clock frequency to achieve higher frame rates.
Frame Format
The frame format in 8−bit mode is identical to the 10−bit
mode with the exception that the Sync and data word depth
is reduced to eight bits.
The frame format in 10−bit mode is explained by example
of the readout of two (overlapping) windows as shown in
Figure 33(a).
The readout of a frame occurs on a line−by−line basis. The
read pointer goes from left to right, bottom to top.
For additional information on the
synchronization codes, please refer to
Application Note AND5001.
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41
NOIP1SN5000A, NOIP1SN2000A
y1_end
ROI 1
y0_end
y1_start
ROI 0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Integration Time
Handling
Readout
Handling
FOT
É
É
B
L
Reset
N
Exposure Time N
FOT
Readout Frame N-1
ROI
1
ROI 0
FS0
FS1
FOT
FE1
Reset
N+1
É
É
B
L
Exposure Time N+1
FOT
Readout Frame N
ROI
1
ROI 0
FS0
FS1
FOT
FE1
(b)
Figure 33. Frame Sync Codes
Figure 34 shows the detail of a black line readout during global or full−frame readout.
Sequencer
Internal State
FOT
ROT
ROT
black
line Ys
ROT
ROT
line Ys+1
line Ye
data channels
sync channel
data channels
sync channel
Training
TR
Training
LS
BL
timeslot
0
timeslot
1
BL
BL
BL
timeslot
157
BL
timeslot
158
BL
LE
timeslot
159
Figure 34. Time Line for Black Line Readout
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42
CRC
CRC
timeslot
TR
NOIP1SN5000A, NOIP1SN2000A
Figure 35 shows the details of the readout of a number of lines for single window readout, at the beginning of the frame.
Sequencer
Internal State
FOT
ROT
black
ROT
line Ys+1
ROT
line Ys
line Ye
ROT
data channels
sync channel
Training
data channels
TR
sync channel
Training
FS
ID
timeslot
Xstart
IMG
IMG
IMG
timeslot
Xstart + 1
IMG
timeslot
Xend - 2
IMG
IMG
timeslot
Xend - 1
ID
LE
CRC
timeslot
Xend
TR
CRC
timeslot
Figure 35. Time Line for Single Window Readout (at the start of a frame)
Figure 36 shows the detail of the readout of a number of lines for readout of two overlapping windows.
Sequencer
Internal State
FOT
ROT
ROT
black
line Ys
ROT
ROT
line Ys+1
line Ye
data channels
sync channel
data channels
sync channel
Training
Training
TR
LS
IDM
IMG
IMG
LS
timeslot
XstartM
IDN
IMG
IMG
IMG LE
timeslot
XstartN
IDN
CRC
TR
timeslot
XendN
Figure 36. Time Line Showing the Readout of Two Overlapping Windows
Frame Synchronization for 10−bit Mode
active at the same time, the sync channel transmits the frame
synchronization codes of the window with highest index
only.
Table 29 shows the structure of the frame synchronization
code. Note that the table shows the default data word
(configurable) for 10−bit mode. If more than one window is
Table 29. FRAME SYNCHRONIZATION CODE DETAILS FOR 10−BIT MODE
Sync Word Bit
Position
Register
Address
Default Value
9:7
N/A
0x5
Frame start (FS) indication
9:7
N/A
0x6
Frame end (FE) indication
9:7
N/A
0x1
Line start (LS) indication
Line end (LE) indication
9:7
N/A
0x2
6:0
117[6:0]
0x2A
Description
These bits indicate that the received sync word is a frame synchronization code. The value is programmable by a register setting
number, ranging from 0 to 15, indicating the active window.
If more than one window is active for the current cycle, the
highest window ID is transmitted.
Window Identification
Frame synchronization codes are always followed by a
4−bit window identification (bits 3:0). This is an integer
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43
NOIP1SN5000A, NOIP1SN2000A
(BL), image data (IMG), or training pattern (TR). These
codes are programmable by a register setting. The default
values are listed in Table 30.
Data Classification Codes
For the remaining cycles, the sync channel indicates the
type of data sent through the data links: black pixel data
Table 30. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 10−BIT MODE
Sync Word Bit
Position
Register Address
Default Value
9:0
118 [9:0]
0x015
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
9:0
119 [9:0]
0x035
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the image).
9:0
125 [9:0]
0x059
CRC value. The data on the data output channels is the CRC code of the finished image data line.
9:0
126 [9:0]
0x3A6
Training pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
Description
Frame Synchronization in 8−bit Mode
and not sent out. Table 32 shows the structure of the frame
synchronization code, together with the default value, as
specified in SPI registers. The same restriction for
overlapping windows applies in 8−bit mode.
The frame synchronization words are configured using
the same registers as in 10−bit mode. The two least
significant bits of these configuration registers are ignored
Table 31. FRAME SYNCHRONIZATION CODE DETAILS FOR 8−BIT MODE
Sync Word Bit
Position
Register Address
Default Value
7:5
N/A
0x5
Frame start (FS) indication
7:5
N/A
0x6
Frame end (FE) indication
7:5
N/A
0x1
Line start (LS) indication
Line end (LE) indication
7:5
N/A
0x2
4:0
117 [6:2]
0x0A
Description
These bits indicate that the received sync word is a frame synchronization code.
The value is programmable by a register setting.
Data Classification Codes
BL, IMG, CRC, and TR codes are defined by the same
registers as in 10−bit mode. Bits 9:2 of the respective
configuration registers are used as classification code with
default values shown in Table 32.
Window Identification
Similar to 10−bit operation mode, the frame
synchronization codes are followed by a window
identification. The window ID is located in bits 5:2 (all other
bit positions are ‘0’). The same restriction for overlapping
windows applies in 8−bit mode.
Table 32. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 8−BIT MODE
Sync Word Bit
Position
Register Address
Default Value
7:0
118 [9:2]
0x05
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
7:0
119 [9:2]
0x0D
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the image).
7:0
125 [9:2]
0x16
CRC value. The data on the data output channels is the CRC code of the finished image data line.
7:0
126 [9:2]
0xE9
Training Pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
Description
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NOIP1SN5000A, NOIP1SN2000A
Training Patterns on Data Channels
In 10−bit mode, during idle periods, the data channels transmit training patterns, indicated on the sync channel by a TR code.
These training patterns are configurable independent of the training code on the sync channel as shown in Table 33.
Table 33. TRAINING CODE ON SYNC CHANNEL IN 10−BIT MODE
Sync Word Bit
Position
Register Address
Default
Value
[9:0]
116 [9:0]
0x3A6
Description
Data channel training pattern. The data output channels send out the training pattern, which can be
programmed by a register setting. The default value of the training pattern is 0x3A6, which is identical
to the training pattern indication code on the sync channel.
In 8−bit mode, the training pattern for the data channels is defined by the same register as in 10−bit mode, where the lower
two bits are omitted; see Table 34.
Table 34. TRAINING PATTERN ON DATA CHANNEL IN 8−BIT MODE
Data Word Bit
Position
Register Address
Default
Value
[7:0]
116 [9:2]
0xE9
Description
Data Channel Training Pattern (Training pattern).
Cyclic Redundancy Code
Data Order for P1−SN/SE Version
At the end of each line, a CRC code is calculated to allow
error detection at the receiving end. Each data channel
transmits a CRC code to protect the data words sent during
the previous cycles. Idle and training patterns are not
included in the calculation.
The sync channel is not protected. A special character
(CRC indication) is transmitted whenever the data channels
send their respective CRC code.
The polynomial in 10−bit operation mode is
x10 + x9 + x6 + x3 + x2 + x + 1. The CRC encoder is seeded
at the start of a new line and updated for every (valid) data
word received. The CRC seed is configurable using the
crc_seed register. When ‘0’, the CRC is seeded by all−‘0’;
when ‘1’ it is seeded with all−‘1’.
In 8−bit mode, the polynomial is x8 + x6 + x3 + x2 + 1.
The CRC seed is configured by means of the crc_seed
register.
NOTE: The CRC is calculated for every line. This
implies that the CRC code can protect lines from
multiple windows.
To read out the image data through the output channels,
the pixel array is organized in kernels. The kernel size is
sixteen pixels in x−direction by one pixel in y−direction. The
data order in 8−bit mode is identical to the 10−bit mode.
Figure 37 indicates how the kernels are organized. The first
kernel (kernel [0, 0]) is located in the bottom left corner. The
data order of this image data on the data output channels
depends on the subsampling mode.
kernel
(161,2047)
pixel array
ROI
kernel
(x_start,y_start)
kernel
(0,0)
0
1
2
3
13
14
15
Figure 37. Kernel Organization in Pixel Array
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45
NOIP1SN5000A, NOIP1SN2000A
• P1−SN/SE: Subsampling Disabled
Figure 38 shows how a kernel is read out over the eight
output channels. For even positioned kernels, the kernels are
read out ascending, while for odd positioned kernels the data
order is reversed (descending).
8 LVDS Output Channels
The image data is read out in kernels of 16 pixels in
x−direction by one pixel in y−direction. One data channel
output delivers two pixel values of one kernel sequentially.
♦
kernel N−2
kernel N−1
kernel N
kernel N+1
3
4
11
12
13
14
15
pixel # (odd kernel)
15
14
13
12
11
4
3
2
1
0
MSB
LSB
MSB
channel #7
2
channel #6
1
channel #1
0
channel #0
pixel # (even kernel)
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 38. 8 LVDS Data Output Order when Subsampling is Disabled
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46
NOIP1SN5000A, NOIP1SN2000A
♦ 4 LVDS Output Channels
Figure 39 shows how a kernel is read out over the four
output channels. For even positioned kernels, the kernels are
kernel N−2
kernel N−1
read out ascending but in pair of even and odd pixels, while
for odd positioned kernels, the data order is reversed
(descending − in pair of even and odd pixels).
kernel N
kernel N+1
3
4
6
5
7
8
10
9
11
12
14
13
15
pixel # (odd kernel)
15
13
14
12
11
9
10
8
7
5
6
4
3
1
2
0
MSB
LSB
MSB
channel #6
1
channel #4
2
channel #2
0
channel #0
pixel # (even kernel)
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 39. 4 LVDS Data Output Order when Subsampling is Disabled
♦ 2 LVDS Output Channels
Figure 40 shows how a kernel is read out over 2 output
channels. Each group of four adjacent channels is
multiplexed on to one channel. For even positioned kernels,
kernel N−2
kernel N−1
the kernels are read out in an ascending order but in sets of
four even and four odd pixels, while for odd positioned
kernels the data order is reversed (descending and in sets of
four odd and four even pixels).
kernel N
kernel N+1
2
4
6
1
3
5
7
8
10
12
14
9
11
13
15
pixel # (odd kernel)
15
13
11
9
14
12
10
8
7
5
3
1
6
4
2
0
MSB
LSB
10−bit
channel #4
0
channel #0
pixel # (even kernel)
MSB
LSB
10−bit
Note: The bit order is always MSB first
Figure 40. 2 LVDS Data Output Order when Subsampling is Disabled
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47
NOIP1SN5000A, NOIP1SN2000A
♦ 1 LVDS Output Channel
Figure 41 shows how a kernel is read out over 1 output
channel. Eight adjacent channels are multiplexed into one
channel. For even positioned kernels, the kernels are read
kernel N−2
kernel N−1
out ascending but in sets of 8 even and 8 odd pixels, while
for odd positioned kernels the data order is reversed
(descending − in sets of 8 odd and 8 even pixels).
kernel N
kernel N+1
0
2
4
6
8
10
12
14
1
3
5
7
9
11
13
15
pixel # (odd kernel)
15
13
11
9
7
5
3
1
14
12
10
8
6
4
2
0
channel #0
pixel # (even kernel)
MSB
MSB
LSB
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 41. 1 LVDS Data Output Order when Subsampling is Disabled
• Subsampling on Monochrome Sensor
Only the pixels at the even pixel positions inside that kernel
are read out.
♦ 8 LVDS Output Channels
Figure 42 shows the data order for 8 LVDS output
channels. Note that there is no difference in data order for
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
26
6
24
8
22
10
20
12
18
14
16
channel #7
4
kernel N+1
channel #5
28
channel #4
2
kernel N
channel #3
30
channel #1
0
channel #0
pixel #
kernel N−1
channel #2
kernel N−2
channel #6
During subsampling on a monochrome sensor, every
other pixel is read out and the lines are read in a
read-1-skip-1 manner. To read out the image data with
subsampling enabled on a monochrome sensor, two
neighboring kernels are combined to a single kernel of
32 pixels in the x−direction and one pixel in the y−direction.
Figure 42. Data Output Order for 8 LVDS Output Channels in Subsampling Mode on a Monochrome Sensor
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48
NOIP1SN5000A, NOIP1SN2000A
2
30
28
4
6
kernel N
26
24
8
kernel N+1
10
channel #2
0
channel #0
pixel #
kernel N−1
22
20
12
14
channel #4
kernel N−2
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
18
16
channel #6
♦ 4 LVDS Output Channels
Figure 43 shows the data order for 4 LVDS output
channels. Note that there is no difference in data order for
Figure 43. Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a Monochrome Sensor
♦ 2 LVDS Output Channels
Figure 44 shows the data order for 2 LVDS output
channels. Note that there is no difference in data order for
0
2
4
6
30
28
kernel N
26
24
8
kernel N+1
10
12
channel #0
pixel #
kernel N−1
14
22
20
18
16
channel #4
kernel N−2
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 44. Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a Monochrome Sensor
♦ 1 LVDS Output Channel
Figure 45 shows the data order for 1 LVDS output
channel. Note that there is no difference in data order for
kernel N−2
0
2
kernel N−1
4
6
8
10
kernel N
12
14
30
kernel N+1
28
26
24
22
20
18
16
channel #0
pixel #
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 45. Data Output Order for 1 LVDS Output Channels in Subsampling Mode on a Monochrome Sensor
• Binning on Monochrome Sensor
The output order in binning mode is identical to the
subsampled mode.
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49
NOIP1SN5000A, NOIP1SN2000A
• Subsampling on Color Sensor
♦ 8 LVDS Output Channels
Figure 46 shows the data order for 8 LVDS output
channels. Note that there is no difference in data order for
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
25
5
24
8
21
9
20
12
17
13
16
channel #7
4
channel #5
28
kernel N+1
channel #4
1
kernel N
channel #2
29
channel #1
0
channel #0
pixel #
kernel N−1
channel #3
kernel N−2
channel #6
During subsampling on a color sensor, lines are read in a
read-2-skip−2 manner. To read out the image data with
subsampling enabled on a color sensor, two neighboring
kernels are combined to a single kernel of 16 pixels in the
x−direction and one pixel in the y−direction. Only the pixels
0, 1, 4, 5, 8, 9, … 28, 29 are read out.
Figure 46. Data Output Order for 8 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 4 LVDS Output Channels
Figure 47 shows the data order for 4 LVDS output
channels. Note that there is no difference in data order for
29
28
4
5
25
24
8
kernel N+1
9
21
20
12
13
17
16
channel #6
1
kernel N
channel #2
0
channel #0
pixel #
kernel N−1
channel #4
kernel N−2
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 47. Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 2 LVDS Output Channels
Figure 48 shows the data order for 2 LVDS output
channels. Note that there is no difference in data order for
0
1
4
5
29
28
kernel N
25
24
8
channel #0
pixel #
kernel N−1
kernel N+1
9
12
13
21
20
17
16
channel #4
kernel N−2
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 48. Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a Color Sensor
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50
NOIP1SN5000A, NOIP1SN2000A
♦ 1 LVDS Output Channel
Figure 49 shows the data order for 1 LVDS output
channel. Note that there is no difference in data order for
kernel N−2
0
1
kernel N−1
4
5
8
9
kernel N
12
13
29
kernel N+1
28
25
24
21
20
17
16
channel #0
pixel #
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 49. Data Output Order for 1 LVDS Output Channel in Subsampling Mode on a Color Sensor
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51
NOIP1SN5000A, NOIP1SN2000A
REGISTER MAP
The table below represents the register map for the NOIP1xx5000A part. Deviating default values for the NOIP1xx2000A
sensor are mentioned between brackets (“[ ]”).
Table 35. REGISTER MAP
Address
Offset
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
Type
Chip ID [Block Offset: 0]
0
0
chip_id
0x5032
20530
Chip ID
id
0x5032
20530
Chip ID
reserved
0x0001
[0x0101]
1
[257]
Reserved
[3:0]
reserved
0x1
1
Reserved
[9:8]
resolution
0x0 [0x1]
0 [1]
Sensor Resolution
‘0’: NOIP1xx5000A
‘1’: NOIP1xx2000A
[11:10]
reserved
0x0
0
Reserved
chip_configuration
0x0000
0
Chip General Configuration
color
0x0
0
Colour/Monochrome Configuration
‘0’: Monochrome
‘1’: Color
[3:2]
glob_config
0x0
0
Sensor pinout configuration
[15:4]
reserved
0x000
0
Reserved
[15:0]
1
2
1
2
[0]
Status
Status
RW
Reset Generator [Block Offset: 8]
0
1
8
soft_reset_pll
0x0099
153
PLL Soft Reset Configuration
[3:0]
pll_soft_reset
0x9
9
PLL Reset
0x9: Soft Reset State
others: Operational
[7:4]
pll_lock_soft_reset
0x9
9
PLL Lock Detect Reset
0x9: Soft Reset State
others: Operational
soft_reset_cgen
0x0009
9
Clock Generator Soft Reset
cgen_soft_reset
0x9
9
Clock Generator Reset
0x9: Soft Reset State
others: Operational
soft_reset_analog
0x0999
2457
Analog Block Soft Reset
[3:0]
mux_soft_reset
0x9
9
Column MUX Reset
0x9: Soft Reset State
others: Operational
[7:4]
afe_soft_reset
0x9
9
AFE Reset
0x9: Soft Reset State
others: Operational
[11:8]
ser_soft_reset
0x9
9
Serializer Reset
0x9: Soft Reset State
others: Operational
9
[3:0]
2
10
RW
RW
RW
PLL [Block Offset: 16]
0
1
16
power_down
0x0004
4
PLL Configuration
[0]
pwd_n
0x0
0
PLL Power Down
‘0’: Power Down,
‘1’: Operational
[1]
enable
0x0
0
PLL Enable
‘0’: disabled,
‘1’: enabled
[2]
bypass
0x1
1
PLL Bypass
‘0’: PLL Active,
‘1’: PLL Bypassed
reserved
0x2113
8467
Reserved
reserved
0x13
19
Reserved
17
[7:0]
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52
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
[12:8]
reserved
0x1
1
Reserved
[14:13]
reserved
0x1
1
Reserved
config1
0x0000
0
IO Configuration
clock_in_pwd_n
0x0
0
Power down Clock Input
[9:8]
reserved
0x0
0
Reserved
[10]
reserved
0x0
0
Reserved
pll_lock
0x0000
0
PLL Lock Indication
lock
0x0
0
PLL Lock Indication
reserved
0x2280
8832
Reserved
Type
I/O [Block Offset: 20]
0
20
[0]
RW
PLL Lock Detector [Block Offset: 24]
0
24
[0]
2
3
26
[7:0]
reserved
0x80
128
Reserved
[10:8]
reserved
0x2
2
Reserved
[14:12]
reserved
0x2
2
Reserved
reserved
0x3D2D
15661
Reserved
[7:0]
reserved
0x2D
45
Reserved
[15:8]
reserved
0x3D
61
Reserved
27
Status
RW
RW
Clock Generator [Block Offset: 32]
0
32
config0
0x0004
4
Clock Generator Configuration
[0]
enable_analog
0x0
0
Enable analogue clocks
‘0’: disabled,
‘1’: enabled
[1]
enable_log
0x0
0
Enable logic clock
‘0’: disabled,
‘1’: enabled
[2]
select_pll
0x1
1
Input Clock Selection
‘0’: Select LVDS clock input,
‘1’: Select PLL clock input
[3]
adc_mode
0x0
0
Set operation mode of CGEN block
‘0’: divide by 5 mode (10−bit mode),
‘1’: divide by 4 mode (8−bit mode)
[5:4]
mux
0x0
0
Multiplex Mode
[11:8]
reserved
0x0
0
Reserved
[14:12]
reserved
0x0
0
Reserved
config0
0x0000
0
Clock Generator Configuration
enable
0x0
0
Logic General Enable Configuration
‘0’: Disable
‘1’: Enable
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
image_core_config0
0x0000
0
Image Core Configuration
imc_pwd_n
0x0
0
Image Core Power Down
‘0’: powered down,
‘1’: powered up
RW
General Logic [Block Offset: 34]
0
34
[0]
0
38
[15:0]
1
39
[15:0]
RW
RW
RW
Image Core [Block Offset: 40]
0
40
[0]
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53
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
1
2
3
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
[1]
mux_pwd_n
0x0
0
Column Multiplexer Power Down
‘0’: powered down,
‘1’: powered up
[2]
colbias_enable
0x0
0
Bias Enable
‘0’: disabled
‘1’: enabled
image_core_config1
0x0B5A
2906
Image Core Configuration
[3:0]
dac_ds
0xA
10
Double Slope Reset Level
[7:4]
dac_ts
0x5
5
Triple Slope Reset Level
41
[10:8]
reserved
0x3
3
Reserved
[12:11]
reserved
0x1
1
Reserved
[13]
reserved
0x0
0
Reserved
[14]
reserved
0x0
0
Reserved
[15]
reserved
0x0
0
Reserved
42
reserved
0x0001
1
Reserved
[0]
reserved
0x1
1
Reserved
[1]
reserved
0x0
0
Reserved
[6:4]
reserved
0x0
0
Reserved
[10:8]
reserved
0x0
0
Reserved
[15:12]
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
[0]
reserved
0x0
0
Reserved
[1]
reserved
0x0
0
Reserved
[2]
reserved
0x0
0
Reserved
43
[3]
reserved
0x0
0
Reserved
[6:4]
reserved
0x0
0
Reserved
[7]
reserved
0x0
0
Reserved
[15:8]
reserved
0x0
0
Reserved
power_down
0x0000
0
AFE Configuration
pwd_n
0x0
0
Power down for AFE’s
‘0’: powered down,
‘1’: powered up
power_down
0x0000
0
Bias Power Down Configuration
pwd_n
0x0
0
Power down bandgap
‘0’: powered down,
‘1’: powered up
configuration
0x888B
34955
Bias Configuration
extres
0x1
1
External Resistor Selection
‘0’: internal resistor,
‘1’: external resistor
[3:1]
reserved
0x5
5
Reserved
[7:4]
reserved
0x8
8
Reserved
[11:8]
reserved
0x8
8
Reserved
[15:12]
reserved
0x8
8
Reserved
Type
RW
RW
RW
AFE [Block Offset: 48]
0
48
[0]
RW
Bias [Block Offset: 64]
0
64
[0]
1
65
[0]
2
66
reserved
0x53C8
21448
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0xC
12
Reserved
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54
RW
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
Bit Field
[14:8]
3
4
5
6
7
67
Register Name
Default
(Hex)
Default
Description
reserved
0x53
83
Reserved
reserved
0x8888
34952
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0x8
8
Reserved
[11:8]
reserved
0x8
8
Reserved
[15:12]
reserved
0x8
8
Reserved
68
lvds_bias
0x0088
136
LVDS Bias Configuration
[3:0]
lvds_ibias
0x8
8
LVDS Ibias
[7:4]
lvds_iref
0x8
8
LVDS Iref
reserved
0x0888
2184
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0x8
8
Reserved
[11:8]
reserved
0x8
8
Reserved
69
70
reserved
0x8888
34952
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0x8
8
Reserved
[11:8]
reserved
0x8
8
Reserved
[15:12]
reserved
0x8
8
Reserved
reserved
0x8888
34952
Reserved
reserved
0x8888
34952
Reserved
71
[15:0]
Type
RW
RW
RW
RW
RW
Charge Pump [Block Offset: 72]
0
72
configuration
0x2220
8736
Charge Pump Configuration
[0]
trans_pwd_n
0x0
0
PD Trans Charge Pump Enable
‘0’: disabled,
‘1’: enabled
[1]
resfd_calib_pwd_n
0x0
0
FD Charge Pump Enable
‘0’: disabled,
‘1’: enabled
[2]
sel_sample_pwd_n
0x0
0
Select/Sample Charge Pump Enable
‘0’: disabled
‘1’: enabled
[6:4]
reserved
0x2
2
Reserved
[10:8]
reserved
0x2
2
Reserved
[14:12]
reserved
0x2
2
Reserved
RW
Charge Pump [Block Offset: 80]
0
1
80
reserved
0x0000
0
Reserved
[1:0]
reserved
0x0
0
Reserved
[3:2]
reserved
0x0
0
Reserved
[5:4]
reserved
0x0
0
Reserved
[7:6]
reserved
0x0
0
Reserved
[9:8]
reserved
0x0
0
Reserved
reserved
0x8881
34945
Reserved
reserved
0x8881
34945
Reserved
enable
0x0000
0
Temperature Sensor Configuration
enable
0x0
0
Temperature Diode Enable
‘0’: disabled,
‘1’: enabled
81
[15:0]
RW
RW
Temperature Sensor [Block Offset: 96]
0
96
[0]
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55
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
Bit Field
Default
(Hex)
Default
Description
[1]
reserved
0x0
0
Reserved
[2]
reserved
0x0
0
Reserved
[3]
reserved
0x0
0
Reserved
[4]
reserved
0x0
0
Reserved
[5]
reserved
0x0
0
Reserved
offset
0x0
0
Temperature Offset (signed)
temp
0x0000
0
Temperature Sensor Status
temp
0x00
0
Temperature Readout
reserved
0x0000
0
Reserved
reserved
0x0
0
Reserved
[13:8]
1
Register Name
97
[7:0]
Type
Status
Temperature Sensor [Block Offset: 104]
0
104
[15:0]
1
2
105
reserved
0x0000
0
Reserved
[1:0]
reserved
0x0
0
Reserved
[6:2]
reserved
0x0
0
Reserved
[7]
reserved
0x0
0
Reserved
[9:8]
reserved
0x0
0
Reserved
[14:10]
reserved
0x0
0
Reserved
[15]
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
106
[15:0]
3
107
4
108
5
109
[15:0]
[15:0]
[15:0]
6
110
[15:0]
7
111
[15:0]
RW
RW
Status
Status
Status
Status
Status
Status
Serializers / LVDS / IO [Block Offset: 112]
0
112
power_down
0x0000
0
LVDS Power Down Configuration
[0]
clock_out_pwd_n
0x0
0
Power down for Clock Output.
‘0’: powered down,
‘1’: powered up
[1]
sync_pwd_n
0x0
0
Power down for Sync channel
‘0’: powered down,
‘1’: powered up
[2]
data_pwd_n
0x0
0
Power down for data channels (4 channels)
‘0’: powered down,
‘1’: powered up
trainingpattern
0x03A6
934
Data Formating − Training Pattern
trainingpattern
0x3A6
934
Training pattern sent on Data channels during
idle mode. This data is used to perform word
alignment on the LVDS data channels.
sync_code0
0x002A
42
LVDS Power Down Configuration
frame_sync_0
0x02A
42
Frame Sync Code LSBs − Even kernels
RW
Sync Words [Block Offset: 116]
4
116
[9:0]
5
117
[6:0]
www.onsemi.com
56
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
6
118
Bit Field
[9:0]
7
119
[9:0]
8
120
[9:0]
9
121
[6:0]
10
122
[9:0]
11
123
[9:0]
12
124
[9:0]
13
125
14
126
15
127
[9:0]
[9:0]
[9:0]
Register Name
Default
(Hex)
Default
Description
sync_code1
0x0015
21
Data Formating − BL Indication
bl_0
0x015
21
Black Pixel Identification Sync Code − Even
kernels
sync_code2
0x0035
53
Data Formating − IMG Indication
img_0
0x035
53
Valid Pixel Identification Sync Code − Even
kernels
sync_code3
0x0025
37
Data Formating − IMG Indication
ref_0
0x025
37
Reference Pixel Identification Sync Code −
Even kernels
sync_code4
0x002A
42
LVDS Power Down Configuration
frame_sync_1
0x02A
42
Frame Sync Code LSBs − Odd kernels
sync_code5
0x0015
21
Data Formating − BL Indication
bl_1
0x015
21
Black Pixel Identification Sync Code − Odd
kernels
sync_code6
0x0035
53
Data Formating − IMG Indication
img_1
0x035
53
Valid Pixel Identification Sync Code − Odd
kernels
sync_code7
0x0025
37
Data Formating − IMG Indication
ref_1
0x025
37
Reference Pixel Identification Sync Code −
Odd kernels
sync_code8
0x0059
89
Data Formating − CRC Indication
crc
0x059
89
CRC Value Identification Sync Code
sync_code9
0x03A6
934
Data Formating − TR Indication
tr
0x3A6
934
Training Value Identification Sync Code
reserved
0x02AA
682
Reserved
reserved
0x2AA
682
Reserved
blackcal
0x4008
16392
Black Calibration Configuration
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Data Block [Block Offset: 128]
0
1
128
[7:0]
black_offset
0x08
8
Desired black level at output
[10:8]
black_samples
0x0
0
Black pixels taken into account for black calibration.
Total samples = 2**black_samples
[14:11]
reserved
0x8
8
Reserved
[15]
crc_seed
0x0
0
CRC Seed
‘0’: All−0
‘1’: All−1
general_configuration
0x0001
1
Black Calibration and Data Formating
Configuration
auto_blackcal_enable
0x1
1
Automatic blackcalibration is enabled when 1,
bypassed when 0
[9:1]
blackcal_offset
0x00
0
Black Calibration offset used when auto_black_cal_en = ‘0’.
[10]
blackcal_offset_dec
0x0
0
blackcal_offset is added when 0, subtracted
when 1
129
[0]
[11]
reserved
0x0
0
Reserved
[12]
reserved
0x0
0
Reserved
[13]
8bit_mode
0x0
0
Shifts window ID indications by 4 cycles.
‘0’: 10 bit mode,
‘1’: 8 bit mode
[14]
ref_mode
0x0
0
Data contained on reference lines:
‘0’: reference pixels
‘1’: black average for the corresponding data
channel
www.onsemi.com
57
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
Bit Field
[15]
2
8
130
139
12
140
Reserved
Reserved
[1]
reserved
0x1
1
Reserved
[2]
reserved
0x1
1
Reserved
[3]
reserved
0x1
1
Reserved
[4]
reserved
0x0
0
Reserved
[8]
reserved
0x0
0
Reserved
blackcal_error0
0x0000
0
Black Calibration Status
blackcal_error[15:0]
0x0000
0
Black Calibration Error. This flag is set when
not enough black samples are available.
Black Calibration shall not be valid. Channels
0−16
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0xFFFF
65535
Reserved
reserved
0xFFFF
65535
Reserved
141
[15:0]
144
145
18
146
test_configuration
0x0000
0
Data Formating Test Configuration
[0]
testpattern_en
0x0
0
Insert synthesized testpattern when ‘1’
[1]
inc_testpattern
0x0
0
Incrementing testpattern when ‘1’, constant
testpattern when ‘0’
[2]
prbs_en
0x0
0
Insert PRBS when ‘1’
[3]
frame_testpattern
0x0
0
Frame test patterns when ‘1’, unframed testpatterns when ‘0’
[4]
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
[15:0]
19
Enable black calibration on reference lines
‘0’: Disabled
‘1’: Enabled
1
[15:0]
17
0
15
[15:0]
16
0x0
0x1
[15:0]
13
ref_bcal_enable
0x000F
[15:0]
11
Description
reserved
137
138
Default
reserved
136
10
Default
(Hex)
[0]
[15:0]
9
Register Name
0
Reserved
test_configuration0
0x0100
256
Data Formating Test Configuration
[7:0]
testpattern0_lsb
0x00
0
Testpattern used on datapath #0 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
[15:8]
testpattern1_lsb
0x01
1
Testpattern used on datapath #1 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
test_configuration1
0x0302
770
Data Formating Test Configuration
testpattern2_lsb
0x02
2
Testpattern used on datapath #2 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
147
[7:0]
reserved
www.onsemi.com
58
Type
RW
Status
Status
Status
Status
RW
RW
RW
RW
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
Bit Field
[15:8]
20
21
22
26
148
Default
(Hex)
Default
Description
testpattern3_lsb
0x03
3
Testpattern used on datapath #3 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
test_configuration2
0x0504
1284
Data Formating Test Configuration
[7:0]
testpattern4_lsb
0x04
4
Testpattern used on datapath #4 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
[15:8]
testpattern5_lsb
0x05
5
Testpattern used on datapath #5 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
test_configuration3
0x0706
1798
Data Formating Test Configuration
[7:0]
testpattern6_lsb
0x06
6
Testpattern used on datapath #6 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
[15:8]
testpattern7_lsb
0x07
7
Testpattern used on datapath #7 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in
register 150.
test_configuration16
0x0000
0
Data Formating Test Configuration
[1:0]
testpattern0_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[3:2]
testpattern1_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[5:4]
testpattern2_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[7:6]
testpattern3_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[9:8]
testpattern4_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
149
150
[11:10]
testpattern5_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[13:12]
testpattern6_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
[15:14]
testpattern7_msb
0x0
0
Testpattern used when testpattern_en = ‘1’
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
154
[15:0]
27
Register Name
155
[15:0]
Type
RW
RW
RW
RW
RW
AEC [Block Offset: 160]
0
1
160
configuration
0x0010
16
AEC Configuration
[0]
enable
0x0
0
AEC Enable
[1]
restart_filter
0x0
0
Restart AEC filter
[2]
freeze
0x0
0
Freeze AEC filter and enforcer gains
[3]
pixel_valid
0x0
0
Use every pixel from channel when 0, every
4th pixel when 1
[4]
amp_pri
0x1
1
Column amplifier gets higher priority than AFE
PGA in gain distribution if 1. Vice versa if 0
intensity
0x60B8
24760
AEC Configuration
desired_intensity
0xB8
184
Target average intensity
reserved
0x018
24
Reserved
red_scale_factor
0x0080
128
Red Scale Factor
red_scale_factor
0x80
128
Red Scale Factor
3.7 unsigned
161
[9:0]
[15:10]
2
162
[9:0]
www.onsemi.com
59
RW
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
3
163
Bit Field
[9:0]
4
164
[9:0]
5
165
[9:0]
6
166
[15:0]
7
167
8
168
9
169
12
13
14
128
Green1 Scale Factor
green1_scale_factor
0x80
128
Green1 Scale Factor
3.7 unsigned
green2_scale_factor
0x0080
128
Green2 Scale Factor
green2_scale_factor
0x80
128
Green2 Scale Factor
3.7 unsigned
blue_scale_factor
0x0080
128
Blue Scale Factor
blue_scale_factor
0x80
128
Blue Scale Factor
3.7 unsigned
reserved
0x03FF
1023
Reserved
reserved
0x03FF
1023
Reserved
2048
Reserved
0
Reserved
[3:2]
reserved
0x0
0
Reserved
[15:4]
reserved
0x080
128
Reserved
min_exposure
0x0001
1
Minimum Exposure Time
min_exposure
0x0001
1
Minimum Exposure Time
min_gain
0x0800
2048
Minimum Gain
[1:0]
min_mux_gain
0x0
0
Minimum Column Amplifier Gain
[3:2]
min_afe_gain
0x0
0
Minimum AFE PGA Gain
[15:4]
min_digital_gain
0x080
128
Minimum Digital Gain
5.7 unsigned
max_exposure
0x03FF
1023
Maximum Exposure Time
max_exposure
0x03FF
1023
Maximum Exposure Time
max_gain
0x100D
4109
Maximum Gain
[1:0]
max_mux_gain
0x1
1
Maximum Column Amplifier Gain
[3:2]
max_afe_gain
0x3
3
Maximum AFE PGA Gain
[15:4]
max_digital_gain
0x100
256
Maximum Digital Gain
5.7 unsigned
reserved
0x0083
131
Reserved
[7:0]
reserved
0x083
131
Reserved
[13:8]
reserved
0x00
0
Reserved
[15:14]
reserved
0x0
0
Reserved
reserved
0x2824
10276
Reserved
[7:0]
reserved
0x024
36
Reserved
[15:8]
reserved
0x028
40
Reserved
reserved
0x2A96
10902
Reserved
[3:0]
reserved
0x6
6
Reserved
[7:4]
reserved
0x9
9
Reserved
[11:8]
reserved
0xA
10
Reserved
[15:12]
reserved
0x2
2
Reserved
reserved
0x0080
128
Reserved
reserved
0x080
128
Reserved
reserved
0x0100
256
Reserved
reserved
0x100
256
Reserved
173
174
176
0x0080
0x0
172
16
green1_scale_factor
0x0800
171
175
Description
reserved
170
15
Default
reserved
[15:0]
11
Default
(Hex)
[1:0]
[15:0]
10
Register Name
[9:0]
[9:0]
www.onsemi.com
60
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
17
177
18
178
19
179
Bit Field
Reserved
reserved
0x100
256
Reserved
reserved
0x0080
128
Reserved
reserved
0x080
128
Reserved
reserved
0x00AA
170
Reserved
reserved
0x0AA
170
Reserved
reserved
0x0100
256
Reserved
reserved
0x100
256
Reserved
reserved
0x0155
341
Reserved
reserved
0x155
341
Reserved
total_pixels0
0x0000
0
AEC Status
total_pixels[15:0]
0x0000
0
Total number of pixels sampled for Average,
LSB
total_pixels1
0x0000
0
AEC Status
total_pixels[23:16]
0x0
0
Total number of pixels sampled for Average,
MSB
average_status
0x0000
0
ASE Status
[9:0]
average
0x000
0
AEC Average Status
[12]
avg_locked
0x0
0
AEC Average Lock Status
exposure_status
0x0000
0
ASE Status
exposure
0x0000
0
AEC Expsosure Status
gain_status
0x0000
0
ASE Status
[1:0]
mux_gain
0x0
0
AEC MUX Gain Status
[3:2]
afe_gain
0x0
0
AEC AFE Gain Status
[15:4]
digital_gain
0x000
0
AEC Digital Gain Status
5.7 unsigned
180
[9:0]
181
[9:0]
184
[15:0]
25
185
[7:0]
26
186
27
187
28
188
[15:0]
29
Description
256
[9:0]
24
Default
0x0100
[9:0]
21
Default
(Hex)
reserved
[9:0]
20
Register Name
189
reserved
0x0000
0
Reserved
[12:0]
reserved
0x000
0
Reserved
[13]
reserved
0x0
0
Reserved
general_configuration
0x0000
0
Sequencer General Cofniguration
[0]
enable
0x0
0
Enable sequencer
‘0’: Idle,
‘1’: enabled
[1]
reserved
0x0
0
Reserved
[2]
zero_rot_enable
0x0
0
Zero ROT mode Selection.
‘0’: Non−Zero ROT,
‘1’: Zero ROT’
[3]
reserved
0x0
0
Reserved
[4]
triggered_mode
0x0
0
Triggered Mode Selection (Snapshot Shutter
only)
‘0’: Normal Mode,
‘1’: Triggered Mode
[5]
slave_mode
0x0
0
Master/Slave Selection (Snapshot Shutter
only)
‘0’: master,
‘1’: slave
[6]
nzrot_xsm_delay_
enable
0x0
0
Insert delay between end of ROT and start of
readout in Non−Zero ROT readout mode if ‘1’.
ROT delay is defined by register xsm_delay
Type
RW
RW
RW
RW
RW
Status
Status
Status
Status
Status
Status
Sequencer [Block Offset: 192]
0
192
www.onsemi.com
61
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
1
2
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
[7]
subsampling
0x0
0
Subsampling mode selection
‘0’: no subsampling,
‘1’: subsampling
[8]
binning
0x0
0
Binning mode selection
‘0’: no binning,
‘1’: binning
[10]
roi_aec_enable
0x0
0
Enable windowing for AEC Statistics.
‘0’: Subsample all windows
‘1’: Subsample configured window
[13:11]
monitor_select
0x0
0
Control of the monitor pins
[14]
reserved
0x0
0
Reserved
[15]
sequence
0x0
0
Enable a sequenced readout with different
parameters for even and odd frames.
reserved
0x0000
0
Reserved
[7:0]
reserved
0x00
0
Reserved
[15:8]
reserved
0x00
0
Reserved
193
194
integration_control
0x00E4
228
Integration Control
[0]
dual_slope_enable
0x0
0
Enable Dual Slope
[1]
triple_slope_enable
0x0
0
Enable Triple Slope
[2]
fr_mode
0x1
1
Representation of fr_length.
‘0’: reset length
‘1’: frame length
[3]
reserved
0x0
0
Reserved
[4]
int_priority
0x0
0
Integration Priority
‘0’: Frame readout has priority over integration
‘1’: Integration End has priority over frame
readout
[5]
halt_mode
0x1
1
The current frame will be completed when the
sequencer is disabled and halt_mode = ‘1’.
When ‘0’, the sensor stops immediately when
disabled, without finishing the current frame.
[6]
fss_enable
0x1
1
Generation of Frame Sequence Start Sync
code (FSS)
‘0’: No generation of FSS
‘1’: Generation of FSS
[7]
fse_enable
0x1
1
Generation of Frame Sequence End Sync
code (FSE)
‘0’: No generation of FSE
‘1’: Generation of FSE
[8]
reverse_y
0x0
0
Reverse readout
‘0’: bottom to top readout
‘1’: top to bottom readout
[9]
reserved
0x0
0
Reserved
[11:10]
subsampling_mode
0x0
0
Subsampling mode
0x0: Subsampling in x and y (VITA
compatible)
0x1: Subsampling in x, not y
0x2: Subsampling in y, not x
0x3: Subsampling in x an y
[13:12]
binning_mode
0x0
0
Binning mode
0x0: Binning in x and y (VITA compatible)
0x1: Binning in x, not y
0x2: Binning in y, not x
0x3: Binning in x an y
[14]
reserved
0x0
0
Reserved
[15]
reserved
0x0
0
Reserved
www.onsemi.com
62
Type
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
3
195
Bit Field
196
5
197
198
7
199
Active ROI Selection
roi_active0
0x01
1
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[15] Roi15 Active
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
black_lines
0x0102
258
Black Line Configuration
[7:0]
black_lines
0x02
2
Number of black lines. Minimum is 1.
Range 1−255
[12:8]
gate_first_line
0x1
1
Blank out first lines
0: no blank
1−31: blank 1−31 lines
reserved
0x0000
0
Reserved
reserved
0x000
0
Reserved
mult_timer0
0x0001
1
Exposure/Frame Rate Configuration
mult_timer0
0x0001
1
Mult Timer
Defines granularity (unit = 1/PLL clock) of
exposure and reset_length
fr_length0
0x0000
0
Exposure/Frame Rate Configuration
fr_length0
0x0000
0
Frame/Reset length
Reset length when fr_mode = ‘0’,
Frame Length when fr_mode = ‘1’
Granularity defined by mult_timer
exposure0
0x0000
0
Exposure/Frame Rate Configuration
exposure0
0x0000
0
Exposure Time
Granularity defined by mult_timer
exposure_ds0
0x0000
0
Exposure/Frame Rate Configuration
exposure_ds0
0x0000
0
Exposure Time (Dual Slope)
Granularity defined by mult_timer
exposure_ts0
0x0000
0
Exposure/Frame Rate Configuration
exposure_ts0
0x0000
0
Exposure Time (Triple Slope)
Granularity defined by mult_timer
[15:0]
200
[15:0]
9
201
[15:0]
10
202
[15:0]
11
203
[15:0]
12
204
gain_configuration0
0x01E3
483
Gain Configuration
[4:0]
mux_gainsw0
0x03
3
Column Gain Setting
[12:5]
afe_gain0
0xF
15
AFE Programmable Gain Setting
gain_lat_comp
0x0
0
Postpone gain update by 1 frame when ‘1’ to
compensate for exposure time updates
latency.
Gain is applied at start of next frame if ‘0’
digital_gain_
configuration0
0x0080
128
Gain Configuration
db_gain0
0x080
128
Digital Gain
sync_configuration
0x037F
895
Synchronization Configuration
[0]
sync_rs_x_length
0x1
1
Update of rs_x_length will not be sync’ed at
start of frame when ‘0’
[1]
sync_black_lines
0x1
1
Update of black_lines will not be sync’ed at
start of frame when ‘0’
[2]
sync_dummy_lines
0x1
1
Update of dummy_lines will not be sync’ed at
start of frame when ‘0’
[3]
sync_exposure
0x1
1
Update of exposure will not be sync’ed at start
of frame when ‘0’
[4]
sync_gain
0x1
1
Update of gain settings (gain_sw, afe_gain)
will not be sync’ed at start of frame when ‘0’
[13]
13
205
14
206
Description
1
[11:0]
8
Default
0x0001
[15:0]
6
Default
(Hex)
roi_active0_0
[15:0]
4
Register Name
[11:0]
www.onsemi.com
63
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
15
Address
Bit Field
19
20
1
Update of roi updates (active_roi) will not be
sync’ed at start of frame when ‘0’
[6]
sync_ref_lines
0x1
1
Update of ref_lines will not be sync’ed at start
of frame when ‘0’
[8]
blank_roi_switch
0x1
1
Blank first frame after ROI switching
[9]
blank_
subsampling_ss
0x1
1
Blank first frame after subsampling/binning
mode switching
‘0’: No blanking
‘1’: Blanking
[10]
exposure_sync_
mode
0x0
0
When ‘0’, exposure configurations are sync’ed
at the start of FOT. When ‘1’, exposure configurations sync is disabled (continuously
syncing). This mode is only relevant for
Triggered snapshot − master mode, where the
exposure configurations are sync’ed at the
start of exposure rather than the start of FOT.
For all other modes it should be set to ‘0’.
Note: Sync is still postponed if
sync_exposure=‘0’.
ref_lines
0x0000
0
Reference Line Configuration
ref_lines
0x00
0
Number of Reference Lines
0−255
reserved
0xA100
41216
Reserved
[7:0]
reserved
0x00
0
Reserved
[15:8]
reserved
0xA1
161
Reserved
reserved
0x0E5B
3675
Reserved
[0]
reserved
0x1
1
Reserved
[1]
reserved
0x1
1
Reserved
[2]
reserved
0x0
0
Reserved
211
[3]
reserved
0x1
1
Reserved
[6:4]
reserved
0x5
5
Reserved
[15:8]
reserved
0xE
14
Reserved
reserved
0x0000
0
Reserved
[12:0]
reserved
0x0000
0
Reserved
[15]
reserved
0x0
0
Reserved
reserved
0x07FF
2047
Reserved
reserved
0x07FF
2047
Reserved
reserved
0x0000
0
Reserved
[7:0]
reserved
0x00
0
Reserved
[15:8]
reserved
0x0
0
Reserved
reserved
0x0103
259
Reserved
[0]
reserved
0x1
1
Reserved
[1]
reserved
0x1
1
Reserved
[2]
reserved
0x0
0
Reserved
[3]
reserved
0x0
0
Reserved
[4]
reserved
0x0
0
Reserved
[5]
reserved
0x0
0
Reserved
[6]
reserved
0x0
0
Reserved
[7]
reserved
0x0
0
Reserved
[8]
reserved
0x1
1
Reserved
[9]
reserved
0x0
0
Reserved
212
22
214
[12:0]
23
Description
0x1
208
213
Default
sync_roi
207
21
Default
(Hex)
[5]
[7:0]
16
Register Name
215
www.onsemi.com
64
Type
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
24
25
26
27
28
29
30
31
Address
Bit Field
33
34
Default
(Hex)
Default
Description
[10]
reserved
0x0
0
Reserved
[11]
reserved
0x0
0
Reserved
[12]
reserved
0x0
0
Reserved
[13]
reserved
0x0
0
Reserved
[14]
reserved
0x0
0
Reserved
reserved
0x7F08
32520
Reserved
[6:0]
reserved
0x08
8
Reserved
[14:8]
reserved
0x7F
127
Reserved
216
217
reserved
0x4444
17476
Reserved
[6:0]
reserved
0x44
68
Reserved
[14:8]
reserved
0x44
68
Reserved
218
reserved
0x4444
17476
Reserved
[6:0]
reserved
0x44
68
Reserved
[14:8]
reserved
0x44
68
Reserved
reserved
0x0016
22
Reserved
[6:0]
reserved
0x016
22
Reserved
[14:8]
reserved
0x00
0
Reserved
reserved
0x301F
12319
Reserved
[6:0]
reserved
0x1F
31
Reserved
[14:8]
reserved
0x30
48
Reserved
reserved
0x6245
25157
Reserved
[6:0]
reserved
0x45
69
Reserved
[14:8]
reserved
0x62
98
Reserved
219
220
221
222
reserved
0x6230
25136
Reserved
[6:0]
reserved
0x30
48
Reserved
[14:8]
reserved
0x62
98
Reserved
reserved
0x001A
26
Reserved
reserved
0x1A
26
Reserved
223
[6:0]
32
Register Name
224
reserved
0x3E01
15873
Reserved
[3:0]
reserved
0x1
1
Reserved
[7:4]
reserved
0x00
0
Reserved
[8]
reserved
0x0
0
Reserved
[9]
reserved
0x1
1
Reserved
[10]
reserved
0x1
1
Reserved
[11]
reserved
0x1
1
Reserved
[12]
reserved
0x1
1
Reserved
[13]
reserved
0x1
1
Reserved
reserved
0x5EF1
24305
Reserved
[4:0]
reserved
0x11
17
Reserved
[9:5]
reserved
0x17
23
Reserved
[14:10]
reserved
0x17
23
Reserved
[15]
reserved
0x0
0
Reserved
reserved
0x6000
24576
Reserved
reserved
0x00
0
Reserved
225
226
[4:0]
www.onsemi.com
65
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
35
36
Address
Bit Field
0
Reserved
[14:10]
reserved
0x18
24
Reserved
[15]
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
[0]
reserved
0x0
0
Reserved
[1]
reserved
0x0
0
Reserved
[2]
reserved
0x0
0
Reserved
[3]
reserved
0x0
0
Reserved
[4]
reserved
0x0
0
Reserved
roi_active0_1
0x0001
1
Active ROI Selection
roi_active1
0x01
1
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[15] Roi15 Active
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0001
1
Reserved
reserved
0x0001
1
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
228
229
230
[15:0]
231
40
232
41
233
[15:0]
[15:0]
[15:0]
42
234
[15:0]
43
44
235
reserved
0x01E3
483
Reserved
[4:0]
reserved
0x03
3
Reserved
[12:5]
reserved
0xF
15
Reserved
reserved
0x0080
128
Reserved
reserved
0x080
128
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0xFFFF
65535
Reserved
reserved
0xFFFF
65535
Reserved
reserved
0x0000
0
Reserved
reserved
0x0
0
Reserved
x_resolution
0x00A2
[0x007C]
162
[124]
Sequencer Status
x_resolution
0x000A2
[0x007C]
162
[124]
Sensor x resolution
y_resolution
0x0800
[0x04F0]
2048
[1264]
Sequencer Status
y_resolution
0x0800
[0x04F0]
2048
[1264]
Sensor y resolution
236
[11:0]
45
237
[15:0]
46
238
[15:0]
47
239
48
240
[15:0]
[7:0]
49
Description
0x00
227
39
Default
reserved
[15:0]
38
Default
(Hex)
[9:5]
[7:0]
37
Register Name
241
[12:0]
www.onsemi.com
66
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Status
Status
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
50
242
Bit Field
243
52
244
Sequencer Status
mult_timer
0x0000
0
Mult Timer Status (Master Snapshot Shutter
only)
reset_length_status
0x0000
0
Sequencer Status
reset_length
0x0000
0
Current Reset Length (not in Slave mode)
exposure_status
0x0000
0
Sequencer Status
exposure
0x0000
0
Current Exposure Time (not in Slave mode)
exposure_ds_status
0x0000
0
Sequencer Status
exposure_ds
0x0000
0
Current Exposure Time (not in Slave mode)
exposure_ts_status
0x0000
0
Sequencer Status
exposure_ts
0x0000
0
Current Exposure Time (not in Slave mode)
gain_status
0x0000
0
Sequencer Status
[4:0]
mux_gainsw
0x00
0
Current Column Gain Setting
[12:5]
afe_gain
0x00
0
Current AFE Programmable Gain
digital_gain_status
0x0000
0
Sequencer Status
db_gain
0x000
0
Digital Gain
[12]
dual_slope
0x0
0
Dual Slope Enabled
[13]
triple_slope
0x0
0
Triple Slope Enabled
reserved
0x0423
1059
Reserved
[4:0]
reserved
0x03
3
Reserved
[9:5]
reserved
0x01
1
Reserved
[14:10]
reserved
0x01
1
Reserved
245
[15:0]
246
[15:0]
55
56
247
248
[11:0]
58
59
60
61
62
250
251
reserved
0x030F
783
Reserved
[7:0]
reserved
0xF
15
Reserved
[15:8]
reserved
0x3
3
Reserved
reserved
0x0601
1537
Reserved
[7:0]
reserved
0x1
1
Reserved
[15:8]
reserved
0x6
6
Reserved
roi_aec_
configuration0
0x0000
0
AEC ROI Configuration
[7:0]
x_start
0x00
0
AEC ROI X Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
[15:8]
x_end
0x00
0
AEC ROI X End Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
roi_aec_
configuration1
0x0000
0
AEC ROI Configuration
y_start
0x0000
0
AEC ROI Y Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
roi_aec_
configuration2
0x0000
0
AEC ROI Configuration
y_end
0x0000
0
AEC ROI Y End Configuration (used for AEC
statistics when roi_aec_enable=‘1’)
roi0_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi0_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
252
253
254
[12:0]
63
Description
0
[15:0]
54
Default
0x0000
[15:0]
53
Default
(Hex)
mult_timer_status
[15:0]
51
Register Name
255
[12:0]
Type
Status
Status
Status
Status
Status
Status
Status
RW
RW
RW
RW
RW
RW
Sequencer ROI [Block Offset: 256]
0
1
256
257
[12:0]
www.onsemi.com
67
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
2
258
3
259
Bit Field
260
5
261
6
262
8
264
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi1_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi1_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi1_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi2_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi2_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi2_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
[12:0]
[12:0]
9
10
265
roi3_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi3_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi3_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
266
[12:0]
11
267
[12:0]
12
13
268
roi4_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi4_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi4_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi5_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi5_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi5_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi6_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi6_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi6_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
269
[12:0]
14
270
[12:0]
15
16
271
272
[12:0]
17
273
18
274
[12:0]
19
275
[12:0]
20
Description
2047
[12:0]
263
Default
0x07FF
[12:0]
7
Default
(Hex)
roi0_configuration2
[12:0]
4
Register Name
276
[12:0]
www.onsemi.com
68
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
21
277
22
Bit Field
24
280
281
26
282
27
283
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi7_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi7_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi8_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi8_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi8_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi9_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi9_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi9_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
[12:0]
[12:0]
28
284
29
285
[12:0]
[12:0]
30
31
286
roi10_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi10_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi10_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
287
[12:0]
32
288
[12:0]
33
34
289
roi11_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi11_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi11_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi12_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi12_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi12_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi13_configuration0
0xA100
41216
ROI Configuration
x_start
0x00
0
X Start Configuration
290
[12:0]
35
291
[12:0]
36
37
292
293
[12:0]
38
294
[12:0]
39
Description
41216
[12:0]
25
Default
0xA100
[12:0]
279
Default
(Hex)
roi7_configuration0
278
23
Register Name
295
[7:0]
www.onsemi.com
69
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A, NOIP1SN2000A
Table 35. REGISTER MAP
Address
Offset
Address
Bit Field
[15:8]
40
43
X End Configuration
roi13_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi13_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi14_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi14_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi14_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi15_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi15_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi15_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
297
298
299
[12:0]
300
45
301
[12:0]
46
302
47
303
Description
161
296
44
Default
0xA1
[12:0]
42
Default
(Hex)
x_end
[12:0]
41
Register Name
[12:0]
[12:0]
Type
RW
RW
RW
RW
RW
RW
RW
RW
Sequencer ROI [Block Offset: 384]
0
384
[15:0]
…
127
…
511
[15:0]
reserved
Reserved
reserved
Reserved
…
…
…
…
reserved
Reserved
reserved
Reserved
www.onsemi.com
70
RW
RW
NOIP1SN5000A, NOIP1SN2000A
PACKAGE INFORMATION
Table 36. PIN LIST
The LVDS I/Os comply to the TIA/EIA−644−A Standard and the CMOS I/Os have a 3.3 V signal level.
This table reflects pin out for ISP8 compatibility.
Pkg Pin #
Signal
Description
1
vdd_33
Supply 3.3 V supply
2
nc
No connect
3
mosi
CMOS Input SPI Master Out Slave In
4
miso
CMOS Output SPI Master In Slave Out
5
sck
CMOS Input SPI Input Clock
6
gnd_18
Supply 1.8 V Ground
7
vdd_18
Supply 1.8 V Supply
8
doutn1
LVDS Output LVDS Data Output Channel #1 (Negative)
9
doutp1
LVDS Output LVDS Data Output Channel #1 (Positive)
10
doutn0
LVDS Output LVDS Data Output Channel #0 (Negative)
11
doutp0
LVDS Output LVDS Data Output Channel #1 (Positive)
12
nc
No connect
13
nc
No connect
14
clock_outn
LVDS Output LVDS Clock Output (Negative)
15
clock_outp
LVDS Output LVDS Clock Output (Positive)
16
doutn2
LVDS Output LVDS Data Output Channel #2 (Negative)
17
doutp2
LVDS Output LVDS Data Output Channel #2 (Positive)
18
doutn3
LVDS Output LVDS Data Output Channel #3 (Negative)
19
doutp3
LVDS Output LVDS Data Output Channel #3 (Positive)
20
gnd_18
Supply 1.8 V Ground
21
vdd_18
Supply 1.8 V Supply
22
nc
No connect
23
vdd_33
Supply 3.3 V Supply
24
gnd_33
Supply 3.3 V Ground
25
doutn4
LVDS Output LVDS Data Output Channel #4 (Negative)
26
doutp4
LVDS Output LVDS Data Output Channel #4 (Positive)
27
doutn5
LVDS Output LVDS Data Output Channel #5 (Negative)
28
doutp5
LVDS Output LVDS Data Output Channel #5 (Positive)
29
syncn
LVDS Output LVDS Sync Channel Output (Negative)
30
syncp
LVDS Output LVDS Sync Channel Output (Positive)
31
nc
No connect
32
nc
No connect
33
doutn7
LVDS Output LVDS Data Output Channel #7 (Negative)
34
doutp7
LVDS Output LVDS Data Output Channel #7 (Positive)
35
doutn6
LVDS Output LVDS Data Output Channel #6 (Negative)
36
doutp6
LVDS Output LVDS Data Output Channel #6 (Positive)
37
vdd_33
Supply 3.3 V Supply
38
gnd_33
Supply 3.3 V Ground
39
gnd_18
Supply 1.8 V Ground
40
vdd_18
Supply 1.8 V Supply
41
lvds_clock_inn
LVDS Input LVDS Clock Input (Positive)
42
lvds_clock_inp
LVDS Input LVDS Clock Input (Positive)
43
nc
No connect
44
clk_pll
CMOS Input Reference Clock Input for PLL
www.onsemi.com
71
NOIP1SN5000A, NOIP1SN2000A
Table 36. PIN LIST
The LVDS I/Os comply to the TIA/EIA−644−A Standard and the CMOS I/Os have a 3.3 V signal level.
This table reflects pin out for ISP8 compatibility.
Pkg Pin #
Signal
Description
45
vdd_18
1.8 V Supply
46
gnd_18
Supply 1.8 V Ground
47
ibias_master
Analog I/O Master Bias Reference
48
nc
No connect
49
vdd_33
Supply 3.3 V Supply
50
gnd_33
Supply 3.3 V Ground
51
nc
No connect
52
nc
No connect
53
nc
No connect
54
nc
No connect
55
nc
No connect
56
nc
No connect
57
vdd_pix
Supply Pixel Array Supply
58
gnd_colpc
Supply Pixel Array Ground
59
nc
No connect
60
vdd_pix
Supply Pixel Array Supply
61
gnd_colpc
Supply Pixel Array Ground
62
gnd_33
Supply 3.3 V Ground
63
vdd_33
Supply 3.3 V Supply
64
nc
No connect
65
gnd_colpc
Supply Pixel Array Ground
66
vdd_pix
Supply Pixel Array Supply
67
gnd_colpc
Supply Pixel Array Ground
68
vdd_pix
Supply Pixel Array Supply
69
nc
No connect
70
trigger0
CMOS Input Trigger Input #0
71
trigger1
CMOS Input Trigger Input #1
72
nc
No connect
73
nc
No connect
74
nc
No connect
75
nc
No connect
76
nc
No connect
77
trigger2
CMOS Input Trigger Input #0
78
monitor0
CMOS Output Monitor Output #0
79
vdd_33
Supply 3.3 V supply
80
gnd_33
Supply 3.3 V Ground
81
monitor1
CMOS Output Monitor Output #1
82
reset_n
CMOS Input Sensor Reset (Active Low)
83
ss_n
CMOS Input SPI Slave Select.
84
gnd_33
Supply 3.3 V Ground
www.onsemi.com
72
NOIP1SN5000A, NOIP1SN2000A
Selectable Pin−Out
Table 37. OPTIONS FOR PIN−OUT IN THE 84 PIN LCC
PACKAGE
The PYTHON sensor has a built−in possibility to route
some of the internal signals to different pads at the side of the
chip.
The pin−out is controlled by glob_config in the
chip_configuration register, located at address 2. The two
possible pin outs in the 84 pin package are listed in Table 37.
By default, the 0x3 setting is selected to ensure compatibility
of the 84−pin package with the ISP8 foot print. More details
on the ISP8 footprint can be found in AND9158.
Pin Name
(84−pin LCC)
Pin Name
(84−pin LCC)
glob_config = 0x3
glob_config = 0x0
Pin No.
(84−pin LCC)
doutn1
clock_outn
8
doutp1
clock_outp
9
clock_outn
doutn1
14
clock_outp
doutp1
15
syncn
doutn6
29
syncp
doutp6
30
doutn6
syncn
35
doutp6
syncp
36
Mechanical Specification
Parameter
Die
(with Pin 1 to the left center)
Glass Lid Specification
Description
Min
Die thickness
Die Size
Typ
Max
Units
725
mm
14.7 x 14.25
mm2
Die center, X offset to the center of package
−50
0
50
Die center, Y offset to the center of the package
−50
0
50
mm
mm
Die position, tilt to the Die Attach Plane
0
deg
Die rotation accuracy (referenced to die scribe and lead
fingers on package on all four sides)
0
deg
Optical center referenced from the die/package center (X−dir)
−231
mm
Optical center referenced from the die/package center (Y−dir)
1697
mm
Distance from bottom of the package to top of the die surface
1.25
mm
Distance from top of the die surface to top of the glass lid
1.16
mm
XY size
19 x 19
Thickness
0.45
Spectral response range
400
Transmission of glass lid (refer to Figure 52)
0.55
mm
0.65
mm
1000
nm
92
%
Glass Lid Material
D263 Teco (no coatings on glass)
Mechanical Shock
JESD22−B104C; Condition G
2000
g
Vibration
JESD22−B103B; Condition 1
2000
Hz
Mounting Profile
Reflow profile according to J−STD−020D.1
260
°C
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NOIP1SN5000A, NOIP1SN2000A
Package Drawing
NOTE: Unless noted otherwise, all dimensions represent nominal values.
Figure 50. Package Drawing for the 84−pin LCC Package
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74
NOIP1SN5000A, NOIP1SN2000A
• Active Area outer dimensions
Optical Center Information
The Center of the Die (CD) is the center of the cavity.
The center of the die is exactly at 50% between the
outsides of the two outer seal rings
The center of the cavity is exactly at 50% between the
insides of the finger pads.
• Die outer dimensions:
♦ B4 is the reference for the Die (0,0) in mm
♦ B1 is at (0, 14250) mm
♦ B2 is at (14700, 14250) mm
♦ B3 is at (14700, 0) mm
A1 is the at (881, 13754) mm
A2 is at (13356, 13754) mm
♦ A3 is at (13356, 3890) mm
♦ A4 is at (881, 3890) mm
Center of the Active Area
♦ AA is at (7119, 8822) mm
Center of the Die
♦ CD is at (7350, 7125) mm
♦
♦
•
•
1.697
0.231
Center of
optical area
Pin 84
Pin 1
Package center
Pin 2
Pixel 0,0
Optical area
Chip
Top View
9.73
9.27
Center of
optical area
R0.15
7.80
0.40
0.15
0.75
0.75
1.80
0.35
0.25
DETAIL C
DETAIL G
SCALE 10:1
SCALE 10:1
11.20
1.80
G
Center of
package
Pin 1
Pin 2
C
Bottom View
NOTE: Unless noted otherwise, all dimensions represent nominal values.
Figure 51. Graphical Representation of the Optical Center
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NOIP1SN5000A, NOIP1SN2000A
Glass Lid
The PYTHON sensor uses a glass lid without any coatings. Figure 52 shows the transmission characteristics of the glass lid.
As shown in Figure 52, no infrared attenuating color filter glass is used. A filter must be provided in the optical path when
color devices are used (source: http://www.pgo−online.com).
Figure 52. Transmission Characteristics of the Glass Lid
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NOIP1SN5000A, NOIP1SN2000A
SPECIFICATIONS AND USEFUL REFERENCES
Product Application Notes
Specifications, Application Notes and useful resources
can be accessed via customer login account at MyON −
CISP Extranet.
https://www.onsemi.com/PowerSolutions/myon/erCispFol
der.do
AND9158: PYTHON ISP8 Solution Ref Board Design
Considerations
AND5001: Sync Codes in the PYTHON Family
Acceptance Criteria Specification
Useful References
The Product Acceptance Criteria ACSPYTHON5000 is
available at MyON- CISP Extranet. This document contains
the criteria to which the PYTHON sensors are tested prior
to being shipped.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
Return Material Authorization (RMA)
Refer to the ON Semiconductor RMA policy procedure at
http://www.onsemi.com/site/pdf/CAT_Returns_FailureAn
alysis.pdf
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77
NOIP1SN5000A, NOIP1SN2000A
ACRONYMS
Acronym
Description
Acronym
Description
ADC
Analog−to−Digital Converter
IP
Intellectual Property
AFE
Analog Front End
LE
Line End
BL
Black pixel data
LS
Line Start
CDM
Charged Device Model
LSB
least significant bit
CDS
Correlated Double Sampling
LVDS
Low−Voltage Differential Signaling
CMOS
Complementary Metal Oxide Semiconductor
MSB
most significant bit
CRC
Cyclic Redundancy Check
PGA
Programmable Gain Amplifier
DAC
Digital−to−Analog Converter
PLS
Parasitic Light Sensitivity
DDR
Double Data Rate
PRBS
Pseudo−Random Binary Sequence
DNL
Differential Non−Llinearity
PRNU
Photo Response Non−Uniformity
DS
Double Sampling
QE
Quantum Efficiency
DSNU
Dark Signal Non−Uniformity
RGB
Red−Green−Blue
EIA
Electronic Industries Alliance
RMA
Return Material Authorization
ESD
Electrostatic Discharge
rms
Root Mean Square
FE
Frame End
ROI
Region of Interest
FF
Fill Factor
ROT
Row Overhead Time
FOT
Frame Overhead Time
S/H
Sample and Hold
FPGA
Field Programmable Gate Array
SNR
Signal−to−Noise Ratio
FPN
Fixed Pattern Noise
SPI
Serial Peripheral Interface
FPS
Frame per Second
TIA
Telecommunications Industry Association
FS
Frame Start
TJ
Junction temperature
HBM
Human Body Model
TR
Training pattern
IMG
Image data (regular pixel data)
% RH
Percent Relative Humidity
INL
Integral Non−Linearity
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NOIP1SN5000A, NOIP1SN2000A
GLOSSARY
conversion gain
A constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. Conversion gain =
q/C where q is the charge of an electron (1.602E 19 Coulomb) and C is the capacitance of the photodiode or sense node.
CDS
Correlated double sampling. This is a method for sampling a pixel where the pixel voltage after reset is sampled and subtracted from the voltage after exposure to light.
CFA
Color filter array. The materials deposited on top of pixels that selectively transmit color.
DNL
Differential non−linearity (for ADCs)
DSNU
Dark signal non−uniformity. This parameter characterizes the degree of non−uniformity in dark leakage currents, which
can be a major source of fixed pattern noise.
fill−factor
A parameter that characterizes the optically active percentage of a pixel. In theory, it is the ratio of the actual QE of a pixel
divided by the QE of a photodiode of equal area. In practice, it is never measured.
INL
Integral nonlinearity (for ADCs)
IR
Infrared. IR light has wavelengths in the approximate range 750 nm to 1 mm.
Lux
Photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m2 = 1/683 W/m2)
pixel noise
Variation of pixel signals within a region of interest (ROI). The ROI typically is a rectangular portion of the pixel array and
may be limited to a single color plane.
photometric units
Units for light measurement that take into account human physiology.
PLS
Parasitic light sensitivity. Parasitic discharge of sampled information in pixels that have storage nodes.
PRNU
Photo−response non−uniformity. This parameter characterizes the spread in response of pixels, which is a source of FPN
under illumination.
QE
Quantum efficiency. This parameter characterizes the effectiveness of a pixel in capturing photons and converting them
into electrons. It is photon wavelength and pixel color dependent.
read noise
Noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output
signal.
reset
The process by which a pixel photodiode or sense node is cleared of electrons. ”Soft” reset occurs when the reset transistor is operated below the threshold. ”Hard” reset occurs when the reset transistor is operated above threshold.
reset noise
Noise due to variation in the reset level of a pixel. In 3T pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). In 4T pixel designs, reset noise can be
removed with CDS.
responsivity
The standard measure of photodiode performance (regardless of whether it is in an imager or not). Units are typically A/W
and are dependent on the incident light wavelength. Note that responsivity and sensitivity are used interchangeably in
image sensor characterization literature so it is best to check the units.
ROI
Region of interest. The area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. The ROI can
be the entire array or a small subsection; it can be confined to a single color plane.
sense node
In 4T pixel designs, a capacitor used to convert charge into voltage. In 3T pixel designs it is the photodiode itself.
sensitivity
A measure of pixel performance that characterizes the rise of the photodiode or sense node signal in Volts upon illumination with light. Units are typically V/(W/m2)/sec and are dependent on the incident light wavelength. Sensitivity measurements are often taken with 550 nm incident light. At this wavelength, 1 683 lux is equal to 1 W/m2; the units of sensitivity
are quoted in V/lux/sec. Note that responsivity and sensitivity are used interchangeably in image sensor characterization
literature so it is best to check the units.
spectral response
The photon wavelength dependence of sensitivity or responsivity.
SNR
Signal−to−noise ratio. This number characterizes the ratio of the fundamental signal to the noise spectrum up to half the
Nyquist frequency.
temporal noise
Noise that varies from frame to frame. In a video stream, temporal noise is visible as twinkling pixels.
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79
NOIP1SN5000A, NOIP1SN2000A
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NOIP1SN5000A/D