PIC18F2220 DATA SHEET (12/12/2007) DOWNLOAD

PIC18F2220/2320/4220/4320
Data Sheet
28/40/44-Pin High-Performance,
Enhanced Flash Microcontrollers
with 10-Bit A/D and nanoWatt Technology
© 2007 Microchip Technology Inc.
DS39599G
Note the following details of the code protection feature on Microchip devices:
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•
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•
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•
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39599G-page ii
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
28/40/44-Pin High-Performance, Enhanced Flash MCUs
with 10-Bit A/D and nanoWatt Technology
Low-Power Features:
Peripheral Highlights:
• Power-Managed modes:
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Power Consumption modes:
- PRI_RUN: 150 μA, 1 MHz, 2V
- PRI_IDLE: 37 μA, 1 MHz, 2V
- SEC_RUN: 14 μA, 32 kHz, 2V
- SEC_IDLE: 5.8 μA, 32 kHz, 2V
- RC_RUN: 110 μA, 1 MHz, 2V
- RC_IDLE: 52 μA, 1 MHz, 2V
- Sleep: 0.1 μA, 1 MHz, 2V
• Timer1 Oscillator: 1.1 μA, 32 kHz, 2V
• Watchdog Timer: 2.1 μA
• Two-Speed Oscillator Start-up
• High-Current Sink/Source 25 mA/25 mA
• Three External Interrupts
• Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution is 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution is 100 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit
• Enhanced Capture/Compare/PWM (ECCP) module:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
• Compatible 10-Bit, Up to 13-Channel
Analog-to-Digital Converter (A/D) module with
Programmable Acquisition Time
• Dual Analog Comparators
• Addressable USART module:
- RS-232 operation using internal oscillator
block (no external crystal required)
Oscillators:
• Four Crystal modes:
- LP, XT, HS: up to 25 MHz
- HSPLL: 4-10 MHz (16-40 MHz internal)
• Two External RC modes, Up to 4 MHz
• Two External Clock modes, Up to 40 MHz
• Internal Oscillator Block:
- 8 user-selectable frequencies: 31 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz
- 125 kHz-8 MHz calibrated to 1%
- Two modes select one or two I/O pins
- OSCTUNE – Allows user to shift frequency
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor
- Allows for safe shutdown if peripheral clock stops
Special Microcontroller Features:
Comparators
• 100,000 Erase/Write Cycle Enhanced Flash Program
Memory Typical
• 1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
• Flash/Data EEPROM Retention: > 40 Years
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
- 2% stability over VDD and Temperature
• Single-Supply 5V In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Wide Operating Voltage Range: 2.0V to 5.5V
Timers
8/16-bit
PIC18F2220
4096
2048
512
256
25
10
2/0
Y
Y
Y
2
2/3
PIC18F2320
8192
4096
512
256
25
10
2/0
Y
Y
Y
2
2/3
PIC18F4220
4096
2048
512
256
36
13
1/1
Y
Y
Y
2
2/3
PIC18F4320
8192
4096
512
256
36
13
1/1
Y
Y
Y
2
2/3
Program Memory
Device
Data Memory
Flash # Single Word SRAM EEPROM
(bytes) Instructions (bytes) (bytes)
© 2007 Microchip Technology Inc.
MSSP
I/O
10-Bit
A/D (ch)
CCP/
ECCP
(PWM)
SPI
Master USART
I2C™
DS39599G-page 1
PIC18F2220/2320/4220/4320
Pin Diagrams
28-Pin SPDIP, SOIC
40-Pin PDIP
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN/C2OUT
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
VDD
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1/P1A
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIC18F2220
PIC18F2320
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC18F4220
PIC18F4320
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN/C2OUT
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1/P1A
RC3/SCK/SCL
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2*
RB2/AN8/INT2
RB1/AN10/INT1
RB0/AN12/INT0
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2*
RB2/AN8/INT2
RB1/AN10/INT1
RB0/AN12/INT0
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 40-pin PIC16C7X devices.
DS39599G-page 2
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2*
NC
Pin Diagrams (Cont.’d)
44
43
42
41
40
39
38
37
36
35
34
44-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PIC18F4220
PIC18F4320
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN/C2OUT
RA4/T0CKI/C1OUT
NC
NC
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2*
* RB3 is the alternate pin for the CCP2 pin multiplexing.
PIC18F4220
PIC18F4320
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VSS
VDD
NC
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN/C2OUT
RA4/T0CKI/C1OUT
RB3/AN9/CCP2*
NC
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
VDD
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2*
RC0/T1OSO/T1CKI
44-Pin QFN
* RB3 is the alternate pin for the CCP2 pin multiplexing.
© 2007 Microchip Technology Inc.
DS39599G-page 3
PIC18F2220/2320/4220/4320
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 19
3.0 Power-Managed Modes ............................................................................................................................................................. 29
4.0 Reset .......................................................................................................................................................................................... 43
5.0 Memory Organization ................................................................................................................................................................. 53
6.0 Flash Program Memory .............................................................................................................................................................. 71
7.0 Data EEPROM Memory ............................................................................................................................................................. 81
8.0 8 X 8 Hardware Multiplier ........................................................................................................................................................... 85
9.0 Interrupts .................................................................................................................................................................................... 87
10.0 I/O Ports ................................................................................................................................................................................... 101
11.0 Timer0 Module ......................................................................................................................................................................... 117
12.0 Timer1 Module ......................................................................................................................................................................... 121
13.0 Timer2 Module ......................................................................................................................................................................... 127
14.0 Timer3 Module ......................................................................................................................................................................... 129
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 133
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 141
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 155
18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 195
19.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 211
20.0 Comparator Module.................................................................................................................................................................. 221
21.0 Comparator Voltage Reference Module ................................................................................................................................... 227
22.0 Low-Voltage Detect .................................................................................................................................................................. 231
23.0 Special Features of the CPU .................................................................................................................................................... 237
24.0 Instruction Set Summary .......................................................................................................................................................... 257
25.0 Development Support............................................................................................................................................................... 301
26.0 Electrical Characteristics .......................................................................................................................................................... 305
27.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 347
28.0 Packaging Information.............................................................................................................................................................. 365
Appendix A: Revision History............................................................................................................................................................. 375
Appendix B: Device Differences......................................................................................................................................................... 376
Appendix C: Conversion Considerations ........................................................................................................................................... 377
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 377
Appendix E: Migration from Mid-range to Enhanced Devices............................................................................................................ 378
Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 378
Index .................................................................................................................................................................................................. 379
The Microchip Web Site ..................................................................................................................................................................... 389
Customer Change Notification Service .............................................................................................................................................. 389
Customer Support .............................................................................................................................................................................. 389
Reader Response .............................................................................................................................................................................. 390
PIC18F2220/2320/4220/4320 Product Identification System ............................................................................................................ 391
DS39599G-page 4
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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We welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2007 Microchip Technology Inc.
DS39599G-page 5
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 6
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F2220
• PIC18F4220
• PIC18F2320
• PIC18F4320
This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance
at an economical price with the addition of highendurance Enhanced Flash program memory. On top
of these features, the PIC18F2220/2320/4220/4320
family introduces design enhancements that make
these microcontrollers a logical choice for many
high-performance, power sensitive applications.
1.1
1.1.1
New Core Features
nanoWatt TECHNOLOGY
All of the devices in the PIC18F2220/2320/4220/4320
family incorporate a range of features that can significantly reduce power consumption during operation.
Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled, but the peripherals are
still active. In these states, power consumption
can be reduced even further, to as little as 4%, of
normal operation requirements.
• On-the-Fly Mode Switching: The power-managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
• Lower Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer have been reduced by up to 80%, with typical
values of 1.8 and 2.2 μA, respectively.
1.1.2
MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F2220/2320/4220/4320
family offer nine different oscillator options, allowing
users a wide range of choices in developing application
hardware. These include:
• Four Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input with the
second pin reassigned as general I/O).
• Two External RC Oscillator modes with the same
pin options as the External Clock modes.
• An internal oscillator block, which provides a
31 kHz INTRC clock and an 8 MHz clock with
6 program selectable divider ratios (4 MHz to
125 kHz) for a total of 8 clock frequencies.
© 2007 Microchip Technology Inc.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference signal provided by the internal oscillator. If a
clock failure occurs, the controller is switched to
the internal oscillator block, allowing for continued
low-speed operation or a safe application
shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
This allows for code execution during what would
otherwise be the clock start-up interval and can
even allow an application to perform routine background activities and return to Sleep without
returning to full power operation.
1.2
Other Special Features
• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
• Self-Programmability: These devices can write
to their own program memory spaces under internal software control. By using a bootloader routine
located in the protected Boot Block at the top of
program memory, it becomes possible to create
an application that can update itself in the field.
• Enhanced CCP Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include Auto-Shutdown for disabling PWM outputs on interrupt or other select
conditions and Auto-Restart to reactivate outputs
once the condition has cleared.
• Addressable USART: This serial communication
module is capable of standard RS-232 operation
using the internal oscillator block, removing the
need for an external crystal (and its accompanying power requirement) in applications that talk to
the outside world.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be initiated without waiting for a sampling period and
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing a time-out range from 4 ms to over
2 minutes, that is stable across operating voltage
and temperature.
DS39599G-page 7
PIC18F2220/2320/4220/4320
1.3
Details on Individual Family
Members
3.
Devices in the PIC18F2220/2320/4220/4320 family are
available in 28-pin (PIC18F2X20) and 40/44-pin
(PIC18F4X20) packages. Block diagrams for the two
groups are shown in Figure 1-1 and Figure 1-2.
4.
The devices are differentiated from each other in five
ways:
5.
1.
All other features for devices in this family are identical.
These are summarized in Table 1-1.
2.
Flash program memory (4 Kbytes for
PIC18FX220 devices, 8 Kbytes for PIC18FX320)
A/D channels (10 for PIC18F2X20 devices, 13 for
PIC18F4X20 devices)
TABLE 1-1:
I/O ports (3 bidirectional ports and 1 input only
port on PIC18F2X20 devices, 5 bidirectional
ports on PIC18F4X20 devices)
CCP and Enhanced CCP implementation
(PIC18F2X20 devices have 2 standard CCP
modules, PIC18F4X20 devices have one
standard CCP module and one ECCP module)
Parallel Slave Port (present only on
PIC18F4X20 devices)
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
DEVICE FEATURES
Features
PIC18F2220
PIC18F2320
PIC18F4220
PIC18F4320
Operating Frequency
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
DC – 40 MHz
Program Memory (Bytes)
4096
8192
4096
8192
Program Memory (Instructions)
2048
4096
2048
4096
Data Memory (Bytes)
512
512
512
512
Data EEPROM Memory (Bytes)
256
256
256
256
Interrupt Sources
19
19
20
20
Ports A, B, C (E)
Ports A, B, C (E)
4
4
I/O Ports
Timers
Ports A, B, C, D, E Ports A, B, C, D, E
4
4
Capture/Compare/PWM Modules
2
2
1
1
Enhanced Capture/
Compare/PWM Modules
0
0
1
1
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
Parallel Communications (PSP)
No
No
Yes
Yes
10-Bit Analog-to-Digital Module
10 Input Channels
10 Input Channels
13 Input Channels
13 Input Channels
Resets (and Delays)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Programmable Low-Voltage
Detect
Yes
Yes
Yes
Yes
Programmable Brown-out Reset
Yes
Yes
Yes
Yes
Instruction Set
75 Instructions
75 Instructions
75 Instructions
75 Instructions
Packages
28-Pin SPDIP
28-Pin SOIC
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
Serial Communications
DS39599G-page 8
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 1-1:
PIC18F2220/2320 BLOCK DIAGRAM
Data Bus<8>
21 Table Pointer <2>
21
8
8
8
PORTA
Data Latch
8
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN/C2OUT
OSC2/CLKO/RA6(2)
OSC1/CLKI/RA7(2)
Data RAM
(512 Bytes)
inc/dec logic
21
Address Latch
20
Address Latch
Program Memory
(4 Kbytes)
PCLATU PCLATH
12
Address<12>
PCU PCH PCL
Program Counter
Data Latch
4
BSR
31 Level Stack
16
Decode
Table Latch
8
12
4
FSR0 Bank0, F
FSR1
FSR2
12
PORTB
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2(1)
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
inc/dec
logic
ROM Latch
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Instruction
Register
8
Instruction
Decode &
Control
PRODH PRODL
3
8 x 8 Multiply
8
OSC1(2)
OSC2(2)
T1OSI
Internal
Oscillator
Block
INT RC
Oscillator
T1OSO
BIT OP
8
Power-up
Timer
Oscillator
Start-up Timer
ALU<8>
8
Watchdog
Timer
MCLR
VDD, VSS
Note
Brown-out
Reset
In-Circuit
Debugger
Fail-Safe
Clock Monitor
8
8
Power-on
Reset
Low-Voltage
Programming
WREG
8
Precision
Voltage
Reference
Timer0
(8 or 16-bit)
Timer1
(16-bit)
Timer2
(8-bit)
Timer3
(16-bit)
10-Bit A/D
Converter
CCP1
CCP2
Master
Synchronous
Serial Port
Addressable
USART
Data EEPROM
(256 Bytes)
1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCPMX2 Configuration bit.
2: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
© 2007 Microchip Technology Inc.
DS39599G-page 9
PIC18F2220/2320/4220/4320
FIGURE 1-2:
PIC18F4220/4320 BLOCK DIAGRAM
Data Bus<8>
PORTA
21 Table Pointer <2>
21
8
8
Data Latch
8
8
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN/C2OUT
OSC2/CLKO/RA6(3)
OSC1/CLKI/RA7(3)
Data RAM
(512 Bytes)
inc/dec logic
21
Address Latch
20
Address Latch
Program Memory
(8 Kbytes)
PCLATU PCLATH
12(2)
Address<12>
PCU PCH PCL
Program Counter
Data Latch
4
BSR
31 Level Stack
16
Decode
Table Latch
8
12
4
FSR0 Bank0, F
FSR1
FSR2
12
PORTB
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2(1)
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
inc/dec
logic
ROM Latch
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Instruction
Register
8
Instruction
Decode &
Control
PRODH PRODL
3
8 x 8 Multiply
8
OSC1(3)
OSC2(3)
T1OSI
Internal
Oscillator
Block
INT RC
Oscillator
T1OSO
BIT OP
8
Power-up
Timer
Oscillator
Start-up Timer
VDD, VSS
Brown-out
Reset
In-Circuit
Debugger
Fail-Safe
Clock Monitor
Timer0
(8 or 16-bit)
Timer1
(16-bit)
Enhanced
CCP
CCP2
Note
8
ALU<8>
Power-on
Reset
Low-Voltage
Programming
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
8
8
Watchdog
Timer
MCLR(2)
WREG
8
PORTD
PORTE
Precision
Voltage
Reference
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
RE3(2)
Timer2
(8-bit)
Master
Synchronous
Serial Port
Timer3
(16-bit)
Addressable
USART
10-Bit A/D
Converter
Data EEPROM
(256 Bytes)
1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCP2MX Configuration bit.
2: RE3 is available only when the MCLR Resets are disabled.
3: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
DS39599G-page 10
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 1-2:
PIC18F2220/2320 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin Buffer
PDIP SOIC Type Type
1
MCLR/VPP
MCLR
1
I
VPP
P
9
OSC1/CLKI/RA7
OSC1
9
I
CLKI
I
RA7
I/O
OSC2/CLKO/RA6
OSC2
ST
10
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low Reset
to the device.
Programming voltage input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
CMOS
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)
TTL
General purpose I/O pin.
ST
10
O
—
CLKO
O
—
RA6
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2
RA1/AN1
RA1
AN1
3
RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF
4
RA3/AN3/VREF+
RA3
AN3
VREF+
5
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6
RA5/AN4/SS/LVDIN/C2OUT
RA5
AN4
SS
LVDIN
C2OUT
7
2
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
O
ST/OD
ST
—
Digital I/O. Open drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
Low-Voltage Detect input.
Comparator 2 output.
3
4
5
6
7
RA6
See the OSC2/CLKO/RA6 pin.
RA7
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
OD = Open-drain (no diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is cleared.
2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
© 2007 Microchip Technology Inc.
DS39599G-page 11
PIC18F2220/2320/4220/4320
TABLE 1-2:
PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin Buffer
PDIP SOIC Type Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0
RB0
AN12
INT0
21
RB1/AN10/INT1
RB1
AN10
INT1
22
RB2/AN8/INT2
RB2
AN8
INT2
23
RB3/AN9/CCP2
RB3
AN9
CCP2(1)
24
RB4/AN11/KBI0
RB4
AN11
KBI0
25
RB5/KBI1/PGM
RB5
KBI1
PGM
26
RB6/KBI2/PGC
RB6
KBI2
PGC
27
RB7/KBI3/PGD
RB7
KBI3
PGD
28
21
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 12.
External interrupt 0.
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 10.
External interrupt 1.
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input, Compare 2 output, PWM2 output.
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-voltage ICSP™ programming enable pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
22
23
24
25
26
27
28
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
OD = Open-drain (no diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is cleared.
2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
DS39599G-page 12
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 1-2:
PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin Buffer
PDIP SOIC Type Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
12
RC2/CCP1/P1A
RC2
CCP1
P1A
13
RC3/SCK/SCL
RC3
SCK
SCL
14
RC4/SDI/SDA
RC4
SDI
SDA
15
RC5/SDO
RC5
SDO
16
RC6/TX/CK
RC6
TX
CK
17
RC7/RX/DT
RC7
RX
DT
18
VSS
VDD
11
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input, Compare 2 output, PWM2 output.
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Enhanced CCP1 output.
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
I/O
ST
—
ST
Digital I/O.
USART asynchronous transmit.
USART synchronous clock (see related RX/DT).
I/O
I
I/O
ST
ST
ST
Digital I/O.
USART asynchronous receive.
USART synchronous data (see related TX/CK).
P
—
Ground reference for logic and I/O pins.
P
—
Positive supply for logic and I/O pins.
12
13
14
15
16
17
18
8, 19 8, 19
20
I/O
O
I
20
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
OD = Open-drain (no diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is cleared.
2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
© 2007 Microchip Technology Inc.
DS39599G-page 13
PIC18F2220/2320/4220/4320
TABLE 1-3:
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS
Pin Name
MCLR/VPP/RE3
MCLR
Pin Number
Pin Buffer
Type
Type
PDIP TQFP QFN
1
18
18
VPP
RE3
OSC1/CLKI/RA7
OSC1
13
30
ST
P
I
ST
32
I
CLKI
I
RA7
OSC2/CLKO/RA6
OSC2
I
I/O
14
31
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
CMOS
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
TTL
ST
33
O
—
CLKO
O
—
RA6
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2
RA1/AN1
RA1
AN1
3
RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF
4
RA3/AN3/VREF+
RA3
AN3
VREF+
5
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6
RA5/AN4/SS/LVDIN/
C2OUT
RA5
AN4
SS
LVDIN
C2OUT
7
19
20
21
22
23
24
19
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
O
ST/OD
ST
—
Digital I/O. Open drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
Low-Voltage Detect input.
Comparator 2 output.
20
21
22
23
24
RA6
See the OSC2/CLKO/RA6 pin.
RA7
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
OD = Open-drain (no diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is cleared.
2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
DS39599G-page 14
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type
Type
PDIP TQFP QFN
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0
RB0
AN12
INT0
33
RB1/AN10/INT1
RB1
AN10
INT1
34
RB2/AN8/INT2
RB2
AN8
INT2
35
RB3/AN9/CCP2
RB3
AN9
CCP2(1)
36
RB4/AN11/KBI0
RB4
AN11
KBI0
37
RB5/KBI1/PGM
RB5
KBI1
PGM
38
RB6/KBI2/PGC
RB6
KBI2
PGC
39
RB7/KBI3/PGD
RB7
KBI3
PGD
40
8
9
10
11
14
15
16
17
9
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 12.
External interrupt 0.
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 10.
External interrupt 1.
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input, Compare 2 output, PWM2 output.
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-voltage ICSP™ programming enable pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
10
11
12
14
15
16
17
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
OD = Open-drain (no diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is cleared.
2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
© 2007 Microchip Technology Inc.
DS39599G-page 15
PIC18F2220/2320/4220/4320
TABLE 1-3:
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP TQFP QFN
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
16
RC2/CCP1/P1A
RC2
CCP1
P1A
17
RC3/SCK/SCL
RC3
SCK
SCL
18
RC4/SDI/SDA
RC4
SDI
SDA
23
RC5/SDO
RC5
SDO
24
RC6/TX/CK
RC6
TX
CK
25
RC7/RX/DT
RC7
RX
DT
26
32
35
36
37
42
43
44
1
34
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input, Compare 2 output, PWM2 output.
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Enhanced CCP1 output.
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
I/O
O
ST
—
Digital I/O.
SPI data out.
I/O
O
I/O
ST
—
ST
Digital I/O.
USART asynchronous transmit.
USART synchronous clock (see related RX/DT).
I/O
I
I/O
ST
ST
ST
Digital I/O.
USART asynchronous receive.
USART synchronous data (see related TX/CK).
35
36
37
42
43
44
1
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
OD = Open-drain (no diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is cleared.
2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
DS39599G-page 16
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type
Type
PDIP TQFP QFN
Description
PORTD is a bidirectional I/O port or a Parallel Slave Port
(PSP) for interfacing to a microprocessor port. These pins
have TTL input buffers when PSP module is enabled.
RD0/PSP0
RD0
PSP0
19
RD1/PSP1
RD1
PSP1
20
RD2/PSP2
RD2
PSP2
21
RD3/PSP3
RD3
PSP3
22
RD4/PSP4
RD4
PSP4
27
RD5/PSP5/P1B
RD5
PSP5
P1B
28
RD6/PSP6/P1C
RD6
PSP6
P1C
29
RD7/PSP7/P1D
RD7
PSP7
P1D
30
38
39
40
41
2
3
4
5
38
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
39
40
41
2
3
4
5
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
OD = Open-drain (no diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is cleared.
2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
© 2007 Microchip Technology Inc.
DS39599G-page 17
PIC18F2220/2320/4220/4320
TABLE 1-3:
Pin Name
PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type
Type
PDIP TQFP QFN
Description
PORTE is a bidirectional I/O port.
RE0/AN5/RD
RE0
AN5
RD
8
RE1/AN6/WR
RE1
AN6
WR
9
RE2/AN7/CS
RE2
AN7
CS
10
RE3
1
VSS
12,
31
VDD
NC
25
26
27
18
I/O
I
I
ST
Analog
TTL
Digital I/O.
Analog input 5.
Read control for Parallel Slave Port
(see also WR and CS pins).
I/O
I
I
ST
Analog
TTL
Digital I/O.
Analog input 6.
Write control for Parallel Slave Port
(see CS and RD pins).
I/O
I
I
ST
Analog
TTL
Digital I/O.
Analog input 7.
Chip select control for Parallel Slave Port
(see related RD and WR).
—
—
See MCLR/VPP/RE3 pin.
P
—
Ground reference for logic and I/O pins.
7, 8
29
P
—
Positive supply for logic and I/O pins.
13,
28
NC
NC
No connect.
26
27
18
6, 29 6, 30,
31
11, 32 7, 28
—
25
—
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
OD = Open-drain (no diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is cleared.
2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set.
DS39599G-page 18
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
2.0
OSCILLATOR
CONFIGURATIONS
2.1
Oscillator Types
FIGURE 2-1:
C1(1)
The PIC18F2X20 and PIC18F4X20 devices can be
operated in ten different oscillator modes. The user can
program the Configuration bits, FOSC3:FOSC0, in
Configuration Register 1H to select one of these ten
modes:
1.
2.
3.
4.
LP
XT
HS
HSPLL
5.
RC
6.
RCIO
7.
INTIO1
8.
INTIO2
9. EC
10. ECIO
2.2
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
High-Speed Crystal/Resonator
with PLL Enabled
External Resistor/Capacitor with
FOSC/4 Output on RA6
External Resistor/Capacitor with
I/O on RA6
Internal Oscillator with FOSC/4
Output on RA6 and I/O on RA7
Internal Oscillator with I/O on RA6
and RA7
External Clock with FOSC/4 Output
External Clock with I/O on RA6
Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
Note:
Use of a series cut crystal may give a frequency out of the crystal manufacturers
specifications.
CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
OSC1
XTAL
To
Internal
Logic
RF(3)
Sleep
RS(2)
C2(1)
Note 1:
2:
3:
PIC18FXXXX
OSC2
See Table 2-1 and Table 2-2 for initial values
of C1 and C2.
A series resistor (RS) may be required for AT
strip cut crystals.
RF varies with the oscillator mode chosen.
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes on page 20 for additional information.
Resonators Used:
455 kHz
4.0 MHz
2.0 MHz
8.0 MHz
16.0 MHz
© 2007 Microchip Technology Inc.
DS39599G-page 19
PIC18F2220/2320/4220/4320
Osc Type
LP
XT
HS
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Crystal
Freq
Typical Capacitor Values
Tested:
C1
C2
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
1 MHz
33 pF
33 pF
4 MHz
27 pF
27 pF
4 MHz
27 pF
27 pF
8 MHz
22 pF
22 pF
20 MHz
15 pF
15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Crystals Used:
32 kHz
4 MHz
200 kHz
8 MHz
1 MHz
20 MHz
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
4: RS may be required to avoid overdriving
crystals with low drive level specification.
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
DS39599G-page 20
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.
FIGURE 2-2:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
OSC1
Clock from
Ext. System
PIC18FXXXX
OSC2
Open
2.3
(HS Mode)
HSPLL
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
crystal oscillator circuit, or to clock the device up to its
highest rated frequency from a crystal oscillator. This
may be useful for customers who are concerned with
EMI due to high-frequency crystals.
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.
The PLL is enabled only when the oscillator Configuration bits are programmed for HSPLL mode. If
programmed for any other mode, the PLL is not
enabled.
FIGURE 2-3:
PLL BLOCK DIAGRAM
HS Osc Enable
PLL Enable
(from Configuration Register 1H)
OSC2
HS Mode
OSC1 Crystal
Osc
FIN
Phase
Comparator
FOUT
Loop
Filter
÷4
VCO
MUX
TABLE 2-2:
SYSCLK
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
2.4
External Clock Input
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
OSC1/CLKI
Clock from
Ext. System
PIC18FXXXX
FOSC/4
OSC2/CLKO
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
2.5
RC Oscillator
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due to
normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package
types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take
into account variation due to tolerance of external R
and C components used. Figure 2-6 shows how the
R/C combination is connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
FIGURE 2-6:
RC OSCILLATOR MODE
VDD
REXT
OSC1
Internal
Clock
CEXT
FIGURE 2-5:
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
PIC18FXXXX
VSS
FOSC/4
OSC2/CLKO
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
OSC1/CLKI
Clock from
Ext. System
PIC18FXXXX
RA6
I/O (OSC2)
The RCIO Oscillator mode (Figure 2-7) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 2-7:
RCIO OSCILLATOR MODE
VDD
REXT
OSC1
Internal
Clock
CEXT
PIC18FXXXX
VSS
RA6
I/O (OSC2)
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
© 2007 Microchip Technology Inc.
DS39599G-page 21
PIC18F2220/2320/4220/4320
2.6
Internal Oscillator Block
The PIC18F2X20/4X20 devices include an internal
oscillator block that generates two independent clock
signals. Either can be used as the system’s clock
source. This can eliminate the need for external
oscillator circuits on the OSC1 or OSC2 pins.
The main output (INTOSC) is an 8-MHz clock source
that can be used to directly drive the system clock. It
also drives a post-scaler that can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when the system clock
frequency is set from 125 kHz to 8 MHz.
2.6.1
INTIO MODES
Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pins.
This frees the pins to be used for digital I/O.
Two configurations are available:
• INTIO1 mode – The OSC2 pin outputs FOSC/4
while OSC1 functions as RA7 for digital input and
output.
• INTIO2 mode – OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
The other clock source is the internal RC oscillator
(INTRC) that provides a 31-kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source or by enabling any of
the following:
•
•
•
•
Power-up Timer
Fail-Safe Clock Monitor
Watchdog Timer
Two-Speed Start-up
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC post-scaler) is selected by configuring the IRCF bits of the OSCCON register
(Register 2-2).
DS39599G-page 22
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
2.6.2
OSCTUNE REGISTER
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of approximately 8 MHz. (See parameters F14–F19 in
Table 26-8.)
The INTOSC frequency can be adjusted using the
TUN5:TUN1 bits in the OSCTUNE register
OSCTUNE<5:1>. OSCTUNE<0> has no effect, but is
readable and writable, enabling changes of the
INTOSC frequency using two increment or decrement
instructions.
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies begin shifting to the new frequency. The INTOSC and INTRC clocks will stabilize at
the new frequency within 100 μs. Code execution
continues during this shift.
There is no indication when the shift occurs. Operation
of features that depend on the INTRC clock source
frequency also will be affected by the change in
frequency. This includes the WDT, Fail-Safe Clock
Monitor and peripherals.
The internal oscillator’s output can be adjusted in the
user’s application. This is done by writing to the
OSCTUNE register (Register 2-1). The tuning
sensitivity is constant throughout the tuning range.
REGISTER 2-1:
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-1
TUN<5:1>: Frequency Tuning bits – Adjusts the frequency of INTOSC. Can adjust INTRC, depending
on TUNSEL (OSCTUN2<7>)
011111 = Maximum frequency
•
•
•
•
000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111
•
•
•
•
100000 = Minimum frequency
bit 0
TUN<0>: A placeholder with no effect on the INTRC frequency. Provided to facilitate incrementation
and decrementation of the OSCTUN2 register and adjustment of the INTRC frequency.
© 2007 Microchip Technology Inc.
DS39599G-page 23
PIC18F2220/2320/4220/4320
2.6.3
OSCTUN2 REGISTER
The internal oscillator block is calibrated at the factory
to produce an INTRC output frequency of approximately 31 kHz. (See parameters F20 and F21 in
Table 26-8.)
The INTRC frequency can be adjusted two ways:
• If TUNSEL (OSCTUN2<7>) is clear –
TUN5:TUN1 in OSCTUNE<5:1> adjusts the
INTRC clock frequency and also can adjust the
INTOSC clock frequency. (See Register 2-1,
OSCTUNE.)
• If TUNSEL (OSCTUN2<7>) is set – TUN5:TUN1
in OSCTUN2<5:1> adjusts the INTRC clock frequency without affecting the INTOSC frequency.
(See Register 2-2, OSCTUN2.)
REGISTER 2-2:
In OSCTUN2, the OSCTUN2<0> bit has no effect, but
is readable and writable, enabling changes of the
INTRC frequency using two increment or decrement
instructions.
When the OSCTUN2 register is modified, the INTRC
frequency will begin shifting to the new frequency, and
will stabilize at the new frequency within 100 μs. Code
execution continues during this shift.
There is no indication when the shift occurs. Operation
of features that depend on the INTRC clock source frequency also will be affected by the change in frequency. This includes the WDT, Fail-Safe Clock
Monitor and peripherals.
OSCTUN2: INTRC OSCILLATOR TUNING REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUNSEL
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TUNSEL: Enables tuning of INTRC using OCSTUN2<5:1>
1 = INTRC adjusted by OSCTUN2<5:1>
0 = INTRC adjusted by OSCTUNE<5:1>
bit 6
Unimplemented: Read as ‘0’
bit 5-1
TUN<5:1>: Frequency Tuning bits – Adjusts the frequency of INTRC when TUNSEL is set
011111 = Maximum frequency
•
•
•
•
000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111
•
•
•
•
100000 = Minimum frequency
bit 0
TUN<0>: A placeholder with no effect on the INTRC frequency. Provided to facilitate incrementation
and decrementation of the OSCTUN2 register and adjustment of the INTRC frequency.
DS39599G-page 24
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
2.7
Clock Sources and Oscillator
Switching
Like previous PIC18 devices, the PIC18F2X20 and
PIC18F4X20 devices include a feature that allows the
system clock source to be switched from the main
oscillator to an alternate, low-frequency clock source.
PIC18F2X20/4X20 devices offer two alternate clock
sources. When enabled, these give additional options
for switching to the various power-managed operating
modes.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined on POR by the contents
of Configuration Register 1H. The details of these
modes are covered earlier in this chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F2X20/4X20 devices offer only the Timer1
oscillator as a secondary oscillator. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock (RTC).
Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T1CKI and RC1/T1OSI pins.
Like the LP Oscillator mode circuit, loading capacitors
are also connected from each pin to ground.
The Timer1 oscillator is discussed in greater detail in
Section 12.2 “Timer1 Oscillator”.
In addition to being a primary clock source, the internal
oscillator block is available as a power-managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
The clock sources for the PIC18F2X20/4X20 devices
are shown in Figure 2-8. See Section 12.0 “Timer1
Module” for further details of the Timer1 oscillator. See
Section 23.1 “Configuration Bits” for Configuration
register details.
© 2007 Microchip Technology Inc.
2.7.1
OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-3) controls several aspects of the system clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating
in power-managed modes. The available clock sources
are the primary clock (defined in Configuration
Register 1H), the secondary clock (Timer1 oscillator)
and the internal oscillator block. The clock selection
has no effect until a SLEEP instruction is executed and
the device enters a power-managed mode of
operation. The SCS bits are cleared on all forms of
Reset.
The Internal Oscillator Select bits, IRCF2:IRCF0, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source, the INTOSC source (8 MHz) or one of
the six frequencies derived from the INTOSC
postscaler (125 kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of these bits will have an immediate change on
the internal oscillator’s output.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the system clock. The
OSTS indicates that the Oscillator Start-up Timer
(OST) has timed out and the primary clock is providing
the system clock in primary clock modes. The IOFS bit
indicates when the internal oscillator block has stabilized and is providing the system clock in RC Clock
modes. The T1RUN bit (T1CON<6>) indicates when
the Timer1 oscillator is providing the system clock in
secondary clock modes. If none of these bits are set,
the INTRC is providing the system clock, or the internal
oscillator block has just started and is not yet stable.
The IDLEN bit controls the selective shutdown of the
controller’s CPU in power-managed modes. The use of
these bits is discussed in more detail in Section 3.0
“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to set the
SCS0 bit will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
DS39599G-page 25
PIC18F2220/2320/4220/4320
FIGURE 2-8:
PIC18F2X20/4X20 CLOCK DIAGRAM
PIC18F2X20/4X20
Primary Oscillator
OSCCON<1:0>
HSPLL
4 x PLL
Sleep
Clock
Control
CONFIG1H <3:0>
OSC2
Secondary Oscillator
T1OSC
T1OSO
OSCCON<6:4>
8 MHz
OSCCON<6:4>
4 MHz
Internal
Oscillator
Block
8 MHz
(INTOSC)
Postscaler
INTRC
Source
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
31 kHz
DS39599G-page 26
Peripherals
Internal Oscillator
CPU
111
110
IDLEN
101
100
011
MUX
T1OSI
Clock Source Option
for Other Modules
T1OSCEN
Enable
Oscillator
MUX
LP, XT, HS, RC, EC
OSC1
010
001
000
WDT, FSCM
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 2-3:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R(1)
R-0
R/W-0
R/W-0
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1 = Idle mode enabled; CPU core is not clocked in power-managed modes
0 = Run mode enabled; CPU core is clocked in power-managed modes
bit 6-4
IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (8 MHz source drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (INTRC source drives clock directly)
bit 3
OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2
IOFS: INTOSC Frequency Stable bit
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable
bit 1-0
SCS1:SCS0: System Clock Select bits
1x = Internal oscillator block (RC modes)
01 = Timer1 oscillator (Secondary modes)(2)
00 = Primary oscillator (Sleep and PRI_IDLE modes)
Note 1:
2:
Depends on state of IESO bit in Configuration Register 1H.
SCS0 may not be set while T1OSCEN (T1CON<3>) is clear.
© 2007 Microchip Technology Inc.
DS39599G-page 27
PIC18F2220/2320/4220/4320
2.7.2
OSCILLATOR TRANSITIONS
The PIC18F2X20/4X20 devices contain circuitry to prevent clocking “glitches” when switching between clock
sources. A short pause in the system clock occurs during the clock switch. The length of this pause is
between 8 and 9 clock periods of the new clock source.
This ensures that the new clock source is stable and
that its pulse width will not be less than the shortest
pulse width of the two clock sources.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
2.8
Effects of Power-Managed Modes
on the Various Clock Sources
When the device executes a SLEEP instruction, the
system is switched to one of the power-managed
modes, depending on the state of the IDLEN and
SCS1:SCS0 bits of the OSCCON register. See
Section 3.0 “Power-Managed Modes” for details.
When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and providing the system clock. The Timer1 oscillator may also
run in all power-managed modes if required to clock
Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock and may be enabled to
support various special features, regardless of the
power-managed mode (see Section 23.2 “Watchdog
Timer (WDT)” through Section 23.4 “Fail-Safe Clock
Monitor”). The INTOSC output at 8 MHz may be used
directly to clock the system or may be divided down
first. The INTOSC output is disabled if the system clock
is provided directly from the INTRC output.
TABLE 2-3:
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a RealTime Clock. Other features may be operating that do
not require a system clock source (i.e., MSSP slave,
PSP, INTx pins, A/D conversions and others).
2.9
Power-up Delays
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most applications. The delays ensure that the device is kept in
Reset until the device power supply is stable under normal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.1 “Power-on Reset (POR)”
through Section 4.5 “Brown-out Reset (BOR)”.
The first timer is the Power-up Timer (PWRT) which
provides a fixed delay on power-up (parameter 33,
Table 26-10), if enabled, in Configuration Register 2L.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST
does this by counting 1024 oscillator cycles before
allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of 5 to 10 μs, following POR, while the
controller becomes ready to execute instructions. This
delay runs concurrently with any other delays. This
may be the only delay that occurs when any of the EC,
RC or INTIO modes are used as the primary clock
source.
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode
OSC1 Pin
OSC2 Pin
RC, INTIO1
Floating, external resistor
should pull high
At logic low (clock/4 output)
RCIO, INTIO2
Floating, external resistor
should pull high
Configured as PORTA, bit 6
ECIO
Floating, pulled by external clock
Configured as PORTA, bit 6
EC
Floating, pulled by external clock
At logic low (clock/4 output)
LP, XT, and HS
Feedback inverter disabled at
quiescent voltage level
Feedback inverter disabled at
quiescent voltage level
Note:
See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
DS39599G-page 28
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
3.0
POWER-MANAGED MODES
For PIC18F2X20/4X20 devices, the power-managed
modes are invoked by using the existing SLEEP
instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a Reset, or a WDT time-out
(PRI_RUN mode is the normal full-power execution
mode; the CPU and peripherals are clocked by the primary oscillator source). In addition, power-managed
Run modes may also exit to Sleep mode or their
corresponding Idle mode.
The PIC18F2X20 and PIC18F4X20 devices offer a total
of six operating modes for more efficient power
management (see Table 3-1). These operating modes
provide a variety of options for selective power
conservation in applications where resources may be
limited (i.e., battery-powered devices).
There are three categories of power-managed modes:
• Sleep mode
• Idle modes
• Run modes
3.1
Selecting a power-managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit controls CPU clocking while the
SC1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
3.1.1
The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator) and the Sleep mode offered by all
PIC® devices (where all system clocks are stopped) are
both offered in the PIC18F2X20/4X20 devices
(SEC_RUN and Sleep modes, respectively). However,
additional power-managed modes are available that
allow the user greater flexibility in determining what
portions of the device are operating. The powermanaged modes are event driven; that is, some
specific event must occur for the device to enter or
(more particularly) exit these operating modes.
TABLE 3-1:
CLOCK SOURCES
The clock source is selected by setting the SCS bits of
the OSCCON register. Three clock sources are available for use in power-managed Idle modes: the primary
clock (as configured in Configuration Register 1H), the
secondary clock (Timer1 oscillator) and the internal
oscillator block. The secondary and internal oscillator
block sources are available for the power-managed
modes (PRI_RUN mode is the normal full-power
execution mode; the CPU and peripherals are clocked
by the primary oscillator source).
POWER-MANAGED MODES
OSCCON<7,1:0>
Mode
Selecting Power-Managed Modes
Module Clocking
Available Clock and Oscillator Source
IDLEN
SCS1:SCS0
CPU
Peripherals
Sleep
0
00
Off
Off
PRI_RUN
0
00
Clocked
Clocked
Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(1).
This is the normal full-power execution mode.
SEC_RUN
0
01
Clocked
Clocked
Secondary – Timer1 Oscillator
RC_RUN
0
1x
Clocked
Clocked
Internal Oscillator Block(1)
PRI_IDLE
1
00
Off
Clocked
Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE
1
01
Off
Clocked
Secondary – Timer1 Oscillator
RC_IDLE
1
1x
Off
Clocked
Internal Oscillator Block(1)
Note 1:
None – All clocks are disabled
Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
© 2007 Microchip Technology Inc.
DS39599G-page 29
PIC18F2220/2320/4220/4320
3.1.2
ENTERING POWER-MANAGED
MODES
In general, entry, exit and switching between powermanaged clock sources requires clock source
switching. In each case, the sequence of events is the
same.
Any change in the power-managed mode begins with
loading the OSCCON register and executing a SLEEP
instruction. The SCS1:SCS0 bits select one of three
power-managed clock sources; the primary clock (as
defined in Configuration Register 1H), the secondary
clock (the Timer1 oscillator) and the internal oscillator
block (used in RC modes). Modifying the SCS bits will
have no effect until a SLEEP instruction is executed.
Entry to the power-managed mode is triggered by the
execution of a SLEEP instruction.
Figure 3-5 shows how the system is clocked while
switching from the primary clock to the Timer1 oscillator. When the SLEEP instruction is executed, clocks to
the device are stopped at the beginning of the next
instruction cycle. Eight clock cycles from the new clock
source are counted to synchronize with the new clock
source. After eight clock pulses from the new clock
source are counted, clocks from the new clock source
resume clocking the system. The actual length of the
pause is between eight and nine clock periods from the
new clock source. This ensures that the new clock
source is stable and that its pulse width will not be less
than the shortest pulse width of the two clock sources.
Three bits indicate the current clock source: OSTS and
IOFS in the OSCCON register and T1RUN in the
T1CON register. Only one of these bits will be set while
in a power-managed mode other than PRI_RUN. When
the OSTS bit is set, the primary clock is providing the
system clock. When the IOFS bit is set, the INTOSC
output is providing a stable 8 MHz clock source and is
providing the system clock. When the T1RUN bit is set,
the Timer1 oscillator is providing the system clock. If
none of these bits are set, then either the INTRC clock
source is clocking the system or the INTOSC source is
not yet stable.
If the internal oscillator block is configured as the primary clock source in Configuration Register 1H, then
both the OSTS and IOFS bits may be set when in
PRI_RUN or PRI_IDLE modes. This indicates that the
primary clock (INTOSC output) is generating a stable
8 MHz output. Entering a power-managed RC mode
(same frequency) would clear the OSTS bit.
DS39599G-page 30
Note 1: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode; executing a SLEEP instruction is
simply a trigger to place the controller into
a power-managed mode selected by the
OSCCON register, one of which is Sleep
mode.
3.1.3
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the settings of the
IDLEN and SCS bits at the time the instruction is executed. If another SLEEP instruction is executed, the
device will enter the power-managed mode specified
by these same bits at that time. If the bits have
changed, the device will enter the new power-managed
mode specified by the new bit settings.
3.1.4
COMPARISONS BETWEEN RUN
AND IDLE MODES
Clock source selection for the Run modes is identical to
the corresponding Idle modes. When a SLEEP instruction is executed, the SCS bits in the OSCCON register
are used to switch to a different clock source. As a
result, if there is a change of clock source at the time a
SLEEP instruction is executed, a clock switch will occur.
In Idle modes, the CPU is not clocked and is not running. In Run modes, the CPU is clocked and executing
code. This difference modifies the operation of the
WDT when it times out. In Idle modes, a WDT time-out
results in a wake from power-managed modes. In Run
modes, a WDT time-out results in a WDT Reset (see
Table 3-2).
During a wake-up from an Idle mode, the CPU starts
executing code by entering the corresponding Run
mode until the primary clock becomes ready. When the
primary clock becomes ready, the clock source is automatically switched to the primary clock. The IDLEN and
SCS bits are unchanged during and after the wake-up.
Figure 3-2 shows how the system is clocked during the
clock source switch. The example assumes the device
was in SEC_IDLE or SEC_RUN mode when a wake is
triggered (the primary clock was configured in HSPLL
mode).
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 3-2:
Power -Managed
Mode
COMPARISON BETWEEN POWER-MANAGED MODES
CPU is Clocked by ...
WDT
Time-out
Causes a ...
Peripherals are
Clocked by ...
Clock During Wake-up
(while primary becomes
ready)
Sleep
Not clocked (not running) Wake-up
Not clocked
Any Idle mode
Not clocked (not running) Wake-up
Primary, Secondary or Unchanged from Idle mode
INTOSC multiplexer
(CPU operates as in
corresponding Run mode).
Any Run mode
Secondary or INTOSC
multiplexer
Secondary or
INTOSC multiplexer
3.2
Reset
Sleep Mode
The power-managed Sleep mode in the PIC18F2X20/
4X20 devices is identical to that offered in all other PIC
microcontrollers. It is entered by clearing the IDLEN
and SCS1:SCS0 bits (this is the Reset state) and
executing the SLEEP instruction. This shuts down the
primary oscillator and the OSTS bit is cleared (see
Figure 3-1).
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the system will not be clocked
until the primary clock source becomes ready (see
Figure 3-2), or it will be clocked from the internal
oscillator block if either the Two-Speed Start-up or the
Fail-Safe Clock Monitor are enabled (see Section 23.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock is providing the
system clocks. The IDLEN and SCS bits are not
affected by the wake-up.
3.3
Idle Modes
The IDLEN bit allows the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Clearing IDLEN allows the CPU to be clocked.
Setting IDLEN disables clocks to the CPU, effectively
stopping program execution (see Register 2-3). The
peripherals continue to be clocked regardless of the
setting of the IDLEN bit.
None or INTOSC multiplexer if
Two-Speed Start-up or
Fail-Safe Clock Monitor is
enabled.
Unchanged from Run mode.
There is one exception to how the IDLEN bit functions.
When all the low-power OSCCON bits are cleared
(IDLEN:SCS1:SCS0 = 000), the device enters Sleep
mode upon the execution of the SLEEP instruction. This
is both the Reset state of the OSCCON register and the
setting that selects Sleep mode. This maintains
compatibility with other PIC devices that do not offer
power-managed modes.
If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a
‘1’ when a SLEEP instruction is executed, the
peripherals will be clocked from the clock source
selected using the SCS1:SCS0 bits; however, the CPU
will not be clocked. Since the CPU is not executing
instructions, the only exits from any of the Idle modes
are by interrupt, WDT time-out or a Reset.
When a wake-up event occurs, CPU execution is
delayed approximately 10 μs while it becomes ready to
execute code. When the CPU begins executing code,
it is clocked by the same clock source as was selected
in the power-managed mode (i.e., when waking from
RC_IDLE mode, the internal oscillator block will clock
the CPU and peripherals until the primary clock source
becomes ready – this is essentially RC_RUN mode).
This continues until the primary clock source becomes
ready. When the primary clock becomes ready, the
OSTS bit is set and the system clock source is
switched to the primary clock (see Figure 3-4). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT time-out will
result in a WDT wake-up to full-power operation.
© 2007 Microchip Technology Inc.
DS39599G-page 31
PIC18F2220/2320/4220/4320
FIGURE 3-1:
TIMING TRANSITION FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
FIGURE 3-2:
PC + 2
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(1)
PLL Clock
Output
TPLL(1)
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake-up Event
PC + 2
PC + 4
PC + 6
PC + 8
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39599G-page 32
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
3.3.1
PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes in that it does not disable the primary system
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation, with its
more accurate primary clock source, since the clock
source does not have to “warm up” or transition from
another oscillator.
When a wake-up event occurs, the CPU is clocked
from the primary clock source. A delay of approximately 10 μs is required between the wake-up event
and when code execution starts. This is required to
allow the CPU to become ready to execute instructions.
After the wake-up, the OSTS bit remains set. The
IDLEN and SCS bits are not affected by the wake-up
(see Figure 3-4).
PRI_IDLE mode is entered by setting the IDLEN bit,
clearing the SCS bits and executing a SLEEP instruction. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified in Configuration Register 1H. The OSTS bit
remains set in PRI_IDLE mode (see Figure 3-3).
FIGURE 3-3:
TRANSITION TIMING TO PRI_IDLE MODE
Q1
Q3
Q2
Q4
Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
FIGURE 3-4:
PC
PC + 2
TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
Q1
Q3
Q2
Q4
OSC1
CPU Start-up Delay
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
Wake-up Event
© 2007 Microchip Technology Inc.
DS39599G-page 33
PIC18F2220/2320/4220/4320
3.3.2
SEC_IDLE MODE
When a wake-up event occurs, the peripherals continue
to be clocked from the Timer1 oscillator. After a 10 μs
delay following the wake-up event, the CPU begins executing code, being clocked by the Timer1 oscillator. The
microcontroller operates in SEC_RUN mode until the
primary clock becomes ready. When the primary clock
becomes ready, a clock switch back to the primary clock
occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run.
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered by setting the IDLEN
bit, modifying to SCS1:SCS0 = 01 and executing a
SLEEP instruction. When the clock source is switched
to the Timer1 oscillator (see Figure 3-5), the primary
oscillator is shut down, the OSTS bit is cleared and the
T1RUN bit is set.
Note:
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when trying to set the SCS0 bit (OSCCON<0>),
the write to SCS0 will not occur. If the
Timer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the oscillator has started; in such situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
FIGURE 3-5:
TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
Q1 Q2 Q3 Q4 Q1
1
T1OSI
2
3
OSC1
4
5
6
Clock Transition
7
8
CPU
Clock
Peripheral
Clock
Program
Counter
PC
FIGURE 3-6:
PC + 2
TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
T1OSI
OSC1
TOST(1)
TPLL(1)
PLL Clock
Output
1
2
3 4 5 6
Clock Transition
7
8
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake-up from Interrupt Event
PC + 2
PC + 4
PC + 6
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39599G-page 34
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
3.3.3
RC_IDLE MODE
was executed and the INTOSC source was already
stable, the IOFS bit will remain set. If the IRCF bits are
all clear, the INTOSC output is not enabled and the
IOFS bit will remain clear; there will be no indication of
the current clock source.
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
When a wake-up event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After
a 10 μs delay following the wake-up event, the CPU
begins executing code, being clocked by the INTOSC
multiplexer. The microcontroller operates in RC_RUN
mode until the primary clock becomes ready. When the
primary clock becomes ready, a clock switch back to
the primary clock occurs (see Figure 3-8). When the
clock switch is complete, the IOFS bit is cleared, the
OSTS bit is set and the primary clock is providing the
system clock. The IDLEN and SCS bits are not affected
by the wake-up. The INTRC source will continue to run
if either the WDT or the Fail-Safe Clock Monitor is
enabled.
This mode is entered by setting the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer
(see Figure 3-7), the primary oscillator is shut down
and the OSTS bit is cleared.
If the IRCF bits are set to a non-zero value (thus
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable, in about
1 ms. Clocks to the peripherals continue while the
INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value before the SLEEP instruction
FIGURE 3-7:
TIMING TRANSITION TO RC_IDLE MODE
Q1 Q2 Q3 Q4 Q1
1
INTRC
2
3
4
5
6
7
8
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
FIGURE 3-8:
PC + 2
TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
Q4
Q1
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3
Q1
INTOSC
Multiplexer
OSC1
TOST(1)
TPLL(1)
PLL Clock
Output
1
2
3 4 5 6
Clock Transition
7
8
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake-up from Interrupt Event
PC + 2
PC + 4
PC + 6
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
© 2007 Microchip Technology Inc.
DS39599G-page 35
PIC18F2220/2320/4220/4320
3.4
Run Modes
SEC_RUN mode is entered by clearing the IDLEN bit,
setting SCS1:SCS0 = 01 and executing a SLEEP
instruction. The system clock source is switched to the
Timer1 oscillator (see Figure 3-9), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
If the IDLEN bit is clear when a SLEEP instruction is
executed, the CPU and peripherals are both clocked
from the source selected using the SCS1:SCS0 bits.
While these operating modes may not afford the power
conservation of Idle or Sleep modes, they do allow the
device to continue executing instructions by using a
lower frequency clock source. RC_RUN mode also
offers the possibility of executing code at a frequency
greater than the primary clock.
Note:
Wake-up from a power-managed Run mode can be
triggered by an interrupt, or any Reset, to return to fullpower operation. As the CPU is executing code in Run
modes, several additional exits from Run modes are
possible. They include exit to Sleep mode, exit to a corresponding Idle mode, and exit by executing a RESET
instruction. While the device is in any of the powermanaged Run modes, a WDT time-out will result in a
WDT Reset.
3.4.1
When a wake-up event occurs, the peripherals and
CPU continue to be clocked from the Timer1 oscillator
while the primary clock is started. When the primary
clock becomes ready, a clock switch back to the primary
clock occurs (see Figure 3-6). When the clock switch is
complete, the T1RUN bit is cleared, the OSTS bit is set
and the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run.
PRI_RUN MODE
The PRI_RUN mode is the normal full-power execution
mode. If the SLEEP instruction is never executed, the
microcontroller operates in this mode (a SLEEP instruction is executed to enter all other power-managed
modes). All other power-managed modes exit to
PRI_RUN mode when an interrupt or WDT time-out
occur.
Firmware can force an exit from SEC_RUN mode. By
clearing the T1OSCEN bit (T1CON<3>), an exit from
SEC_RUN back to normal full-power operation is triggered. The Timer1 oscillator will continue to run and
provide the system clock even though the T1OSCEN bit
is cleared. The primary clock is started. When the
primary clock becomes ready, a clock switch back to the
primary clock occurs (see Figure 3-6). When the clock
switch is complete, the Timer1 oscillator is disabled, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the system clock. The IDLEN
and SCS bits are not affected by the wake-up.
There is no entry to PRI_RUN mode. The OSTS bit is
set. The IOFS bit may be set if the internal oscillator
block is the primary clock source (see Section 2.7.1
“Oscillator Control Register”).
3.4.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
FIGURE 3-9:
The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when trying to set the SCS0 bit, the write to
SCS0 will not occur. If the Timer1 oscillator is enabled, but not yet running, system
clocks will be delayed until the oscillator
has started; in such situations, initial oscillator operation is far from stable and
unpredictable operation may result.
TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
1
T1OSI
OSC1
2
3
4
5
6
Clock Transition
7
Q3
Q4
Q1
Q2
Q3
8
CPU
Clock
Peripheral
Clock
Program
Counter
PC
DS39599G-page 36
PC + 2
PC + 2
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
3.4.3
RC_RUN MODE
Note:
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode provides the best power conservation of all the Run modes
while still executing code. It works well for user applications which are not highly timing sensitive or do not
require high-speed clocks at all times.
If the IRCF bits are all clear, the INTOSC output is not
enabled and the IOFS bit will remain clear; there will be
no indication of the current clock source. The INTRC
source is providing the system clocks.
If the primary clock source is the internal oscillator
block (either of the INTIO1 or INTIO2 oscillators), there
are no distinguishable differences between PRI_RUN
and RC_RUN modes during execution. However, a
clock switch delay will occur during entry to, and exit
from, RC_RUN mode. Therefore, if the primary clock
source is the internal oscillator block, the use of
RC_RUN mode is not recommended.
If the IRCF bits are changed from all clear (thus
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable. Clocks to
the system continue while the INTOSC source
stabilizes in approximately 1 ms.
If the IRCF bits were previously at a non-zero value
before the SLEEP instruction was executed and the
INTOSC source was already stable, the IOFS bit will
remain set.
This mode is entered by clearing the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The IRCF bits may select the clock
frequency before the SLEEP instruction is executed.
When the clock source is switched to the INTOSC
multiplexer (see Figure 3-10), the primary oscillator is
shut down and the OSTS bit is cleared.
When a wake-up event occurs, the system continues to
be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes
ready, a clock switch to the primary clock occurs (see
Figure 3-8). When the clock switch is complete, the
IOFS bit is cleared, the OSTS bit is set and the primary
clock is providing the system clock. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
The IRCF bits may be modified at any time to immediately change the system clock speed. Executing a
SLEEP instruction is not required to select a new clock
frequency from the INTOSC multiplexer.
FIGURE 3-10:
Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
TIMING TRANSITION TO RC_RUN MODE
Q4 Q1 Q2 Q3 Q4
Q1
1
INTRC
Q2
2
3
4
5
6
7
Q3
Q4
Q1
Q2
Q3
8
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
© 2007 Microchip Technology Inc.
PC + 2
PC + 4
DS39599G-page 37
PIC18F2220/2320/4220/4320
3.4.4
EXIT TO IDLE MODE
An exit from a power-managed Run mode to its corresponding Idle mode is executed by setting the IDLEN
bit and executing a SLEEP instruction. The CPU is
halted at the beginning of the instruction following the
SLEEP instruction. There are no changes to any of the
clock source status bits (OSTS, IOFS or T1RUN).
While the CPU is halted, the peripherals continue to be
clocked from the previously selected clock source.
3.4.5
EXIT TO SLEEP MODE
An exit from a power-managed Run mode to Sleep
mode is executed by clearing the IDLEN and
SCS1:SCS0 bits and executing a SLEEP instruction.
The code is no different than the method used to invoke
Sleep mode from the normal operating (full power)
mode.
The primary clock and internal oscillator block are disabled. The INTRC will continue to operate if the WDT
is enabled. The Timer1 oscillator will continue to run, if
enabled, in the T1CON register. All clock source status
bits are cleared (OSTS, IOFS and T1RUN).
DS39599G-page 38
3.5
Wake-up From Power-Managed
Modes
An exit from any of the power-managed modes is triggered by an interrupt, a Reset, or a WDT time-out. This
section discusses the triggers that cause exits from
power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Sleep Mode” through
Section 3.4 “Run Modes”).
Note:
If application code is timing sensitive, it
should wait for the OSTS bit to become set
before continuing. Use the interval during
the low-power exit sequence (before
OSTS is set) to perform timing insensitive
“housekeeping” tasks.
Device behavior during Low-Power mode exits is
summarized in Table 3-3.
3.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit a power-managed mode and resume fullpower operation. To enable this functionality, an
interrupt source must be enabled by setting its enable
bit in one of the INTCON or PIE registers. The exit
sequence is initiated when the corresponding interrupt
flag bit is set. On all exits from Lower Power mode by
interrupt, code execution branches to the interrupt
vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without
branching (see Section 9.0 “Interrupts”).
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 3-3:
ACTIVITY AND EXIT DELAY ON WAKE-UP FROM SLEEP MODE OR
ANY IDLE MODE (BY CLOCK SOURCES)
Clock in
Power-Managed
Mode
Primary System
Clock
(PRI_IDLE mode)
Primary System
Clock
LP, XT, HS
EC, RC, INTRC(1)
OST
HSPLL
OST + 2 ms
(1)
EC, RC, INTRC
LP, XT, HS
HSPLL
EC, RC, INTRC(1)
INTOSC(2)
LP, XT, HS
HSPLL
INTOSC
Note 1:
2:
3:
4:
5:
—
5-10 μs(4)
IOFS
OST
OSTS
5-10 μs(5)
—
None
IOFS
OST
OST + 2 ms
EC, RC, INTRC(1)
OSTS
5-10 μs(5)
OST + 2 ms
(2)
—
IOFS
INTOSC
Sleep mode
5-10 μs(5)
INTOSC(2)
(2)
INTOSC(2)
Clock Ready
Status Bit
(OSCCON)
OSTS
HSPLL
LP, XT, HS
T1OSC or INTRC(1)
Power-Managed
Mode Exit Delay
OSTS
5-10 μs(5)
—
5-10 μs(4)
IOFS
Activity During Wake-up from
Power-Managed Mode
Exit by Interrupt
Exit by Reset
CPU and peripherals
clocked by primary clock
and executing
instructions.
Not clocked or
Two-Speed
Start-up
(if enabled)(3).
CPU and peripherals
clocked by selected
power-managed mode
clock and executing
instructions until primary
clock source becomes
ready.
Not clocked or
Two-Speed Start-up (if
enabled) until primary
clock source becomes
ready(3).
In this instance, refers specifically to the INTRC clock source.
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
Two-Speed Start-up is covered in greater detail in Section 23.3 “Two-Speed Start-up”.
Execution continues during the INTOSC stabilization period.
Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).
© 2007 Microchip Technology Inc.
DS39599G-page 39
PIC18F2220/2320/4220/4320
3.5.2
EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock (defined in
Configuration Register 1H) becomes ready. At that
time, the OSTS bit is set and the device begins
executing code.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 23.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 23.4 “Fail-Safe Clock
Monitor”) are enabled in Configuration Register 1H,
the device may begin execution as soon as the Reset
source has cleared. Execution is clocked by the
INTOSC multiplexer driven by the internal oscillator
block. Since the OSCCON register is cleared following
all Resets, the INTRC clock source is selected. A higher
speed clock may be selected by modifying the IRCF bits
in the OSCCON register. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready, or a power-managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.
3.5.3
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in a wake-up from
the power-managed mode (see Section 3.2 “Sleep
Mode” through Section 3.4 “Run Modes”).
If the device is executing code (all Run modes), the
time-out will result in a WDT Reset (see Section 23.2
“Watchdog Timer (WDT)”).
The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
system clock source.
DS39599G-page 40
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. These are:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these cases, the primary clock source either does
not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes).
However, a fixed delay (approximately 10 μs) following
the wake-up event is required when leaving Sleep and
Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on
the first clock cycle following this delay.
3.6
INTOSC Frequency Drift
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways.
It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has the
side effect that the INTRC clock source frequency is
also affected. However, the features that use the
INTRC source often do not require an exact frequency.
These features include the Fail-Safe Clock Monitor, the
Watchdog Timer and the RC_RUN/RC_IDLE modes
when the INTRC clock source is selected.
Being able to adjust the INTOSC requires knowing
when an adjustment is required, in which direction it
should be made and in some cases, how large a
change is needed. Three examples are shown but
other techniques may be used.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
3.6.1
EXAMPLE – USART
An adjustment may be indicated when the USART
begins to generate framing errors or receives data
with errors while in Asynchronous mode. Framing
errors indicate that the system clock frequency is too
high – try decrementing the value in the OSCTUNE
register to reduce the system clock frequency. Errors in
data may suggest that the system clock speed is too
low – increment OSCTUNE.
3.6.2
EXAMPLE – TIMERS
This technique compares system clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared but the timer clocked by the reference generates interrupts. When an interrupt occurs,
the internally clocked timer is read and both timers are
cleared. If the internally clocked timer value is greater
than expected, then the internal oscillator block is
running too fast – decrement OSCTUNE.
© 2007 Microchip Technology Inc.
3.6.3
EXAMPLE – CCP IN CAPTURE
MODE
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast – decrement OSCTUNE. If the measured time
is much less than the calculated time, the internal
oscillator block is running too slow – increment
OSCTUNE.
DS39599G-page 41
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 42
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
4.0
RESET
The PIC18F2X20/4X20 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Power-on Reset (POR)
MCLR Reset while executing instructions
MCLR Reset when not executing instructions
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
FIGURE 4-1:
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 4-2. These bits
are used in software to determine the nature of the
Reset. See Table 4-3 for a full description of the Reset
states of all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
The enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
The MCLR input provided by the MCLR pin can be disabled with the MCLRE bit in Configuration Register 3H
(CONFIG3H<7>). See Section 23.1 “Configuration
Bits” for more information.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLR
MCLRE
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
VDD
POR Pulse
Brown-out
Reset
BOREN
S
OST/PWRT
1024 Cycles
OST
10-Bit Ripple Counter
OSC1
32 μs
INTRC(1)
PWRT
R
Q
Chip_Reset
65.5 ms
11-bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-1 for time-out situations.
© 2007 Microchip Technology Inc.
DS39599G-page 43
PIC18F2220/2320/4220/4320
4.1
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin through a resistor (1k to
10 kΩ) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified
(parameter D004). For a slow rise time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 4-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD
VDD
D
R
C
MCLR
PIC18FXXXX
Note 1: External Power-on Reset circuit is
required only if the VDD power-up slope is
too slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that the voltage drop across R does not
violate the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the
event of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC18F2X20/4X20
devices is an 11-bit counter, which uses the INTRC
source as the clock input. This yields a count of
2048 x 32 μs = 65.6 ms. While the PWRT is counting,
the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter #33 for details.
The PWRT is enabled by clearing Configuration bit,
PWRTEN.
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most power-managed modes.
4.4
PLL Lock Time-out
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A portion of the
Power-up Timer is used to provide a fixed time-out that
is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms
and follows the oscillator start-up time-out.
4.5
R1
4.2
4.3
Brown-out Reset (BOR)
A Configuration bit, BOREN, can disable (if clear/
programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below VBOR (parameter D005) for
greater than TBOR (parameter #35), the brown-out situation will reset the chip. A Reset may not occur if VDD
falls below VBOR for less than TBOR. The chip will
remain in Brown-out Reset until VDD rises above VBOR.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay TPWRT (parameter
#33). If VDD drops below VBOR while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
VDD rises above VBOR, the Power-up Timer will execute
the additional time delay. Enabling BOR Reset does
not automatically enable the PWRT.
4.6
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, after the POR pulse has cleared, PWRT time-out
is invoked (if enabled). Then, the OST is activated. The
total time-out will vary based on oscillator configuration
and the status of the PWRT. For example, in RC mode
with the PWRT disabled, there will be no time-out at all.
Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and
Figure 4-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
Table 4-2 shows the Reset conditions for some Special
Function Registers, while Table 4-3 shows the Reset
conditions for all the registers.
DS39599G-page 44
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 4-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out
Oscillator
Configuration
PWRTEN = 1
Exit from
Power-Managed Mode
1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
PWRTEN = 0
HSPLL
66 ms
(1)
+ 1024 TOSC + 2 ms
(2)
HS, XT, LP
66 ms(1) + 1024 TOSC
1024 TOSC
1024 TOSC
EC, ECIO
66 ms(1)
—
—
RC, RCIO
(1)
66 ms
—
—
INTIO1, INTIO2
66 ms(1)
—
—
Note 1:
2:
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2 ms is the nominal time required for the 4x PLL to lock.
REGISTER 4-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
U-0
U-0
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
—
RI
TO
PD
POR
BOR
bit 7
Note:
TABLE 4-2:
bit 0
Refer to Section 5.14 “RCON Register” for bit definitions.
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
RI
TO
PD
POR
BOR
STKFUL
STKUNF
Power-on Reset
0000h
0--1 1100
1
1
1
0
0
0
0
RESET Instruction
0000h
0--0 uuuu
0
u
u
u
u
u
u
Brown-out Reset
0000h
0--1 11u-
1
1
1
u
0
u
u
MCLR Reset during
power-managed Run modes
0000h
0--u 1uuu
u
1
u
u
u
u
u
MCLR Reset during
power-managed Idle modes and
Sleep mode
0000h
0--u 10uu
u
1
0
u
u
u
u
WDT time-out during full power
or power-managed Run mode
0000h
0--u 0uuu
u
0
u
u
u
u
u
u
u
1
u
u
1
Condition
MCLR Reset during full-power
execution
Stack Full Reset (STVREN = 1)
0000h
0--u uuuu
u
u
u
u
u
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
u--u uuuu
u
u
u
u
u
u
1
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
u--u 00uu
u
0
0
u
u
u
u
Interrupt exit from
power-managed modes
PC + 2
u--u u0uu
u
u
0
u
u
u
u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
© 2007 Microchip Technology Inc.
DS39599G-page 45
PIC18F2220/2320/4220/4320
TABLE 4-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
2220 2320 4220 4320
---0 0000
---0 0000
---0 uuuu(3)
TOSH
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu(3)
TOSL
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu(3)
STKPTR
2220 2320 4220 4320
uu-0 0000
00-0 0000
uu-u uuuu(3)
PCLATU
2220 2320 4220 4320
---0 0000
---0 0000
---u uuuu
PCLATH
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
PCL
2220 2320 4220 4320
0000 0000
0000 0000
PC + 2(2)
TBLPTRU
2220 2320 4220 4320
--00 0000
--00 0000
--uu uuuu
TBLPTRH
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
TBLPTRL
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
TABLAT
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
PRODH
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
INTCON
2220 2320 4220 4320
0000 000x
0000 000u
uuuu uuuu(1)
INTCON2
2220 2320 4220 4320
1111 -1-1
1111 -1-1
uuuu -u-u(1)
INTCON3
2220 2320 4220 4320
11-0 0-00
11-0 0-00
uu-u u-uu(1)
INDF0
2220 2320 4220 4320
N/A
N/A
N/A
POSTINC0
2220 2320 4220 4320
N/A
N/A
N/A
Register
POSTDEC0 2220 2320 4220 4320
N/A
N/A
N/A
PREINC0
N/A
N/A
N/A
2220 2320 4220 4320
PLUSW0
2220 2320 4220 4320
N/A
N/A
N/A
FSR0H
2220 2320 4220 4320
---- xxxx
---- uuuu
---- uuuu
FSR0L
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
2220 2320 4220 4320
N/A
N/A
N/A
POSTINC1
2220 2320 4220 4320
N/A
N/A
N/A
POSTDEC1 2220 2320 4220 4320
N/A
N/A
N/A
PREINC1
2220 2320 4220 4320
N/A
N/A
N/A
PLUSW1
2220 2320 4220 4320
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
DS39599G-page 46
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 4-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
2220 2320 4220 4320
---- xxxx
---- uuuu
---- uuuu
FSR1L
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
2220 2320 4220 4320
---- 0000
---- 0000
---- uuuu
INDF2
2220 2320 4220 4320
N/A
N/A
N/A
POSTINC2
2220 2320 4220 4320
N/A
N/A
N/A
Register
POSTDEC2 2220 2320 4220 4320
N/A
N/A
N/A
PREINC2
N/A
N/A
N/A
2220 2320 4220 4320
PLUSW2
2220 2320 4220 4320
N/A
N/A
N/A
FSR2H
2220 2320 4220 4320
---- xxxx
---- uuuu
---- uuuu
FSR2L
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
2220 2320 4220 4320
---x xxxx
---u uuuu
---u uuuu
TMR0H
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
TMR0L
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
2220 2320 4220 4320
1111 1111
1111 1111
uuuu uuuu
OSCCON
2220 2320 4220 4320
0000 q000
0000 q000
uuuu qquu
LVDCON
2220 2320 4220 4320
--00 0101
--00 0101
--uu uuuu
WDTCON
2220 2320 4220 4320
---- ---0
---- ---0
---- ---u
RCON
2220 2320 4220 4320
0--1 11q0
0--q qquu
u--u qquu
TMR1H
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
2220 2320 4220 4320
0000 0000
u0uu uuuu
uuuu uuuu
TMR2
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
PR2
2220 2320 4220 4320
1111 1111
1111 1111
1111 1111
T2CON
2220 2320 4220 4320
-000 0000
-000 0000
-uuu uuuu
SSPBUF
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
SSPCON1
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
SSPCON2
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
(4)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
© 2007 Microchip Technology Inc.
DS39599G-page 47
PIC18F2220/2320/4220/4320
TABLE 4-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
2220 2320 4220 4320
--00 0000
--00 0000
--uu uuuu
Register
ADRESH
ADCON1
2220 2320 4220 4320
--00 0000
--00 0000
--uu uuuu
ADCON2
2220 2320 4220 4320
0-00 0000
0-00 0000
u-uu uuuu
CCPR1H
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
2220 2320 4220 4320
--00 0000
--00 0000
--uu uuuu
CCPR2H
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
2220 2320 4220 4320
--00 0000
--00 0000
--uu uuuu
PWM1CON
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
ECCPAS
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
CVRCON
2220 2320 4220 4320
000- 0000
000- 0000
uuu- uuuu
CMCON
2220 2320 4220 4320
0000 0111
0000 0111
uuuu uuuu
TMR3H
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
2220 2320 4220 4320
0000 0000
uuuu uuuu
uuuu uuuu
SPBRG
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
RCREG
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
TXREG
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
TXSTA
2220 2320 4220 4320
0000 -010
0000 -010
uuuu -uuu
RCSTA
2220 2320 4220 4320
0000 000x
0000 000x
uuuu uuuu
EEADR
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
EEDATA
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
EECON1
2220 2320 4220 4320
xx-0 x000
uu-0 u000
uu-0 u000
EECON2
2220 2320 4220 4320
0000 0000
0000 0000
0000 0000
CCP1CON
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
DS39599G-page 48
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 4-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
IPR2
2220 2320 4220 4320
11-1 1111
11-1 1111
uu-u uuuu
PIR2
2220 2320 4220 4320
00-0 0000
00-0 0000
uu-u uuuu(1)
PIE2
2220 2320 4220 4320
00-0 0000
00-0 0000
uu-u uuuu
Register
IPR1
PIR1
PIE1
2220 2320 4220 4320
1111 1111
1111 1111
uuuu uuuu
2220 2320 4220 4320
-111 1111
-111 1111
-uuu uuuu
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu(1)
2220 2320 4220 4320
-000 0000
-000 0000
-uuu uuuu(1)
2220 2320 4220 4320
0000 0000
0000 0000
uuuu uuuu
2220 2320 4220 4320
-000 0000
-000 0000
-uuu uuuu
OSCTUNE
2220 2320 4220 4320
--00 0000
--00 0000
--uu uuuu
OSCTUN2
2220 2320 4220 4320
0-00 0000
0-00 0000
u-uu uuuu
TRISE
2220 2320 4220 4320
0000 -111
0000 -111
uuuu -uuu
TRISD
2220 2320 4220 4320
1111 1111
1111 1111
uuuu uuuu
TRISC
2220 2320 4220 4320
1111 1111
1111 1111
uuuu uuuu
TRISB
2220 2320 4220 4320
1111 1111
1111 1111
uuuu uuuu
(5)
1111(5)
1111(5)
uuuu uuuu(5)
TRISA
2220 2320 4220 4320
1111
LATE
2220 2320 4220 4320
---- -xxx
---- -uuu
---- -uuu
LATD
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATA(5)
2220 2320 4220 4320
xxxx xxxx(5)
uuuu uuuu(5)
uuuu uuuu(5)
PORTE
2220 2320 4220 4320
---- xxxx
---- xxxx
---- uuuu
PORTD
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
2220 2320 4220 4320
xxxx xxxx
uuuu uuuu
uuuu uuuu
(5)
PORTA
2220 2320 4220 4320
xx0x
0000(5)
1111
uu0u
0000(5)
uuuu uuuu(5)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
© 2007 Microchip Technology Inc.
DS39599G-page 49
PIC18F2220/2320/4220/4320
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 4-5:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
DS39599G-page 50
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD
0V
1V
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
TOST
TPLL
PLL Time-out
Internal Reset
Note:
TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
© 2007 Microchip Technology Inc.
DS39599G-page 51
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 52
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.0
MEMORY ORGANIZATION
There are three memory types in enhanced MCU
devices. These memory types are:
• Program Memory
• Data RAM
• Data EEPROM
5.1
Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).
Data and program memory use separate busses which
allow for concurrent access of these types.
The PIC18F2220 and PIC18F4220 each have
4 Kbytes of Flash memory and can store up to 2,048
single-word instructions.
Additional detailed information for Flash program memory and data EEPROM is provided in Section 6.0
“Flash Program Memory” and Section 7.0 “Data
EEPROM Memory”, respectively.
The PIC18F2320 and PIC18F4320 each have
8 Kbytes of Flash memory and can store up to 4,096
single-word instructions.
The Reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h.
The Program Memory Maps for PIC18F2220/4220 and
PIC18F2320/4320 devices are shown in Figure 5-1
and Figure 5-2, respectively.
PROGRAM MEMORY MAP
AND STACK FOR
PIC18F2220/4220
PC<20:0>
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
FIGURE 5-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18F2320/4320
PC<20:0>
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
•
•
•
•
•
•
Stack Level 31
Stack Level 31
Reset Vector
0000h
Reset Vector
0000h
High-Priority Interrupt Vector 0008h
High-Priority Interrupt Vector 0008h
Low-Priority Interrupt Vector 0018h
Low-Priority Interrupt Vector 0018h
Read ‘0’
1FFFh
2000h
Read ‘0’
1FFFFFh
200000h
© 2007 Microchip Technology Inc.
On-Chip
Program Memory
0FFFh
1000h
User Memory Space
On-Chip
Program Memory
User Memory Space
FIGURE 5-1:
1FFFFFh
200000h
DS39599G-page 53
PIC18F2220/2320/4220/4320
5.2
Return Address Stack
5.2.2
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is executed or an interrupt is
Acknowledged. The PC value is pulled off the stack on
a RETURN, RETLW or a RETFIE instruction. PCLATU
and PCLATH are not affected by any of the RETURN or
CALL instructions.
The STKPTR register (Register 5-1) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. At Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System for return stack maintenance.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, with the Stack Pointer initialized to
00000b after all Resets. There is no RAM associated
with Stack Pointer, 00000b. This is only a Reset value.
During a CALL type instruction, causing a push onto the
stack, the Stack Pointer is first incremented and the
RAM location pointed to by the Stack Pointer is written
with the contents of the PC (already pointing to the
instruction following the CALL). During a RETURN type
instruction, causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR are
transferred to the PC and then the Stack Pointer is
decremented.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to
Section 23.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
The stack space is not part of either program or data
space. The Stack Pointer is readable and writable and
the address on the top of the stack is readable and writable through the top-of-stack Special File Registers.
Data can also be pushed to, or popped from, the stack
using the top-of-stack SFRs. Status bits indicate if the
stack is full, has overflowed or underflowed.
5.2.1
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push,
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or a POR occurs.
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, hold the
contents of the stack location pointed to by the
STKPTR register (Figure 5-3). This allows users to
implement a software stack if necessary. After a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU, TOSH and TOSL registers.
These values can be placed on a user-defined software
stack. At return time, the software can replace the
TOSU, TOSH and TOSL and do a return.
Note:
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-3:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
TOSU
00h
TOSH
1Ah
TOSL
34h
Return Address Stack
11111
11110
11101
Top-of-Stack
DS39599G-page 54
RETURN STACK POINTER
(STKPTR)
STKPTR<4:0>
00010
00011
001A34h 00010
000D58h 00001
00000
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 5-1:
R/C-0
STKPTR: STACK POINTER REGISTER
R/C-0
(1)
STKFUL
STKUNF
(1)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SP4
SP3
SP2
SP1
SP0
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6
STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1:
5.2.3
x = Bit is unknown
Bit 7 and bit 6 are cleared by user software or by a POR.
PUSH AND POP INSTRUCTIONS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the Stack Pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place data or a return address
on the stack.
5.2.4
STACK FULL/UNDERFLOW RESETS
These Resets are enabled by programming the
STVREN bit in Configuration Register 4L. When the
STVREN bit is cleared, a full or underflow condition will
set the appropriate STKFUL or STKUNF bit but not
cause a device Reset. When the STVREN bit is set, a
full or underflow condition will set the appropriate
STKFUL or STKUNF bit and then cause a device
Reset. The STKFUL or STKUNF bits are cleared by the
user software or a POR Reset.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the
Stack Pointer. The previous value pushed onto the
stack then becomes the TOS value.
© 2007 Microchip Technology Inc.
DS39599G-page 55
PIC18F2220/2320/4220/4320
5.3
Fast Register Stack
A “fast return” option is available for interrupts. A Fast
Register Stack is provided for the STATUS, WREG and
BSR registers and are only one in depth. The stack is
not readable or writable and is loaded with the current
value of the corresponding register when the processor
vectors for an interrupt. The values in the registers are
then loaded back into the working registers if the
RETFIE, FAST instruction is used to return from the
interrupt.
All interrupt sources will push values into the stack registers. If both low and high-priority interrupts are
enabled, the stack registers cannot be used reliably to
return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the
stack register values stored by the low-priority interrupt
will be overwritten. Users must save the key registers
in software during a low-priority interrupt.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt.
If no interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
5.4
PCL, PCLATH and PCLATU
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte, known as the PCL register, is both
readable and writable. The high byte, or PCH register,
contains the PC<15:8> bits and is not directly readable
or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is
called PCU. This register contains the PC<20:16> bits
and is not directly readable or writable. Updates to the
PCU register may be performed through the PCLATU
register.
The contents of PCLATH and PCLATU will be transferred to the program counter by any operation that
writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 5.8.1
“Computed GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ‘0’.
The PC increments by 2 to address sequential
instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 5-1:
CALL SUB1, FAST
•
•
•
•
RETURN FAST
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
DS39599G-page 56
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.5
Clocking Scheme/Instruction
Cycle
5.6
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 5-2).
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the Program Counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 5-4.
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-4:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
OSC2/CLKO
(RC mode)
EXAMPLE 5-2:
PC+2
PC
Execute INST (PC-2)
Fetch INST (PC)
PC+4
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+2)
Fetch INST (PC+4)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
3. BRA
SUB_1
4. BSF
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush (NOP)
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
© 2007 Microchip Technology Inc.
DS39599G-page 57
PIC18F2220/2320/4220/4320
5.7
Instructions in Program Memory
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 5-5 shows an
example of how instruction words are stored in the program memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 5.4 “PCL,
PCLATH and PCLATU”).
FIGURE 5-5:
INSTRUCTIONS IN PROGRAM MEMORY
Program Memory
Byte Locations →
5.7.1
The CALL and GOTO instructions have the absolute program memory address embedded into the instruction.
Since instructions are always stored on word boundaries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-5 shows how the
instruction ‘GOTO 000006h’ is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner.
The offset value stored in a branch instruction represents the number of single-word instructions that the
PC will be offset by. Section 24.0 “Instruction Set
Summary” provides further details of the instruction
set.
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
000006h
Instruction 3:
MOVFF
123h, 456h
TWO-WORD INSTRUCTIONS
PIC18F2X20/4X20 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the 4 MSBs set to ‘1’s
and is decoded as a NOP instruction. The lower 12 bits
of the second word contain data to be used by the
instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the
EXAMPLE 5-3:
LSB = 1
LSB = 0
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Word Address
↓
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that results in a skip operation. A program example that demonstrates this concept is shown in Example 5-3. Refer to Section 24.0
“Instruction Set Summary” for further details of the
instruction set.
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; No, skip this word
1111 0100 0101 0110
0010 0100 0000 0000
; Execute this word as a NOP
ADDWF
REG3
; continue code
CASE 2:
Object Code
Source Code
0110 0110 0000 0000
TSTFSZ
REG1
; is RAM location 0?
1100 0001 0010 0011
MOVFF
REG1, REG2
; Yes, execute this word
ADDWF
REG3
; continue code
1111 0100 0101 0110
0010 0100 0000 0000
DS39599G-page 58
; 2nd word of instruction
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.8
Look-up Tables
Look-up tables are implemented two ways:
• Computed GOTO
• Table Reads
5.8.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 5-4.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSB = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 5-4:
MOVFW
CALL
ORG
0xnn00
TABLE ADDWF
RETLW
RETLW
RETLW
•
•
•
5.8.2
COMPUTED GOTO USING
AN OFFSET VALUE
OFFSET
TABLE
PCL
0xnn
0xnn
0xnn
TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per program word by using table reads and writes. The Table
Pointer (TBLPTR) specifies the byte address and the
Table Latch (TABLAT) contains the data that is read
from, or written to program memory. Data is transferred
to/from program memory, one byte at a time.
The Table Read/Table Write operation is discussed
further in Section 6.1 “Table Reads and Table
Writes”.
© 2007 Microchip Technology Inc.
5.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 5-6
shows the data memory organization for the
PIC18F2X20/4X20 devices.
The data memory map is divided into as many as
16 banks that contain 256 bytes each. The lower 4 bits
of the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits of the BSR are
not implemented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user’s application. The SFRs start at the last location of Bank 15
(FFFh) and extend towards F80h. Any remaining space
beyond the SFRs in the bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any read of an unimplemented location
will read as ‘0’s.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indirect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the data memory map without banking. See
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” for indirect addressing details.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 5.10
“Access Bank” provides a detailed description of the
Access RAM.
5.9.1
GENERAL PURPOSE
REGISTER FILE
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Data RAM is available for use as GPR registers by all
instructions. The second half of Bank 15 (F80h to
FFFh) contains SFRs. All other banks of data memory
contain GPRs, starting with Bank 0.
DS39599G-page 59
PIC18F2220/2320/4220/4320
FIGURE 5-6:
DATA MEMORY MAP FOR PIC18F2X20/4X20 DEVICES
BSR<3:0>
= 0000
= 0001
Data Memory Map
00h
Access RAM
FFh
00h
GPR
Bank 0
Bank 1
000h
07Fh
080h
0FFh
100h
GPR
1FFh
200h
FFh
Access Bank
Access RAM Low
= 0010
= 1110
Bank 2
to
Bank 14
00h
7Fh
Access RAM High 80h
(SFRs)
FFh
Unused
Read ‘00h’
When a = 0:
The BSR is ignored and the
Access Bank is used.
= 1111
00h
Unused
FFh
SFR
Bank 15
EFFh
F00h
F7Fh
F80h
FFFh
The first 128 bytes are
general purpose RAM
(from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1:
The BSR specifies the bank
used by the instruction.
DS39599G-page 60
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those associated with the “core” function and those related to the
peripheral functions. Those registers related to the
TABLE 5-1:
Address
FFFh
FFEh
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the
peripherals whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s.
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2X20/4X20 DEVICES
Name
Address
TOSU
FDFh
TOSH
Name
INDF2
Address
(2)
Name
Address
Name
FBFh
CCPR1H
F9Fh
IPR1
F9Eh
PIR1
FDEh
POSTINC2(2)
FBEh
CCPR1L
FBDh
CCP1CON
F9Dh
PIE1
FBCh
CCPR2H
F9Ch
—
FFDh
TOSL
FDDh
POSTDEC2(2)
FFCh
STKPTR
FDCh
PREINC2(2)
FBBh
CCPR2L
F9Bh
OSCTUNE
FBAh
CCP2CON
F9Ah
OSCTUN2
F99h
—
—
FFBh
PCLATU
FDBh
PLUSW2(2)
FFAh
PCLATH
FDAh
FSR2H
FF9h
PCL
FD9h
FSR2L
FB9h
—
FF8h
TBLPTRU
FD8h
STATUS
FB8h
—
F98h
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
PWM1CON(1)
F97h
—
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
ECCPAS(1)
F96h
TRISE(1)
FF5h
TABLAT
FD5h
T0CON
FB5h
CVRCON
F95h
TRISD(1)
FF4h
PRODH
FD4h
—
FB4h
CMCON
F94h
TRISC
FF3h
PRODL
FD3h
OSCCON
FB3h
TMR3H
F93h
TRISB
FF2h
INTCON
FD2h
LVDCON
FB2h
TMR3L
F92h
TRISA
FF1h
INTCON2
FD1h
WDTCON
FB1h
T3CON
F91h
—
FF0h
INTCON3
FD0h
RCON
FB0h
—
F90h
—
FEFh
INDF0(2)
FCFh
TMR1H
FAFh
SPBRG
F8Fh
—
FEEh
POSTINC0(2)
FCEh
TMR1L
FAEh
RCREG
F8Eh
—
(2)
FCDh
T1CON
FADh
TXREG
F8Dh
LATE(1)
FCCh
TMR2
FACh
TXSTA
F8Ch
LATD(1)
FEDh POSTDEC0
FECh
PREINC0(2)
FEBh
PLUSW0(2)
FCBh
PR2
FABh
RCSTA
F8Bh
LATC
FEAh
FSR0H
FCAh
T2CON
FAAh
—
F8Ah
LATB
FE9h
FSR0L
FC9h
SSPBUF
FA9h
EEADR
F89h
LATA
FE8h
WREG
FC8h
SSPADD
FA8h
EEDATA
F88h
—
FC7h
SSPSTAT
FA7h
EECON2
F87h
—
—
FE7h
INDF1
(2)
FE6h
POSTINC1(2)
FC6h
SSPCON1
FA6h
EECON1
F86h
FE5h
POSTDEC1(2)
FC5h
SSPCON2
FA5h
—
F85h
—
FE4h
PREINC1(2)
FC4h
ADRESH
FA4h
—
F84h
PORTE(1)
FE3h
PLUSW1(2)
FC3h
ADRESL
FA3h
—
F83h
PORTD(1)
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
FE0h
BSR
FC0h
ADCON2
FA0h
PIE2
F80h
PORTA
Legend: — = Unimplemented registers, read as ‘0’.
Note 1: This register is not available on PIC18F2X20 devices.
2: This is not a physical register.
© 2007 Microchip Technology Inc.
DS39599G-page 61
PIC18F2220/2320/4220/4320
TABLE 5-2:
File Name
TOSU
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320)
Bit 7
Bit 6
Bit 5
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details on
page:
---0 0000
46, 54
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
46, 54
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
46, 54
Return Stack Pointer
00-0 0000
46, 55
Holding Register for PC<20:16>
STKPTR
STKFUL
STKUNF
—
PCLATU
—
—
bit 21(3)
Top-of-Stack Upper Byte (TOS<20:16>)
Value on
POR, BOR
---0 0000
46, 56
PCLATH
Holding Register for PC<15:8>
0000 0000
46, 56
PCL
PC Low Byte (PC<7:0>)
0000 0000
46, 56
--00 0000
46, 74
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
46, 74
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
46, 74
TABLAT
Program Memory Table Latch
0000 0000
46, 74
PRODH
Product Register High Byte
xxxx xxxx
46, 85
PRODL
Product Register Low Byte
xxxx xxxx
46, 85
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
46, 89
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
—
TMR0IP
—
RBIP
1111 -1-1
46, 90
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
INTCON3
11-0 0-00
46, 91
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
n/a
46, 66
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
n/a
46, 66
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
n/a
46, 66
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
n/a
46, 66
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
n/a
46, 66
---- 0000
46, 66
46, 66
INDF0
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
WREG
Working Register
xxxx xxxx
46
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
n/a
46, 66
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
n/a
46, 66
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
n/a
46, 66
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
n/a
46, 66
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
n/a
46, 66
---- 0000
47, 66
FSR1H
—
FSR1L
—
—
—
Indirect Data Memory Address Pointer 1 High
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
xxxx xxxx
47, 66
---- 0000
47, 65
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
n/a
47, 66
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
n/a
47, 66
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
n/a
47, 66
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
n/a
47, 66
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
n/a
47, 66
---- 0000
47, 66
FSR2H
—
FSR2L
—
—
—
Indirect Data Memory Address Pointer 2 High
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
—
—
—
N
OV
Z
DC
C
xxxx xxxx
47, 66
---x xxxx
47, 68
TMR0H
Timer0 Register High Byte
0000 0000
47, 119
TMR0L
Timer0 Register Low Byte
xxxx xxxx
47, 119
1111 1111
47, 117
T0CON
TMR0ON
Legend:
Note 1:
2:
3:
4:
5:
6:
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read
as ‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read as ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown and if PBADEN = 1, PORTB<4:0> are configured as
analog inputs and read as ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2X20 devices and read as 0x00.
The RE3 port bit is available as an input only pin only in 40-pin devices when Master Clear functionality is disabled (CONFIG3H<7> = 0).
DS39599G-page 62
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 5-2:
File Name
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
0000 q000
27, 47
LVDCON
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
--00 0101
47, 233
—
—
—
—
—
—
—
SWDTEN
--- ---0
47, 247
IPEN
—
—
RI
TO
PD
POR
BOR
0--1 11q0
45, 69, 98
WDTCON
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details on
page:
Bit 6
RCON
Bit 5
Value on
POR, BOR
Bit 7
TMR1H
Timer1 Register High Byte
xxxx xxxx
47, 125
TMR1L
Timer1 Register Low Byte
xxxx xxxx
47, 125
T1CON
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
0000 0000
47, 121
TMR2
Timer2 Register
0000 0000
47, 127
PR2
Timer2 Period Register
1111 1111
47, 127
-000 0000
47, 127
xxxx xxxx
47, 156,
164
T2CON
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
TMR1CS
T2CKPS1
TMR1ON
T2CKPS0
SSPBUF
MSSP Receive Buffer/Transmit Register
SSPADD
MSSP Address Register in I2C™ Slave mode. MSSP Baud Rate Reload Register in I2C Master mode.
0000 0000
47, 164
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
47, 156,
165
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
47, 157,
166
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
SSPCON2
0000 0000
47, 167
ADRESH
A/D Result Register High Byte
xxxx xxxx
48, 220
ADRESL
A/D Result Register Low Byte
xxxx xxxx
48, 220
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
48, 211
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0qqq
48, 212
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
ADCON2
0-00 0000
48, 213
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
48, 134
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
48, 134
0000 0000
48, 133,
141
48, 134
P1M1(5)
CCP1CON
P1M0(5)
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
48, 134
--00 0000
48, 133
CCP2CON
—
PWM1CON(5)
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
0000 0000
48, 149
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
0000 0000
48, 150
CVRCON
CVREN
CVROE
CVRR
—
CVR3
CVR2
CVR1
CVR0
000- 0000
48, 227
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111
48, 221
48, 131
ECCPAS(5)
TMR3H
Timer3 Register High Byte
xxxx xxxx
TMR3L
Timer3 Register Low Byte
xxxx xxxx
48, 131
0000 0000
48, 129
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
SPBRG
USART Baud Rate Generator
0000 0000
48, 198
RCREG
USART Receive Register
0000 0000
48, 204,
203
TXREG
USART Transmit Register
0000 0000
48, 202,
203
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
48, 196
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
48, 197
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read
as ‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read as ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown and if PBADEN = 1, PORTB<4:0> are configured as
analog inputs and read as ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2X20 devices and read as 0x00.
The RE3 port bit is available as an input only pin only in 40-pin devices when Master Clear functionality is disabled (CONFIG3H<7> = 0).
© 2007 Microchip Technology Inc.
DS39599G-page 63
PIC18F2220/2320/4220/4320
TABLE 5-2:
File Name
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
48, 81
EEADR
EEPROM Address Register
0000 0000
EEDATA
EEPROM Data Register
0000 0000
48, 84
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000
48, 72, 81
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000
48, 73, 82
IPR2
OSCFIP
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
11-1 1111
49, 97
PIR2
OSCFIF
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
00-0 0000
49, 93
PIE2
OSCFIE
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
00-0 0000
49, 95
IPR1
PSPIP(5)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
49, 96
PIR1
PSPIF(5)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
49, 92
PIE1
PSPIE(5)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
49, 94
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
23, 49
TRISE(5)
IBF
OBF
IBOV
PSPMODE
—
0000 -111
49, 112
Data Direction bits for PORTE
TRISD(5)
Data Direction Control Register for PORTD
1111 1111
49, 110
TRISC
Data Direction Control Register for PORTC
1111 1111
49, 108
TRISB
Data Direction Control Register for PORTB
TRISA
LATE(5)
TRISA7(2)
TRISA6(1)
—
—
Data Direction Control Register for PORTA
—
—
—
Read/Write PORTE Data Latch
1111 1111
49, 106
1111 1111
49, 103
---- -xxx
49, 113
LATD(5)
Read/Write PORTD Data Latch
xxxx xxxx
49, 110
LATC
Read/Write PORTC Data Latch
xxxx xxxx
49, 108
LATB
Read/Write PORTB Data Latch
xxxx xxxx
49, 106
LATA
LATA<7>(2) LATA<6>(1) Read/Write PORTA Data Latch
xxxx xxxx
49, 103
---- qxxx
49, 113
PORTE(5)
—
—
—
—
RE3(6)
Read PORTE pins,
Write PORTE Data Latch
PORTD(5)
Read PORTD pins, Write PORTD Data Latch
xxxx xxxx
49, 110
PORTC
Read PORTC pins, Write PORTC Data Latch
xxxx xxxx
49, 108
PORTB
Read PORTB pins, Write PORTB Data Latch(4)
RA7(2)
PORTA
Legend:
Note 1:
2:
3:
4:
5:
6:
RA6(1)
Read PORTA pins, Write PORTA Data Latch
xxxx xxxx
49, 106
xx0x 0000
49, 103
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read
as ‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read as ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown and if PBADEN = 1, PORTB<4:0> are configured as
analog inputs and read as ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2X20 devices and read as 0x00.
The RE3 port bit is available as an input only pin only in 40-pin devices when Master Clear functionality is disabled (CONFIG3H<7> = 0).
DS39599G-page 64
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.10
Access Bank
5.11
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into as many as sixteen banks. When using
direct addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
•
•
•
•
•
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect (see Figure 5-7).
Intermediate computational values
Local variables of subroutines
Faster context saving/switching of variables
Common variables
Faster evaluation/control of SFRs (no banking)
A MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
The Access Bank is comprised of the last 128 bytes in
Bank 15 (SFRs) and the first 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 5-6
indicates the Access RAM areas.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted as the ‘a’ bit (for
access bit).
A MOVFF instruction ignores the BSR since the 12-bit
addresses are embedded into the instruction word.
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect addressing which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so these registers can
be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
FIGURE 5-7:
Bank Select Register (BSR)
DIRECT ADDRESSING
Direct Addressing
BSR<7:4>
0
0
0
BSR<3:0>
7
From Opcode(3)
0
0
Bank Select(2)
Location Select(3)
00h
01h
0Eh
0Fh
000h
100h
E00h
F00h
0FFh
1FFh
EFFh
FFFh
Bank 14
Bank 15
Data
Memory(1)
Bank 0
Bank 1
Note 1: For register file map detail, see Table 5-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
registers of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
© 2007 Microchip Technology Inc.
DS39599G-page 65
PIC18F2220/2320/4220/4320
5.12
Indirect Addressing, INDF and
FSR Registers
Indirect Addressing is a mode of addressing data memory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 5-8
shows how the fetched instruction is modified prior to
being executed.
Indirect Addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address which is shown in
Figure 5-9.
The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer); this is indirect addressing.
Example 5-5 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
FSR0,0x100 ;
POSTINC0
; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1
; All done with
; Bank1?
GOTO NEXT
; NO, clear next
CONTINUE
; YES, continue
NEXT
LFSR
CLRF
There are three Indirect Addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12 bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required:
1.
2.
3.
FSR0: composed of FSR0H:FSR0L
FSR1: composed of FSR1H:FSR1L
FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates Indirect Addressing with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads
the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
DS39599G-page 66
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
Status bits are not affected.
5.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Performing an operation using one of these five registers
determines how the FSR will be modified during
indirect addressing.
When data access is performed using one of the five
INDFn locations, the address selected will configure
the FSRn register to:
• Do nothing to FSRn after an indirect access (no
change) – INDFn
• Auto-decrement FSRn after an indirect access
(post-decrement) – POSTDECn
• Auto-increment FSRn after an indirect access
(post-increment) – POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) – PREINCn
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) – PLUSWn
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
Auto-incrementing or auto-decrementing an FSR
affects all 12 bits. That is, when FSRnL overflows from
an increment, FSRnH will be incremented
automatically.
Adding these features allows the FSRn to be used as a
Stack Pointer, in addition to its use for table operations
in data memory.
Each FSR has an address associated with it that performs an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the signed value in the WREG register and the value in FSR to form the address before an
indirect access. The FSR value is not changed. The
WREG offset range is -128 to +127.
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is set)
while an indirect write will be equivalent to a NOP
(Status bits are not affected).
If an Indirect Addressing write is performed when the
target address is an FSRnH or FSRnL register, the
data is written to the FSR register but no pre- or
post-increment/decrement is performed.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 5-8:
INDIRECT ADDRESSING OPERATION
RAM
0h
Instruction
Executed
Opcode
Address
FFFh
12
File Address = access of an Indirect Addressing register
BSR<3:0>
Instruction
Fetched
4
Opcode
FIGURE 5-9:
12
12
8
File
FSR
INDIRECT ADDRESSING
Indirect Addressing
FSRnH:FSRnL
3
0
7
0
11
0
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 5-1.
© 2007 Microchip Technology Inc.
DS39599G-page 67
PIC18F2220/2320/4220/4320
5.13
STATUS Register
The STATUS register, shown in Register 5-2, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction as with any other
register. If the STATUS register is the destination for an
instruction that affects the Z, DC, C, OV or N bits, then
the write to these five bits is disabled. These bits are set
or cleared according to the device logic. Therefore, the
result of an instruction with the STATUS register as
destination may be different than intended.
REGISTER 5-2:
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the STATUS register, because these instructions
do not affect the Z, C, DC, OV or N bits in the STATUS
register. For other instructions not affecting any Status
bits (see Table 24-2).
Note:
The C and DC bits operate as a borrow
and digit borrow bit respectively, in
subtraction.
STATUS REGISTER
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
N
OV
Z
DC(1)
C(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude
which causes the sign bit (bit 7 of the result) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
DS39599G-page 68
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
5.14
RCON Register
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device Reset. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
Note 1: If the BOREN Configuration bit is set
(Brown-out Reset enabled), the BOR bit
is ‘1’ on a Power-on Reset. After a Brownout Reset has occurred, the BOR bit will
be cleared and must be set by firmware to
indicate the occurrence of the next
Brown-out Reset.
2: It is recommended that the POR bit be set
after a Power-on Reset has been
detected so that subsequent Power-on
Resets may be detected.
REGISTER 5-3:
RCON: RESET CONTROL REGISTER
R/W-0
U-0
U-0
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
—
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5
Unimplemented: Read as ‘0’
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Cleared by execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
© 2007 Microchip Technology Inc.
DS39599G-page 69
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 70
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
6.0
FLASH PROGRAM MEMORY
The program memory space is 16 bits wide while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
Table read operations retrieve data from program
memory and place it into TABLAT in the data RAM
space. Figure 6-1 shows the operation of a table read
with program memory and data RAM.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A bulk erase operation
may not be issued from user code.
Table write operations store data from TABLAT in the
data memory space into holding registers in program
memory. The procedure to write the contents of the
holding registers into program memory is detailed in
Section 6.5 “Writing to Flash Program Memory”.
Figure 6-2 shows the operation of a table write with
program memory and data RAM.
While writing or erasing program memory, instruction
fetches cease until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned
(TBLPTRL<0> = 0).
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.1
Table Reads and Table Writes
The EEPROM on-chip timer controls the write and
erase times. The write and erase voltages are generated by an on-chip charge pump rated to operate over
the voltage range of the device for byte or word
operations.
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data
RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
FIGURE 6-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
© 2007 Microchip Technology Inc.
DS39599G-page 71
PIC18F2220/2320/4220/4320
FIGURE 6-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1)
TBLPTRU
TBLPTRH
Table Latch (8-bit)
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
6.2
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
•
•
•
•
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
6.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit, EEPGD, determines if the access will be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The FREE bit controls program memory erase operations. When the FREE bit is set, the erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
DS39599G-page 72
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled – the WR bit cannot be set while the WREN bit
is clear. This process helps to prevent accidental writes
to memory due to errant (unexpected) code execution.
Firmware should keep the WREN bit clear at all times
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location. It will be
necessary to reload the data and address registers
(EEDATA and EEADR) as these registers have cleared
as a result of the Reset.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.3 “Reading the
Flash Program Memory” regarding table reads.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
be cleared in software.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 6-1:
EECON1: DATA EEPROM CONTROL REGISTER 1
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR(1)
WREN
WR
RD
bit 7
bit 0
Legend:
S = Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by
completion of erase operation)
0 = Perform write-only
bit 3
WRERR: EEPROM Error Flag bit(1)
1 = A write operation was prematurely terminated (any Reset during self-timed programming)
0 = The write operation completed normally
bit 2
WREN: Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle completed
bit 0
RD: Read Control bit
1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be
set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
0 = Read completed
Note 1:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
© 2007 Microchip Technology Inc.
DS39599G-page 73
PIC18F2220/2320/4220/4320
6.2.2
TABLAT – TABLE LATCH REGISTER
6.2.4
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.3
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program or
configuration memory into TABLAT.
TBLPTR – TABLE POINTER
REGISTER
When a TBLWT is executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the TBLPTR (TBLPTR<21:3>) will determine which program memory block of 8 bytes is written
to (TBLPTR<2:0> are ignored). For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. Setting the 22nd bit allows
access to the Device ID, the user ID and the
Configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLPTR<21:6>) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
The Table Pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.
TABLE 6-1:
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example
TBLRD*
TBLWT*
TABLE POINTER BOUNDARIES
Operation on Table Pointer
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
FIGURE 6-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU
16
15
TBLPTRH
8
7
TBLPTRL
0
ERASE – TBLPTR<21:6>
LONG WRITE – TBLPTR<21:3>
READ or WRITE – TBLPTR<21:0>
DS39599G-page 74
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
6.3
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and place it into data RAM. Table
reads from program memory are performed one byte at
a time.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
TBLPTR points to a byte address in program space.
Executing a TBLRD instruction places the byte pointed
to into TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
FIGURE 6-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
Odd (High) Byte
Even (Low) Byte
TBLPTR
LSB = 0
TBLPTR
LSB = 1
Instruction Register
(IR)
EXAMPLE 6-1:
TABLAT
Read Register
READING A FLASH PROGRAM MEMORY WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
READ_WORD
TBLRD*+
MOVFW
MOVWF
TBLRD*+
MOVFW
MOVWF
TABLAT
WORD_EVEN
TABLAT
WORD_ODD
© 2007 Microchip Technology Inc.
; read into TABLAT and increment TBLPTR
; get data
; read into TABLAT and increment TBLPTR
; get data
DS39599G-page 75
PIC18F2220/2320/4220/4320
6.4
Erasing Flash Program Memory
6.4.1
The minimum erase block size is 32 words or 64 bytes
under firmware control. Only through the use of an
external programmer, or through ICSP control, can
larger blocks of program memory be bulk erased. Word
erase in Flash memory is not supported.
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased;
TBLPTR<5:0> are ignored.
2.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash program memory. The CFGS bit must be clear to access
program Flash and data EEPROM memory. The
WREN bit must be set to enable write operations. The
FREE bit is set to select an erase operation. The WR
bit is set as part of the required instruction sequence
(as shown in Example 6-2) and starts the actual erase
operation. It is not necessary to load the TABLAT
register with any data as it is ignored.
3.
4.
5.
6.
For protection, the write initiate sequence using
EECON2 must be used.
8.
9.
7.
Load Table Pointer with address of row being
erased.
Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program
memory;
• clear the CFGS bit to access program
memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase
(about 2 ms using internal timer).
Execute a NOP.
Re-enable interrupts.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 6-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
EECON1,EEPGD
EECON1,WREN
EECON1,FREE
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON2,WR
;
;
;
;
INTCON,GIE
; re-enable interrupts
ERASE_ROW
Required
Sequence
DS39599G-page 76
point to Flash program memory
enable write to memory
enable Row Erase operation
disable interrupts
; write 55H
; write AAH
; start erase (CPU stall)
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
6.5
Writing to Flash Program Memory
The programming block size is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding registers needed to program the Flash memory. There are
8 holding registers used by the table writes for
programming.
FIGURE 6-5:
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
TBLPTR = xxxxx0
8
TBLPTR = xxxxx2
TBLPTR = xxxxx1
Holding Register
Holding Register
Holding Register
8
TBLPTR = xxxxx7
Holding Register
Program Memory
6.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer with address being erased.
Do the row erase procedure (see Section 6.4.1
“Flash Program Memory Erase Sequence”).
Load Table Pointer with address of first byte
being written.
Write the first 8 bytes into the holding registers
with auto-increment.
Set the EECON1 register for the write operation:
• set EEPGD bit to point to program
memory;
• clear the CFGS bit to access program
memory;
• set WREN bit to enable byte writes.
© 2007 Microchip Technology Inc.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write (about
2 ms using internal timer).
Execute a NOP.
Re-enable interrupts.
Repeat steps 6-14 seven times, to write 64
bytes.
Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
DS39599G-page 77
PIC18F2220/2320/4220/4320
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
D'64
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; number of bytes in erase block
TBLRD*+
MOVFW
MOVWF
DECFSZ
GOTO
TABLAT
POSTINC0
COUNTER
READ_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1,CFGS
EECON1,EEPGD
EECON1,WREN
EECON1,FREE
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
; load TBLPTR with the base
; address of the memory block
INTCON,GIE
; re-enable interrupts
8
COUNTER_HI
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
; number of write buffer groups of 8 bytes
; point to buffer
; Load TBLPTR with the base
; address of the memory block
; 6 LSB = 0
READ_BLOCK
;
;
;
;
;
read into TABLAT, and inc
get data
store data and increment FSR0
done?
repeat
MODIFY_WORD
; update buffer word and increment FSR0
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
WRITE_BUFFER_BACK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
PROGRAM_LOOP
MOVLW
MOVWF
WRITE_WORD_TO_HREGS
MOVFW
MOVWF
TBLWT+*
;
;
;
;
;
;
;
point to PROG/EEPROM memory
point to Flash program memory
enable write to memory
enable Row Erase operation
disable interrupts
Required sequence
write 55H
; write AAH
; start erase (CPU stall)
; point to buffer
8
COUNTER
; number of bytes in holding register
POSTINC0
TABLAT
;
;
;
;
DECFSZ COUNTER
GOTO
WRITE_WORD_TO_HREGS
DS39599G-page 78
; 6 LSB = 0
get low byte of buffer data and increment FSR0
present data to table latch
short write
to internal TBLWT holding register, increment
TBLPTR
; loop until buffers are full
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ
GOTO
BCF
6.5.2
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
; disable interrupts
; required sequence
; write 55H
INTCON,GIE
COUNTER_HI
PROGRAM_LOOP
EECON1,WREN
; re-enable interrupts
; loop until done
; write AAH
; start program (CPU stall)
; disable write to memory
6.6
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the memory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.5.3
Flash Program Operation During
Code Protection
See Section 23.0 “Special Features of the CPU”
(Section 23.5 “Program Verification and Code Protection”) for details on code protection of Flash
program memory.
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset, during normal operation. In
these situations, users can check the WRERR bit and
rewrite the location.
TABLE 6-2:
Name
TBLPTRU
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Bit 7
Bit 6
Bit 5
—
—
bit 21
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
Value on:
POR, BOR
Value on
all other
Resets
--00 0000 --00 0000
TBPLTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 0000 0000
TBLPTRL
Program Memory Table Pointer High Byte (TBLPTR<7:0>)
0000 0000 0000 0000
TABLAT
Program Memory Table Latch
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000 0000 0000
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
—
—
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 uu-0 u000
IPR2
OSCFIP
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
11-1 1111 ---1 1111
PIR2
OSCFIF
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
00-0 0000 ---0 0000
PIE2
OSCFIE
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
00-0 0000 ---0 0000
Legend:
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
© 2007 Microchip Technology Inc.
DS39599G-page 79
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 80
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
7.0
DATA EEPROM MEMORY
The data EEPROM is readable and writable during normal operation over the entire VDD range. The data
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:
•
•
•
•
EECON1
EECON2
EEDATA
EEADR
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 00h to FFh.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write). The
write time is controlled by an on-chip timer. The write time
will vary with voltage and temperature, as well as from
chip to chip. Please refer to parameter D122 (Table 26-1
in Section 26.0 “Electrical Characteristics”) for exact
limits.
7.1
EEADR
The address register can address 256 bytes of data
EEPROM.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers. When CFGS is clear,
the EEPGD bit selects either Flash program or data
EEPROM memory.
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled; the WR bit cannot be set while the WREN bit
is clear. This mechanism helps to prevent accidental
writes to memory due to errant (unexpected) code
execution.
Firmware should keep the WREN bit clear at all times
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers
(EEDATA and EEADR), as these registers have
cleared as a result of the Reset.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
Note:
7.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit EEPGD determines if the access will be to
program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When
set, program memory is accessed.
© 2007 Microchip Technology Inc.
DS39599G-page 81
PIC18F2220/2320/4220/4320
REGISTER 7-1:
EECON1: DATA EEPROM CONTROL REGISTER 1
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR(1)
WREN
WR
RD
bit 7
bit 0
Legend:
S = Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration or Calibration registers
0 = Access Flash program or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by
completion of erase operation)
0 = Perform write-only
bit 3
WRERR: EEPROM Error Flag bit(1)
1 = A write operation was prematurely terminated (MCLR or WDT Reset during self-timed erase or
program operation)
0 = The write operation completed normally
bit 2
WREN: Erase/Write Enable bit
1 = Allows write cycles
0 = Inhibits write cycles
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle is completed
bit 0
RD: Read Control bit
1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be
set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
0 = Read completed
Note 1:
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error
condition.
DS39599G-page 82
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available for the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation or until it is written to
by the user (during a write operation).
7.4
To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write AAh to EECON2,
then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should
be kept clear at all times except when updating the
EEPROM. The WREN bit is not cleared by hardware.
MOVLW
MOVWF
BCF
BSF
MOVF
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the memory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
7.6
Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
DATA EEPROM READ
DATA_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, RD
EEDATA, W
EXAMPLE 7-2:
Required
Sequence
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt
or poll this bit. EEIF must be cleared by software.
7.5
Writing to the Data EEPROM
Memory
EXAMPLE 7-1:
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same
instruction.
;
;
;
;
;
Data Memory Address to read
Point to DATA memory
EEPROM Read
W = EEDATA
DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
;
;
;
;
;
;
;
;
;
;
;
;
;
SLEEP
BCF
EECON1, WREN
; Wait for interrupt to signal write complete
; Disable writes
© 2007 Microchip Technology Inc.
Data Memory Address to write
Data Memory Value to write
Point to DATA memory
Enable writes
Disable Interrupts
Write 55h
Write AAh
Set WR bit to begin write
Enable Interrupts
DS39599G-page 83
PIC18F2220/2320/4220/4320
7.7
Operation During Code-Protect
7.8
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write operations are disabled if either of these mechanisms are
enabled.
Using the Data EEPROM
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of
frequently changing information (e.g., program variables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D124 or D124A. If this is not the
case, an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
The microcontroller itself can both read and write to the
internal Data EEPROM regardless of the state of the
code-protect Configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:
EXAMPLE 7-3:
DATA EEPROM REFRESH ROUTINE
CLRF
BCF
BCF
BCF
BSF
EEADR
EECON1,
EECON1,
INTCON,
EECON1,
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
Loop
BCF
BSF
EECON1, WREN
INTCON, GIE
;
;
;
;
;
;
;
;
;
;
;
;
;
CFGS
EEPGD
GIE
WREN
LOOP
TABLE 7-1:
Name
INTCON
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124 or D124A.
Start at address 0
Set for memory
Set for Data EEPROM
Disable interrupts
Enable writes
Loop to refresh array
Read current address
Write 55h
Write AAh
Set WR bit to begin write
Wait for write to complete
; Increment address
; Not zero, do it again
; Disable writes
; Enable interrupts
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
GIE/GIEH
PEIE/GIEL
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
EEADR
EEPROM Address Register
0000 0000 0000 0000
EEDATA
EEPROM Data Register
0000 0000 0000 0000
EECON2
EEPROM Control Register 2 (not a physical register)
—
—
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 uu-0 u000
11-1 1111 ---1 1111
IPR2
OSCFIP
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
PIR2
OSCFIF
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
00-0 0000 ---0 0000
PIE2
OSCFIE
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
00-0 0000 ---0 0000
Legend:
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
DS39599G-page 84
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
8.0
8 X 8 HARDWARE MULTIPLIER
8.1
Introduction
8.2
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F2X20/4X20 devices. By making the multiply
a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the STATUS register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
Making the 8 x 8 multiplier execute in a single-cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
MOVF
MULWF
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
;
; ARG1 * ARG2 ->
;
PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
BTFSC
SUBWF
ARG2, SB
PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
;
;
;
;
;
ARG1 * ARG2 ->
PRODH:PRODL
Test Sign Bit
PRODH = PRODH
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
PERFORMANCE COMPARISON
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
8 x 8 UNSIGNED
MULTIPLY ROUTINE
ARG1, W
ARG2
EXAMPLE 8-2:
Table 8-1 shows a performance comparison between
enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 8-1:
Operation
Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Without hardware multiply
13
Hardware multiply
1
Without hardware multiply
33
Hardware multiply
6
Without hardware multiply
Hardware multiply
Without hardware multiply
Hardware multiply
© 2007 Microchip Technology Inc.
Time
@ 40 MHz
@ 10 MHz
@ 4 MHz
69
6.9 μs
27.6 μs
69 μs
1
100 ns
400 ns
1 μs
91
9.1 μs
36.4 μs
91 μs
6
600 ns
2.4 μs
6 μs
21
242
24.2 μs
96.8 μs
242 μs
28
28
2.8 μs
11.2 μs
28 μs
52
254
25.4 μs
102.6 μs
254 μs
35
40
4.0 μs
16.0 μs
40 μs
DS39599G-page 85
PIC18F2220/2320/4220/4320
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 8-1:
RES3:RES0
=
=
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
ARG1H:ARG1L • ARG2H:ARG2L
(ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L)
EQUATION 8-2:
RES3:RES0
= ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H ² 28) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 216)
EXAMPLE 8-4:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the arguments, each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
DS39599G-page 86
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
;
;
;
;
;
;
ARG1L * ARG2H ->
PRODH:PRODL
Add cross
products
;
;
;
;
;
;
;
;
;
;
;
MOVF
MULWF
;
;
;
;
;
;
;
;
;
;
16 x 16 SIGNED
MULTIPLY ROUTINE
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
;
;
;
;
;
;
;
;
;
ARG1H * ARG2L ->
PRODH:PRODL
Add cross
products
;
;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE
:
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
9.0
INTERRUPTS
The PIC18F2320/4320 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high-priority
level or a low-priority level. The high-priority interrupt
vector is at 000008h and the low-priority interrupt vector is at 000018h. High-priority interrupt events will
interrupt any low-priority interrupts that may be in
progress.
There are ten registers which are used to control
interrupt operation. These registers are:
•
•
•
•
•
•
•
RCON
INTCON
INTCON2
INTCON3
PIR1, PIR2
PIE1, PIE2
IPR1, IPR2
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
In general, each interrupt source has three bits to
control its operation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
(most interrupt sources have priority bits)
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual interrupts can be disabled through their corresponding
enable bits.
© 2007 Microchip Technology Inc.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In Compatibility mode, the interrupt priority bits for each source
have no effect. INTCON<6> is the PEIE bit which
enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High-priority interrupt sources can interrupt a lowpriority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
Note:
Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
DS39599G-page 87
PIC18F2220/2320/4220/4320
FIGURE 9-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
PSPIF
PSPIE
PSPIP
Wake-up if in
Power-Managed Mode
Interrupt to CPU
Vector to Location
0008h
GIE/GIEH
ADIF
ADIE
ADIP
IPE
IPEN
RCIF
RCIE
RCIP
PEIE/GIEL
IPEN
Additional Peripheral Interrupts
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RBIF
RBIE
RBIP
RCIF
RCIE
RCIP
PEIE/GIEL
INT0IF
INT0IE
Additional Peripheral Interrupts
DS39599G-page 88
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
9.1
INTCON Registers
Note:
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
REGISTER 9-1:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high-priority interrupts
0 = Disables all high-priority interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low-priority peripheral interrupts
0 = Disables all low-priority peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1:
A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and
allow the bit to be cleared.
© 2007 Microchip Technology Inc.
DS39599G-page 89
PIC18F2220/2320/4220/4320
REGISTER 9-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-1
INTEDG0
RBPU
R/W-1
INTEDG1
R/W-1
U-0
INTEDG2
—
R/W-1
U-0
R/W-1
TMR0IP
—
RBIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4
INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3
Unimplemented: Read as ‘0’
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
Unimplemented: Read as ‘0’
bit 0
RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature allows for software polling.
DS39599G-page 90
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 9-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
R/W-1
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
Unimplemented: Read as ‘0’
bit 4
INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2
Unimplemented: Read as ‘0’
bit 1
INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Note:
x = Bit is unknown
Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature allows for software polling.
© 2007 Microchip Technology Inc.
DS39599G-page 91
PIC18F2220/2320/4220/4320
9.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Flag registers (PIR1, PIR2).
REGISTER 9-4:
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
2: User software should ensure the appropriate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The USART transmit buffer is full
bit 3
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1:
This bit is reserved on PIC18F2X20 devices; always maintain this bit clear.
DS39599G-page 92
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIF
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 6
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred (must be cleared in software)
0 = No bus collision occurred
bit 2
LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (must be cleared in software)
0 = The device voltage is above the Low-Voltage Detect trip point
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 or TMR3 register capture occurred (must be cleared in software)
0 = No TMR1 or TMR3 register capture occurred
Compare mode:
1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1 or TMR3 register compare match occurred
PWM mode:
Unused in this mode.
© 2007 Microchip Technology Inc.
DS39599G-page 93
PIC18F2220/2320/4220/4320
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the
PEIE bit must be set to enable any of these peripheral
interrupts.
REGISTER 9-6:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1:
x = Bit is unknown
This bit is reserved on PIC18F2X20 devices; always maintain this bit clear.
DS39599G-page 94
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 9-7:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OSCFIE
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
© 2007 Microchip Technology Inc.
x = Bit is unknown
DS39599G-page 95
PIC18F2220/2320/4220/4320
9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority
bits requires that the Interrupt Priority Enable (IPEN) bit
be set.
REGISTER 9-8:
R/W-1
(1)
PSPIP
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1 = High priority
0 = Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RCIP: USART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TXIP: USART Transmit Interrupt Priority bit
x = Bit is unknown
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Note 1:
This bit is reserved on PIC18F2X20 devices; always maintain this bit set.
DS39599G-page 96
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 9-9:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OSCFIP
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
LVDIP: Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
© 2007 Microchip Technology Inc.
x = Bit is unknown
DS39599G-page 97
PIC18F2220/2320/4220/4320
9.5
RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from powermanaged mode. RCON also contains the bit that
enables interrupt priorities (IPEN).
REGISTER 9-10:
RCON: RESET CONTROL REGISTER
R/W-0
U-0
U-0
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
—
—
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5
Unimplemented: Read as ‘0’
bit 4
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2
PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Cleared by execution of the SLEEP instruction
bit 1
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
DS39599G-page 98
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
9.6
INTx Pin Interrupts
9.8
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge triggered: either rising if the
corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit, INTxIF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxIE. Flag bit,
INTxIF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt. All
external interrupts (INT0, INT1 and INT2) can wake-up
the processor from the power-managed modes if bit
INTxIE was set prior to going into power-managed
modes. If the global interrupt enable bit GIE is set, the
processor will branch to the interrupt vector following
wake-up.
Interrupt priority for INT1 and INT2 is determined by
the value contained in the Interrupt Priority bits,
INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>).
There is no priority bit associated with INT0. It is
always a high-priority interrupt source.
9.7
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (See Section 5.3
“Fast Register Stack”), the user may need to save the
WREG, STATUS and BSR registers on entry to the
Interrupt Service Routine. Depending on the user’s
application, other registers may also need to be saved.
Example 9-1 saves and restores the WREG, STATUS
and BSR registers during an Interrupt Service Routine.
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow
(FFh → 00h) in the TMR0 register will set flag bit
TMR0IF. In 16-bit mode, an overflow (FFFFh → 0000h)
in the TMR0H:TMR0L registers will set flag bit TMR0IF.
The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority
for Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP (INTCON2<2>). See
Section 11.0 “Timer0 Module” for further details on
the Timer0 module.
EXAMPLE 9-1:
MOVWF
MOVFF
MOVFF
;
; USER
;
MOVFF
MOVF
MOVFF
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
ISR CODE
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
© 2007 Microchip Technology Inc.
; Restore BSR
; Restore WREG
; Restore STATUS
DS39599G-page 99
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 100
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
10.0
I/O PORTS
10.1
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be
used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Data Latch)
The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are
driving.
A simplified model of a generic I/O port without the
interfaces to other peripherals is shown in Figure 10-1.
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
RD LAT
Data
Bus
D
Q
I/O pin(1)
WR LAT
or PORT
CK
Data Latch
D
Q
PORTA is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RA4/T0CKI/C1OUT pin. Pins RA6 and
RA7 are multiplexed with the main oscillator pins; they
are enabled as oscillator or I/O pins by the selection of
the main oscillator in Configuration Register 1H (see
Section 23.1 “Configuration Bits” for details). When
they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins,
RA3:RA0 and RA5, as A/D converter inputs is selected
by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). Pins RA0 through RA5
may also be used as comparator inputs or outputs by
setting the appropriate bits in the CMCON register.
Note:
WR TRIS
CK
TRIS Latch
Input
Buffer
RD TRIS
Q
D
ENEN
RD PORT
Note 1:
I/O pins have diode protection to VDD and VSS.
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input
and an open-drain output. All other PORTA pins have
TTL input levels and full CMOS output drivers.
The TRISA register controls the direction of the RA pins
even when they are being used as analog inputs. The
user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 10-1:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
© 2007 Microchip Technology Inc.
PORTA, TRISA and LATA
Registers
PORTA
;
;
;
LATA
;
;
;
0x0F
;
ADCON1 ;
0xCF
;
;
;
TRISA
;
;
INITIALIZING PORTA
Initialize PORTA by
clearing output
data latches
Alternate method
to clear output
data latches
Set all A/D pins as
digital I/O pins
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
DS39599G-page 101
PIC18F2220/2320/4220/4320
FIGURE 10-2:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 10-4:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
RD LATA
RD LATA
Data
Bus
WR LATA
or
PORTA
D
Data
Bus
WR LATA
or
PORTA
Q
VDD
CK
Q
P
Data Latch
WR TRISA
Analog
Input
Mode
D
Q
CK
Q
D
Q
CK
Q
I/O pin(1)
N
Data Latch
N
I/O pin(1)
WR TRISA
VSS
D
Q
CK
Q
VSS
Schmitt
Trigger
Input
Buffer
TRIS Latch
TRIS Latch
RD TRISA
RD TRISA
Q
TTL
Input
Buffer
D
Q
ENEN
EN
RD PORTA
RD PORTA
SS Input (RA5 only)
TMR0 Clock Input
To A/D Converter and LVD Modules
Note 1:
I/O pins have protection diodes to VDD and VSS.
FIGURE 10-3:
BLOCK DIAGRAM OF
RA6 PIN
Note 1:
I/O pins have protection diodes to VDD and VSS.
FIGURE 10-5:
RA6 Enable
Data
Bus
RA7 Enable
Data
Bus
RD LATA
RD LATA
WR LATA
or
PORTA
D
Q
CK
Q
VDD
WR LATA
or
PORTA
P
Data Latch
WR
TRISA
D
D
Q
CK
Q
To Oscillator
D
Q
CK
Q
VDD
P
Data Latch
N
I/O pin(1)
WR
TRISA
VSS
TRIS Latch
D
Q
CK
Q
N
I/O pin(1)
VSS
TRIS Latch
RD
TRISA
TTL
Input
Buffer
ECIO or
RCIO
Enable
Q
RD
TRISA
TTL
Input
Buffer
RA7
Enable
D
Q
EN
RD PORTA
Note 1:
Note 1:
I/O pins have protection diodes to VDD and VSS.
D
EN
RD PORTA
DS39599G-page 102
BLOCK DIAGRAM OF
RA7 PIN
I/O pins have protection diodes to VDD and VSS.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 10-1:
PORTA FUNCTIONS
Name
RA0/AN0
Bit#
Buffer
bit 0
TTL
Function
Input/output or analog input.
RA1/AN1
bit 1
TTL
Input/output or analog input.
RA2/AN2/VREF-/CVREF
bit 2
TTL
Input/output, analog input, VREF- or comparator VREF output.
RA3/AN3/VREF+
bit 3
TTL
Input/output, analog input or VREF+.
RA4/T0CKI/C1OUT
bit 4
ST
Input/output, external clock input for Timer0 or Comparator 1
output. Output is open-drain type.
RA5/AN4/SS/LVDIN/C2OUT
bit 5
TTL
Input/output, analog input, slave select input for Master
Synchronous Serial Port, Low-Voltage Detect input or
Comparator 2 output.
OSC2/CLKO/RA6
bit 6
TTL
OSC2, clock output or I/O pin.
OSC1/CLKI/RA7
bit 7
TTL
OSC1, clock input or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2:
Name
PORTA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
(1)
LATA6(1) LATA Data Latch Register
LATA
LATA7
TRISA
TRISA7(1) TRISA6(1) PORTA Data Direction Register
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
Value on
POR, BOR
xx0x 0000
uu0u 0000
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
PCFG0
--00 0000
--00 0000
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111
CVRCON
CVREN
CVROE
CVRR
—
CVR3
CVR2
CVR1
CVR0
000- 0000
Legend:
Note 1:
Value on
all other
Resets
0000 0111
000- 0000
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as ‘0’.
© 2007 Microchip Technology Inc.
DS39599G-page 103
PIC18F2220/2320/4220/4320
10.2
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 10-2:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
PORTB
;
;
;
LATB
;
;
;
0x07
;
ADCON1 ;
0xCF
;
;
;
TRISB
;
;
;
INITIALIZING PORTB
Initialize PORTB by
clearing output
data latches
Alternate method
to clear output
data latches
Set RB<4:0> as
digital I/O pins
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB3 can be configured by the Configuration bit,
CCP2MX, as the alternate peripheral pin for the CCP2
module (CCP2MX = 0).
FIGURE 10-6:
BLOCK DIAGRAM OF
RB7:RB5 PINS
VDD
RBPU(2)
Weak
P Pull-up
Data Latch
Data Bus
WR LATB
or PORTB
D
Q
I/O pin(1)
CK
TRIS Latch
D
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Note:
On a Power-on Reset, RB4:RB0 are configured as analog inputs by default and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
By programming the Configuration bit,
PBADEN (CONFIG3H<1>), RB4:RB0 will
alternatively be configured as digital inputs
on POR.
Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
DS39599G-page 104
WR TRISB
Q
TTL
Input
Buffer
CK
ST
Buffer
RD TRISB
RD LATB
Latch
Q
D
RD PORTB
EN
Set RBIF
Q
From other
RB7:RB5 and
RB4 pins
D
Q1
RD PORTB
EN
Q3
RB7:RB5 in Serial Programming Mode
Note 1:
2:
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 10-7:
BLOCK DIAGRAM OF
RB2:RB0 PINS
RBPU(2)
Weak
P Pull-up
D
D
WR LATB
or PORTB
I/O pin
I/O pin(1)
CK
WR TRISB
Q
CK
TRIS Latch
D
Q
Data Latch
D
Weak
P Pull-up
Data Latch
Data Bus
Q
(1)
WR LATB
or PORTB
BLOCK DIAGRAM OF
RB4 PIN
VDD
VDD
RBPU(2)
Analog Input Mode
Data Bus
FIGURE 10-8:
Q
WR TRISB
CK
TTL
Input
Buffer
TRIS Latch
TTL
Input
Buffer
CK
RD TRISB
RD TRISB
RD LATB
Latch
RD LATB
Q
Q
D
RD PORTB
D
EN
Set RBIF
ENEN
Q1
RD PORTB
INTx
Q
Schmitt Trigger
Buffer
RD PORTB
From RB7:RB5
To A/D Converter
Note 1:
2:
D
Q3
To A/D Converter
Note 1:
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2<7>).
FIGURE 10-9:
EN
2:
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
BLOCK DIAGRAM OF RB3/CCP2 PIN
VDD
Port/CCP2 Select
RBPU
Analog Input Mode
CCP2 Data Out
0
RD LATC
Data Bus
D
WR LATB
or PORTB
Q
Weak
P Pull-up
VDD
P
1
CK
Data Latch
D
WR TRISB
Q
TTL Input
Buffer
N
CK
RB3 pin(1)
VSS
TRIS Latch
RD TRISC
Q
D
ENEN
RD PORTB
CCP2 Input
Schmitt
Trigger
Analog Input Mode
To A/D Converter
Note 1:
I/O pins have diode protection to VDD and VSS.
© 2007 Microchip Technology Inc.
DS39599G-page 105
PIC18F2220/2320/4220/4320
TABLE 10-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
RB0/AN12/INT0
bit 0
TTL(1)/ST(2)
Input/output pin, analog input or external interrupt input 0.
Internal software programmable weak pull-up.
RB1/AN10/INT1
bit 1
TTL(1)/ST(2)
Input/output pin, analog input or external interrupt input 1.
Internal software programmable weak pull-up.
RB2/AN8/INT2
bit 2
TTL(1)/ST(2)
Input/output pin, analog input or external interrupt input 2.
Internal software programmable weak pull-up.
RB3/AN9/CCP2
bit 3
TTL(1)/ST(3)
Input/output pin or analog input. Capture 2 input/Compare 2 output/
PWM output when CCP2MX Configuration bit is set(4).
Internal software programmable weak pull-up.
RB4/AN11/KBI0
bit 4
TTL
RB5/KBI1/PGM
bit 5
TTL/ST(5)
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Low-voltage ICSP™ enable pin.
RB6/KBI2/PGC
bit 6
TTL/ST(5)
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming clock.
RB7/KBI3/PGD
bit 7
TTL/ST(5)
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming data.
Legend:
Note 1:
2:
3:
4:
5:
PORTB
Input/output pin (with interrupt-on-change) or analog input.
Internal software programmable weak pull-up.
TTL = TTL input, ST = Schmitt Trigger input
This buffer is a TTL input when configured as digital I/O.
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when configured as the CCP2 input.
A device Configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 10-4:
Name
Function
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
LATB
LATB Data Latch Register
TRISB
PORTB Data Direction Register
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
1111 1111
1111 1111
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
—
TMR0IP
—
RBIP
1111 -1-1
1111 -1-1
INTCON2
RBPU
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
11-0 0-00
11-0 0-00
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0000
--00 0000
Legend:
INTEDG0 INTEDG1 INTEDG2
x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
DS39599G-page 106
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
10.3
PORTC, TRISC and LATC
Registers
Note:
PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). The pins have Schmitt Trigger input buffers. RC1 is normally configured by Configuration bit,
CCP2MX (CONFIG3H<0>), as the default peripheral
pin of the CCP2 module (default/erased state,
CCP2MX = 1).
On a Power-on Reset, these pins are
configured as digital inputs.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3:
CLRF
PORTC
CLRF
LATC
MOVLW
0xCF
MOVWF
TRISC
INITIALIZING PORTC
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
FIGURE 10-10:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select(2)
VDD
Peripheral Data Out
RD LATC
Data Bus
WR LATC or
WR PORTC
0
D
Q
CK
Q
P
1
I/O pin(1)
Data Latch
WR TRISC
D
Q
CK
Q
N
TRIS Latch
VSS
RD TRISC
Peripheral Output
Enable(3)
Q
Schmitt
Trigger
D
EN
RD PORTC
Peripheral Data In
Note 1:
I/O pins have diode protection to VDD and VSS.
2:
Port/Peripheral Select signal selects between port data (output) and peripheral output.
3:
Peripheral Output Enable is only active if Peripheral Select is active.
© 2007 Microchip Technology Inc.
DS39599G-page 107
PIC18F2220/2320/4220/4320
TABLE 10-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit 0
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2
bit 1
ST
Input/output port pin, Timer1 oscillator input or Capture 2 input/
Compare 2 output/PWM output when CCP2MX Configuration bit is
disabled.
RC2/CCP1/P1A(1)
bit 2
ST
Input/output port pin, Capture 1 input/Compare 1 output/PWM1 output
or Enhanced PWM output A(1).
RC3/SCK/SCL
bit 3
ST
RC3 can also be the synchronous serial clock for both SPI and I2C™
modes.
RC4/SDI/SDA
bit 4
ST
RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode).
RC5/SDO
bit 5
ST
Input/output port pin or Master Synchronous Serial Port data output.
RC6/TX/CK
bit 6
ST
Input/output port pin, addressable USART asynchronous transmit or
addressable USART synchronous clock.
RC7/RX/DT
bit 7
ST
Input/output port pin, addressable USART asynchronous receive or
addressable USART synchronous data.
Legend: ST = Schmitt Trigger input
Note 1: Enhanced PWM output is available only on PIC18F4X20 devices.
TABLE 10-6:
Name
PORTC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
LATC
LATC Data Latch Register
xxxx xxxx
uuuu uuuu
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
Legend: x = unknown, u = unchanged
DS39599G-page 108
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
10.4
Note:
PORTD, TRISD and LATD
Registers
PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.6 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
PORTD is only available on PIC18F4X20
devices.
PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
Note:
EXAMPLE 10-4:
The Data Latch register (LATD) is also memory mapped.
Read-modify-write operations on the LATD register read
and write the latched output value for PORTD.
All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable
as an input or output.
Three of the PORTD pins are multiplexed with outputs
P1B, P1C and P1D of the Enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
Note:
When the enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
CLRF
PORTD
CLRF
LATD
MOVLW
0xCF
MOVWF
TRISD
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
:
;
;
Initialize PORTD by
clearing output
data latches
Alternate method
to clear output
data latches
Value used to
initialize data
direction
Set RD<3:0> as inputs
RD<5:4> as outputs
RD<7:6> as inputs
On a Power-on Reset, these pins are
configured as digital inputs.
FIGURE 10-11:
BLOCK DIAGRAM OF RD7:RD5 PINS
PORTD/CCP1 Select
CCP Data Out
PSPMODE
RD LATD
Data Bus
WR LATD
or PORTD
D
Q
0
CK
Q
1
VDD
P
Data Latch
WR TRISD
D
Q
CK
Q
I/O pin(1)
0
N
1
VSS
TRIS Latch
PSP Read
TTL Buffer
RD TRISD
1
Q
D
0
RD PORTD
PSP Write
Note 1:
0
ENEN
Schmitt Trigger
Input Buffer
1
I/O pins have diode protection to VDD and VSS.
© 2007 Microchip Technology Inc.
DS39599G-page 109
PIC18F2220/2320/4220/4320
FIGURE 10-12:
BLOCK DIAGRAM OF RD4:RD0 PINS
PORTD/CCP1 Select
PSPMODE
RD LATD
Data Bus
D
Q
CK
Q
WR LATD
or PORTD
VDD
P
Data Latch
D
Q
CK
Q
I/O pin(1)
WR TRISD
0
N
TRIS Latch
PSP Read
VSS
1
TTL Buffer
RD TRISD
1
Q
D
0
RD PORTD
PSP Write
Note 1:
TABLE 10-7:
ENEN
0
Schmitt Trigger
Input Buffer
1
I/O pins have diode protection to VDD and VSS.
PORTD FUNCTIONS
Name
Bit#
Buffer Type
bit 0
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 0.
RD1/PSP1
bit 1
(1)
ST/TTL
Input/output port pin or Parallel Slave Port bit 1.
RD2/PSP2
bit 2
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 2.
RD3/PSP3
bit 3
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 3.
RD4/PSP4
bit 4
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 4.
RD5/PSP5/P1B
bit 5
(1)
ST/TTL
Input/output port pin, Parallel Slave Port bit 5 or Enhanced PWM output P1B.
RD6/PSP6/P1C
bit 6
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 6 or Enhanced PWM output P1C.
bit 7
(1)
Input/output port pin, Parallel Slave Port bit 7 or Enhanced PWM output P1D.
RD0/PSP0
RD7/PSP7/P1D
ST/TTL
Function
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 10-8:
Name
PORTD
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
LATD
LATD Data Latch Register
xxxx xxxx
uuuu uuuu
TRISD
PORTD Data Direction Register
1111 1111
1111 1111
TRISE
CCP1CON
Legend:
IBF
OBF
IBOV
PSPMODE
P1M1
P1M0
DC1B1
DC1B0
—
PORTE Data Direction bits
CCP1M3 CCP1M2 CCP1M1 CCP1M0
0000 -111
0000 -111
0000 0000
0000 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
DS39599G-page 110
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
10.5
PORTE, TRISE and LATE
Registers
PORTE is available only in PIC18F4X20 devices.
PIC18F2X20 devices always will read back 0x00 from
PORTE.
For PIC18F4X20 devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/RD, RE1/AN6/WR and RE2/
AN7/CS) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers.
When selected as an analog input, these pins will read
as ‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
TRISE controls the direction of the RE pins even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note:
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE Configuration bit in Configuration Register 3H
(CONFIG3H<7>). When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RE3 also
functions as the programming voltage input during
programming.
Note:
EXAMPLE 10-5:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
PORTE
;
;
;
LATE
;
;
;
0x0A
;
ADCON1 ;
0x03
;
;
;
TRISC
;
;
;
FIGURE 10-13:
INITIALIZING PORTE
Initialize PORTE by
clearing output
data latches
Alternate method
to clear output
data latches
Configure A/D
for digital inputs
Value used to
initialize data
direction
Set RE<0> as inputs
RE<1> as outputs
RE<2> as inputs
BLOCK DIAGRAM OF
RE2:RE0 PINS
RD LATE
Data
Bus
WR LATE
or
PORTE
D
Q
I/O pin(1)
CK
Data Latch
D
WR TRISE
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRISE
Q
D
ENEN
RD PORTE
To Analog Converter
Note 1:
I/O pins have diode protection to VDD and VSS.
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
© 2007 Microchip Technology Inc.
DS39599G-page 111
PIC18F2220/2320/4220/4320
FIGURE 10-14:
BLOCK DIAGRAM OF
MCLR/VPP/RE3 PIN
MCLRE
Data Bus
MCLR/VPP/
RE3
RD TRISE
Schmitt
Trigger
RD LATE
Latch
Q
D
EN
RD PORTE
High-Voltage Detect
HV
Internal MCLR
Filter
Low-Level
MCLR Detect
REGISTER 10-1:
TRISE REGISTER
R-0
R-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General Purpose I/O mode
bit 3
Unimplemented: Read as ‘0’
bit 2
TRISE2: RE2 Direction Control bit
1 = Input
0 = Output
bit 1
TRISE1: RE1 Direction Control bit
1 = Input
0 = Output
bit 0
TRISE0: RE0 Direction Control bit
1 = Input
0 = Output
DS39599G-page 112
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 10-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
Function
RE0/AN5/RD
bit 0
ST/TTL(1)
Input/output port pin, analog input or read control input in Parallel Slave
Port mode.
For RD (PSP Control mode):
1 = PSP is Idle
0 = Read operation. Reads PORTD register (if chip selected).
RE1/AN6/WR
bit 1
ST/TTL(1)
Input/output port pin, analog input or write control input in Parallel
Slave Port mode.
For WR (PSP Control mode):
1 = PSP is Idle
0 = Write operation. Writes PORTD register (if chip selected).
RE2/AN7/CS
bit 2
ST/TTL(1)
Input/output port pin, analog input or chip select control input in Parallel
Slave Port mode.
For CS (PSP Control mode):
1 = PSP is Idle
0 = External device is selected
MCLR/VPP/RE3(2)
bit 3
ST
Input only port pin or programming voltage input (if MCLR is disabled);
Master Clear input or programming voltage input (if MCLR is enabled).
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
2: The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear functionality is disabled (CONFIG3H<7>=0).
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RE2
RE1
RE0
---- qxxx
---- quuu
---- -xxx
---- -uuu
0000 -111
0000 -111
--00 0000
--00 0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PORTE
—
—
—
—
RE3(1)
LATE
—
—
—
—
—
LATE Data Latch Register
TRISE
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction bits
—
—
VCFG1
VCFG0
PCFG3
ADCON1
Legend:
Note 1:
PCFG2
PCFG1
PCFG0
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used by PORTE.
The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear functionality is disabled
(CONFIG3H<7>=0).
© 2007 Microchip Technology Inc.
DS39599G-page 113
PIC18F2220/2320/4220/4320
10.6
Note:
Parallel Slave Port
The Parallel Slave Port is only available on
PIC18F4X20 devices.
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is controlled by the 4 upper bits of the TRISE register
(Register 10-1). Setting control bit, PSPMODE
(TRISE<4>), enables PSP operation, as long as the
Enhanced CCP module is not operating in dual output
or quad output PWM mode. In Slave mode, the port is
asynchronously readable and writable by the external
world.
The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the control bit, PSPMODE, enables the PORTE I/O
pins to become control inputs for the microprocessor
port. When set, port pin RE0 is the RD input, RE1 is the
WR input and RE2 is the CS (Chip Select) input. For
this functionality, the corresponding data direction bits
of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits
PFCG3:PFCG0 (ADCON1<3:0>) must also be set to
‘1010’.
The timing for the control signals in Write and Read
modes is shown in Figure 10-16 and Figure 10-17,
respectively.
FIGURE 10-15:
One bit of PORTD
Data Bus
WR LATD
or
WR PORTD
Q
RDx pin
CK
Data Latch
RD PORTD
TTL
D
ENEN
RD LATD
Set Interrupt Flag
PSPIF (PIR1<7>)
PORTE Pins
Read
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
DS39599G-page 114
D
Q
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
When either the CS or RD lines are detected high, the
PORTD pins return to the input state and the PSPIF bit is
set. User applications should wait for PSPIF to be set
before servicing the PSP; when this happens, the IBF and
OBF bits can be polled and the appropriate action taken.
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
TTL
RD
Chip Select
TTL
CS
Write
Note:
TTL
WR
I/O pins have diode protection to VDD and VSS.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 10-16:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 10-17:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
PORTD
Port Data Latch when written; Port pins when read
xxxx xxxx
uuuu uuuu
LATD
LATD Data Latch bits
xxxx xxxx
uuuu uuuu
TRISD
PORTD Data Direction bits
PORTE
—
—
—
—
RE3
RE2
RE1
RE0
1111 1111
1111 1111
---- qxxx
---- quuu
LATE
—
—
—
—
—
LATE Data Latch bits
---- -xxx
---- -uuu
TRISE
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction bits
0000 -111
0000 -111
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IF
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
1111 1111
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0000
--00 0000
ADCON1
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
© 2007 Microchip Technology Inc.
DS39599G-page 115
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 116
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
11.0
TIMER0 MODULE
Figure 11-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
The Timer0 module has the following features:
• Software selectable as an 8-bit or 16-bit
timer/counter
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 11-1:
The T0CON register (Register 11-1) is a readable and
writable register that controls all the aspects of Timer0,
including the prescale selection.
T0CON: TIMER0 CONTROL REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6
T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0
T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value
© 2007 Microchip Technology Inc.
DS39599G-page 117
PIC18F2220/2320/4220/4320
FIGURE 11-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
RA4/T0CKI/C1OUT
pin
FOSC/4
0
0
1
Programmable
Prescaler
1
8
Sync with
Internal
Clocks
TMR0
(2 TCY delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
RA4/T0CKI/C1OUT FOSC/4
pin
0
0
1
T0SE
Programmable
Prescaler
1
Sync with
Internal
Clocks
TMR0L
TMR0
High Byte
8
(2 TCY delay)
3
Set Interrupt
Flag bit TMR0IF
on Overflow
Read TMR0L
T0PS2, T0PS1, T0PS0
T0CS
PSA
Write TMR0L
8
8
TMR0H
8
Data Bus<7:0>
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
DS39599G-page 118
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
11.1
Timer0 Operation
11.2.1
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
11.3
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
11.4
Prescaler
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4,..., 1:256 are
selectable.
A write to the high byte of Timer0 must also take place
through the TMR0H Buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to be
updated at once.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x....etc.) will clear the prescaler
count.
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
TABLE 11-1:
Name
16-Bit Mode Timer Reads and
Writes
TMR0H is not the high byte of the timer/counter in
16-bit mode but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0, without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not readable or writable.
Note:
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF bit. The interrupt can be masked by clearing
the TMR0IE bit. The TMR0IF bit must be cleared in
software by the Timer0 module Interrupt Service
Routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from Sleep
mode, since the timer requires clock cycles, even when
T0CS is set.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment, either on every
rising or falling edge of pin RA4/T0CKI/C1OUT. The
incrementing edge is determined by the Timer0 Source
Edge Select bit (T0SE). Clearing the T0SE bit selects
the rising edge.
11.2
SWITCHING PRESCALER
ASSIGNMENT
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
uuuu uuuu
TMR0L
Timer0 Low Byte Register
xxxx xxxx
TMR0H
Timer0 High Byte Register
0000 0000
0000 0000
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
1111 1111
1111 1111
1111 1111
1111 1111
TRISA
Legend:
Note 1:
RA7
(1)
RA6
(1)
PORTA Data Direction Register
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H.
© 2007 Microchip Technology Inc.
DS39599G-page 119
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 120
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
12.0
TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter (two 8-bit registers: TMR1H
and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module Special Event Trigger
• Status of system clock operation
Figure 12-1 is a simplified block diagram of the Timer1
module.
REGISTER 12-1:
Register 12-1 details the Timer1 Control register. This
register controls the operating mode of the Timer1
module and contains the Timer1 Oscillator Enable bit
(T1OSCEN). Timer1 can be enabled or disabled by
setting or clearing control bit, TMR1ON (T1CON<0>).
The Timer1 oscillator can be used as a secondary clock
source in power-managed modes. When the T1RUN bit
is set, the Timer1 oscillator is providing the system clock.
If the Fail-Safe Clock Monitor is enabled and the Timer1
oscillator fails while providing the system clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
T1CON: TIMER1 CONTROL REGISTER
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T1RUN
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6
T1RUN: Timer1 System Clock Status bit
1 = Device clock is derived from Timer1 oscillator
0 = Device clock is derived from another source
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1 (External Clock):
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0 (Internal Clock):
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from RC0/T1OSO/T13CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
© 2007 Microchip Technology Inc.
DS39599G-page 121
PIC18F2220/2320/4220/4320
12.1
Timer1 Operation
When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. The TRISC1:TRISC0 values are
ignored and the pins read as ‘0’.
The operating mode is determined by the Clock Select
bit, TMR1CS (T1CON<1>).
FIGURE 12-1:
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
TMR1
TMR1H
1
TMR1ON
On/Off
T1OSC
T1CKI/T1OSO
T1OSCEN
Enable
Oscillator(1)
T1OSI
Synchronized
Clock Input
0
CLR
TMR1L
T1SYNC
1
Synchronize
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
det
0
2
T1CKPS1:T1CKPS0
Peripheral Clocks
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
CCP Special Event Trigger
Read TMR1L
TMR1IF
Overflow
Interrupt
Flag bit
TMR1
8
Timer 1
High Byte
CLR
TMR1L
1
TMR1ON
on/off
T1OSC
T1CKI/T1OSO
T1OSI
Synchronized
Clock Input
0
T1SYNC
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
Peripheral Clocks
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39599G-page 122
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
12.2
Timer1 Oscillator
12.3
A crystal oscillator circuit is built-in between pins,
T1OSI (input) and T1OSO (amplifier output). It is
enabled by setting control bit, T1OSCEN (T1CON<3>).
The oscillator is a low-power oscillator rated for 32 kHz
crystals. It will continue to run during all powermanaged modes. The circuit for a typical LP oscillator
is shown in Figure 12-3. Table 12-1 shows the
capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3:
EXTERNAL COMPONENTS
FOR THE TIMER1 LP
OSCILLATOR
C1
22 pF
PIC18FXXXX
Timer1 Oscillator Layout
Considerations
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in output compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 12-4:
T1OSI
XTAL
32.768 kHz
OSCILLATOR CIRCUIT
WITH GROUNDED GUARD
RING
VDD
T1OSO
VSS
C2
22 pF
Note:
TABLE 12-1:
Osc Type
LP
OSC1
See the Notes with Table 12-1 for additional
information about capacitor selection.
OSC2
RC0
CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR(2,3,4)
Freq
32 kHz
C1
22
pF(1)
RC1
C2
22 pF(1)
RC2
Note: Not drawn to scale.
Note 1: Microchip suggests this value as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
4: Capacitor values are for design guidance
only.
© 2007 Microchip Technology Inc.
DS39599G-page 123
PIC18F2220/2320/4220/4320
12.4
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing Timer1 interrupt enable bit, TMR1IE
(PIE1<0>).
12.5
Resetting Timer1 Using a CCP
Trigger Output
If the CCP module is configured in Compare mode to
generate a “Special Event Trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion if the A/D module is enabled (see
Section 15.4.4 “Special Event Trigger” for more
information).
Note:
The Special Event Triggers from the CCP1
module will not set interrupt flag bit,
TMR1IF (PIR1<0>).
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
12.6
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is valid
due to a rollover between reads.
DS39599G-page 124
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place
through the Timer1 High Byte Buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
12.7
Using Timer1 as a Real-Time
Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.2 “Timer1 Oscillator”
above), gives users the option to include RTC functionality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1 register pair to overflow, triggers the interrupt and calls the
routine, which increments the seconds counter by one;
additional counters for minutes and hours are
incremented as the previous counter overflow.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to preload it; the simplest method is to set the MSbit of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
MOVLW
MOVWF
CLRF
CLRF
MOVLW
MOVWF
BSF
RETURN
0x80
TMR1H
TMR1L
b’00001111’
T1OSC
secs
mins
.12
hours
PIE1, TMR1IE
BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
MOVLW
MOVWF
RETURN
TMR1H,7
PIR1,TMR1IF
secs,F
.59
secs
; Preload TMR1 register pair
; for 1 second overflow
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
; Enable Timer1 interrupt
RTCisr
TABLE 12-2:
Name
secs
mins,F
.59
mins
mins
hours,F
.23
hours
;
;
;
;
Preload for 1 sec overflow
Clear interrupt flag
Increment seconds
60 seconds elapsed?
;
;
;
;
No, done
Clear seconds
Increment minutes
60 minutes elapsed?
;
;
;
;
No, done
clear minutes
Increment hours
24 hours elapsed?
; No, done
; Reset hours to 1
.01
hours
; Done
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
TMR1L
Timer1 Low Byte Register
xxxx xxxx uuuu uuuu
TMR1H
Timer1 High Byte Register
xxxx xxxx uuuu uuuu
T1CON
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
DS39599G-page 125
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 126
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
13.0
TIMER2 MODULE
13.1
The Timer2 module timer has the following features:
•
•
•
•
•
•
•
8-bit Timer register (TMR2)
8-bit Period register (PR2)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match with PR2
MSSP module optional use of TMR2 output to
generate clock shift
Timer2 has a control register shown in Register 13-1.
TMR2 can be shut-off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. Register 13-1 shows the Timer2 Control register. The prescaler and postscaler selection of Timer2
are controlled by this register.
REGISTER 13-1:
Timer2 Operation
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits,
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
T2CON: TIMER2 CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
© 2007 Microchip Technology Inc.
x = Bit is unknown
DS39599G-page 127
PIC18F2220/2320/4220/4320
13.2
Timer2 Interrupt
13.3
The Timer2 module has an 8-bit Period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
FIGURE 13-1:
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate the shift clock.
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
TMR2
Output(1)
Prescaler
1:1, 1:4, 1:16
FOSC/4
TMR2
2
Comparator
Reset
EQ
Postscaler
1:1 to 1:16
T2CKPS1:T2CKPS0
4
PR2
TOUTPS3:TOUTPS0
Note 1: TMR2 register output can be software selected by the MSSP module as a baud clock.
TABLE 13-1:
Name
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
TMR2
T2CON
PR2
OSCCON
PSPIP
Timer2 Module Register
—
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register
IDLEN
IRCF2
1111 1111 1111 1111
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
0000 qq00 0000 qq00
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1:
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.
DS39599G-page 128
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
14.0
TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
• 16-bit timer/counter (two 8-bit registers: TMR3H
and TMR3L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module trigger
REGISTER 14-1:
Figure 14-1 is a simplified block diagram of the Timer3
module.
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN) which can be a clock source for
Timer3.
T3CON: TIMER3 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6, 3
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the capture/compare clock source for both CCP modules
01 = Timer3 is the capture/compare clock source for CCP2;
Timer1 is the capture/compare clock source for CCP1
00 = Timer1 is the capture/compare clock source for both CCP modules
bit 5-4
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)
bit 0
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
© 2007 Microchip Technology Inc.
DS39599G-page 129
PIC18F2220/2320/4220/4320
14.1
Timer3 Operation
When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator if enabled.
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC1:TRISC0 value
is ignored and the pins are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
FIGURE 14-1:
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
TIMER3 BLOCK DIAGRAM
CCP Special Event Trigger
T3CCPx
TMR3IF
Overflow
Interrupt
Flag bit
TMR3H
Synchronized
Clock Input
0
CLR
TMR3L
1
TMR3ON
On/Off
T3SYNC
T1OSC
T1OSO/
T1CKI
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
T1OSI
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
Peripheral Clocks
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
Set TMR3IF Flag bit
on Overflow
8
TMR3
Timer3
High Byte
TMR3L
To Timer1 Clock Input
T1OSO/
T1CKI
T1OSI
CCP Special Event Trigger
T3CCPx
Synchronized
0
Clock Input
T1OSC
CLR
1
TMR3ON
On/Off
T3SYNC
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
Peripheral Clocks
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39599G-page 130
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
14.2
Timer1 Oscillator
14.4
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a lowpower oscillator rated for 32 kHz crystals. See
Section 12.2 “Timer1 Oscillator” for further details.
14.3
Timer3 Interrupt
TABLE 14-1:
If the CCP module is configured in Compare mode
to generate
a
“Special
Event
Trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3. See Section 15.4.4 “Special Event Trigger”
for more information.
Note:
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
Resetting Timer3 Using a CCP
Trigger Output
The Special Event Triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
Timer3 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this Reset operation may not work. In the event that a
write to Timer3 coincides with a Special Event Trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR2
OSCIF
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
00-0 0000 00-0 0000
PIE2
OSCIE
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
00-0 0000 00-0 0000
IPR2
OSCIP
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
11-1 1111 11-1 1111
TMR3L
Timer3 Low Byte Register
xxxx xxxx uuuu uuuu
TMR3H
Timer3 High Byte Register
xxxx xxxx uuuu uuuu
T1CON
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN
T1SYNC
TMR1CS TMR1ON 0000 0000 u0uu uuuu
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
T3SYNC
TMR3CS TMR3ON 0000 0000 uuuu uuuu
T3CCP1
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
© 2007 Microchip Technology Inc.
DS39599G-page 131
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 132
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
15.0
CAPTURE/COMPARE/PWM
(CCP) MODULES
Note:
The standard CCP (Capture/Compare/PWM) module
contains a 16-bit register that can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register. Table 15-1 shows
the timer resources required for each of the CCP
module modes.
Please see Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module” for a discussion of the enhanced
PWM capabilities of the CCP1 module.
The operation of CCP1 is identical to that of CCP2, with
the exception of the Special Event Trigger. Therefore,
operation of a CCP module is described with respect to
CCP1 except where noted. Table 15-2 shows the
interaction of the CCP modules.
REGISTER 15-1:
In 28-pin devices, both CCP1 and CCP2
function as standard CCP modules. In
40-pin devices, CCP1 is implemented as
an Enhanced CCP module, offering additional capabilities in PWM mode. Capture
and Compare modes are identical in all
modules regardless of the device.
CCPxCON: CCPx CONTROL REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DCxB1:DCxB0: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs of the duty
cycle are found in CCPR1L.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode: toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode: every falling edge
0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit
is set)
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit
is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
operates as a port pin for input and output)
1011 = Compare mode: trigger special event (CCPxIF bit is set)
11xx = PWM mode
© 2007 Microchip Technology Inc.
DS39599G-page 133
PIC18F2220/2320/4220/4320
15.1
CCP1 Module
15.2
CCP2 Module
Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Capture/Compare/PWM Register 2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
TABLE 15-1:
CCP2 functions identically to CCP1 except for the
enhanced PWM modes offered by CCP2
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
TABLE 15-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
TMR1 or TMR3 time base. Time base can be different for each CCP.
Capture
Compare
The compare could be configured for the Special Event Trigger which clears either TMR1
or TMR3 depending upon which time base is used.
Compare
Compare
The compare(s) could be configured for the Special Event Trigger which clears TMR1 or
TMR3 depending upon which time base is used.
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
Capture
None.
PWM
Compare
None.
DS39599G-page 134
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
15.3
Capture Mode
15.3.3
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on pin RC2/CCP1/P1A. An event is defined as
one of the following:
•
•
•
•
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
15.3.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1/P1A pin should be
configured as an input by setting the TRISC<2> bit.
Note:
15.3.2
If the RC2/CCP1/P1A is configured as an
output, a write to the port can cause a
capture condition.
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(either Timer1 and/or Timer3) must be running in Timer
mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not
work. The timer to be used with each CCP module is
selected in the T3CON register.
FIGURE 15-1:
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
15.3.4
The event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<2>), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
SOFTWARE INTERRUPT
CCP PRESCALER
There are four prescaler settings specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
MOVLW
CCP1CON, F
NEW_CAPT_PS
MOVWF
CCP1CON
;
;
;
;
;
;
Turn CCP module off
Load WREG with the
new prescaler mode
value and CCP ON
Load CCP1CON with
this value
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
Set Flag bit CCP1IF
T3CCP2
Prescaler
÷ 1, 4, 16
CCP1 pin
TMR3
Enable
CCPR1H
and
Edge Detect
T3CCP2
TMR3L
CCPR1L
TMR1
Enable
TMR1H
TMR1L
TMR3H
TMR3L
CCP1CON<3:0>
Q’s
Set Flag bit CCP2IF
T3CCP1
T3CCP2
TMR3
Enable
Prescaler
÷ 1, 4, 16
CCP2 pin
CCPR2H
and
Edge Detect
Q’s
CCPR2L
TMR1
Enable
T3CCP2
T3CCP1
TMR1H
TMR1L
CCP2CON<3:0>
© 2007 Microchip Technology Inc.
DS39599G-page 135
PIC18F2220/2320/4220/4320
15.4
Compare Mode
15.4.2
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the
TMR1 register pair value, or the TMR3 register pair
value. When a match occurs, the RC2/CCP1/P1A
(RC1/T1OSI/CCP2) pin:
•
•
•
•
15.4.3
Is driven high
Is driven low
Toggles output (high-to-low or low-to-high)
Remains unchanged (interrupt only)
15.4.4
The Special Event Trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable Period register for
Timer1.
CCP PIN CONFIGURATION
The special trigger output of CCP2 resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will start an A/D conversion if the
A/D module is enabled.
Clearing the CCP1CON register will force
the RC2/CCP1/P1A compare output latch
to the default low level. This is not the
PORTC I/O data latch.
Note:
FIGURE 15-2:
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
Note:
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit, CCP1IF (CCP2IF), is set.
15.4.1
TIMER1/TIMER3 MODE SELECTION
The Special Event Trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1 or Timer3 but not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
CCPR1H CCPR1L
Q
RC2/CCP1/P1A
pin
S
R
TRISC<2>
Output Enable
Output
Logic
Comparator
Match
CCP1CON<3:0>
Mode Select
0
T3CCP2
TMR1H
1
TMR1L
TMR3H
TMR3L
Special Event Trigger
Set Flag bit CCP2IF
Q
RC1/T1OSI/CCP2
pin
S
R
TRISC<1>
Output Enable
DS39599G-page 136
Output
Logic
CCP2CON<3:0>
Mode Select
Match
T3CCP1
T3CCP2
0
1
Comparator
CCPR2H CCPR2L
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 15-3:
Name
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
all other
Resets
Bit 0
Value on
POR, BOR
RBIF
0000 000x 0000 000u
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP 1111 1111 1111 1111
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON
RD16
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
CCP1CON
—
—
DC1B1
DC1B0
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
CCP2CON
—
—
DC2B1
DC2B0
CCP1M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M3
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
PIR2
OSCFIF
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
PIE2
OSCFIE
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE 00-0 0000 00-0 0000
OSCFIP
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP 11-1 1111 11-1 1111
IPR2
00-0 0000 00-0 0000
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
T3CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
T3CCP1
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note 1: These bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
DS39599G-page 137
PIC18F2220/2320/4220/4320
15.5
PWM Mode
15.5.1
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.5.3
“Setup for PWM Operation”.
FIGURE 15-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
EQUATION 15-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
Note:
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
15.5.2
CCPR1H (Slave)
R
Comparator
Q
RC2/CCP1/P1A
TMR2
(Note 1)
S
TRISC<2>
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note: 8-bit timer is concatenated with 2-bit internal Q clock or
2 bits of the prescaler to create 10-bit time base.
A PWM output (Figure 15-4) has a time base (period)
and a time that the output is high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-4:
PWM PERIOD
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation.
EQUATION 15-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
PWM OUTPUT
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS39599G-page 138
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
15.5.3
EQUATION 15-3:
4.
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
log ⎛ FOSC ⎞
⎝ FPWM ⎠
bits
PWM Resolution (max) =
log(2)
Note:
5.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and the CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
TRISC<2> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TABLE 15-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 15-5:
Name
SETUP FOR PWM OPERATION
2.44 kHz
9.77 kHz
39.06 kHz
156.25 kHz
312.50 kHz
416.67 kHz
16
4
1
1
1
1
FFh
FFh
FFh
3Fh
1Fh
17h
10
10
10
8
7
6.58
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0000 000x 0000 000u
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TMR2
Timer2 Module Register
0000 0000 0000 0000
PR2
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
CCP1CON
—
—
DC1B1
DC1B0
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3
CCP1M2
CCP1M1
CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
CCP2M0 --00 0000 --00 0000
SCS0
0000 qq00 0000 qq00
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
DS39599G-page 139
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 140
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
16.0
ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
Note:
The ECCP (Enhanced Capture/ Compare/
PWM) module is only available on
PIC18F4X20 devices.
In 40 and 44-pin devices, the CCP1 module is
implemented as a standard CCP module with
enhanced PWM capabilities. Operation of the Capture,
Compare and standard single output PWM modes is
described in Section 15.0 “Capture/Compare/PWM
(CCP) Modules”. Discussion in that section relating to
PWM frequency and duty cycle also apply to the
enhanced PWM mode.
REGISTER 16-1:
The ECCP module differs from the CCP with the addition of an enhanced PWM mode which allows for 2 or
4 output channels, user-selectable polarity, dead band
control and automatic shutdown and restart. These
features are discussed in detail in Section 16.4
“Enhanced PWM Mode”.
The control register for CCP1 is shown in Register 16-1.
It differs from the CCP1CON register of PIC18F2X20
devices in that the two Most Significant bits are
implemented to control enhanced PWM functionality.
CCP1CON: ECCP CONTROL REGISTER (40/44-PIN DEVICES)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
P1M1:P1M0: PWM Output Configuration bits
If CCP1M3:CCP1M2 = 00, 01, 10 (Capture, Compare or disabled):
xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins
If CCP1M3:CCP1M2 = 11 (PWM modes):
00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
DC1B1:DC1B0: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found
in CCPR1L.
© 2007 Microchip Technology Inc.
DS39599G-page 141
PIC18F2220/2320/4220/4320
REGISTER 16-1:
bit 3-0
CCP1CON: ECCP CONTROL REGISTER (40/44-PIN DEVICES) (CONTINUED)
CCP1M3:CCP1M0: ECCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0011 = Unused (reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin operates
as a port pin for input and output)
1011 = Compare mode, trigger special event (CCP1IF bit is set, ECCP resets TMR1or TMR2 and
starts an A/D conversion if the A/D module is enabled)
1100 = PWM mode, P1A, P1C active-high, P1B, P1D active-high
1101 = PWM mode, P1A, P1C active-high, P1B, P1D active-low
1110 = PWM mode, P1A, P1C active-low, P1B, P1D active-high
1111 = PWM mode, P1A, P1C active-low, P1B, P1D active-low
In addition to the expanded functions of the CCP1CON
register, the ECCP module has two additional registers
associated with enhanced PWM operation and
Auto-Shutdown features:
• PWM1CON
• ECCPAS
All other registers associated with the ECCP module are
identical to those used for the CCP1 module in
PIC18F2X20 devices, including register and individual bit
names. Likewise, the timer assignments and interactions
between the two CCP modules are identical, regardless
of whether CCP1 is a standard or enhanced module.
16.1
ECCP Outputs
16.2
The Capture and Compare modes of the ECCP module
are identical in operation to that of CCP1, as discussed
in Section 15.3 “Capture Mode” and Section 15.4
“Compare Mode”. No changes are required when
moving between these modules on PIC18F2X20 and
PIC18F4X20 devices.
16.3
Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode, as described in Section 15.4
“Compare Mode”.
Note:
The Enhanced CCP module may have up to four outputs
depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with
I/O pins on PORTC and PORTD. The pin assignments
are summarized in Table 16-1.
To configure I/O pins as PWM outputs, the proper PWM
mode must be selected by setting the P1Mx and
CCP1Mx bits (CCP1CON<7:6> and <3:0>, respectively). The appropriate TRISC and TRISD direction
bits for the port pins must also be set as outputs.
TABLE 16-1:
Capture and Compare Modes
When setting up single output PWM operations, users are free to use either of the processes described in Section 15.5.3 “Setup
for PWM Operation” or Section 16.4.7
“Setup for PWM Operation”. The latter is
more generic but will work for either single
or multi output PWM.
PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
ECCP Mode
CCP1CON Configuration
RC2
RD5
RD6
RD7
Compatible CCP
00xx11xx
CCP1
RD5/PSP5
RD6/PSP6
RD7/PSP7
Dual PWM
10xx11xx
P1A
P1B
RD6/PSP6
RD6/PSP6
Quad PWM
x1xx11xx
P1A
P1B
P1C
P1D
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
Note 1: TRIS register values must be configured appropriately.
2: With ECCP in Dual or Quad PWM mode, the PSP input/output control of PORTD is overridden by P1B,
P1C and P1D.
DS39599G-page 142
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
16.4
Enhanced PWM Mode
waveforms do not exactly match the standard PWM
waveforms but are instead offset by one full instruction
cycle (4 TOSC).
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applications. The module is an upwardly compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the P1M1:P1M0 and
CCP1M3:CCP1M0 bits of the CCP1CON register
(CCP1CON<7:6> and CCP1CON<3:0>, respectively).
As before, the user must manually configure the
appropriate TRISD bits for output.
16.4.1
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
•
•
•
•
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is the
PWM Delay register, ECCP1DEL, which is loaded at
either the duty cycle boundary or the boundary period
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets instead of
starting immediately. This means that enhanced PWM
FIGURE 16-1:
PWM OUTPUT CONFIGURATIONS
Single Output
Half-Bridge Output
Full-Bridge Output, Forward mode
Full-Bridge Output, Reverse mode
The Single Output mode is the Standard PWM mode
discussed in Section 15.5 “PWM Mode”. The HalfBridge and Full-Bridge Output modes are covered in
detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2.
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
Duty Cycle Registers
CCP1CON<5:4>
CCP1M<3:0>
4
P1M1<1:0>
2
CCPR1L
CCP1/P1A
RC2/CCP1/P1A
TRISD<2>
CCPR1H (Slave)
P1B
R
Comparator
Q
Output
Controller
RD5/PSP5/P1B
TRISD<5>
RD6/PSP6/P1C
P1C
TMR2
Comparator
PR2
Note:
(Note 1)
TRISD<6>
S
P1D
Clear Timer,
set CCP1 pin and
latch D.C.
RD7/PSP7/P1D
TRISD<7>
PWM1CON
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock or 2 bits of the prescaler to create the 10-bit time base.
© 2007 Microchip Technology Inc.
DS39599G-page 143
PIC18F2220/2320/4220/4320
FIGURE 16-2:
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
SIGNAL
CCP1CON
<7:6>
00
0
PR2+1
Duty
Cycle
Period
(Single Output)
P1A Modulated
Delay(1)
Delay(1)
P1A Modulated
10
(Half-Bridge)
P1B Modulated
P1A Active
01
P1B Inactive
(Full-Bridge,
Forward)
P1C Inactive
P1D Modulated
P1A Inactive
11
P1B Modulated
(Full-Bridge,
Reverse)
P1C Active
P1D Inactive
FIGURE 16-3:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
CCP1CON
<7:6>
00
(Single Output)
SIGNAL
0
Period
P1A Modulated
P1A Modulated
10
(Half-Bridge)
PR2+1
Duty
Cycle
P1B Modulated
Delay(1)
Delay(1)
P1A Active
01
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
11
(Full-Bridge,
Reverse)
P1B Modulated
P1C Active
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead band delay is programmed using the PWM1CON register (see Section 16.4.4 “Programmable Dead-Band Delay”).
DS39599G-page 144
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
16.4.2
HALF-BRIDGE MODE
FIGURE 16-4:
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal is output on the RC2/CCP1/P1A pin, while the complementary PWM output signal is output on the RD5/
PSP5/P1B pin (Figure 16-4). This mode can be used
for half-bridge applications, as shown in Figure 16-5, or
for full-bridge applications where four power switches
are being modulated with two PWM signals.
HALF-BRIDGE PWM
OUTPUT
Period
Period
Duty Cycle
P1A(2)
td
td
P1B(2)
In Half-Bridge Output mode, the programmable dead
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.4.4
“Programmable Dead-Band Delay” for more details
of the dead band delay operations.
(1)
(1)
(1)
td = Dead Band Delay
Note 1: At this time, the TMR2 register is equal to the PR2
register.
2: Output signals are shown as active-high.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F4220/4320
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F4220/4320
FET
Driver
FET
Driver
P1A
FET
Driver
Load
FET
Driver
P1B
V-
© 2007 Microchip Technology Inc.
DS39599G-page 145
PIC18F2220/2320/4220/4320
16.4.3
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In
the Forward mode, pin RC2/CCP1/P1A is continuously
active and pin RD7/PSP7/P1D is modulated. In the
Reverse mode, RD6/PSP6/P1C pin is continuously
active and RD5/PSP5/P1B pin is modulated. These are
illustrated in Figure 16-6.
FIGURE 16-6:
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTC<2> and PORTD<5:7> data latches. The
TRISC<2> and TRISD<5:7> bits must be cleared to
make the P1A, P1B, P1C and P1D pins output.
FULL-BRIDGE PWM OUTPUT
FORWARD MODE
Period
P1A(2)
Duty Cycle
P1B(2)
P1C(2)
P1D(2)
(1)
(1)
REVERSE MODE
Period
Duty Cycle
P1A
(2)
P1B(2)
P1C(2)
P1D(2)
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
DS39599G-page 146
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 16-7:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC18F4220/4320
FET
Driver
QC
QA
FET
Driver
P1A
Load
P1B
FET
Driver
P1C
FET
Driver
QD
QB
VP1D
16.4.3.1
Direction Change in Full-Bridge
Mode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows users to control the forward/
reverse direction. When the application firmware
changes this direction control bit, the module will
assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive
state, while the unmodulated outputs (P1A and P1C) are
switched to drive in the opposite direction. This occurs in
a time interval of 4 TOSC * (Timer2 Prescale Value)
before the next PWM period begins. The Timer2
prescaler will be either 1, 4 or 16, depending on the
value of the T2CKPS bit (T2CON<1:0>). During the
interval from the switch of the unmodulated outputs to
the beginning of the next period, the modulated outputs
(P1B and P1D) remain inactive. This relationship is
shown in Figure 16-8.
Figure 16-9 shows an example where the PWM direction changes from forward to reverse at a near 100%
duty cycle. At time t1, the outputs P1A and P1D
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current may flow through power devices QC and QD
(see Figure 16-7) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1.
2.
Reduce PWM for a PWM period before
changing directions.
Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any dead band delay. In general, since only one output is modulated at all times,
dead band delay is not required. However, there is a
situation where a dead band delay might be required.
This situation occurs when both of the following
conditions are true:
1.
2.
The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
© 2007 Microchip Technology Inc.
DS39599G-page 147
PIC18F2220/2320/4220/4320
FIGURE 16-8:
PWM DIRECTION CHANGE
Period(1)
SIGNAL
Period
P1A (Active High)
P1B (Active High)
DC
P1C (Active High)
(Note 2)
P1D (Active High)
DC
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of
4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are
inactive at this time.
FIGURE 16-9:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE(1)
Forward Period
t1
Reverse Period
P1A
P1B
DC
P1C
P1D
DC
ton(2)
External Switch C
toff(3)
External Switch D
Potential
Shoot-Through
Current
t = toff – ton(2,3)
Note 1: All signals are shown as active-high.
2: ton is the turn-on delay of power switch QC and its driver.
3: toff is the turn-off delay of power switch QD and its driver.
DS39599G-page 148
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
16.4.4
PROGRAMMABLE DEAD-BAND
DELAY
In half-bridge applications, where all power switches
are modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shootthrough current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In the Half-Bridge Output mode, a digitally programmable dead band delay is available to avoid shootthrough current from destroying the bridge power
switches. The delay occurs at the signal transition from
the non-active state to the active state. See Figure 16-4
for illustration. The lower seven bits of the PWM1CON
register (Register 16-2) set the delay period in terms of
microcontroller instruction cycles (TCY or 4 TOSC).
16.4.5
ENHANCED PWM
AUTO-SHUTDOWN
When the ECCP is programmed for any of the
enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immediately places the enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
REGISTER 16-2:
A shutdown event can be caused by either of the two
comparator modules or the INT0 pin (or any combination of these three sources). The comparators may be
used to monitor a voltage input proportional to a current
being monitored in the bridge circuit. If the voltage
exceeds a threshold, the comparator switches state
and triggers a shutdown. Alternatively, a digital signal
on the INT0 pin can also trigger a shutdown. The autoshutdown feature can be disabled by not selecting any
auto-shutdown sources. The auto-shutdown sources to
be used are selected using the ECCPAS2:ECCPAS0
bits (ECCPAS<6:4>).
When a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified
by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits
(ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/
P1D) may be set to drive high, drive low or be tri-stated
(not driving). The ECCPASE bit (ECCPAS<7>) is also
set to hold the enhanced PWM outputs in their
shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
PWM1CON: PWM CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away;
the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0
PDC6:PDC0: PWM Delay Count bits
Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled time when a PWM signal
should transition to active and the actual time it transitions active.
© 2007 Microchip Technology Inc.
DS39599G-page 149
PIC18F2220/2320/4220/4320
REGISTER 16-3:
ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
0 = ECCP outputs are operating
bit 6-4
ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits
000 = Auto-shutdown is disabled
001 = Comparator 1 output
010 = Comparator 2 output
011 = Either Comparator 1 or 2
100 = INT0
101 = INT0 or Comparator 1
110 = INT0 or Comparator 2
111 = INT0 or Comparator 1 or Comparator 2
bit 3-2
PSSAC<1:0>: Pin A and C Shutdown State Control bits
00 = Drive Pins A and C to ‘0’
01 = Drive Pins A and C to ‘1’
1x = Pins A and C tri-state
bit 1-0
PSSBD<1:0>: Pin B and D Shutdown State Control bits
00 = Drive Pins B and D to ‘0’
01 = Drive Pins B and D to ‘1’
1x = Pins B and D tri-state
DS39599G-page 150
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
16.4.5.1
Auto-Shutdown and Automatic
Restart
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the PRSEN bit of the
PWM1CON register (PWM1CON<7>).
In Shutdown mode with PRSEN = 1 (Figure 16-10), the
ECCPASE bit will remain set for as long as the cause
of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is cleared. If PRSEN = 0
(Figure 16-11), once a shutdown condition occurs, the
ECCPASE bit will remain set until it is cleared by firmware. Once ECCPASE is cleared, the enhanced PWM
will resume at the beginning of the next PWM period.
Note:
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Independent of the PRSEN bit setting, if the autoshutdown source is one of the comparators, the shutdown condition is a level. The ECCPASE bit cannot be
cleared as long as the cause of the shutdown persists.
The Auto-Shutdown mode can be forced by writing a ‘1’
to the ECCPASE bit.
FIGURE 16-10:
16.4.6
START-UP CONSIDERATIONS
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pullup and/or pull-down resistors on the PWM output pins.
When the microcontroller is released from Reset, all of
the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the
off state until the microcontroller drives the I/O pins with
the proper signal levels or activates the PWM output(s).
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration
while the PWM pins are configured as outputs is not
recommended since it may result in damage to the
application circuits.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP module may cause damage to the application
circuit. The ECCP module must be enabled in the proper
output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a
full PWM cycle is indicated by the TMR2IF bit being set
as the second PWM period begins.
PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
PWM Period
PWM Activity
Dead Time
Duty Cycle
PWM Period
Dead Time
Duty Cycle
PWM Period
Dead Time
Duty Cycle
Shutdown Event
ECCPASE bit
FIGURE 16-11:
PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
PWM Period
PWM Activity
Dead Time
Duty Cycle
PWM Period
Dead Time
Duty Cycle
PWM Period
Dead Time
Duty Cycle
Shutdown Event
ECCPASE bit
ECCPASE
Cleared by Firmware
© 2007 Microchip Technology Inc.
DS39599G-page 151
PIC18F2220/2320/4220/4320
16.4.7
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP module for PWM operation:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Configure the PWM pins P1A and P1B (and
P1C and P1D, if used) as inputs by setting the
corresponding TRISC and TRISD bits.
Set the PWM period by loading the PR2 register.
Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
• Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
For Half-Bridge Output mode, set the dead band
delay by loading PWM1CON<6:0> with the
appropriate value.
If auto-shutdown operation is required, load the
ECCPAS register:
• Select the auto-shutdown sources using the
ECCPAS<2:0> bits.
• Select the shutdown states of the PWM
output pins using PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCPAS<7>).
• Configure the comparators using the CMCON
register.
• Configure the comparator inputs as analog
inputs.
If auto-restart operation is required, set the
PRSEN bit (PWM1CON<7>).
Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
• Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMR2 overflows (TMR2IF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRISC
and TRISD bits.
• Clear the ECCPASE bit (ECCPAS<7>).
DS39599G-page 152
16.4.8
OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will continue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from INTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change.
In all other power-managed modes, the selected
power-managed mode clock will clock Timer2. Other
power-managed mode clocks will most likely be
different than the primary clock frequency.
16.4.8.1
OPERATION WITH FAIL-SAFE
CLOCK MONITOR
If the Fail-Safe Clock Monitor is enabled
(CONFIG1H<6> is programmed), a clock failure will
force the device into the power-managed RC_RUN
mode and the OSCFIF bit (PIR2<7>) will be set. The
ECCP will then be clocked from the internal oscillator
clock source which may have a different clock
frequency than the primary clock. By loading the
IRCF2:IRCF0 bits on Resets, the user can obtain a
frequency higher than the default INTRC clock source
in the event of a clock failure.
See the previous section for additional details.
16.4.9
EFFECTS OF A RESET
Both Power-on and subsequent Resets will force all
ports to Input mode and the CCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 16-2:
Name
INTCON
RCON
REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Bit 7
Bit 6
GIE/GIEH PEIE/GIEL
IPEN
—
Value on
all other
Resets
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
—
RI
TO
PD
POR
BOR
0--1 11q0 0--q qquu
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP 1111 1111 1111 1111
IPR1
TMR2
Timer2 Module Register
PR2
Timer2 Module Period Register
T2CON
—
TOUTPS3
0000 0000 0000 0000
1111 1111 1111 1111
TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TRISD
PORTD Data Direction Register
1111 1111 1111 1111
CCPR1H
Enhanced Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
CCPR1L
Enhanced Capture/Compare/PWM Register 1 Low Byte
CCP1CON
ECCPAS
P1M1
P1M0
ECCPASE ECCPAS2
DC1B1
DC1B0
ECCPAS1 ECCPAS0
xxxx xxxx uuuu uuuu
CCP1M3
CCP1M2
CCP1M1
CCP1M0 0000 0000 0000 0000
PSSAC1
PSSAC0
PSSBD1
PSSBD0 0000 0000 0000 0000
PWM1CON
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
0000 0000 0000 0000
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
0000 q000 0000 q000
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used by the ECCP module in enhanced PWM mode.
© 2007 Microchip Technology Inc.
DS39599G-page 153
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 154
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.0
17.1
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
- Slave mode (with general address call)
17.3
SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/LVDIN/C2OUT
Register 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
Read
• Master mode
• Multi-Master mode
• Slave mode
17.2
Write
SSPBUF reg
Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual Configuration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
SSPSR reg
RC4/SDI/SDA
Shift
Clock
bit 0
RC5/SDO
SS Control
Enable
RA5/AN4/SS/
LVDIN/C2OUT
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE 4
TMR2 Output
2
2
(
RC3/SCK/
SCL
Edge
Select
)
Prescaler TOSC
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
© 2007 Microchip Technology Inc.
DS39599G-page 155
PIC18F2220/2320/4220/4320
17.3.1
REGISTERS
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
The MSSP module has four registers for SPI mode
operation. These are:
•
•
•
•
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
MSSP Control Register 1 (SSPCON1)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) – Not directly
accessible
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower six bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 17-1:
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Edge Select bit
When CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
When CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5
D/A: Data/Address bit
Used in I2C mode only.
bit 4
P: Stop bit
Used in I2C mode only.
bit 3
S: Start bit
Used in I2C mode only.
bit 2
R/W: Read/Write Information bit
Used in I2C mode only.
bit 1
UA: Update Address bit
Used in I2C mode only.
bit 0
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
DS39599G-page 156
x = Bit is unknown
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 17-2:
SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV(1)
SSPEN(2)
CKP
SSPM3(3)
SSPM2(3)
SSPM1(3)
SSPM0(3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0 = No overflow
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(2)
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(3)
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1:
2:
3:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
When the MSSP is enabled in SPI mode, these pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
© 2007 Microchip Technology Inc.
DS39599G-page 157
PIC18F2220/2320/4220/4320
17.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a Transmit/Receive Shift register (SSPSR) and a Buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received data is ready. Once the 8 bits
of data have been received, that byte is moved to the
SSPBUF register. Then the Buffer Full Detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
EXAMPLE 17-1:
LOOP
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision Detect bit,
WCOL (SSPCON1<7>), will be set. User software
must clear the WCOL bit so that it can be determined if
the following write(s) to the SSPBUF register
completed successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
Full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 17-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
LOADING THE SSPBUF (SSPSR) REGISTER
BTFSS
BRA
MOVF
SSPSTAT, BF
LOOP
SSPBUF, W
;Has data been received(transmit complete)?
;No
;WREG reg = contents of SSPBUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSPBUF
;W reg = contents of TXDATA
;New data to xmit
DS39599G-page 158
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.3.3
ENABLING SPI I/O
17.3.4
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
• SDI must have TRISC<4> bit cleared
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISA<5> bit set
TYPICAL CONNECTION
Register 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
Any serial port function that is not desired may be overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 17-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
Serial Input Buffer
(SSPBUF)
LSb
© 2007 Microchip Technology Inc.
Shift Register
(SSPSR)
MSb
SCK
PROCESSOR 1
SDO
Serial Clock
LSb
SCK
PROCESSOR 2
DS39599G-page 159
PIC18F2220/2320/4220/4320
17.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would
give waveforms for SPI communication, as shown in
FIGURE 17-3:
Figure 17-3, Figure 17-5 and Figure 17-6, where the
MSB is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user-programmable to be one of the
following:
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
(Timer2 output)/2
The maximum data rate is approximately 3.0 Mbps,
limited by timing requirements (see Table 26-14
through Table 26-17).
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
DS39599G-page 160
Next Q4 Cycle
after Q2↓
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in power-managed modes, the slave can transmit/receive data. When a byte is received, the device
will wake-up from power-managed modes.
17.3.7
SLAVE SELECT CONTROL
The SS pin allows a master controller to select one of
several slave controllers for communications in systems with more than one slave. The SPI must be in
Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). The SS pin is configured for
input by setting TRISA<5>. When the SS pin is low,
transmission and reception are enabled and the SDO
pin is driven. When the SS pin goes high, the SDO pin
FIGURE 17-4:
is tri-stated, even if in the middle of a transmitted byte.
External pull-up/pull-down resistors may be desirable,
depending on the application.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0> = 0100),
the SPI module will reset when the SS pin is
set high.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
When the SPI module resets, SSPSR is cleared. This
can be done by either driving the SS pin to a high level
or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 7
bit 0
bit 0
bit 7
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
© 2007 Microchip Technology Inc.
Next Q4 Cycle
after Q2↓
DS39599G-page 161
PIC18F2220/2320/4220/4320
FIGURE 17-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 17-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS39599G-page 162
Next Q4 Cycle
after Q2↓
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.3.8
MASTER IN POWER-MANAGED
MODES
17.3.8.1
Slave in Power-Managed Modes
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in any power-managed mode and
data to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the MSSP
interrupt flag bit will be set and if MSSP interrupts are
enabled, will wake the device from a power-managed
mode.
In Master mode, module clocks may be operating at a
different speed than when in full-power mode, or in the
case of the power-managed Sleep mode, all clocks are
halted.
In most power-managed modes, a clock is provided
to the peripherals and is derived from the primary
clock source, the secondary clock (Timer1 oscillator
at 32.768 kHz) or the internal oscillator block (one of
eight frequencies between 31 kHz and 8 MHz). See
Section 2.7 “Clock Sources and Oscillator
Switching” for additional information.
17.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
17.3.10
BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
If MSSP interrupts are enabled, they can wake the controller from a power-managed mode when the master
completes sending data. If an exit from a powermanaged mode is not desired, MSSP interrupts should
be disabled.
TABLE 17-1:
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will pause until
the device wakes from the power-managed mode.
After the device returns to full-power mode, the module
will resume transmitting and receiving data.
SPI BUS MODES
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0
There is also an SMP bit which controls when the data
is sampled.
TABLE 17-2:
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
INTCON
GIE/GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111 1111 1111
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
SSPBUF
MSSP Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
Name
SSPCON1
TRISA
SSPSTAT
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
R/W
UA
BF
0000 0000 0000 0000
TRISA7(1) TRISA6(1) PORTA Data Direction Register
SMP
CKE
D/A
P
S
--11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
DS39599G-page 163
PIC18F2220/2320/4220/4320
17.4
I2C Mode
17.4.1
The MSSP module in I 2C mode fully implements all
master and slave functions (including general call support) and provides interrupts on Start and Stop bits in
hardware to determine a free bus (multi-master function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial Clock (SCL) – RC3/SCK/SCL
• Serial Data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs using the
TRISC<4:3> bits.
FIGURE 17-7:
MSSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
Read
Write
Shift
Clock
LSb
MSb
Match Detect
Addr Match
SSPADD reg
Start and
Stop bit Detect
DS39599G-page 164
•
•
•
•
•
MSSP Control Register 1 (SSPCON1)
MSSP Control Register 2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower six bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
SSPSR reg
RC4/SDI/
SDA
The MSSP module has six registers for I2C operation.
These are:
SSPADD register holds the slave device address
when the MSSP is configured in I2C Slave mode.
When the MSSP is configured in Master mode, the
lower seven bits of SSPADD act as the Baud Rate
Generator reload value.
SSPBUF reg
RC3/SCK/
SCL
REGISTERS
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
Set, Reset
S, P bits
(SSPSTAT reg)
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 17-3:
SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P(1)
S(2)
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled
0 = Slew rate control enabled
bit 6
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3
S: Start bit(2)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2
R/W: Read/Write bit Information (I2C mode only)
In Slave mode:(3)
1 = Read
0 = Write
In Master mode:(4)
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1
UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
In Transmit mode:
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
In Receive mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Note 1:
2:
3:
4:
This bit is cleared on Reset when SSPEN is cleared or a Start bit has been detected.
This bit is cleared on Reset when SSPEN is cleared or a Stop bit has been detected.
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
ORing this bit with the SSPCON2 bits, SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in
Idle mode.
© 2007 Microchip Technology Inc.
DS39599G-page 165
PIC18F2220/2320/4220/4320
REGISTER 17-4:
R/W-0
SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE)
R/W-0
WCOL
SSPOV
R/W-0
SSPEN
(1)
R/W-0
CKP
R/W-0
SSPM3
(2)
R/W-0
SSPM2
(2)
R/W-0
SSPM1
(2)
R/W-0
SSPM0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in
software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
SSPEN: Master Synchronous Serial Port Enable bit(1)
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(2)
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address(2)
0110 = I2C Slave mode, 7-bit address(2)
Note 1:
2:
When enabled, the SDA and SCL pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
DS39599G-page 166
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 17-5:
SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT(1)
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence Idle
bit 3
RCEN: Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2
PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enabled bit (Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enabled/Stretch Enabled bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
© 2007 Microchip Technology Inc.
DS39599G-page 167
PIC18F2220/2320/4220/4320
17.4.2
OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I 2C operation. Four mode selection bits (SSPCON1<3:0>) allow
one of the following I 2C modes to be selected:
I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
I 2C Slave mode (7-bit address)
I 2C Slave mode (10-bit address)
I 2C Slave mode (7-bit address), with Start and
Stop bit interrupts enabled
• I 2C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled
• I 2C Firmware Controlled Master mode,
slave is Idle
•
•
•
•
Selection of any I 2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain, provided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I 2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
17.4.3.1
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1.
2.
3.
4.
In this case, the SSPSR register value is not loaded
into the SSPBUF but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared by software.
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for
10-bit addressing is as follows, with steps 7 through 9
for the slave-transmitter:
1.
2.
3.
4.
5.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON1<6>), was
set before the transfer was received.
Addressing
6.
7.
8.
9.
Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit, UA, and releases the
SCL line).
Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
Receive second (low) byte of address (bits,
SSPIF, BF and UA, are set).
Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit, UA.
Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits, SSPIF
and BF, are set).
Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
DS39599G-page 168
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.4.3.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPSTAT<0>), is
set or bit, SSPOV (SSPCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit,
CKP (SSPCON1<4>). See Section 17.4.4 “Clock
Stretching” for more detail.
17.4.3.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low regardless of SEN (see Section 17.4.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
which also loads the SSPSR register. Then the RC3/
SCK/SCL pin should be enabled by setting bit, CKP
(SSPCON1<4>). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 17-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, the RC3/SCK/SCL pin must be enabled by
setting bit, CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
© 2007 Microchip Technology Inc.
DS39599G-page 169
DS39599G-page 170
CKP
2
A6
3
4
A4
5
A3
Receiving Address
A5
6
A2
(CKP does not reset to ‘0’ when SEN = 0)
SSPOV (SSPCON1<6>)
BF (SSPSTAT<0>)
SSPIF (PIR1<3>)
1
SCL
S
A7
7
A1
8
9
ACK
R/W = 0
1
D7
3
4
D4
5
D3
Receiving Data
D5
Cleared in software
SSPBUF is read
2
D6
6
D2
7
D1
8
D0
9
ACK
1
D7
2
D6
3
4
D4
5
D3
Receiving Data
D5
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
9
ACK
FIGURE 17-8:
SDA
PIC18F2220/2320/4220/4320
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
1
CKP
2
A6
Data in
sampled
BF (SSPSTAT<0>)
SSPIF (PIR1<3>)
S
A7
3
A5
4
A4
5
A3
6
A2
Receiving Address
7
A1
8
R/W = 1
9
ACK
SCL held low
while CPU
responds to SSPIF
1
D7
3
D5
4
D4
5
D3
6
D2
CKP is set in software
SSPBUF is written in software
Cleared in software
2
D6
Transmitting Data
7
8
D0
9
ACK
From SSPIF ISR
D1
1
D7
4
D4
5
D3
6
D2
CKP is set in software
7
8
D0
9
ACK
From SSPIF ISR
D1
Transmitting Data
Cleared in software
3
D5
SSPBUF is written in software
2
D6
P
FIGURE 17-9:
SCL
SDA
PIC18F2220/2320/4220/4320
I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
DS39599G-page 171
DS39599G-page 172
2
1
4
1
5
0
7
A8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
6
A9
8
9
(CKP does not reset to ‘0’ when SEN = 0)
UA (SSPSTAT<1>)
SSPOV (SSPCON1<6>)
CKP
3
1
Cleared in software
BF (SSPSTAT<0>)
SSPIF (PIR1<3>)
1
SCL
S
1
ACK
R/W = 0
A7
2
4
A4
5
A3
6
A2
8
9
A0 ACK
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware
when SSPADD is updated
with low byte of address
7
A1
Cleared in software
3
A5
Dummy read of SSPBUF
to clear BF flag
1
A6
Receive Second Byte of Address
1
D7
4
5
6
Cleared in software
3
7
D1
Cleared by hardware when
SSPADD is updated with high
byte of address
2
D3 D2
Receive Data Byte
D6 D5 D4
Clock is held low until
update of SSPADD has
taken place
8
9
1
2
4
5
6
Cleared in software
3
D0 ACK D7 D6 D5 D4 D3 D2
Receive Data Byte
7
8
D1 D0
9
P
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 17-10:
SDA
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
PIC18F2220/2320/4220/4320
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
2
CKP (SSPCON1<4>)
UA (SSPSTAT<1>)
BF (SSPSTAT<0>)
SSPIF (PIR1<3>)
1
S
SCL
1
4
1
5
0
6
7
A9 A8
8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
3
1
Receive First Byte of Address
1
9
ACK
1
3
4
5
Cleared in software
2
7
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address
6
A6 A5 A4 A3 A2 A1
8
A0
Receive Second Byte of Address
Dummy read of SSPBUF
to clear BF flag
A7
9
ACK
2
3
1
4
1
Cleared in software
1
1
5
0
6
8
9
ACK
R/W = 1
1
2
4
5
6
Cleared in software
3
CKP is set in software
9
P
Completion of
data transmission
clears BF flag
8
ACK
Bus master
terminates
transfer
CKP is automatically cleared in hardware holding SCL low
7
D7 D6 D5 D4 D3 D2 D1 D0
Transmitting Data Byte
Clock is held low until
CKP is set to ‘1’
Write of SSPBUF
BF flag is clear
initiates transmit
at the end of the
third address sequence
7
A9 A8
Cleared by hardware when
SSPADD is updated with high
byte of address.
Dummy read of SSPBUF
to clear BF flag
Sr
1
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
FIGURE 17-11:
SDA
R/W = 0
Clock is held low until
update of SSPADD has
taken place
PIC18F2220/2320/4220/4320
I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
DS39599G-page 173
PIC18F2220/2320/4220/4320
17.4.4
CLOCK STRETCHING
Both 7 and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
17.4.4.1
Clock Stretching for 7-Bit Slave
Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF bit
is set, the CKP bit in the SSPCON1 register is automatically cleared, forcing the SCL output to be held low.
The CKP being cleared to ‘0’ will assert the SCL line
low. The CKP bit must be set in the user’s ISR before
reception is allowed to continue. By holding the SCL
line low, the user has time to service the ISR and read
the contents of the SSPBUF before the master device
can initiate another receive sequence. This will prevent
buffer overruns from occurring (see Figure 17-13).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
17.4.4.2
17.4.4.3
Clock Stretching for 7-Bit Slave
Transmit Mode
7-Bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-9).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
17.4.4.4
Clock Stretching for 10-Bit Slave
Transmit Mode
In 10-Bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the
state of the UA bit, just as it is in 10-Bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-Bit Slave Transmit mode (see Figure 17-11).
Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but the CKP bit is not cleared. During this time, if the
UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte
of the 10-bit address and following the receive of the
second byte of the 10-bit address with the R/W bit
cleared to ‘0’. The release of the clock line occurs
upon updating SSPADD. Clock stretching will occur on
each data receive sequence as described in 7-bit
mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by reading the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
DS39599G-page 174
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.4.4.5
Clock Synchronization and
the CKP bit (SEN = 1)
The SEN bit is also used to synchronize writes to the
CKP bit. If a user clears the CKP bit, the SCL output is
forced to ‘0’. When the SEN bit is set to ‘1’, setting the
CKP bit will not assert the SCL output low until the
SCL output is already sampled low. If the user
attempts to drive SCL low, the CKP bit will not assert
the SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
FIGURE 17-12:
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
Note:
If the SEN bit is ‘0’, clearing the CKP bit
will result in immediately driving the SCL
output to ‘0’ regardless of the current
state.
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device
asserts clock
Master device
deasserts clock
WR
SSPCON1
© 2007 Microchip Technology Inc.
DS39599G-page 175
DS39599G-page 176
CKP
SSPOV (SSPCON1<6>)
BF (SSPSTAT<0>)
SSPIF (PIR1<3>)
1
SCL
S
A7
2
A6
3
4
A4
5
A3
Receiving Address
A5
6
A2
7
A1
8
9
ACK
R/W = 0
3
4
D4
5
D3
Receiving Data
D5
Cleared in software
2
D6
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
SSPBUF is read
1
D7
6
D2
7
D1
9
ACK
1
D7
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
8
D0
3
4
D4
5
D3
Receiving Data
D5
CKP
written
to ‘1’ in
software
2
D6
Clock is held low until
CKP is set to ‘1’
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
9
ACK
Clock is not held low
because ACK = 1
FIGURE 17-13:
SDA
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock
PIC18F2220/2320/4220/4320
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
2
1
UA (SSPSTAT<1>)
SSPOV (SSPCON1<6>)
CKP
3
1
4
1
5
0
6
7
A9 A8
8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
Cleared in software
BF (SSPSTAT<0>)
SSPIF (PIR1<3>)
1
SCL
S
1
9
ACK
R/W = 0
A7
2
4
5
A4 A3
6
A2
Cleared in software
3
A5
7
A1
8
A0
Note:
An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
of ninth clock
Dummy read of SSPBUF
to clear BF flag
1
A6
Receive Second Byte of Address
9
ACK
2
4
5
6
D3 D2
Cleared in software
3
D5 D4
7
D1
8
Note:
An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
9
ACK
1
4
5
6
D3 D2
Cleared in software
3
D5 D4
Receive Data Byte
CKP written to ‘1’
in software
2
D7 D6
Clock is held low until
CKP is set to ‘1’
D0
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
of ninth clock.
Dummy read of SSPBUF
to clear BF flag
1
D7 D6
Receive Data Byte
Clock is held low until
update of SSPADD has
taken place
7
8
9
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D1 D0
ACK
Clock is not held low
because ACK = 1
FIGURE 17-14:
SDA
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
PIC18F2220/2320/4220/4320
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DS39599G-page 177
PIC18F2220/2320/4220/4320
17.4.5
GENERAL CALL ADDRESS
SUPPORT
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually determines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set while the slave is
configured in 10-Bit Addressing mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 17-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit (GCEN) is enabled
(SSPCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the
general call address and fixed in hardware.
FIGURE 17-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESSING MODE)
Address is compared to general call address
after ACK, set interrupt
R/W = 0
ACK D7
General Call Address
SDA
SCL
S
1
2
3
4
5
6
7
8
9
1
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
‘0’
GCEN (SSPCON2<7>)
‘1’
DS39599G-page 178
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
MASTER MODE
Note:
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I 2C bus may be taken when the P bit is set or the
bus is Idle, with both the S and P bits clear.
The following events will cause MSSP Interrupt Flag
bit, SSPIF, to be set (MSSP interrupt if enabled):
In Firmware Controlled Master mode, user code
conducts all I 2C bus operations based on Start and
Stop bit conditions.
•
•
•
•
•
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write to the SSPBUF register initiating
transmission of data/address.
Configure the I2C port to receive data.
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDA and SCL.
FIGURE 17-16:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condition is complete. In this case, the SSPBUF
will not be written to and the WCOL bit will
be set, indicating that a write to the
SSPBUF did not occur.
Start Condition
Stop Condition
Data Transfer Byte Transmitted/Received
Acknowledge Transmit
Repeated Start
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Internal
Data Bus
Read
SSPM3:SSPM0
SSPADD<6:0>
Write
SSPBUF
SDA
Baud
Rate
Generator
Shift
Clock
SDA In
SCL In
Bus Collision
© 2007 Microchip Technology Inc.
LSb
Start bit, Stop bit,
Acknowledge
Generate
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
Clock Cntl
SCL
Receive Enable
SSPSR
MSb
Clock Arbitrate/WCOL Detect
(hold off clock source)
17.4.6
Set/Reset, S, P, WCOL (SSPSTAT);
Set SSPIF, BCLIF;
Reset ACKSTAT, PEN (SSPCON2)
DS39599G-page 179
PIC18F2220/2320/4220/4320
17.4.6.1
I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning
and end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate” for more detail.
DS39599G-page 180
A typical transmit sequence would go as follows:
1.
The user generates a Start condition by setting
the Start enable bit, SEN (SSPCON2<0>).
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.4.7
BAUD RATE
17.4.7.1
2
In I C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Register 17-17). When a write
occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to ‘0’
and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(TCY) on the Q2 and Q4 clocks. In I2C Master mode, the
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Baud Rate Generation in
Power-Managed Modes
When the device is operating in a power-managed
mode, the clock source to the Baud Rate Generator
may change frequency or stop, depending on the
power-managed mode and clock source selected.
In most power modes, the Baud Rate Generator
continues to be clocked but may be clocked from the
primary clock (selected in a Configuration Word), the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the internal oscillator block (one of eight frequencies
between 31 kHz and 8 MHz). If the Sleep mode is
selected, all clocks are stopped and the Baud Rate
Generator will not be clocked.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPM3:SSPM0
SCL
Reload
Control
CLKO
TABLE 17-3:
SSPADD<6:0>
Reload
BRG Down Counter
FOSC/4
I2C CLOCK RATE W/BRG
FOSC
FCY
FCY * 2
SSPADD VALUE
(See Register 17-4,
Mode 1000)
FSCL(2)
(2 Rollovers of BRG)
40 MHz
10 MHz
20 MHz
18h
400 kHz(1)
40 MHz
10 MHz
20 MHz
1Fh
312.5 kHz
40 MHz
10 MHz
20 MHz
63h
100 kHz
16 MHz
4 MHz
8 MHz
09h
400 kHz(1)
16 MHz
4 MHz
8 MHz
0Bh
308 kHz
16 MHz
4 MHz
8 MHz
27h
100 kHz
4 MHz
1 MHz
2 MHz
02h
333 kHz(1)
4 MHz
1 MHz
2 MHz
09h
100kHz
4 MHz
1 MHz
2 MHz
00h
1 MHz(1)
Note 1:
2:
The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
Actual clock rate will depend on bus conditions. Bus capacitance can increase rise time and extend the low
time of the clock period, reducing the effective clock frequency (see Section 17.4.7.2 “Clock Arbitration”).
© 2007 Microchip Technology Inc.
DS39599G-page 181
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17.4.7.2
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 17-18:
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 17-18).
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
DS39599G-page 182
© 2007 Microchip Technology Inc.
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17.4.8
I2C MASTER MODE START
CONDITION TIMING
17.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
To initiate a Start condition, the user sets the Start
Condition Enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0>
and starts its count. If SCL and SDA are both sampled
high when the Baud Rate Generator times out (TBRG),
the SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the Start condition and
causes the S bit (SSPSTAT<3>) to be set. Following
this, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When
the Baud Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by
hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
Note:
WCOL Status Flag
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
If, at the beginning of the Start condition,
the SDA and SCL pins are already sampled low or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
FIGURE 17-19:
FIRST START BIT TIMING
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
SDA = 1,
SCL = 1
TBRG
At completion of Start bit,
hardware clears SEN bit
and sets SSPIF bit
TBRG
Write to SSPBUF occurs here
1st bit
SDA
2nd bit
TBRG
SCL
TBRG
S
© 2007 Microchip Technology Inc.
DS39599G-page 183
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17.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
17.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
FIGURE 17-20:
REPEAT START CONDITION WAVEFORM
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
Set S (SSPSTAT<3>)
SDA = 1,
SCL = 1
TBRG
TBRG
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
TBRG
1st bit
SDA
Falling edge of ninth clock,
end of Xmit
Write to SSPBUF occurs here
TBRG
SCL
TBRG
Sr = Repeated Start
DS39599G-page 184
© 2007 Microchip Technology Inc.
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17.4.10
I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full Flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
#106). SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time specification
parameter #107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit, during the ninth bit time, if an
address match occurred or if data was received properly. The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared; if not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-21).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is
cleared and the Baud Rate Generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
17.4.10.1
BF Status Flag
17.4.10.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
17.4.11
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the Baud Rate
Generator is suspended from counting, holding SCL
low. The MSSP is now in Idle state, awaiting the next
command. When the buffer is read by the CPU, the BF
flag bit is automatically cleared. The user can then
send an Acknowledge bit at the end of reception by
setting the Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>).
17.4.11.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
17.4.11.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
17.4.11.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
17.4.10.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
© 2007 Microchip Technology Inc.
DS39599G-page 185
DS39599G-page 186
S
R/W
PEN
SEN
BF (SSPSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
3
4
5
Cleared in software
2
6
7
8
9
After Start condition, SEN cleared by hardware
SSPBUF written
1
D7
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
SSPBUF is written in software
Cleared in software service routine
from MSSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
SSPBUF written with 7-bit address and R/W,
start transmit
A7
Transmit Address to Slave
From slave, clear ACKSTAT bit SSPCON2<6>
P
Cleared in software
9
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 17-21:
SEN = 0
Write SSPCON2<0> SEN = 1,
Start condition begins
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I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
© 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
S
ACKEN
SSPOV
BF
(SSPSTAT<0>)
SDA = 0, SCL = 1,
while CPU
responds to SSPIF
SSPIF
SCL
SDA
1
A7
2
4
5
Cleared in software
3
6
A6 A5 A4 A3 A2
Transmit Address to Slave
7
A1
8
9
R/W = 1
ACK
ACK from Slave
2
3
5
6
7
8
D0
9
ACK
2
3
4
5
6
7
Cleared in software
Set SSPIF interrupt
at end of Acknowledge
sequence
Data shifted in on falling edge of CLK
1
D7 D6 D5 D4 D3 D2 D1
Cleared in
software
Set SSPIF at end
of receive
9
ACK is not sent
ACK
Bus master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
Set SSPIF interrupt
at end of Acknowledge
sequence
P
PEN bit = 1
written here
SSPOV is set because
SSPBUF is still full
8
D0
RCEN cleared
automatically
Set ACKEN, start Acknowledge sequence,
SDA = ACKDT = 1
Receiving Data from Slave
RCEN = 1, start
next receive
ACK from master,
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Set SSPIF interrupt
at end of receive
4
Cleared in software
1
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN cleared
automatically
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)
FIGURE 17-22:
SEN = 0
Write to SSPBUF occurs here,
start XMIT
Write to SSPCON2<0> (SEN = 1),
begin Start condition
Write to SSPCON2<4>
to start Acknowledge sequence,
SDA = ACKDT (SSPCON2<5>) = 0
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17.4.12
ACKNOWLEDGE SEQUENCE TIMING
17.4.13
An Acknowledge sequence is enabled by setting the
Acknowledge
Sequence
Enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG) and
the SCL pin is deasserted (pulled high). When the SCL
pin is sampled high (clock arbitration), the Baud Rate
Generator counts for TBRG. The SCL pin is then pulled
low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.12.1
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT<4>) is
set. A TBRG later, the PEN bit is cleared and the SSPIF
bit is set (Figure 17-24).
17.4.13.1
WCOL Status Flag
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t
occur).
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
STOP CONDITION TIMING
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2,
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
TBRG
SDA
D0
SCL
ACK
8
9
SSPIF
Set SSPIF at the end
of receive
Cleared in
software
Cleared in software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 17-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2,
set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
DS39599G-page 188
© 2007 Microchip Technology Inc.
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17.4.14
POWER-MANAGED MODE
OPERATION
17.4.17
While in any power-managed mode, the I2C module
can receive addresses or data and when an address
match or complete byte transfer occurs, wake the
processor from Sleep (if the MSSP interrupt is
enabled).
17.4.15
EFFECT OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.4.16
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I 2C bus may
be taken when the P bit (SSPSTAT<4>) is set or the
bus is idle with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I2C port to its Idle state (Figure 17-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine, and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted,
and the respective control bits in the SSPCON2 register
are cleared. When the user services the bus collision
Interrupt Service Routine, and if the I2C bus is free, the
user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register or
the bus is Idle and the S and P bits are cleared.
FIGURE 17-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by master
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Bus collision has occurred.
SDA
SCL
Set Bus Collision
Interrupt Flag (BCLIF)
BCLIF
© 2007 Microchip Technology Inc.
DS39599G-page 189
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17.4.17.1
Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a)
b)
SDA or SCL is sampled low at the beginning of
the Start condition (Figure 17-26).
SCL is sampled low before SDA is asserted low
(Figure 17-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0 and during this time, if the SCL pins
are sampled as ‘0’, a bus collision does not occur. At
the end of the BRG count, the SCL pin is asserted low.
Note:
If the SDA pin is already low or the SCL pin is already
low, then all of the following occur:
• The Start condition is aborted
• The BCLIF flag is set
• The MSSP module is reset to its Idle state
(Figure 17-26)
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 17-26:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus collision because the two masters must be
allowed to arbitrate the first address following the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
MSSP module reset into Idle state.
SEN
BCLIF
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
DS39599G-page 190
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 17-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
SSPIF
‘0’
‘0’
FIGURE 17-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
Set SSPIF
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SCL
S
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCLIF
‘0’
S
SSPIF
SDA = 0, SCL = 1,
set SSPIF
© 2007 Microchip Technology Inc.
Interrupts cleared
in software
DS39599G-page 191
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17.4.17.2
Bus Collision During a Repeated
Start Condition
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low, indicating that another master is attempting to
transmit a data ‘1’.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition
(see Figure 17-30).
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
FIGURE 17-29:
If at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
‘0’
S
‘0’
SSPIF
FIGURE 17-30:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
BCLIF
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
Interrupt cleared
in software
RSEN
S
‘0’
SSPIF
DS39599G-page 192
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
17.4.17.3
Bus Collision During a Stop
Condition
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Register 17-31). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
Bus collision occurs during a Stop condition if:
a)
b)
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 17-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
TBRG
SDA
SDA sampled
low after TBRG,
set BCLIF
SDA asserted low
SCL
PEN
BCLIF
P
‘0’
SSPIF
‘0’
FIGURE 17-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
Assert SDA
SCL
SCL goes low before SDA goes high,
set BCLIF
PEN
BCLIF
P
‘0’
SSPIF
‘0’
© 2007 Microchip Technology Inc.
DS39599G-page 193
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 194
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
18.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules available in the PIC18F2X20/4X20 family
of microcontrollers. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices, such as A/D
or D/A integrated circuits, serial EEPROMs, etc.
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The RC6/TX/CK and RC7/RX/DT pins must be configured as shown for use with the Universal Synchronous
Asynchronous Receiver Transmitter:
• SPEN (RCSTA<7>) bit must be set (= 1)
• TRISC<7> bit must be set (= 1)
• TRISC<6> bit must be cleared (= 0)
18.1
Asynchronous Operation in
Power-Managed Modes
The USART may operate in Asynchronous mode while
the peripheral clocks are being provided by the internal
oscillator block. This mode makes it possible to remove
the crystal or resonator that is commonly connected as
the primary clock on the OSC1 and OSC2 pins.
The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may
drift as VDD or temperature changes and this directly
affects the asynchronous baud rate. Two methods may
be used to adjust the baud rate clock, but both require
a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output back to 8 MHz.
Adjusting the value in the OSCTUNE register allows for
fine resolution changes to the system clock source (see
Section 3.6 “INTOSC Frequency Drift” for more
information).
The other method adjusts the value in the Baud Rate
Generator since there may be not be fine enough resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
Register 18-1 shows the Transmit Status and Control
register (TXSTA) and Register 18-2 shows the Receive
Status and Control register (RCSTA).
© 2007 Microchip Technology Inc.
DS39599G-page 195
PIC18F2220/2320/4220/4320
REGISTER 18-1:
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN(1)
SYNC
—
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4
SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
Unimplemented: Read as ‘0’
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1:
x = Bit is unknown
SREN/CREN overrides TXEN in Sync mode.
DS39599G-page 196
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 18-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6
RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
© 2007 Microchip Technology Inc.
DS39599G-page 197
PIC18F2220/2320/4220/4320
18.2
USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free-running 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is
ignored. Table 18-1 shows the formula for computation
of the baud rate for different USART modes which only
apply in Master mode (internal clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 18-1. From this, the error in
baud rate can be determined.
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
•
•
•
•
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks, because the
FOSC/(16 (X + 1)) equation can reduce the baud rate
error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
18.2.1
POWER-MANAGED MODE
OPERATION
The system clock is used to generate the desired baud
rate; however, when a power-managed mode is
entered, the clock source may be operating at a different frequency than in PRI_RUN mode. In Sleep mode,
no clocks are present and in PRI_IDLE, the primary
clock source continues to provide clocks to the baud
rate generator; however, in other power-managed
modes, the clock frequency will probably change. This
may require the value in SPBRG to be adjusted.
18.2.2
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 18-1:
Desired Baud Rate
CALCULATING BAUD RATE ERROR
= FOSC/(64 (X + 1))
Solving for X:
= ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
X
X
X
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
TABLE 18-1:
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0 (Asynchronous)
1 (Synchronous)
Baud Rate = FOSC/(64 (X + 1))
Baud Rate = FOSC/(4 (X + 1))
Baud Rate = FOSC/(16 (X + 1))
N/A
Legend: X = value in SPBRG (0 to 255)
TABLE 18-2:
Name
TXSTA
RCSTA
SPBRG
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
0000 0000
0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
DS39599G-page 198
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 18-3:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0, LOW SPEED)
FOSC = 40.000 MHz
BAUD
RATE
(K)
FOSC = 20.000 MHz
Actual
Rate
(K)
%
Error
0.3
—
—
—
—
—
1.2
—
—
—
1.22
1.73
2.4
2.44
1.73
255
2.40
0.16
9.6
9.62
0.16
64
9.47
-1.36
19.2
18.94
-1.36
32
19.53
1.73
15
38.4
39.06
1.73
15
39.06
1.73
7
57.6
56.82
-1.36
10
62.50
8.51
4
76.8
78.13
1.73
7
78.13
1.73
3
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
FOSC = 16.000 MHz
Actual
Rate
(K)
%
Error
—
0.98
225.52
255
1.20
0.16
129
2.40
0.16
32
9.62
0.16
19.23
35.71
62.50
83.33
SPBRG
value
(decimal)
FOSC = 10.000 MHz
Actual
Rate
(K)
%
Error
255
0.61
103.45
255
207
1.20
0.16
129
103
2.40
0.16
64
25
9.77
1.73
15
0.16
12
19.53
1.73
7
-6.99
6
39.06
1.73
3
8.51
3
52.08
-9.58
2
8.51
2
78.13
1.73
1
—
SPBRG
value
(decimal)
SPBRG
value
(decimal)
96.0
89.29
-6.99
6
104.17
8.51
2
—
—
—
—
—
115.2
125.00
8.51
4
—
—
—
125.00
8.51
1
78.13
-32.18
1
250.0
208.33
-16.67
2
—
—
250.00
0.00
0
—
—
—
300.0
312.50
4.17
1
312.50
4.17
0
—
—
—
—
—
—
625.0
625.00
0.00
0
—
—
—
—
—
—
—
—
—
FOSC = 8.000000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
0.3
0.49
1.2
1.20
2.4
9.6
FOSC = 7.159090 MHz
(decimal)
Actual
Rate
(K)
%
Error
62.76
255
0.44
0.16
103
1.20
2.40
0.16
51
9.62
0.16
12
19.2
17.86
-6.99
38.4
41.67
8.51
57.6
62.50
—
—
115.2
125.00
BAUD
RATE
(K)
(decimal)
Actual
Rate
(K)
%
Error
45.65
255
0.31
0.23
92
1.20
2.38
-0.83
46
9.32
-2.90
11
6
18.64
-2.90
5
2
37.29
-2.90
2
8.51
1
55.93
-2.90
1
—
—
—
—
—
8.51
0
111.86
-2.90
0
—
SPBRG
value
FOSC = 3.579545 MHz
Actual
Rate
(K)
FOSC = 5.068800 MHz
%
Error
SPBRG
value
(decimal)
SPBRG
value
FOSC = 2.000000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
FOSC = 4.000000 MHz
(decimal)
Actual
Rate
(K)
%
Error
3.13
255
0.30
0.16
207
0.00
65
1.20
0.16
51
2.40
0.00
32
2.40
0.16
25
9.90
3.13
7
8.93
-6.99
6
19.80
3.13
3
20.83
8.51
2
39.60
3.13
1
31.25
-18.62
1
—
—
—
62.50
8.51
0
79.20
3.13
0
—
—
—
—
—
—
—
—
SPBRG
value
FOSC = 1.000000 MHz
Actual
Rate
(K)
%
Error
(decimal)
FOSC = 0.032768 MHz
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
0.3
0.30
0.23
185
0.30
0.16
103
0.30
0.16
51
0.26
-14.67
1
1.2
1.19
-0.83
46
1.20
0.16
25
1.20
0.16
12
—
—
—
2.4
2.43
1.32
22
2.40
0.16
12
2.23
-6.99
6
—
—
—
9.6
9.32
-2.90
5
10.42
8.51
2
7.81
-18.62
1
—
—
—
19.2
18.64
-2.90
2
15.63
-18.62
1
15.63
-18.62
0
—
—
—
38.4
—
—
—
31.25
-18.62
0
—
—
—
—
—
—
57.6
55.93
-2.90
0
—
—
—
—
—
—
—
—
—
© 2007 Microchip Technology Inc.
DS39599G-page 199
PIC18F2220/2320/4220/4320
TABLE 18-4:
BAUD
RATE
(K)
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1, HIGH SPEED)
FOSC = 40.000 MHz
Actual
Rate (K)
%
Error
SPBRG
value
(decimal)
FOSC = 20.000 MHz
Actual
Rate (K)
%
Error
SPBRG
value
(decimal)
FOSC = 16.000 MHz
Actual
Rate (K)
%
Error
FOSC = 10.000 MHz
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
2.4
—
—
—
4.88
103.45
255
3.91
62.76
255
2.44
1.73
255
9.6
9.77
1.73
255
9.62
0.16
129
9.62
0.16
103
9.63
0.16
64
19.2
19.23
0.16
129
19.23
0.16
64
19.23
0.16
51
18.94
-1.36
32
38.4
38.46
0.16
64
37.88
-1.36
32
38.46
0.16
25
39.06
1.73
15
57.6
58.14
0.94
42
56.82
-1.36
21
58.82
2.12
16
56.82
-1.36
10
76.8
75.76
-1.36
32
78.13
1.73
15
76.92
0.16
12
78.13
1.73
7
96.0
96.15
0.16
25
96.15
0.16
12
100.00
4.17
9
89.29
-6.99
6
115.2
113.64
-1.36
21
113.64
-1.36
10
111.11
-3.55
8
125.00
8.51
4
250.0
250.00
0.00
9
250.00
0.00
4
250.00
0.00
3
208.33
-16.67
2
300.0
312.50
4.17
7
312.50
4.17
3
333.33
11.11
2
312.50
4.17
1
500.0
500.00
0.00
4
416.67
-16.67
2
500.00
0.00
1
—
—
—
625.0
625.00
0.00
3
625.00
0.00
1
—
—
—
625.00
0.00
0
1000.0
833.33
-16.67
2
—
—
—
1000.00
0.00
0
—
—
—
1250.0
1250.00
0.00
1
1250.00
0.00
0
—
—
—
—
—
—
FOSC = 8.000000 MHz
BAUD
RATE
(K)
Actual
Rate (K)
%
Error
0.3
—
—
1.2
1.95
2.4
2.40
9.6
19.2
SPBRG
value
FOSC = 7.159090 MHz
Actual
Rate (K)
%
Error
—
—
—
62.76
255
1.75
0.16
207
2.41
9.62
0.16
51
19.23
0.16
SPBRG
value
FOSC = 5.068800 MHz
Actual
Rate (K)
%
Error
—
—
—
45.65
255
1.24
0.23
185
2.40
9.52
-0.83
46
25
19.45
1.32
(decimal)
FOSC = 4.000 MHz
SPBRG
value
SPBRG
value
Actual
Rate (K)
%
Error
—
0.98
225.52
255
3.13
255
1.20
0.16
207
0.00
131
2.40
0.16
103
9.60
0.00
32
9.62
0.16
25
22
18.64
-2.94
16
19.23
0.16
12
6
(decimal)
(decimal)
(decimal)
38.4
38.46
0.16
12
37.29
-2.90
11
39.60
3.13
7
35.71
-6.99
57.6
55.56
-3.55
8
55.93
-2.90
7
52.80
-8.33
5
62.50
8.51
3
76.8
71.43
-6.99
6
74.57
-2.90
5
79.20
3.13
3
83.33
8.51
2
96.0
100.00
4.17
4
89.49
-6.78
4
—
—
—
—
—
—
1
115.2
125.00
8.51
3
111.86
-2.90
3
105.60
-8.33
2
125.00
8.51
250.0
250.00
0.00
1
223.72
-10.51
1
—
—
—
250.00
0.00
0
300.0
—
—
—
—
—
—
316.80
5.60
0
—
—
—
500.0
500.00
0.00
0
447.44
-10.51
0
—
—
—
—
—
—
FOSC = 3.579545 MHz
BAUD
RATE
(K)
Actual
Rate (K)
%
Error
0.3
0.87
191.30
1.2
1.20
2.4
2.41
SPBRG
value
FOSC = 2.000000 MHz
Actual
Rate (K)
%
Error
255
0.49
62.76
0.23
185
1.20
0.23
92
2.40
(decimal)
SPBRG
value
FOSC = 1.000000 MHz
Actual
Rate (K)
%
Error
255
0.30
0.16
0.16
103
1.20
0.16
51
(decimal)
FOSC = 0.032768 MHz
SPBRG
value
SPBRG
value
Actual
Rate (K)
%
Error
207
0.29
-2.48
0.16
51
1.02
-14.67
1
2.40
0.16
25
2.05
-14.67
0
—
(decimal)
(decimal)
6
9.6
9.73
1.32
22
9.62
0.16
12
8.93
-6.99
6
—
—
19.2
18.64
-2.90
11
17.86
-6.99
6
20.83
8.51
2
—
—
—
38.4
37.29
-2.90
5
41.67
8.51
2
31.25
-18.62
1
—
—
—
—
57.6
55.93
-2.90
3
62.50
8.51
1
62.50
8.51
0
—
—
76.8
74.57
-2.90
2
—
—
—
—
—
—
—
—
—
115.2
111.86
-2.90
1
125.00
8.51
0
—
—
—
—
—
—
250.0
223.72
-10.51
0
—
—
—
—
—
—
—
—
—
DS39599G-page 200
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 18-5:
BAUD
RATE
(K)
BAUD RATES FOR SYNCHRONOUS MODE (SYNC = 1)
FOSC = 40.000 MHz
Actual
Rate (K)
%
Error
SPBRG
value
(decimal)
FOSC = 20.000 MHz
Actual
Rate (K)
%
Error
SPBRG
value
(decimal)
FOSC = 16.000 MHz
Actual
Rate (K)
%
Error
SPBRG
value
(decimal)
FOSC = 10.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
9.6
—
—
—
—
—
—
15.63
62.76
255
9.77
1.73
255
19.2
—
—
—
19.53
1.73
255
19.23
0.16
207
19.23
0.16
129
38.4
39.06
1.73
255
38.46
0.16
129
38.46
0.16
103
38.46
0.16
64
57.6
57.47
-0.22
173
57.47
-0.22
86
57.97
0.64
68
58.14
0.94
42
76.8
76.92
0.16
129
76.92
0.16
64
76.92
0.16
51
75.76
-1.36
32
96.0
96.15
0.16
103
96.15
0.16
51
95.24
-0.79
41
96.15
0.16
25
250.0
250.00
0.00
39
250.00
0.00
19
250.00
0.00
15
250.00
0.00
9
300.0
303.03
1.01
32
294.12
-1.96
16
307.69
2.56
12
312.50
4.17
7
500.0
500.00
0.00
19
500.00
0.00
9
500.00
0.00
7
500.00
0.00
4
625.0
625.00
0.00
15
625.00
0.00
7
666.67
6.67
5
625.00
0.00
3
1000.0
1000.00
0.00
9
1000.00
0.00
4
1000.00
0.00
3
833.33
-16.67
2
1250.0
1250.00
0.00
7
1250.00
0.00
3
1333.33
6.67
2
1250.00
0.00
1
FOSC = 8.000000 MHz
BAUD
RATE
(K)
Actual
Rate (K)
%
Error
2.4
7.81
225.52
SPBRG
value
(decimal)
255
FOSC = 7.159090 MHz
SPBRG
value
Actual
Rate (K)
%
Error
6.99
191.30
255
(decimal)
FOSC = 5.068800 MHz
SPBRG
value
Actual
Rate (K)
%
Error
4.95
106.25
255
(decimal)
FOSC = 4.000 MHz
SPBRG
value
Actual
Rate (K)
%
Error
3.91
62.76
255
(decimal)
9.6
9.62
0.16
207
9.62
0.23
185
9.60
0.00
131
9.62
0.16
103
19.2
19.23
0.16
103
19.24
0.23
92
19.20
0.00
65
19.23
0.16
51
38.4
38.46
0.16
51
38.08
-0.83
46
38.40
0.00
32
38.46
0.16
25
57.6
57.14
-0.79
34
57.73
0.23
30
57.60
0.00
21
58.82
2.12
16
12
76.8
76.92
0.16
25
77.82
1.32
22
74.54
-2.94
16
76.92
0.16
96.0
95.24
-0.79
20
94.20
-1.88
18
97.48
1.54
12
100.00
4.17
9
250.0
250.00
0.00
7
255.68
2.27
6
253.44
1.38
4
250.00
0.00
3
300.0
285.71
-4.76
6
298.30
-0.57
5
316.80
5.60
3
333.33
11.11
2
500.0
500.00
0.00
3
447.44
-10.51
3
422.40
-15.52
2
500.00
0.00
1
625.0
666.67
6.67
2
596.59
-4.55
2
633.60
1.38
1
—
—
—
1000.0
1000.00
0.00
1
894.89
-10.51
1
—
—
—
1000.00
0.00
0
1250.0
—
—
—
1789.77
43.18
0
1267.20
1.38
0
—
—
—
FOSC = 3.579545 MHz
FOSC = 2.000000 MHz
BAUD
RATE
(K)
Actual
Rate (K)
%
Error
0.3
—
—
—
—
—
1.2
—
—
—
1.95
62.76
2.4
3.50
45.65
255
2.40
0.16
207
SPBRG
value
(decimal)
Actual
Rate (K)
%
Error
SPBRG
value
FOSC = 1.000000 MHz
SPBRG
value
FOSC = 0.032768 MHz
%
Error
—
0.98
225.52
255
0.30
1.14
255
1.20
0.16
207
1.17
-2.48
6
2.40
0.16
103
2.73
13.78
2
(decimal)
(decimal)
Actual
Rate (K)
%
Error
SPBRG
value
Actual
Rate (K)
(decimal)
26
9.6
9.62
0.23
92
9.62
0.16
51
9.62
0.16
25
8.19
-14.67
0
19.2
19.04
-0.83
46
19.23
0.16
25
19,.23
0.16
12
—
—
—
—
38.4
38.91
1.32
22
38.46
0.16
12
35.71
-6.99
6
—
—
57.6
55.93
-2.90
15
55.56
-3.55
8
62.50
8.51
3
—
—
—
76.8
74.57
-2.90
11
71.43
-6.99
6
83.33
8.51
2
—
—
—
—
96.0
99.43
3.57
8
100.00
4.17
4
—
—
—
—
—
250.0
223.72
-10.51
3
250.00
0.00
1
250.00
0.00
0
—
—
—
500.0
447.44
-10.51
1
500.00
0.00
0
—
—
—
—
—
—
© 2007 Microchip Technology Inc.
DS39599G-page 201
PIC18F2220/2320/4220/4320
18.3
USART Asynchronous Mode
18.3.1
In this mode, the USART uses standard Non-Returnto-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip dedicated 8-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and
receives the LSb first. The USART’s transmitter and
receiver are functionally independent but use the same
data format and baud rate. The Baud Rate Generator
produces a clock, either x16 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware but can be implemented in software (and stored as the ninth data bit). Asynchronous
mode functions in all power-managed modes except
Sleep mode when call clock sources are stopped.
When in PRI_IDLE mode, no changes to the Baud
Rate Generator values are required; however, other
power-managed mode clocks may operate at another
frequency than the primary clock. Therefore, the Baud
Rate generator values may need adjusting.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer, TXREG.
The TXREG register is loaded with data in software.
The TSR register is not loaded until the Stop bit has
been transmitted from the previous load. As soon as
the Stop bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit, TXIF (PIR1<4>), is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. Flag bit TXIF is not cleared immediately upon
loading the Transmit Buffer register, TXREG. TXIF
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following
a load of TXREG will return invalid results. While flag bit
TXIF indicated the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. Status bit TRMT is a read-only bit
which is set when the TSR register is empty. No interrupt logic is tied to this bit, therefore, the user must poll
this bit in order to determine whether the TSR register
is empty.
Asynchronous mode is selected by clearing bit, SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
•
•
•
•
USART ASYNCHRONOUS
TRANSMITTER
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit, TXIF, is set when enable bit,
TXEN, is set.
FIGURE 18-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
TXIE
8
MSb
LSb
(8)
• • •
Pin Buffer
and Control
0
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS39599G-page 202
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 18-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 18-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
Start bit
bit 0
bit 1
Word 1
1 TCY
bit 7/8
Stop bit
Start bit
bit 0
Word 2
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
Word 2
Transmit Shift Reg.
This timing diagram shows two consecutive transmissions.
TABLE 18-6:
Name
Word 1
Transmit Shift Reg.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
Bit 3
RBIE
Bit 2
Bit 1
TMR0IF INT0IF
Value on
all other
Resets
Bit 0
Value on
POR, BOR
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
SPEN
RX9
SREN
RCSTA
TXREG
TXSTA
FERR
OERR
RX9D
0000 000x 0000 000x
SYNC
BRGH
TRMT
TX9D
0000 -010 0000 -010
USART Transmit Register
CSRC
TX9
TXEN
SPBRG Baud Rate Generator Register
Legend:
Note 1:
CREN ADDEN
0000 0000 0000 0000
—
0000 0000 0000 0000
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
DS39599G-page 203
PIC18F2220/2320/4220/4320
18.3.2
USART ASYNCHRONOUS
RECEIVER
18.3.3
The receiver block diagram is shown in Figure 18-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter, operating at x16 times the
baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would
typically be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with address
detect enable:
1.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is required,
set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
To set up an Asynchronous Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.2 “USART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, RCIE.
4. If 9-bit reception is desired, set bit, RX9.
5. Enable the reception by setting bit, CREN.
6. Flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if enable
bit, RCIE, was set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-4:
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
USART RECEIVE BLOCK DIAGRAM
CREN
FERR
OERR
x64 Baud Rate CLK
SPBRG
÷ 64
or
÷ 16
RSR Register
MSb
Stop
(8)
7
• • •
1
LSb
0
Start
Baud Rate Generator
RX9
Pin Buffer
and Control
Data
Recovery
RC7/RX/DT
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
Data Bus
RCIE
DS39599G-page 204
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
To set up an Asynchronous Transmission:
1.
2.
3.
4.
5.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.2 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
If interrupts are desired, set enable bit, TXIE.
If 9-bit transmission is desired, set Transmit bit,
TX9. Can be used as address/data bit.
FIGURE 18-5:
6.
7.
8.
Enable the transmission by setting bit, TXEN,
which will also set bit, TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Load data to the TXREG register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX (pin)
bit 1
bit 7/8 Stop
bit
Rcv Shift
Reg
Rcv Buffer Reg
Start
bit
bit 0
Stop
bit
Start
bit
bit 7/8
Stop
bit
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
bit 7/8
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,
causing the OERR (Overrun) bit to be set.
TABLE 18-7:
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RBIF
0000 000x
0000 000u
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
0000 0000
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
0000 0000
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111
1111 1111
Bit 7
Bit 6
INTCON
GIE/GIEH
PEIE/
GIEL
PIR1
PSPIF(1)
ADIF
RCIF
PIE1
PSPIE(1)
ADIE
IPR1
PSPIP(1)
ADIP
SPEN
RX9
SREN
RCSTA
RCREG
TXSTA
Bit 5
Bit 4
TMR0IE INT0IE
Bit 3
RBIE
Bit 2
Bit 1
TMR0IF INT0IF
CREN ADDEN FERR
OERR
RX9D
USART Receive Register
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 000x
0000 000x
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
SPBRG
Baud Rate Generator Register
Legend:
Note 1:
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
DS39599G-page 205
PIC18F2220/2320/4220/4320
18.4
USART Synchronous Master
Mode
(PIE1<4>). Flag bit, TXIF, will be set regardless of the
state of enable bit, TXIE, and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit, TXIF, indicates the
status of the TXREG register, another bit, TRMT
(TXSTA<1>), shows the status of the TSR register.
TRMT is a read-only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit so the user
has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory
so it is not available to the user.
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit, SYNC (TXSTA<4>). In
addition, enable bit, SPEN (RCSTA<7>), is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit, CSRC (TXSTA<7>).
18.4.1
To set up a Synchronous Master Transmission:
1.
USART SYNCHRONOUS MASTER
TRANSMISSION
2.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and interrupt bit, TXIF (PIR1<4>), is set. The interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
FIGURE 18-6:
3.
4.
5.
6.
7.
8.
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 7
Word 1
RC6/TX/CK
pin
Write to
TXREG Reg
Initialize the SPBRG register for the appropriate
baud rate (Section 18.2 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit, TXIE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting bit, TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
Write Word 1
bit 0
bit 1
bit 7
Word 2
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit TRMT
TXEN bit
Note:
‘1’
‘1’
Sync Master mode, SPBRG = 0; continuous transmission of two 8-bit words.
DS39599G-page 206
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 18-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 18-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
INTCON
GIE/
GIEH
PEIE/
GIEL
Bit 5
Bit 4
TMR0IE INT0IE
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE
0000 0000
0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP TMR2IP TMR1IP
1111 1111
1111 1111
SPEN
RX9
SREN
0000 000x
0000 000x
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
RCSTA
TXREG
TXSTA
CREN ADDEN
FERR
OERR
RX9D
BRGH
TRMT
TX9D
USART Transmit Register
CSRC
TX9
TXEN
SYNC
SPBRG Baud Rate Generator Register
—
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
DS39599G-page 207
PIC18F2220/2320/4220/4320
18.4.2
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit, SREN
(RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data
is sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit, SREN, is set, only a single word
is received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
Initialize the SPBRG register for the appropriate
baud rate (Section 18.2 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
Ensure bits, CREN and SREN, are clear.
FIGURE 18-8:
4.
5.
6.
If interrupts are desired, set enable bit, RCIE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RCIF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RCIE, was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
‘0’
CREN bit
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 18-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
RCIP
TXIP
SSPIP
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
SREN
CREN
ADDEN
Bit 7
Bit 6
INTCON
GIE/
GIEH
PEIE/
GIEL
PIR1
PSPIF(1)
ADIF
RCIF
PIE1
(1)
PSPIE
ADIE
IPR1
PSPIP(1)
ADIP
SPEN
RX9
RCSTA
RCREG
TXSTA
Bit 5
Bit 4
TMR0IE INT0IE
FERR
OERR
RX9D
USART Receive Register
CSRC
TX9
Value on
all other
Resets
Bit 3
Name
TXEN
0000 000x 0000 000x
0000 0000 0000 0000
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
SPBRG
Baud Rate Generator Register
Legend:
Note 1:
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
DS39599G-page 208
0000 0000 0000 0000
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
18.5
USART Synchronous Slave Mode
To set up a Synchronous Slave Transmission:
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in any power-managed mode. Slave
mode is entered by clearing bit, CSRC (TXSTA<7>).
18.5.1
USART SYNCHRONOUS SLAVE
TRANSMIT
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
b)
c)
d)
e)
2.
3.
4.
5.
6.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode.
a)
1.
7.
8.
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit, TXIF, will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit, TXIF, will now be
set.
If enable bit, TXIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If interrupts are desired, set enable bit, TXIE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
0000 000u
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000
0000 0000
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000
0000 0000
RCIP
TXIP
SSPIP
CCP1IP TMR2IP TMR1IP 1111 1111
1111 1111
Name
Bit 7
Bit 6
INTCON
GIE/
GIEH
PEIE/
GIEL
PIR1
PSPIF(1)
ADIF
RCIF
PIE1
PSPIE(1)
ADIE
IPR1
PSPIP(1)
ADIP
SPEN
RX9
SREN
RCSTA
TXREG
TXSTA
SPBRG
Bit 5
Bit 4
TMR0IE INT0IE
CREN ADDEN
FERR
OERR
RX9D
USART Transmit Register
CSRC
TX9
TXEN
SYNC
Baud Rate Generator Register
—
BRGH
TRMT
TX9D
0000 000x
0000 000x
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
© 2007 Microchip Technology Inc.
DS39599G-page 209
PIC18F2220/2320/4220/4320
18.5.2
USART SYNCHRONOUS SLAVE
RECEPTION
To set up a Synchronous Slave Reception:
1.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep or any
Idle mode and bit, SREN, which is a “don’t care” in
Slave mode.
2.
3.
4.
5.
If receive is enabled by setting bit, CREN, prior to
entering Sleep or any Idle mode, then a word may be
received while in this power-managed mode. Once the
word is received, the RSR register will transfer the data
to the RCREG register and if enable bit, RCIE, is set,
the interrupt generated will wake the chip from the
power-managed mode. If the global interrupt is
enabled, the program will branch to the interrupt vector.
6.
7.
8.
9.
Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
If interrupts are desired, set enable bit, RCIE.
If 9-bit reception is desired, set bit, RX9.
To enable reception, set enable bit, CREN.
Flag bit, RCIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit, CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
INTCON
GIE/
GIEH
PEIE/
GIEL
Bit 5
Bit 4
TMR0IE INT0IE
Value on
all other
Resets
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
RCSTA
RCREG
TXSTA
SPBRG
USART Receive Register
CSRC
TX9
TXEN
Baud Rate Generator Register
0000 0000 0000 0000
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
DS39599G-page 210
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
19.0
10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has 10
inputs for the PIC18F2X20 devices and 13 for the
PIC18F4X20 devices. This module allows conversion
of an analog input signal to a corresponding 10-bit
digital number.
A new feature for the A/D converter is the addition of
programmable acquisition time. This feature allows the
user to select a new channel for conversion and setting
the GO/DONE bit immediately. When the GO/DONE bit is
set, the selected channel is sampled for the programmed
acquisition time before a conversion is actually started.
This removes the firmware overhead that may have been
required to allow for an acquisition (sampling) period (see
Register 19-3 and Section 19.3 “Selecting and
Configuring Automatic Acquisition Time”).
REGISTER 19-1:
The module has five registers:
•
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 19-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 19-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 19-3, configures the A/D clock
source, programmed acquisition time and justification.
ADCON0: A/D CONTROL REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-2
CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)(1,2)
0110 = Channel 6 (AN6)(1,2)
0111 = Channel 7 (AN7)(1,2)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)
1101 = Unimplemented(2)
1110 = Unimplemented(2)
1111 = Unimplemented(2)
bit 1
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0
ADON: A/D On bit
1 = A/D converter module is enabled
0 = A/D converter module is disabled
Note 1:
2:
x = Bit is unknown
These channels are not implemented on the PIC18F2X20 (28-pin) devices.
Performing a conversion on unimplemented channels returns full-scale results.
© 2007 Microchip Technology Inc.
DS39599G-page 211
PIC18F2220/2320/4220/4320
REGISTER 19-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0(1)
R/W(1)
R/W(1)
R/W(1)
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PCFG3:
PCFG0
AN6(2)
AN5(2)
AN4
AN3
AN2
AN1
AN0
PCFG3:PCFG0: A/D Port Configuration Control bits:
AN7(2)
bit 3-0
AN8
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = VDD
AN9
bit 4
AN10
VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS
AN11
Unimplemented: Read as ‘0’
bit 5
AN12
bit 7-6
0000(1)
0001
0010
0011
0100
0101
0110
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
D
D
D
D
A
A
A
A
D
D
D
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
0111(1)
1000
1001
1010
1011
1100
1101
1110
1111
A = Analog input
Note 1:
2:
x = Bit is unknown
D = Digital I/O
The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
AN5 through AN7 are available only in PIC18F4X20 devices.
DS39599G-page 212
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 19-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1:
x = Bit is unknown
If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
© 2007 Microchip Technology Inc.
DS39599G-page 213
PIC18F2220/2320/4220/4320
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 19-1.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To operate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter which generates the result via successive
approximation.
FIGURE 19-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1100
1011
1010
1001
1000
0111
0110
0101
0100
VAIN
0011
(Input Voltage)
10-Bit
A/D
Converter
0010
0001
VCFG1:VCFG0
0000
AVDD
Reference
Voltage
VREFH
VREFL
AN12(2)
AN11
AN10
AN9
AN8
AN7(1)
AN6(1)
AN5(1)
AN4
AN3/VREF+
AN2/VREFAN1
AN0
X0
X1
1X
0X
AVSS
Note 1: Channels AN5 through AN7 are not available on PIC18F2X20 devices.
2: I/O pins have diode protection to VDD and VSS.
DS39599G-page 214
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
2.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 19.1
“A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
3.
4.
The following steps should be followed to do an A/D
conversion:
1.
5.
6.
7.
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
FIGURE 19-2:
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time (if required).
Start conversion:
• Set GO/DONE bit (ADCON0 register)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
ANALOG INPUT MODEL
VDD
Rs
ANx
RIC ≤ 1k
CPIN
VAIN
Sampling
Switch
VT = 0.6V
VT = 0.6 V
5 pF
SS
RSS
ILEAKAGE
± 500 nA
CHOLD = 120 pF
VSS
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
RSS
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
various junctions
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
© 2007 Microchip Technology Inc.
VDD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch (kΩ)
DS39599G-page 215
PIC18F2220/2320/4220/4320
19.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the
Charge Holding Capacitor (CHOLD) must be allowed to
fully charge to the input channel voltage level. The analog input model is shown in Figure 19-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to
pin leakage current). The maximum recommended
impedance for analog sources is 2.5 kΩ. After the
analog input channel is selected (changed), the channel
must be sampled for at least the minimum acquisition
time before starting a conversion.
Note:
When the conversion is started, the holding
capacitor is disconnected from the input pin.
19.2
If external voltage references are used instead of the
internal AVDD and AVSS sources, the source impedance of the VREF+ and VREF- voltage sources must be
considered. During acquisition, currents supplied by
these sources are insignificant. However, during conversion, the A/D module sinks and sources current
through the reference sources.
In order to maintain the A/D accuracy, the voltage reference source impedances should be kept low to
reduce voltage changes. These voltage changes occur
as reference currents flow through the reference
source impedance. The maximum recommended
impedance of the VREF+ and VREF- external
reference voltage sources is 75Ω.
Note:
To calculate the minimum acquisition time,
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 19-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is based
on the following application system assumptions:
=
=
≤
=
=
=
CHOLD
RS
Conversion Error
VDD
Temperature
VHOLD
EQUATION 19-1:
TACQ
=
=
120 pF
2.5 kΩ
1/2 LSb
5V → Rss = 7 kΩ
50°C (system max.)
0V @ time = 0
When using external references, the
source impedance of the external voltage
references must be less than 75Ω in order
to achieve the specified ADC resolution. A
higher reference source impedance will
increase the ADC offset and gain errors.
Resistive voltage dividers will not provide a
low enough source impedance. To ensure
the best possible ADC performance, external VREF inputs should be buffered with an
op amp or other low-impedance circuit.
ACQUISITION TIME
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 19-2:
VHOLD
or
TC
A/D VREF+ and VREF- References
MINIMUM A/D HOLDING CAPACITOR
=
(VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS)))
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EXAMPLE 19-1:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TAMP + TC + TCOFF
5 μs
(Temp – 25°C)(0.05 μs/°C)
(50°C – 25°C)(0.05 μs/°C)
1.25 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 μs.
–
-(CHOLD)(RIC + RSS + RS) ln(1/2047) μs
TC
-(120 pF) (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883) μs
9.61 μs
TACQ
=
5 μs + 1.25 μs + 9.61 μs
12.86 μs
TACQ
TAMP
TCOFF
=
=
=
DS39599G-page 216
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
19.3
Selecting and Configuring
Automatic Acquisition Time
19.4
Selecting the A/D Conversion Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensuring the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT2:ACQT0
bits (ADCON2<5:3>) remain in their Reset state (‘000’)
and is compatible with devices that do not offer
programmable acquisition times.
•
•
•
•
•
•
•
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition
time, then automatically begins a conversion. Since the
acquisition time is programmed, there may be no need
to wait for an acquisition time between selecting a
channel and setting the GO/DONE bit.
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (approximately 2 μs, see parameter #130
for more information).
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
Table 19-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 19-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Operation
ADCS2:ADCS0
PIC18FXX20
2 TOSC
000
1.25 MHz
666 kHz
100
2.50 MHz
1.33 MHz
8 TOSC
001
5.00 MHz
2.66 MHz
16 TOSC
101
10.0 MHz
5.33 MHz
32 TOSC
010
20.0 MHz
10.65 MHz
64 TOSC
110
40.0 MHz
21.33 MHz
RC
4:
PIC18LFXX20(4)
4 TOSC
(3)
Note 1:
2:
3:
Maximum Device Frequency
x11
1.00
MHz(1)
1.00 MHz(2)
The RC source has a typical TAD time of 4 μs.
The RC source has a typical TAD time of 6 μs.
For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
Low-power devices only.
© 2007 Microchip Technology Inc.
DS39599G-page 217
PIC18F2220/2320/4220/4320
19.5
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been completed. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits ACQT2:ACQT0 are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have already
been cleared prior to starting the conversion.
DS39599G-page 218
19.6
Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
3: The PBADEN bit in the Configuration
register configures PORTB pins to reset
as analog or digital pins by controlling
how the PCFG0 bits in ADCON1 are
reset.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
19.7
A/D Conversions
Figure 19-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
Figure 19-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 TAD acquisition time before the conversion starts.
After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
Note:
FIGURE 19-3:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b8
b9
b3
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
FIGURE 19-4:
TAD Cycles
TACQT Cycles
1
2
3
Automatic
Acquisition
Time
4
1
2
3
4
5
6
7
8
9
10
11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
© 2007 Microchip Technology Inc.
Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
DS39599G-page 219
PIC18F2220/2320/4220/4320
19.8
Use of the CCP2 Trigger
desired location). The appropriate analog input channel must be selected and the minimum acquisition
period is either timed by the user or an appropriate
TACQ time, selected before the “Special Event Trigger”,
sets the GO/DONE bit (starts a conversion).
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D acquisition and
conversion and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
TABLE 19-2:
If the A/D module is not enabled (ADON is cleared), the
“Special Event Trigger” will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
SUMMARY OF A/D REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
0000 0000
PIE1
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
1111 1111
1111 1111
PIR2
OSCFIF
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
00-0 0000
00-0 0000
PIE2
OSCFIE
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
00-0 0000
00-0 0000
IPR2
OSCFIP
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
11-1 1111
11-1 1111
ADRESH
A/D Result Register High Byte
xxxx xxxx
uuuu uuuu
ADRESL
A/D Result Register Low Byte
xxxx xxxx
uuuu uuuu
ADCON0
—
—
CHS3
CHS3
CHS1
CHS0
GO/DONE
ADON
--00 0000
--00 0000
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0qqq
--00 0qqq
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
0-00 0000
0-00 0000
PORTA
RA7(4)
RA6(4)
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000
--0u 0000
(4)
(4)
TRISA
TRISA7
--11 1111
--11 1111
PORTB
Read PORTB pins, Write LATB Latch
xxxx xxxx
uuuu uuuu
TRISB
PORTB Data Direction Register
1111 1111
1111 1111
LATB
PORTB Output Data Latch
xxxx xxxx
uuuu uuuu
TRISA6
PORTE(2)
—
—
—
—
RE3(1)
TRISE(2)
IBF
OBE
IBOV
PSPMODE
—
LATE(2)
—
—
—
—
Legend:
Note 1:
2:
3:
Read PORTE pins, Write LATE(4) ---- xxxx
---- uuuu
PORTE Data Direction
0000 -111
0000 -111
---- -xxx
---- -uuu
PORTE Output Data Latch
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used for A/D conversion.
The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear functionality is disabled
(CONFIG3H<7>=0).
This register is not implemented on PIC18F2X20 devices and reads back 0x00.
These pins may be configured as port pins depending on the oscillator mode selected.
DS39599G-page 220
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
20.0
COMPARATOR MODULE
20.1
The comparator module contains two analog comparators. The inputs and outputs for the comparators are
multiplexed with the RA0 through RA5 pins. The onchip voltage reference (Section 21.0 “Comparator
Voltage Reference Module”) can also be an input to
the comparators.
The CMCON register, shown as Register 20-1,
controls the comparator module’s input and output
multiplexers. A block diagram of the various
comparator configurations is shown in Figure 20-1.
REGISTER 20-1:
Comparator Configuration
There are eight modes of operation for the comparators.
The CM bits (CMCON<2:0>) are used to select these
modes. Figure 20-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator mode
is changed, the comparator output level may not be valid
for the specified mode change delay shown in the
Electrical Specifications (see Section 26.0 “Electrical
Characteristics”).
Note:
Comparator interrupts should be disabled
during a Comparator mode change.
Otherwise, a false interrupt may occur.
CMCON: COMPARATOR CONTROL REGISTER
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1:
1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1:
1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN-
bit 5
C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4
C1INV: Comparator 1 Output Inversion bit
1 = C1 output inverted
0 = C1 output not inverted
bit 3
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1 = C1 VIN- connects to RA3/AN3
C2 VIN- connects to RA2/AN2
0 = C1 VIN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 20-1 shows the Comparator modes and the CM2:CM0 bit settings.
© 2007 Microchip Technology Inc.
DS39599G-page 221
PIC18F2220/2320/4220/4320
FIGURE 20-1:
COMPARATOR I/O OPERATING MODES
Comparators RESET
CM<2:0> = 000
D
VIN-
RA3/AN3/ D
VREF+
VIN+
D
VIN-
RA2/AN2/ D
VREF-/CVREF
VIN+
RA0/AN0
RA1/AN1
Comparators Off (POR Default Value)
CM<2:0> = 111
C1
Off (Read as ‘0’)
A
VIN-
RA3/AN3/ A
VREF+
VIN+
A
VIN-
RA2/AN2/ A
VREF-/CVREF
VIN+
RA1/AN1
VIN-
RA3/AN3/ D
VREF+
VIN+
D
VIN-
RA2/AN2/ D
VREF-/CVREF
VIN+
RA1/AN1
C2
Off (Read as ‘0’)
RA0/AN0
C1
C1
Off (Read as ‘0’)
C2
Off (Read as ‘0’)
Two Independent Comparators with Outputs
CM<2:0> = 011
Two Independent Comparators
CM<2:0> = 010
RA0/AN0
D
RA0/AN0
C1OUT
RA3/AN3/
VREF+
A
VIN-
A
VIN+
C1
C1OUT
C2
C2OUT
RA4/T0CKI/C1OUT(1)
C2
C2OUT
A
VIN-
RA2/AN2/ A
VREF-/CVREF
VIN+
RA1/AN1
RA5/AN4/SS/LVDIN/C2OUT(1)
Two Common Reference Comparators
CM<2:0> = 100
A
RA0/AN0
Two Common Reference Comparators with Outputs
CM<2:0> = 101
VINVIN+
RA3/AN3/
VREF+
A
RA1/AN1
A
VIN-
RA2/AN2/ D
VREF-/CVREF
VIN+
C1
C1OUT
RA0/AN0
RA3/AN3/
VREF+
A
VIN-
A
VIN+
A
VIN-
D
VIN+
C1
C1OUT
C2
C2OUT
RA4/T0CKI/C1OUT(1)
C2
C2OUT
RA1/AN1
RA2/AN2/
VREF-/CVREF
RA5/AN4/SS/LVDIN/C2OUT(1)
One Independent Comparator with Output
CM<2:0> = 001
A
VIN-
RA3/AN3/ A
VIN+
RA0/AN0
Four Inputs Multiplexed to Two Comparators
CM<2:0> = 110
RA0/AN0
C1
C1OUT
VREF+
RA3/AN3/
VREF+
RA4/T0CKI/C1OUT(1)
RA1/AN1
D
VIN-
RA2/AN2/ D
VREF-/CVREF
VIN+
RA1/AN1
A
A
A
A
C2
Off (Read as ‘0’)
CIS = 0
CIS = 1
RA2/AN2/
VREF-/CVREF
CIS = 0
CIS = 1
VINVIN+
C1
C1OUT
C2
C2OUT
VINVIN+
CVROE = 0
CVREF
CVROE = 1
From VREF Module
A = Analog Input, port reads zeros always, overrides TRISA bit(2).
D = Digital Input.
CIS (CMCON<3>) is the Comparator Input Switch; CVROE (CVRCON<6>) is the Voltage Reference Output Switch.
Note 1:
2:
RA4 must be configured as an output pin in TRISA<4> when used to output C1OUT. RA5 ignores TRISA<5> when
used as an output for C2OUT.
Mode 110 is exception. Comparator input pins obey TRISA bits.
DS39599G-page 222
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
20.2
Comparator Operation
20.3.2
INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 20-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 20-2 represent
the uncertainty due to input offsets and response time.
The comparator module also allows the selection of an
internally generated voltage reference for the comparators. Section 21.0 “Comparator Voltage Reference
Module” contains a detailed description of the comparator voltage reference module that provides this signal.
The internal reference signal is used when comparators
are in mode, CM2:CM0 = 110 (Figure 20-1). In this
mode, the internal voltage reference is applied to the
VIN+ pin of both comparators.
20.3
Depending on the setting of the CVROE bit
(CVRCON<6>), the voltage reference may also be
available on pin RA2.
Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal present at VIN- is compared to the signal
at VIN+ and the digital output of the comparator is
adjusted accordingly (Figure 20-2).
FIGURE 20-2:
SINGLE COMPARATOR
VIN+
+
VIN-
–
Output
20.4
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (see Table 26-2 in
Section 26.0 “Electrical Characteristics”).
20.5
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RA4 and RA5
I/O pins. When enabled, multiplexers in the output path
of the RA4 and RA5 pins will switch and the output of
each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 20-3 shows the
comparator output block diagram.
VIN
VIN–
VIN
+
VIN+
Output
Output
The TRISA bits will still function as an output enable/
disable for the RA4 and RA5 pins while in this mode.
20.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the comparators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
© 2007 Microchip Technology Inc.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5>).
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
DS39599G-page 223
PIC18F2220/2320/4220/4320
FIGURE 20-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
CxINV
To RA4 or
RA5 Pin
Bus
Data
Q
Read CMCON
Set
CMIF
bit
D
EN
Q
From
Other
Comparator
D
EN
CL
Read CMCON
Reset
20.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the Comparator Interrupt Flag. The
CMIF bit is cleared by firmware. Since it is also possible
to write a ‘1’ to this register, a simulated interrupt may
be initiated.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
DS39599G-page 224
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of CMCON will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
20.7
Comparator Operation in
Power-Managed Modes
20.9
When a comparator is active and the device is placed
in a power-managed mode, the comparator remains
active and the interrupt is functional if enabled. This
interrupt will wake-up the device from a powermanaged mode when enabled. Each operational
comparator will consume additional current, as shown
in the comparator specifications. To minimize power
consumption while in a power-managed mode, turn off
the comparators (CM<2:0> = 111) before entering the
power-managed modes. If the device wakes up from a
power-managed mode, the contents of the CMCON
register are not affected.
20.8
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Therefore, the analog input must be between
VSS and VDD. If the input voltage exceeds this range by
more than 0.6V, one of the diodes is forward biased
and a latch-up condition may occur. A maximum source
impedance of 10 kΩ is recommended for the analog
sources.
Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the Comparator Reset mode (CM<2:0> = 111). This ensures
that all potential inputs are analog inputs. Device current is minimized when digital inputs are present at
Reset time. The comparators will be powered down
during the Reset interval.
FIGURE 20-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RS < 10k
RIC
Comparator
Input
AIN
CPIN
5 pF
VA
ILEAKAGE
±500 nA
VT = 0.6V
VSS
Legend:
CPIN
VT
ILEAKAGE
RIC
RS
VA
© 2007 Microchip Technology Inc.
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
DS39599G-page 225
PIC18F2220/2320/4220/4320
TABLE 20-1:
Name
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
POR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111 0000 0111
CVRCON
CVREN
CVROE
CVRR
—
CVR3
CVR2
CVR1
CVR0
000- 0000 000- 0000
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR2
OSCFIF
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
00-0 0000 00-0 0000
PIE2
OSCFIE
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
00-0 0000 00-0 0000
IPR2
OSCFIP
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
11-1 1111 11-1 1111
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
xx0x 0000 xx0x 0000
LATA6(1)
PORTA
LATA
LATA7(1)
TRISA
TRISA7(1) TRISA6(1) Data Direction Register
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are unused by the comparator module.
These pins are enabled based on oscillator configuration (see Configuration Register 1H).
Note 1:
DS39599G-page 226
Data Output Register
xxxx xxxx xxxx xxxx
1111 1111 1111 1111
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
21.0
COMPARATOR VOLTAGE
REFERENCE MODULE
21.1
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two
ranges of CVREF values and has a power-down function to conserve power when the reference is not being
used. The CVRCON register controls the operation of
the reference as shown in Register 21-1. The block
diagram is given in Figure 21-1.
Configuring the Comparator
Voltage Reference
The comparator voltage reference can output 16 distinct
voltage levels for each range. The equations used to calculate the output of the comparator voltage reference
are as follows:
EQUATION 21-1:
If CVRR = 1:
VDD
CVREF = (CVR<3:0>) •
24
The comparator reference supply voltage comes from
VDD and VSS.
If CVRR = 0:
VDD
CVREF = (CVR<3:0> + 8) • 32
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 26-2 in Section 26.0 “Electrical
Characteristics”).
REGISTER 21-1:
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE(1)
CVRR
—
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6
CVROE: Comparator VREF Output Enable bit(1)
1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin
0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = 0.00 VDD to 0.667 VDD, with VDD/24 step size
0 = 0.25 VDD to 0.75 VDD, with VDD/32 step size
bit 4
Unimplemented: Read as ‘0’
bit 3-0
CVR3:CVR0: Comparator VREF Value Selection 0 ≤ VR3:VR0 ≤ 15 bits
When CVRR = 1:
VDD
CVREF = (CVR<3:0>) •
24
When CVRR = 0:
VDD
CVREF = 1/4 • (CVRSRC) + (CVR<3:0> + 8) •
32
Note 1:
x = Bit is unknown
CVROE overrides the TRISA<2> bit setting.
© 2007 Microchip Technology Inc.
DS39599G-page 227
PIC18F2220/2320/4220/4320
FIGURE 21-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
16 Stages
CVREN
8R
R
R
R
R
CVRR
RA2/AN2/VREF-/CVREF
8R
CVROE
CVREF
21.2
Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 21-1) keep CVREF from approaching the reference source rails. The voltage reference is derived
from VDD; therefore, the CVREF output changes with
fluctuations in VDD. The tested absolute accuracy of
the voltage reference can be found in Section 26.0
“Electrical Characteristics”.
21.3
Operation in Power-Managed
Modes
The contents of the CVRCON register are not affected
by entry to or exit from power-managed modes. To minimize current consumption in power-managed modes,
the voltage reference module should be disabled; however, this can cause an interrupt from the comparators
so the comparator interrupt should also be disabled
while the CVRCON register is being modified.
DS39599G-page 228
16-1 Analog Mux
21.4
CVR3
(From CVRCON<3:0>)
CVR0
Effects of a Reset
A device Reset disables the voltage reference by clearing the CVRCON register. This also disconnects the
reference from the RA2 pin, selects the high-voltage
range and selects the lowest voltage tap from the
resistor divider.
21.5
Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be output using the RA2 pin if the
CVROE bit is set. Enabling the voltage reference output onto the RA2 pin, with an input signal present, will
increase current consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, an external buffer must be used on the
voltage reference output for external connections to
VREF. Figure 21-2 shows an example buffering
technique.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 21-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
R(1)
CVREF
Module
RA2
+
–
CVREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration bits (CVRCON<3:0> and CVRCON<5>).
TABLE 21-1:
Name
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
CVRCON CVREN CVROE
CVRR
—
CVR3
CVR2
CVR1
CVR0
000- 0000 000- 0000
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111 0000 0111
TRISA
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
Note 1: These pins are enabled based on oscillator configuration (see Configuration Register 1H).
© 2007 Microchip Technology Inc.
DS39599G-page 229
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 230
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
22.0
LOW-VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application software can do “housekeeping tasks” before the device
voltage exits the valid operating range. This can be
done using the Low-Voltage Detect (LVD) module.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower then the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the interrupt vector address and the software can then respond
to that interrupt source.
The Low-Voltage Detect circuitry is completely under
software control. This allows the circuitry to be turned
off by the software which minimizes the current
consumption for the device.
Figure 22-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
The block diagram for the LVD module is shown in
Figure 22-2. A comparator uses an internally generated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage reference module. The comparator then generates an
interrupt signal setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 22-2). The trip point is selected by programming
the LVDL3:LVDL0 bits (LVDCON<3:0>).
TYPICAL LOW-VOLTAGE DETECT APPLICATION
Voltage
FIGURE 22-1:
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut down the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference, TB – TA, is the total
time for shutdown.
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
Time
© 2007 Microchip Technology Inc.
TA
TB
DS39599G-page 231
PIC18F2220/2320/4220/4320
FIGURE 22-2:
LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM
LVDIN
LVD Control
Register
16-to-1 MUX
VDD
Internally Generated
Reference Voltage
1.2V
LVDEN
The LVD module has an additional feature that allows
the user to supply the sense voltage to the module
from an external source. This mode is enabled when
bits LVDL3:LVDL0 are set to ‘1111’. In this state, the
comparator input is multiplexed from the external input
FIGURE 22-3:
LVDIF
pin, LVDIN (Figure 22-3). This gives users flexibility
because it allows them to configure the Low-Voltage
Detect interrupt to occur at any voltage in the valid
operating range.
LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
16-to-1 MUX
LVD Control
Register
LVDIN
Externally Generated
Trip Point
LVDEN
LVD
VxEN
BODEN
EN
BGAP
DS39599G-page 232
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
22.1
Control Register
The Low-Voltage Detect Control register controls the
operation of the Low-Voltage Detect circuitry.
REGISTER 22-1:
U-0
LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER
U-0
—
—
R-0
IRVST
R/W-0
LVDEN
R/W-0
(1)
LVDL3
R/W-1
LVDL2
(1)
R/W-0
LVDL1
(1)
R/W-1
LVDL0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage
range
0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified
voltage range and the LVD interrupt should not be enabled
bit 4
LVDEN: Low-Voltage Detect Power Enable bit
1 = Enables LVD, powers up LVD circuit
0 = Disables LVD, powers down LVD circuit
bit 3-0
LVDL3:LVDL0: Low-Voltage Detection Limit bits(1)
1111 = External analog input is used (input comes from the LVDIN pin)
1110 = 4.50V-4.78V
1101 = 4.20V-4.46V
1100 = 4.00V-4.26V
1011 = 3.80V-4.04V
1010 = 3.60V-3.84V
1001 = 3.50V-3.72V
1000 = 3.30V-3.52V
0111 = 3.00V-3.20V
0110 = 2.80V-2.98V
0101 = 2.70V-2.86V
0100 = 2.50V-2.66V
0011 = 2.40V-2.55V
0010 = 2.20V-2.34V
0001 = 2.00V-2.12V
0000 = Reserved
Note 1:
LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested.
© 2007 Microchip Technology Inc.
DS39599G-page 233
PIC18F2220/2320/4220/4320
22.2
Operation
The following steps are needed to set up the LVD
module:
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be
constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for
short periods where the voltage is checked. After doing
the check, the LVD module may be disabled.
1.
2.
3.
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4.
5.
6.
Write the value to the LVDL3:LVDL0 bits
(LVDCON register) which selects the desired
LVD trip point.
Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Wait for the LVD module to stabilize (the IRVST
bit to become set).
Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 22-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 22-4:
LOW-VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIRVST
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIRVST
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
DS39599G-page 234
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
22.2.1
REFERENCE VOLTAGE SET POINT
The internal reference voltage of the LVD module may
be used by other internal circuitry (the Programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low-voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low-voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 22-4.
22.2.2
CURRENT CONSUMPTION
22.3
Operation During Sleep
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
22.4
Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
© 2007 Microchip Technology Inc.
DS39599G-page 235
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 236
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
23.0
SPECIAL FEATURES OF THE
CPU
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost
immediately on start-up while the primary clock source
completes its start-up delays.
PIC18F2X20/4X20 devices include several features
intended to maximize system reliability and minimize
cost through elimination of external components.
These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
23.1
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh)
which can only be accessed using table reads and
table writes.
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2X20/4X20
devices have a Watchdog Timer which is either permanently enabled via the Configuration bits or software
controlled (if configured as disabled).
TABLE 23-1:
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
Configuration register. In normal operation mode, a
TBLWT instruction, with the TBLPTR pointing to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
CONFIGURATION BITS AND DEVICE IDS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
CONFIG1H
IESO
FSCM
—
—
FOSC3
FOSC2
FOSC1
FOSC0
11-- 1111
—
BORV1
BORV0
BOR
File Name
300001h
Configuration Bits
300002h
CONFIG2L
—
—
—
300003h
CONFIG2H
—
—
—
300005h
CONFIG3H
MCLRE
—
—
—
300006h
CONFIG4L
DEBUG
—
—
—
—
300008h
CONFIG5L
—
—
—
—
CP3(2)
300009h
CONFIG5H
CPD
CPB
—
—
—
30000Ah
CONFIG6L
—
—
—
—
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
—
30000Ch
CONFIG7L
—
—
—
—
30000Dh
CONFIG7H
—
EBTRB
—
—
—
DEV2
DEV1
DEV0
REV4
DEV10
DEV9
DEV8
DEV7
3FFFFEh DEVID1(1)
(1)
PWRT
---- 1111
WDTEN
---1 1111
PBAD
CCP2MX
1--- --11
LVP
—
STVR
1--- -1-1
CP2(2)
CP1
CP0
---- 1111
—
—
—
11-- ----
WRT3(2)
WRT2(2)
WRT1
WRT0
---- 1111
—
—
111- ----
WDTPS3 WDTPS2 WDTPS1 WDTPS0
—
—
—
—
EBTR1
EBTR0
---- 1111
—
—
—
-1-- ----
REV3
REV2
REV1
REV0
xxxx xxxx(1)
DEV6
DEV5
DEV4
DEV3
0000 0101
EBTR3(2) EBTR2(2)
3FFFFFh
DEVID2
Legend:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
See Register 23-12 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
Unimplemented in PIC18FX220 devices; maintain this bit set.
Note 1:
2:
© 2007 Microchip Technology Inc.
DS39599G-page 237
PIC18F2220/2320/4220/4320
REGISTER 23-1:
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-1
R/P-1
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
IESO
FSCM
—
—
FOSC3
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7
IESO: Internal/External Switchover bit
1 = Internal/External Switchover mode enabled
0 = Internal/External Switchover mode disabled
bit 6
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
FOSC3:FOSC0: Oscillator Selection bits(1)
11xx = External RC oscillator, CLKO function on RA6
1001 = Internal oscillator block, CLKO function on RA6 and port function on RA7
1000 = Internal oscillator block, port function on RA6 and port function on RA7
0111 = External RC oscillator, port function on RA6
0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
0101 = EC oscillator, port function on RA6
0100 = EC oscillator, CLKO function on RA6
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator
DS39599G-page 238
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 23-2:
U-0
CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0
—
—
U-0
—
U-0
—
R/P-1
BORV1
R/P-1
BORV0
R/P-1
(1)
BOR
bit 7
R/P-1
PWRTEN(1)
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7-4
Unimplemented: Read as ‘0’
bit 3-2
BORV1:BORV0: Brown-out Reset Voltage bits
11 = VBOR set to 2.0V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
bit 1
BOR: Brown-out Reset enable bit(1)
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
bit 0
PWRT: Power-up Timer enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
Note 1:
The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled.
© 2007 Microchip Technology Inc.
DS39599G-page 239
PIC18F2220/2320/4220/4320
REGISTER 23-3:
U-0
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
—
—
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
—
WDTPS3
WDTPS2
WDTPS1
WDTPS0
WDTEN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7-5
Unimplemented: Read as ‘0’
bit 4-1
WDPS<3:0>: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
bit 0
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
DS39599G-page 240
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 23-4:
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1
U-0
U-0
U-0
U-0
U-0
R/P-1
R/P-1
MCLRE
—
—
—
—
—
PBAD
CCP2MX
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7
MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled; RE3 input pin disabled
0 = MCLR disabled; RE3 input is enabled in 40-pin devices only (PIC18F4X20)
bit 6-2
Unimplemented: Read as ‘0’
bit 1
PBAD: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin
configuration.)
1 = PORTB<4:0> pins are configured as analog input channels on Reset
0 = PORTB<4:0> pins are configured as digital I/O on Reset
bit 0
CCP2MX: CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
REGISTER 23-5:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
U-0
U-0
U-0
U-0
R/P-1
U-0
R/P-1
DEBUG
—
—
—
—
LVP
—
STVR
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6-3
Unimplemented: Read as ‘0’
bit 2
LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
STVR: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
© 2007 Microchip Technology Inc.
DS39599G-page 241
PIC18F2220/2320/4220/4320
REGISTER 23-6:
U-0
CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
U-0
—
—
U-0
—
U-0
—
R/C-1
R/C-1
(1)
(1)
CP3
CP2
R/C-1
R/C-1
CP1
CP0
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-4
Unimplemented: Read as ‘0’
bit 3
CP3: Code Protection bit(1)
1 = Block 3 (001800-001FFFh) not code-protected
0 = Block 3 (001800-001FFFh) code-protected
bit 2
CP2: Code Protection bit(1)
1 = Block 2 (001000-0017FFh) not code-protected
0 = Block 2 (001000-0017FFh) code-protected
bit 1
CP1: Code Protection bit
1 = Block 1 (000800-000FFFh) not code-protected
0 = Block 1 (000800-000FFFh) code-protected
bit 0
CP0: Code Protection bit
1 = Block 0 (000200-0007FFh) not code-protected
0 = Block 0 (000200-0007FFh) code-protected
Note 1:
Unimplemented in PIC18FX220 devices; maintain this bit set.
REGISTER 23-7:
CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1
R/C-1
U-0
U-0
U-0
U-0
U-0
U-0
CPD
CPB
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7
CPD: Data EEPROM Code Protection bit
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
bit 6
CPB: Boot Block Code Protection bit
1 = Boot block (000000-0001FFh) is not code-protected
0 = Boot block (000000-0001FFh) is code-protected
bit 5-0
Unimplemented: Read as ‘0’
DS39599G-page 242
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 23-8:
CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
WRT3(1)
WRT2(1)
WRT1
WRT0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7-4
Unimplemented: Read as ‘0’
bit 3
WRT3: Write Protection bit(1)
1 = Block 3 (001800-001FFFh) not write-protected
0 = Block 3 (001800-001FFFh) write-protected
bit 2
WRT2: Write Protection bit(1)
1 = Block 2 (001000-0017FFh) not write-protected
0 = Block 2 (001000-0017FFh) write-protected
bit 1
WRT1: Write Protection bit
1 = Block 1 (000800-000FFFh) not write-protected
0 = Block 1 (000800-000FFFh) write-protected
bit 0
WRT0: Write Protection bit
1 = Block 0 (000200-0007FFh) not write-protected
0 = Block 0 (000200-0007FFh) write-protected
Note 1:
Unimplemented in PIC18FX220 devices; maintain this bit set.
REGISTER 23-9:
CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
R/P-1
R/P-1
R-1
U-0
U-0
U-0
U-0
U-0
WRTD
WRTB
WRTC(1)
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7
WRTD: Data EEPROM Write Protection bit
1 = Data EEPROM is not write-protected
0 = Data EEPROM is write-protected
bit 6
WRTB: Boot Block Write Protection bit
1 = Boot block (000000-0001FFh) is not write-protected
0 = Boot block (000000-0001FFh) is write-protected
bit 5
WRTC: Configuration Register Write Protection bit(1)
1 = Configuration registers (300000-3000FFh) are not write-protected
0 = Configuration registers (300000-3000FFh) are write-protected
bit 4-0
Unimplemented: Read as ‘0’
Note 1:
This bit is read-only in normal execution mode; it can be written only in Program mode.
© 2007 Microchip Technology Inc.
DS39599G-page 243
PIC18F2220/2320/4220/4320
REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
EBTR3(1)
EBTR2(1)
EBTR1
EBTR0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7-4
Unimplemented: Read as ‘0’
bit 3
EBTR3: Table Read Protection bit(1)
1 = Block 3 (001800-001FFFh) not protected from table reads executed in other blocks
0 = Block 3 (001800-001FFFh) protected from table reads executed in other blocks
bit 2
EBTR2: Table Read Protection bit(1)
1 = Block 2 (001000-0017FFh) not protected from table reads executed in other blocks
0 = Block 2 (001000-0017FFh) protected from table reads executed in other blocks
bit 1
EBTR1: Table Read Protection bit
1 = Block 1 (000800-000FFFh) not protected from table reads executed in other blocks
0 = Block 1 (000800-000FFFh) protected from table reads executed in other blocks
bit 0
EBTR0: Table Read Protection bit
1 = Block 0 (000200-0007FFh) not protected from table reads executed in other blocks
0 = Block 0 (000200-0007FFh) protected from table reads executed in other blocks
Note 1:
Unimplemented in PIC18FX220 devices; maintain this bit set.
REGISTER 23-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0
R/P-1
U-0
U-0
U-0
U-0
U-0
U-0
—
EBTRB
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7
Unimplemented: Read as ‘0’
bit 6
EBTRB: Boot Block Table Read Protection bit
1 = Boot block (000000-0001FFh) is not protected from table reads executed in other blocks
0 = Boot block (000000-0001FFh) is protected from table reads executed in other blocks
bit 5-0
Unimplemented: Read as ‘0’
DS39599G-page 244
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 23-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2220/2320/4220/4320 DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
bit 7-5
DEV2:DEV0: Device ID bits
000 = PIC18F2320
001 = PIC18F4320
100 = PIC18F2220
101 = PIC18F4220
bit 4-0
REV3:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 23-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2220/2320/4220/4320 DEVICES
R
(1)
DEV10
R
R
R
R
R
R
R
DEV9(1)
DEV8(1)
DEV7(1)
DEV6(1)
DEV5(1)
DEV4(1)
DEV3(1)
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
-n = Value when device is unprogrammed
bit 7-0
Note 1:
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the
part number.
0000 0101 = PIC18F2220/2320/4220/4320 devices
These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified
by using the entire DEV10:DEV0 bit sequence.
© 2007 Microchip Technology Inc.
DS39599G-page 245
PIC18F2220/2320/4220/4320
23.2
Watchdog Timer (WDT)
For PIC18F2X20/4X20 devices, the WDT is driven by
the INTRC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: execute a SLEEP or CLRWDT instruction, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits
(OSCCON<6:4> clears the WDT and
postscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
23.2.1
CONTROL REGISTER
Register 23-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
Adjustments to the internal oscillator clock period using
the OSCTUNE register also affect the period of the
WDT by the same factor. For example, if the INTRC
period is increased by 3%, then the WDT period is
increased by 3%.
FIGURE 23-1:
WDT BLOCK DIAGRAM
SWDTEN
WDTEN
Enable WDT
INTRC Control
WDT Counter
INTRC Source
Wake-up
from Sleep
÷125
Change on IRCF bits
Programmable Postscaler
1:1 to 1:32,768
CLRWDT
All Device Resets
WDTPS<3:0>
Reset
WDT
Reset
WDT
4
Sleep
DS39599G-page 246
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
REGISTER 23-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
SWDTEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1:
This bit has no effect if the Configuration bit, WDTEN (CONFIG2H<0>), is enabled.
TABLE 23-2:
Name
CONFIG2H
RCON
WDTCON
x = Bit is unknown
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
WDTPS3
WDTPS2
WDTPS2
WDTPS0
WDTEN
IPEN
—
—
RI
TO
PD
POR
BOR
—
—
—
—
—
—
—
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
© 2007 Microchip Technology Inc.
DS39599G-page 247
PIC18F2220/2320/4220/4320
23.3
Two-Speed Start-up
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IFRC2:IFRC0 prior to entering Sleep mode.
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is
available. It is enabled by setting the IESO bit in
Configuration Register 1H (CONFIG1H<7>).
In all other power-managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
Two-Speed Start-up is available only if the primary oscillator mode is LP, XT, HS or HSPLL (Crystal-Based
modes). Other sources do not require a OST start-up
delay; for these, Two-Speed Start-up is disabled.
23.3.1
While using the INTRC oscillator in Two-Speed Start-up,
the device still obeys the normal command sequences
for entering power-managed modes, including serial
SLEEP instructions (refer to Section 3.1.3 “Multiple
Sleep Commands”). In practice, this means that user
code can change the SCS1:SCS0 bit settings and issue
SLEEP commands before the OST times out. This would
allow an application to briefly wake-up, perform routine
“housekeeping” tasks and return to Sleep before the
device starts to operate from the primary oscillator.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the internal oscillator block as the clock source, following the
time-out of the Power-up Timer after a POR Reset is
enabled. This allows almost immediate code execution
while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically
switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits IFRC2:IFRC0 immediately after
FIGURE 23-2:
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
User code can also check if the primary clock source is
currently providing the system clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the system clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Q1
Q2
Q3
Q4
Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
INTOSC
Multiplexer
OSC1
TOST(1)
TPLL(1)
PLL Clock
Output
1
2
3 4 5 6
Clock Transition
7
8
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake from Interrupt Event
Note
PC + 2
PC + 4
PC + 6
OSTS bit Set
1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
DS39599G-page 248
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
23.4
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation, in the event of an
external oscillator failure, by automatically switching
the system clock to the internal oscillator block. The
FSCM function is enabled by setting the Fail-Safe
Clock Monitor Enable bit, FCMEN (CONFIG1H<6>).
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide
an instant backup clock in the event of a clock failure.
Clock monitoring (shown in Figure 23-3) is accomplished by creating a sample clock signal, which is the
INTRC output divided by 64. This allows ample time
between FSCM sample clocks for a peripheral clock
edge to occur. The peripheral system clock and the
sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the
system clock source but cleared on the rising edge of
the sample clock.
FIGURE 23-3:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
INTRC
Source
(32 μs)
÷ 64
S
Q
C
Q
To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits IFRC2:IFRC0
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected
by setting IFRC2:IFRC0 prior to entering Sleep mode.
Adjustments to the internal oscillator block using the
OSCTUNE register also affect the period of the FSCM
by the same factor. This can usually be neglected, as
the clock frequency being monitored is generally much
higher than the sample clock frequency.
The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
23.4.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no
effect on the operation of the INTRC oscillator when the
FSCM is enabled.
As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
Depending on the frequency selected by the
IRCF2:IRCF0 bits, this may mean a substantial change
in the speed of code execution. If the WDT is enabled
with a small prescale value, a decrease in clock speed
allows a WDT time-out to occur and a subsequent
device Reset. For this reason, fail-safe clock events
also reset the WDT and postscaler, allowing it to start
timing from when execution speed was changed and
decreasing the likelihood of an erroneous time-out.
488 Hz
(2.048 ms)
Clock
Failure
Detected
Clock failure is tested on the falling edge of the sample
clock. If a sample clock falling edge occurs while CM is
still set, a clock failure has been detected (Figure 23-4).
This causes the following:
• The FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>)
• The system clock source is switched to the
internal oscillator block (OSCCON is not updated
to show the current clock source – this is the
fail-safe condition)
• The WDT is reset
Since the postscaler frequency from the internal oscillator block may not be sufficiently stable, it may be
desirable to select another clock configuration and
enter an alternate power-managed mode (see
Section 23.3.1 “Special Considerations for Using
Two-Speed Start-up” and Section 3.1.3 “Multiple
Sleep Commands” for more details). This can be
done to attempt a partial recovery or execute a
controlled shutdown.
© 2007 Microchip Technology Inc.
DS39599G-page 249
PIC18F2220/2320/4220/4320
23.4.2
EXITING FAIL-SAFE OPERATION
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On Reset,
the controller starts the primary clock source specified in
Configuration Register 1H (with any required start-up
delays that are required for the oscillator mode, such as
OST or PLL timer). The INTOSC multiplexer provides the
system clock until the primary clock source becomes
ready (similar to a Two-speed Start-up). The clock system
source is then switched to the primary clock (indicated by
the OSTS bit in the OSCCON register becoming set). The
Fail-Safe Clock Monitor then resumes monitoring the
peripheral clock.
FIGURE 23-4:
The primary clock source may never become ready during start-up. In this case, operation is clocked by the
INTOSC multiplexer. The OSCCON register will remain in
its Reset state until a power-managed mode is entered.
Entering a power-managed mode by loading the
OSCCON register and executing a SLEEP instruction
will clear the fail-safe condition. When the fail-safe
condition is cleared, the clock monitor will resume
monitoring the peripheral clock.
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
Note:
CM Test
CM Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
DS39599G-page 250
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
23.4.3
FSCM INTERRUPTS IN
POWER-MANAGED MODES
As previously mentioned, entering a power-managed
mode clears the fail-safe condition. By entering a
power-managed mode, the clock multiplexer selects
the clock source selected by the OSCCON register.
Fail-safe monitoring of the power-managed clock
source resumes in the power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexer. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, the device will not exit the
power-managed mode on oscillator failure. Instead, the
device will continue to operate as before but clocked by
the INTOSC multiplexer. While in Idle mode, subsequent interrupts will cause the CPU to begin executing
instructions while being clocked by the INTOSC multiplexer. The device will not transition to a different clock
source until the fail-safe condition is cleared.
23.4.4
POR OR WAKE FROM SLEEP
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
system clock is EC, RC or INTRC modes, monitoring
can begin immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up time
considerably longer than the FCSM sample clock time,
a false clock failure may be detected. To prevent this,
the internal oscillator block is automatically configured
as the system clock and functions until the primary
clock is stable (the OST and PLL timers have timed
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source.
Note:
The same logic that prevents false oscillator failure interrupts on POR or wake from
Sleep will also prevent the detection of the
oscillator’s failure to start at all following
these events. This can be avoided by
monitoring the OSTS bit and using a timing routine to determine if the oscillator is
taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
As noted in Section 23.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an
alternate power-managed mode while waiting for the
primary system clock to become stable. When the new
powered managed mode is selected, the primary clock
is disabled.
© 2007 Microchip Technology Inc.
DS39599G-page 251
PIC18F2220/2320/4220/4320
23.5
Program Verification and
Code Protection
Each of the five blocks has three code protection bits
associated with them. They are:
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® devices.
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The remainder of the memory is divided into four blocks on binary
boundaries.
Figure 23-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code protection bit associated with each block. The actual locations
of the bits are summarized in Table 23-3.
FIGURE 23-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2X20/4X20
MEMORY SIZE/DEVICE
4 Kbytes
(PIC18F2220/4220)
8 Kbytes
(PIC18F2320/4320)
Address
Range
Boot Block
Boot Block
000000h
0001FFh
Block 0
Block 0
Block Code Protection
Controlled By:
CPB, WRTB, EBTRB
000200h
CP0, WRT0, EBTR0
0007FFh
000800h
Block 1
Block 1
CP1, WRT1, EBTR1
000FFFh
001000h
Unimplemented
Read ‘0’s
Block 2
Unimplemented
Read ‘0’s
Block 3
CP2, WRT2, EBTR2
0017FFh
001800h
CP3, WRT3, EBTR3
001FFFh
002000h
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 23-3:
SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h
CONFIG5L
—
—
—
—
CP3
CP2
CP1
CP0
300009h
CONFIG5H
CPD
CPB
—
—
—
—
—
—
30000Ah
CONFIG6L
—
—
—
—
WRT3
WRT2
WRT1
WRT0
30000Bh
CONFIG6H
WRTD
WRTB
WRTC
—
—
—
—
—
30000Ch
CONFIG7L
—
—
—
—
EBTR3
EBTR2
EBTR1
EBTR0
30000Dh
CONFIG7H
—
EBTRB
—
—
—
—
—
—
Legend:
Shaded cells are unimplemented.
DS39599G-page 252
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
23.5.1
PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 23-6 through 23-8
illustrate table write and table read protection.
Note:
In normal execution mode, the CPx bits have no direct
effect. CPx bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTx Configuration bit is ‘0’. The EBTRx
bits control table reads. For a block of user memory
with the EBTRx bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
FIGURE 23-6:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
TABLE WRITE (WRTx) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
000200h
TBLPTR = 0002FFh
PC = 0007FEh
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
TBLWT *
0007FFh
000800h
WRT1, EBTR1 = 11
000FFFh
001000h
PC = 0017FEh
WRT2, EBTR2 = 11
TBLWT *
0017FFh
001800h
WRT3, EBTR3 = 11
001FFFh
Results: All table writes disabled to Blockn whenever WRTx = 0.
© 2007 Microchip Technology Inc.
DS39599G-page 253
PIC18F2220/2320/4220/4320
FIGURE 23-7:
EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
000200h
TBLPTR = 0002FFh
PC = 000FFEh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
TBLRD *
0007FFh
000800h
000FFFh
001000h
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
0017FFh
001800h
WRT3, EBTR3 = 11
001FFFh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0.
TABLAT register returns a value of ‘0’.
FIGURE 23-8:
EXTERNAL BLOCK TABLE READ (EBTRx) ALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
000200h
TBLPTR = 0002FFh
PC = 0007FEh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
TBLRD *
0007FFh
000800h
WRT1, EBTR1 = 11
000FFFh
001000h
WRT2, EBTR2 = 11
0017FFh
001800h
WRT3, EBTR3 = 11
001FFFh
Results: Table reads permitted within Blockn, even when EBTRBx = 0.
TABLAT register returns the value of the data at the location TBLPTR.
DS39599G-page 254
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
23.5.2
DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM
regardless of the protection bit settings.
23.5.3
CONFIGURATION REGISTER
PROTECTION
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
23.6
ID Locations
Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions,
or during program/verify. The ID locations can be read
when the device is code-protected.
23.7
23.9
In-Circuit Debugger
When the DEBUG bit in Configuration register,
CONFIG4L, is programmed to a ‘0’, the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB®
IDE. When the microcontroller has this feature
enabled, some resources are not available for general
use. Table 23-4 shows which resources are required by
the background debugger.
TABLE 23-4:
DEBUGGER RESOURCES
I/O pins:
RB6, RB7
Stack:
2 levels
Program Memory:
512 bytes
Data Memory:
10 bytes
© 2007 Microchip Technology Inc.
Low-Voltage ICSP Programming
The LVP bit in Configuration Register 4L
(CONFIG4L<2>) enables Low-Voltage ICSP Programming (LVP). When LVP is enabled, the microcontroller
can be programmed without requiring high voltage
being applied to the MCLR/VPP pin, but the RB5/PGM
pin is then dedicated to controlling Program mode entry
and is not available as a general purpose I/O pin.
LVP is enabled in erased devices.
While programming using LVP, VDD is applied to the
MCLR/VPP pin as in normal execution mode. To enter
Programming mode, VDD is applied to the PGM pin.
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pin, by applying VIHH
to the MCLR pin.
2: When Low-Voltage Programming is
enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
In-Circuit Serial Programming
PIC18F2X20/4X20 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed (see Table 23-5).
23.8
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, VSS,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
3: When LVP is enabled, externally pull the
PGM pin to VSS to allow normal program
execution.
If Low-Voltage ICSP Programming mode will not be
used, the LVP bit can be cleared and RB5/PGM
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP pin). Once LVP has been disabled, only the standard high-voltage programming is available and must
be used to program the device.
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
erased, a block erase is required. If a block erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with VDD of 4.5V to 5.5V.
TABLE 23-5:
Signal
Pin
PGD
RB7
ICSP™/ICD CONNECTIONS
PGC
RB6
MCLR
MCLR
VDD
VDD
VSS
VSS
PGM
RB5
Notes
May require isolation from
application circuits
Pull RB5 low if LVP is enabled
DS39599G-page 255
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 256
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
24.0
INSTRUCTION SET SUMMARY
The PIC18 instruction set adds many enhancements to
the previous PIC MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction
sets.
Most instructions are a single program memory word
(16 bits) but there are three instructions that require two
program memory locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•
•
•
•
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
The PIC18 instruction set summary in Table 24-2 lists
byte-oriented, bit-oriented, literal and control operations. Table 24-1 shows the opcode field descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The destination of the result
(specified by ‘d’)
The accessed memory
(specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The bit in the file register
(specified by ‘b’)
The accessed memory
(specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register designator ‘f’ represents the number of the file in which the
bit is located.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
© 2007 Microchip Technology Inc.
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
All instructions are a single word except for three double word instructions. These three instructions were
made double word instructions so that all the required
information is available in these 32 bits. In the second
word, the 4 MSbs are ‘1’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
The double word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
Figure 24-1 shows the general formats that the
instructions can have.
All examples use the format ‘nnh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal
digit.
The Instruction Set Summary, shown in Table 24-2,
lists the instructions recognized by the Microchip
Assembler (MPASMTM). Section 24.2 “Instruction
Set” provides a description of each instruction.
24.1 READ-MODIFY-WRITE OPERATIONS
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified and
the result is stored according to either the instruction or
the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that
register.
For example, a “BCF PORTB,1” instruction will read
PORTB, clear bit 1 of the data, then write the result
back to PORTB. The read operation would have the
unintended result that any condition that sets the RBIF
flag would be cleared. The R-M-W operation may also
copy the level of an input pin to its corresponding output
latch.
DS39599G-page 257
PIC18F2220/2320/4220/4320
TABLE 24-1:
OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
d
Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest
Destination either the WREG register or the specified register file location.
f
8-bit register file address (0x00 to 0xFF).
fs
12-bit register file address (0x000 to 0xFFF). This is the source address.
fd
12-bit register file address (0x000 to 0xFFF). This is the destination address.
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label
Label name.
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No Change to register (such as TBLPTR with table reads and writes).
*+
Post-Increment register (such as TBLPTR with table reads and writes).
*-
Post-Decrement register (such as TBLPTR with table reads and writes).
Pre-Increment register (such as TBLPTR with table reads and writes).
+*
n
The relative address (2’s complement number) for relative branch instructions, or the direct address for
Call/Branch and Return instructions.
PRODH
Product of Multiply High Byte.
PRODL
Product of Multiply Low Byte.
s
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or Unchanged.
WREG
Working register (accumulator).
x
Don’t care (‘0’ or ‘1’).
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
21-bit Table Pointer (points to a Program Memory location).
TABLAT
8-bit Table Latch.
TOS
Top-of-Stack.
PC
Program Counter.
PCL
Program Counter Low Byte.
PCH
Program Counter High Byte.
PCLATH
Program Counter High Byte Latch.
PCLATU
Program Counter Upper Byte Latch.
GIE
Global Interrupt Enable bit.
WDT
Watchdog Timer.
TO
Time-out bit.
PD
Power-down bit.
C, DC, Z, OV, N
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
[
]
Optional.
(
)
Contents.
→
Assigned to.
< >
Register bit field.
∈
In the set of.
italics
User-defined term (font is Courier New).
DS39599G-page 258
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 24-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15
10
9 8 7
OPCODE d
a
Example Instruction
0
f (FILE #)
ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
OPCODE
15
0
f (Source FILE #)
12 11
MOVFF MYREG1, MYREG2
0
f (Destination FILE #)
1111
f = 12-bit file register address
Bit-oriented file register operations
15
12 11
9 8 7
OPCODE b (BIT #) a
0
BSF MYREG, bit, B
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
OPCODE
0
k (literal)
MOVLW 0x7F
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
OPCODE
15
0
n<7:0> (literal)
12 11
GOTO Label
0
n<19:8> (literal)
1111
n = 20-bit immediate value
15
8 7
OPCODE
15
S
0
CALL MYFUNC
n<7:0> (literal)
12 11
0
n<19:8> (literal)
S = Fast bit
15
OPCODE
15
OPCODE
© 2007 Microchip Technology Inc.
11 10
0
BRA MYFUNC
n<10:0> (literal)
8 7
n<7:0> (literal)
0
BC MYFUNC
DS39599G-page 259
PIC18F2220/2320/4220/4320
TABLE 24-2:
PIC18FXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
16-Bit Instruction Word
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f s, f d
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
SUBWF
SUBWFB
f, d, a
f, d, a
SWAPF
TSTFSZ
XORWF
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, Skip =
Compare f with WREG, Skip >
Compare f with WREG, Skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
Borrow
Subtract WREG from f
Subtract WREG from f with
Borrow
Swap Nibbles in f
Test f, Skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1
1
1
1
1
1
1
1
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1
1
0101 11da
0101 10da
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N 1, 2
1
0011 10da
1 (2 or 3) 0110 011a
1
0001 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
1
1
1 (2 or 3)
1 (2 or 3)
1
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
None
None
C, DC, Z, OV, N 1, 2
C, Z, N
Z, N
1, 2
C, Z, N
Z, N
None
C, DC, Z, OV, N 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, d, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39599G-page 260
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 24-2:
PIC18FXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
16-Bit Instruction Word
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
n
n
n
n
n
n
n
n
n
n, s
CLRWDT
DAW
GOTO
—
—
n
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
RETLW
RETURN
SLEEP
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
s
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call Subroutine1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to Address 1st word
2nd word
No Operation
No Operation (Note 4)
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS)
Relative Call
Software Device Reset
Return from Interrupt Enable
k
s
—
Return with Literal in WREG
Return from Subroutine
Go into Standby mode
1
1
1
1
2
1
2
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
2
2
1
0000 1100
0000 0000
0000 0000
kkkk
0001
0000
1
1
2
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
None
None
None
None
None
None
None
None
None
None
TO, PD
C, DC
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
kkkk None
001s None
0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
© 2007 Microchip Technology Inc.
DS39599G-page 261
PIC18F2220/2320/4220/4320
TABLE 24-2:
PIC18FXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
16-Bit Instruction Word
MSb
LSb
Status
Affected
Notes
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Add Literal and WREG
AND Literal with WREG
Inclusive OR Literal with WREG
Move Literal (12-bit) 2nd word
to FSRx 1st word
Move Literal to BSR<3:0>
Move Literal to WREG
Multiply Literal with WREG
Return with Literal in WREG
Subtract WREG from Literal
Exclusive OR Literal with
WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*TBLRD+*
TBLWT*
TBLWT*+
TBLWT*TBLWT+*
Table Read
2
Table Read with Post-Increment
Table Read with Post-Decrement
Table Read with Pre-Increment
Table Write
2 (5)
Table Write with Post-Increment
Table Write with Post-Decrement
Table Write with Pre-Increment
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39599G-page 262
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
24.2
Instruction Set
ADDLW
ADD Literal to W
Syntax:
[ label ] ADDLW
Operands:
0 ≤ k ≤ 255
Operation:
(W) + k → W
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1111
k
kkkk
kkkk
Description:
The contents of W are added to the
8-bit literal ‘k’ and the result is
placed in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
ADDLW
0x15
Before Instruction
W
=
0x10
ADDWF
ADD W to f
Syntax:
[ label ] ADDWF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) + (f) → dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0010
01da
f [,d [,a]]
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’,
the BSR is used.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
0x25
Example:
ADDWF
REG, W
Before Instruction
W
REG
=
=
0x17
0xC2
After Instruction
W
REG
© 2007 Microchip Technology Inc.
=
=
0xD9
0xC2
DS39599G-page 263
PIC18F2220/2320/4220/4320
ADDWFC
ADD W and Carry bit to f
ANDLW
AND Literal with W
Syntax:
[ label ] ADDWFC
Syntax:
[ label ] ANDLW
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
f [,d [,a]]
Operation:
(W) + (f) + (C) → dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0010
Description:
1
Cycles:
1
0 ≤ k ≤ 255
Operation:
(W) .AND. k → W
Status Affected:
N, Z
Encoding:
ffff
ffff
Add W, the Carry flag and data
memory location ‘f’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank
will be selected. If ‘a’ is ‘1’, the BSR
will not be overridden.
Words:
0000
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
ADDWFC
REG, W
kkkk
kkkk
The contents of W are ANDed with
the 8-bit literal ‘k’. The result is
placed in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read literal
‘k’
Process
Data
Write to W
ANDLW
0x5F
Before Instruction
W
=
0xA3
After Instruction
W
Example:
1011
Description:
Example:
Q Cycle Activity:
Q1
Decode
00da
Operands:
k
=
0x03
Before Instruction
Carry bit =
REG
=
W
=
1
0x02
0x4D
After Instruction
Carry bit =
REG
=
W
=
DS39599G-page 264
0
0x02
0x50
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
f [,d [,a]]
Operation:
(W) .AND. (f) → dest
Status Affected:
N, Z
Encoding:
0001
ffff
ffff
Operands:
-128 ≤ n ≤ 127
Operation:
if Carry bit is ‘1’,
(PC) + 2 + 2n → PC
Status Affected:
None
1110
0010
nnnn
nnnn
Words:
1
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
ANDWF
REG, W
Before Instruction
=
=
0x17
0xC2
After Instruction
=
=
n
1
Cycles:
W
REG
[ label ] BC
If the Carry bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is
then a two-cycle instruction.
Words:
W
REG
Syntax:
Description:
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected. If ‘a’ is ‘1’, the BSR will
not be overridden (default).
Example:
Branch if Carry
Encoding:
01da
Description:
Decode
BC
0x02
0xC2
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Decode
Example:
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
HERE
BC
JUMP
Before Instruction
PC
=
address (HERE)
=
=
=
=
1;
address (JUMP)
0;
address (HERE + 2)
After Instruction
If Carry
PC
If Carry
PC
© 2007 Microchip Technology Inc.
DS39599G-page 265
PIC18F2220/2320/4220/4320
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operation:
0 → f<b>
Status Affected:
None
Encoding:
1001
Description:
Branch if Negative
Syntax:
[ label ] BN
Operands:
-128 ≤ n ≤ 127
Operation:
if Negative bit is ‘1’,
(PC) + 2 + 2n → PC
Status Affected:
None
Encoding:
bbba
ffff
ffff
1110
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BCF
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
FLAG_REG,
7
n
0110
nnnn
nnnn
Description:
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is
then a two-cycle instruction.
Words:
1
Cycles:
1(2)
Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
Decode
f,b[,a]
BN
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Decode
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BN
Jump
Before Instruction
PC
=
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
After Instruction
If Negative
PC
If Negative
PC
DS39599G-page 266
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
Syntax:
[ label ] BNN
Operands:
-128 ≤ n ≤ 127
Operands:
-128 ≤ n ≤ 127
Operation:
if Carry bit is ‘0’,
(PC) + 2 + 2n → PC
Operation:
if Negative bit is ‘0’,
(PC) + 2 + 2n → PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
n
0011
nnnn
nnnn
Encoding:
1110
n
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is
then a two-cycle instruction.
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is
then a two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
BNC
Jump
Before Instruction
PC
Decode
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BNN
Jump
Before Instruction
=
address (HERE)
After Instruction
If Carry
PC
If Carry
PC
If No Jump:
Q1
PC
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
After Instruction
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
© 2007 Microchip Technology Inc.
If Negative
PC
If Negative
PC
DS39599G-page 267
PIC18F2220/2320/4220/4320
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
Syntax:
[ label ] BNZ
Operands:
-128 ≤ n ≤ 127
Operands:
-128 ≤ n ≤ 127
Operation:
if Overflow bit is ‘0’,
(PC) + 2 + 2n → PC
Operation:
if Zero bit is ‘0’,
(PC) + 2 + 2n → PC
Status Affected:
None
Status Affected:
None
Encoding:
1110
n
0101
nnnn
nnnn
Encoding:
1110
n
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is
then a two-cycle instruction.
Description:
If the Zero bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is
then a two-cycle instruction.
Words:
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
BNOV Jump
Before Instruction
PC
DS39599G-page 268
Decode
Example:
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
HERE
BNZ
Jump
Before Instruction
=
address (HERE)
After Instruction
If Overflow
PC
If Overflow
PC
If No Jump:
Q1
PC
=
address (HERE)
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
After Instruction
=
=
=
=
0;
address (Jump)
1;
address (HERE + 2)
If Zero
PC
If Zero
PC
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
BRA
Unconditional Branch
BSF
Bit Set f
Syntax:
[ label ] BRA
Syntax:
[ label ] BSF
Operands:
-1024 ≤ n ≤ 1023
Operands:
Operation:
(PC) + 2 + 2n → PC
Status Affected:
None
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operation:
1 → f<b>
Status Affected:
None
Encoding:
Description:
1101
1
Cycles:
2
Q Cycle Activity:
Q1
No
operation
0nnn
nnnn
nnnn
Add the 2’s complement number
‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words:
Decode
n
Q2
Q3
Q4
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
Encoding:
HERE
BRA
Jump
PC
=
address (HERE)
=
address (Jump)
After Instruction
PC
© 2007 Microchip Technology Inc.
ffff
ffff
Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’,
Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
BSF
FLAG_REG, 7
Before Instruction
FLAG_REG
Before Instruction
bbba
Description:
Example:
Example:
1000
f,b[,a]
=
0x0A
=
0x8A
After Instruction
FLAG_REG
DS39599G-page 269
PIC18F2220/2320/4220/4320
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f,b[,a]
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0≤b<7
a ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
skip if (f<b>) = 1
Status Affected:
None
Status Affected:
None
Encoding:
1011
bbba
ffff
ffff
Encoding:
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruction fetched during the current
instruction execution is discarded
and a NOP is executed instead, making this a two-cycle instruction. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected
as per the BSR value (default).
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruction fetched during the current
instruction execution is discarded
and a NOP is executed instead, making this a two-cycle instruction. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected
as per the BSR value (default).
Words:
1
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note:
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process Data
No
operation
If skip:
Q Cycle Activity:
Q1
Decode
3 cycles if skip and followed
by a 2-word instruction.
Q2
Q3
Q4
Read
register ‘f’
Process Data
No
operation
If skip:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1
Before Instruction
PC
DS39599G-page 270
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1
Before Instruction
=
address (HERE)
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
Example:
PC
=
address (HERE)
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
After Instruction
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
If FLAG<1>
PC
If FLAG<1>
PC
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
[ label ] BTG f,b[,a]
Syntax:
[ label ] BOV
Operands:
0 ≤ f ≤ 255
0≤b<7
a ∈ [0,1]
Operands:
-128 ≤ n ≤ 127
Operation:
if Overflow bit is ‘1’,
(PC) + 2 + 2n → PC
Status Affected:
None
Operation:
(f<b>) → f<b>
Status Affected:
None
Encoding:
Description:
bbba
ffff
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BTG
PORTC,
4
Before Instruction:
PORTC
=
0111 0101 [0x75]
After Instruction:
PORTC
ffff
1110
=
0110 0101 [0x65]
0100
nnnn
nnnn
Description:
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is
then a two-cycle instruction.
Words:
1
Cycles:
1(2)
Bit ‘b’ in data memory location ‘f’ is
inverted. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
Decode
Encoding:
0111
n
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Decode
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
Example:
HERE
BOV
JUMP
Before Instruction
PC
=
address (HERE)
=
=
=
=
1;
address (JUMP)
0;
address (HERE + 2)
After Instruction
If Overflow
PC
If Overflow
PC
© 2007 Microchip Technology Inc.
DS39599G-page 271
PIC18F2220/2320/4220/4320
BZ
Branch if Zero
CALL
Subroutine Call
Syntax:
[ label ] BZ
Syntax:
[ label ] CALL k [,s]
Operands:
-128 ≤ n ≤ 127
Operands:
Operation:
if Zero bit is ‘1’,
(PC) + 2 + 2n → PC
0 ≤ k ≤ 1048575
s ∈ [0,1]
Operation:
(PC) + 4 → TOS,
k → PC<20:1>;
if s = 1,
(W) → WS,
(STATUS) → STATUSS,
(BSR) → BSRS
Status Affected:
None
Status Affected:
n
None
Encoding:
1110
Description:
0000
nnnn
nnnn
If the Zero bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is
then a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
Read literal
‘n’
Process
Data
No
operation
If No Jump:
Q1
Decode
Example:
HERE
BZ
Jump
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k19kkk
k7kkk
kkkk
Description:
Subroutine call of entire 2 Mbyte
memory range. First, return
address (PC + 4) is pushed onto
the return stack. If ‘s’ = 1, the W,
STATUS and BSR registers are
also pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If ‘s’ = 0, no update
occurs (default). Then, the 20-bit
value ‘k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
Push PC to
stack
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Before Instruction
PC
=
address (HERE)
=
=
=
=
1;
address (Jump)
0;
address (HERE + 2)
After Instruction
If Zero
PC
If Zero
PC
kkkk0
kkkk8
Example:
HERE
CALL
THERE,FAST
Before Instruction
PC
=
address (HERE)
After Instruction
PC
=
TOS
=
WS
=
BSRS
=
STATUSS=
DS39599G-page 272
address (THERE)
address (HERE + 4)
W
BSR
STATUS
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
000h → f,
1→Z
Status Affected:
Z
Encoding:
Description:
0110
f [,a]
101a
ffff
ffff
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD
Status Affected:
TO, PD
Encoding:
0000
0000
0000
0100
Clears the contents of the specified
register. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Decode
Example:
Example:
CLRF
FLAG_REG
Before Instruction
FLAG_REG
Q3
Q4
Process
Data
No
operation
CLRWDT
Before Instruction
WDT Counter
=
0x5A
=
0x00
After Instruction
FLAG_REG
Q2
No
operation
© 2007 Microchip Technology Inc.
=
?
=
=
=
=
0x00
0
1
1
After Instruction
WDT Counter
WDT Postscaler
TO
PD
DS39599G-page 273
PIC18F2220/2320/4220/4320
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
( f ) → dest
Status Affected:
N, Z
Encoding:
0001
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Syntax:
[ label ] CPFSEQ
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110
001a
f [,a]
ffff
ffff
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If ‘f’ = W, then the fetched instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Q2
Q3
Q4
Words:
1
Process
Data
Write to
destination
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
COMF
Before Instruction
=
0x13
After Instruction
REG
W
ffff
Compare f with W, Skip if f = W
Read
register ‘f’
Example:
REG
ffff
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
Decode
11da
f [,d [,a]]
CPFSEQ
=
=
0x13
0xEC
REG, W
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NEQUAL
EQUAL
CPFSEQ REG
:
:
Before Instruction
PC Address
W
REG
=
=
=
HERE
?
?
=
=
≠
=
W;
Address (EQUAL)
W;
Address (NEQUAL)
After Instruction
If REG
PC
If REG
PC
DS39599G-page 274
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
CPFSGT
Compare f with W, Skip if f > W
CPFSLT
Compare f with W, Skip if f < W
Syntax:
[ label ] CPFSGT
Syntax:
[ label ] CPFSLT
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) − (W),
skip if (f) > (W)
(unsigned comparison)
Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
Description:
0110
010a
f [,a]
ffff
ffff
Compares the contents of data
memory location ‘f’ to the contents
of the W by performing an
unsigned subtraction.
If the contents of ‘f’ are greater than
the contents of WREG, then the
fetched instruction is discarded and
a NOP is executed instead, making
this a two-cycle instruction. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
ffff
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If the contents of ‘f’ are less than
the contents of W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’
is ‘1’, the BSR will not be
overridden (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
NLESS
LESS
CPFSLT REG
:
:
No
operation
No
operation
No
operation
No
operation
No
operation
HERE
NGREATER
GREATER
CPFSGT REG
:
:
Before Instruction
=
=
Address (HERE)
?
>
=
≤
=
W;
Address (GREATER)
W;
Address (NGREATER)
After Instruction
© 2007 Microchip Technology Inc.
ffff
No
operation
No
operation
If REG
PC
If REG
PC
000a
No
operation
No
operation
PC
W
0110
No
operation
No
operation
Example:
Encoding:
f [,a]
Example:
Before Instruction
PC
W
=
=
Address (HERE)
?
<
=
≥
=
W;
Address (LESS)
W;
Address (NLESS)
After Instruction
If REG
PC
If REG
PC
DS39599G-page 275
PIC18F2220/2320/4220/4320
DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
[ label ] DAW
Syntax:
[ label ] DECF f [,d [,a]]
Operands:
None
Operands:
Operation:
If [W<3:0> >9] or [DC = 1] then,
(W<3:0>) + 6 → W<3:0>;
else,
(W<3:0>) → W<3:0>;
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest
Status Affected:
C, DC, N, OV, Z
If [W<7:4> >9] or [C = 1] then,
(W<7:4>) + 6 → W<7:4>;
else,
(W<7:4>) → W<7:4>
Status Affected:
0000
Encoding:
0000
0000
0000
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Process
Data
Write
W
Example1:
DAW
ffff
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
Read
register W
ffff
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
0111
DAW adjusts the eight-bit value in
W, resulting from the earlier addition of two variables (each in
packed BCD format) and produces
a correct packed BCD result. The
carry bit may be set by DAW regardless of its setting prior to the DAW
execution.
01da
Description:
C, DC
Description:
Decode
Encoding:
DECF
CNT,
Before Instruction
CNT
Z
=
=
0x01
0
After Instruction
CNT
Z
=
=
0x00
1
Before Instruction
W
C
DC
=
=
=
0xA5
0
0
After Instruction
W
C
DC
=
=
=
0x05
1
0
Example 2:
Before Instruction
W
C
DC
=
=
=
0xCE
0
0
After Instruction
W
C
DC
=
=
=
DS39599G-page 276
0x34
1
0
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
DECFSZ
Decrement f, Skip if 0
DCFSNZ
Decrement f, Skip if not 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Syntax:
[ label ] DCFSNZ
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected:
None
Status Affected:
None
Encoding:
0010
11da
ffff
ffff
Encoding:
0100
11da
f [,d [,a]]
ffff
ffff
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next instruction which is already fetched is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
DECFSZ
GOTO
CNT
LOOP
Example:
CONTINUE
Before Instruction
PC
=
=
=
=
≠
=
DCFSNZ
:
:
TEMP
Before Instruction
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
HERE
ZERO
NZERO
TEMP
=
?
=
=
=
≠
=
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
After Instruction
CNT – 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
© 2007 Microchip Technology Inc.
TEMP
If TEMP
PC
If TEMP
PC
DS39599G-page 277
PIC18F2220/2320/4220/4320
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 1048575
Operands:
Operation:
k → PC<20:1>
Status Affected:
None
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest
Status Affected:
C, DC, N, OV, Z
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
1110
1111
GOTO k
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
GOTO allows an unconditional
branch anywhere within entire
2 Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTO is always a two-cycle
instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example:
GOTO THERE
After Instruction
PC =
Address (THERE)
Encoding:
0010
INCF
f [,d [,a]]
10da
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
INCF
CNT,
Before Instruction
CNT
Z
C
DC
=
=
=
=
0xFF
0
?
?
After Instruction
CNT
Z
C
DC
DS39599G-page 278
=
=
=
=
0x00
1
1
1
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
INCFSZ
Increment f, Skip if 0
INFSNZ
Increment f, Skip if Not 0
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) + 1 → dest,
skip if result = 0
Operation:
(f) + 1 → dest,
skip if result ≠ 0
Status Affected:
None
Status Affected:
None
Encoding:
0011
INCFSZ
11da
f [,d [,a]]
ffff
ffff
Encoding:
0100
INFSNZ
10da
f [,d [,a]]
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
1
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
If skip:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
Before Instruction
PC
=
=
=
=
≠
=
Example:
HERE
ZERO
NZERO
INFSNZ
REG
Before Instruction
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
CNT
PC
=
Address (HERE)
After Instruction
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
© 2007 Microchip Technology Inc.
REG
If REG
PC
If REG
PC
=
≠
=
=
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
DS39599G-page 279
PIC18F2220/2320/4220/4320
IORLW
Inclusive OR Literal with W
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .OR. (f) → dest
Status Affected:
N, Z
IORLW k
Operands:
0 ≤ k ≤ 255
Operation:
(W) .OR. k → W
Status Affected:
N, Z
Encoding:
0000
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
kkkk
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
IORLW
Before Instruction
=
0x9A
After Instruction
W
kkkk
The contents of W are OR’ed with
the eight-bit literal ‘k’. The result is
placed in W.
Words:
W
1001
=
0x35
Encoding:
0001
IORWF
00da
f [,d [,a]]
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If
‘d’ is ‘0’, the result is placed in W. If
‘d’ is ‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
0xBF
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
IORWF
RESULT, W
Before Instruction
RESULT =
W
=
0x13
0x91
After Instruction
RESULT =
W
=
DS39599G-page 280
0x13
0x93
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
LFSR
Load FSR
MOVF
Move f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0≤f≤2
0 ≤ k ≤ 4095
Operands:
Operation:
k → FSRf
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Status Affected:
None
Operation:
f → dest
Status Affected:
N, Z
Encoding:
LFSR f,k
1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description:
The 12-bit literal ‘k’ is loaded into
the file select register pointed to
by ‘f’.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example:
LFSR 2, 0x3AB
After Instruction
FSR2H
FSR2L
=
=
0x03
0xAB
Encoding:
MOVF
0101
00da
f [,d [,a]]
ffff
ffff
Description:
The contents of register ‘f’ are
moved to a destination dependent
upon the status of ‘d’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed back in register ‘f’
(default). Location ‘f’ can be anywhere in the 256-byte bank. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write W
MOVF
REG, W
Before Instruction
REG
W
=
=
0x22
0xFF
=
=
0x22
0x22
After Instruction
REG
W
© 2007 Microchip Technology Inc.
DS39599G-page 281
PIC18F2220/2320/4220/4320
MOVFF
Move f to f
MOVLB
Move Literal to Low Nibble in BSR
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095
Operands:
0 ≤ k ≤ 255
Operation:
k → BSR
None
MOVFF fs,fd
Operation:
(fs) → fd
Status Affected:
Status Affected:
None
Encoding:
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
Description:
ffff
ffff
ffff
ffff
ffffs
ffffd
The contents of source register ‘fs’
are moved to destination register
‘fd’. Location of source ‘fs’ can be
anywhere in the 4096-byte data
space (000h to FFFh) and location
of destination ‘fd’ can also be
anywhere from 000h to FFFh.
Either source or destination can be
W (a useful special situation).
MOVFF is particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
MOVLB k
0000
0001
kkkk
kkkk
Description:
The 8-bit literal ‘k’ is loaded into
the Bank Select Register (BSR).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read literal
‘k’
Process
Data
Write
literal ‘k’ to
BSR
MOVLB
5
Before Instruction
BSR register
=
0x02
=
0x05
After Instruction
BSR register
The MOVFF instruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
The MOVFF instruction should not
be used to modify interrupt settings
while any interrupt is enabled (see
Page 87).
Words:
2
Cycles:
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register ‘f’
(dest)
No dummy
read
Example:
MOVFF
REG1, REG2
Before Instruction
REG1
REG2
=
=
0x33
0x11
=
=
0x33,
0x33
After Instruction
REG1
REG2
DS39599G-page 282
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k→W
0 ≤ f ≤ 255
a ∈ [0,1]
Status Affected:
None
Operation:
(W) → f
Status Affected:
None
Encoding:
0000
Description:
MOVLW k
1110
kkkk
The eight-bit literal ‘k’ is loaded into
W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
MOVLW
0x5A
After Instruction
W
kkkk
=
0x5A
Encoding:
0110
Description:
111a
f [,a]
ffff
ffff
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the
Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
MOVWF
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
MOVWF
REG
Before Instruction
W
REG
=
=
0x4F
0xFF
After Instruction
W
REG
© 2007 Microchip Technology Inc.
=
=
0x4F
0x4F
DS39599G-page 283
PIC18F2220/2320/4220/4320
MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(W) x (f) → PRODH:PRODL
Status Affected:
None
MULLW
k
Operands:
0 ≤ k ≤ 255
Operation:
(W) x k → PRODH:PRODL
Status Affected:
None
Encoding:
Description:
0000
1
Cycles:
1
Q Cycle Activity:
Q1
Example:
kkkk
kkkk
An unsigned multiplication is
carried out between the contents
of W and the 8-bit literal ‘k’. The
16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the Status flags are
affected.
Note that neither overflow nor
carry is possible in this operation. A zero result is possible but
not detected.
Words:
Decode
1101
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
MULLW
0xC4
Before Instruction
W
PRODH
PRODL
=
=
=
0xE2
?
?
=
=
=
0xE2
0xAD
0x08
Encoding:
Description:
0000
001a
1
Cycles:
1
Q Cycle Activity:
Q1
Example:
ffff
ffff
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
After Instruction
W
PRODH
PRODL
f [,a]
An unsigned multiplication is
carried out between the contents
of W and the register file location
‘f’. The 16-bit result is stored in
the PRODH:PRODL register
pair. PRODH contains the high
byte.
Both W and ‘f’ are unchanged.
None of the Status flags are
affected.
Note that neither overflow nor
carry is possible in this operation. A zero result is possible but
not detected. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If
‘a’= 1, then the bank will be
selected as per the BSR value
(default).
Words:
Decode
MULWF
MULWF
REG
Before Instruction
W
REG
PRODH
PRODL
=
=
=
=
0xC4
0xB5
?
?
=
=
=
=
0xC4
0xB5
0x8A
0x94
After Instruction
W
REG
PRODH
PRODL
DS39599G-page 284
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
NEGF
Negate f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
NEGF
Operation:
(f)+1→f
Status Affected:
N, OV, C, DC, Z
Encoding:
0110
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Syntax:
[ label ]
NOP
Operands:
None
Operation:
No operation
Status Affected:
None
0000
1111
ffff
Description:
1
Cycles:
1
Decode
0000
xxxx
0000
xxxx
No operation.
Words:
Q Cycle Activity:
Q1
0000
xxxx
Q2
Q3
Q4
No
operation
No
operation
No
operation
Example:
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
No Operation
Encoding:
ffff
Location ‘f’ is negated using two’s
complement. The result is placed in
the data memory location ‘f’. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value.
Words:
Decode
110a
f [,a]
NOP
NEGF
None.
REG, 1
Before Instruction
REG
=
0011 1010 [0x3A]
After Instruction
REG
=
1100 0110 [0xC6]
© 2007 Microchip Technology Inc.
DS39599G-page 285
PIC18F2220/2320/4220/4320
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
(TOS) → bit bucket
Operation:
(PC + 2) → TOS
Status Affected:
None
Status Affected:
None
Encoding:
0000
POP
0000
0000
0110
Encoding:
0000
PUSH
0000
0000
0101
Description:
The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the previous value that was pushed onto the
return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Description:
The PC + 2 is pushed onto the top
of the return stack. The previous
TOS value is pushed down on the
stack.
This instruction allows to implement
a software stack by modifying TOS,
and then push it onto the return
stack.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
operation
POP TOS
value
No
operation
POP
GOTO
NEW
Example:
Example:
=
=
Q2
Q3
Q4
PUSH PC+2
onto return
stack
No
operation
No
operation
PUSH
Before Instruction
Before Instruction
TOS
Stack (1 level down)
Decode
0x0031A2
0x014332
TOS
PC
=
=
0x00345A
0x000124
=
=
=
0x000126
0x000126
0x00345A
After Instruction
After Instruction
TOS
PC
DS39599G-page 286
=
=
0x014332
NEW
PC
TOS
Stack (1 level down)
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
Syntax:
[ label ]
Operands:
Operation:
-1024 ≤ n ≤ 1023
Operands:
None
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Operation:
Reset all registers and flags that
are affected by a MCLR Reset.
Status Affected:
None
Status Affected:
All
Encoding:
Description:
1101
1nnn
nnnn
nnnn
Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ‘2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the
new address will be PC + 2 + 2n.
This instruction is a two-cycle
instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
n
Encoding:
0000
RESET
0000
1111
1111
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Start
reset
No
operation
No
operation
RESET
After Instruction
Q2
Q3
Q4
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
Registers =
Flags*
=
Reset Value
Reset Value
Push PC to
stack
No
operation
Example:
No
operation
HERE
RCALL Jump
Before Instruction
PC =
Address (HERE)
After Instruction
PC =
TOS =
Address (Jump)
Address (HERE + 2)
© 2007 Microchip Technology Inc.
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PIC18F2220/2320/4220/4320
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
RETFIE [s]
RETLW k
Operands:
s ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL;
if s = 1,
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Operation:
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
Status Affected:
None
Status Affected:
0000
Description:
0000
0001
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
operation
pop PC from
stack
Set GIEH or
GIEL
No
operation
RETFIE
No
operation
No
operation
1
After Interrupt
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
DS39599G-page 288
kkkk
kkkk
W is loaded with the eight-bit literal
‘k’. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
pop PC from
stack, Write
to W
No
operation
No
operation
No
operation
No
operation
Example:
No
operation
Example:
1100
Description:
000s
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low-priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
W, STATUS and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words:
No
operation
0000
GIE/GIEH, PEIE/GIEL.
Encoding:
Decode
Encoding:
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PCL ;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
W contains table
offset value
W now has
table value
W = offset
Begin table
End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of kn
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n+1>,
(f<7>) → C,
(C) → dest<0>
Status Affected:
C, N, Z
RETURN [s]
Operands:
s ∈ [0,1]
Operation:
(TOS) → PC;
if s = 1,
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected:
None
Encoding:
0000
Encoding:
0000
0001
001s
Description:
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’= 1, the contents of the
shadow registers WS, STATUSS
and BSRS are loaded into their corresponding registers, W, STATUS
and BSR. If ‘s’ = 0, no update of
these registers occurs (default).
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
0011
Description:
01da
Q3
Q4
Decode
No
operation
Process
Data
pop PC from
stack
No
operation
No
operation
No
operation
No
operation
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
After Interrupt
PC = TOS
ffff
register f
Q2
Q3
Q4
Process
Data
Write to
destination
RLCF
REG, W
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
© 2007 Microchip Technology Inc.
ffff
Read
register ‘f’
Example:
RETURN
f [,d [,a]]
The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
C
Q2
Example:
RLCF
=
=
=
1110 0110
1100 1100
1
DS39599G-page 289
PIC18F2220/2320/4220/4320
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Operation:
Status Affected:
N, Z
(f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
C, N, Z
Encoding:
0100
Description:
RLNCF
01da
f [,d [,a]]
ffff
ffff
The contents of register ‘f’ are
rotated one bit to the left. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Encoding:
0011
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
RLNCF
REG
Before Instruction
REG
=
1010 1011
After Instruction
REG
=
ffff
ffff
register f
C
Q2
Example:
00da
f [,d [,a]]
The contents of register ‘f’ are
rotated one bit to the right through
the Carry Flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
register f
Words:
RRCF
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
RRCF
REG, W
Before Instruction
0101 0111
REG
C
=
=
1110 0110
0
After Instruction
REG
W
C
DS39599G-page 290
=
=
=
1110 0110
0111 0011
0
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ]
Syntax:
[ label ] SETF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
(f<n>) → dest<n-1>,
(f<0>) → dest<7>
Operation:
FFh → f
Operation:
Status Affected:
None
Status Affected:
N, Z
Encoding:
0100
Description:
RRNCF
00da
f [,d [,a]]
Encoding:
ffff
ffff
The contents of register ‘f’ are
rotated one bit to the right. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as
per the BSR value (default).
register f
Words:
1
Cycles:
1
100a
ffff
ffff
Description:
The contents of the specified register are set to FFh. If ‘a’ is ‘0’, the
Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as
per the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write
register ‘f’
SETF
REG
Before Instruction
Q Cycle Activity:
Q1
Decode
0110
f [,a]
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF
REG
=
0x5A
=
0xFF
After Instruction
REG
REG, 1, 0
Before Instruction
REG
=
1101 0111
After Instruction
REG
=
Example 2:
1110 1011
RRNCF
REG, W
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
© 2007 Microchip Technology Inc.
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PIC18F2220/2320/4220/4320
SLEEP
Enter Sleep mode
SUBFWB
Subtract f from W with Borrow
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SUBFWB
Operands:
None
Operands:
Operation:
00h → WDT,
0 → WDT postscaler,
1 → TO,
0 → PD
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) – (f) – (C) → dest
Status Affected:
N, OV, C, DC, Z
Status Affected:
TO, PD
Encoding:
0000
Encoding:
0000
0000
0011
Description:
The Power-Down status bit (PD)
is cleared. The Time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
No
operation
Process
Data
Go to
Sleep
Example:
SLEEP
Before Instruction
TO =
PD =
?
?
After Instruction
TO =
PD =
1†
0
† If WDT causes wake-up, this bit is cleared.
0101
01da
f [,d [,a]]
ffff
ffff
Description:
Subtract register ‘f’ and carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored in register ‘d’ (default). If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example 1:
SUBFWB REG
Before Instruction
REG
W
C
=
=
=
0x03
0x02
0x01
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 2:
0xFF
0x02
0x00
0x00
0x01
SUBFWB
; result is negative
REG, 0, 0
Before Instruction
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 3:
2
3
1
0
0
; result is positive
SUBFWB
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
Z
N
DS39599G-page 292
=
=
=
=
=
0
2
1
1
0
; result is zero
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
[ label ] SUBLW k
Syntax:
[ label ] SUBWF
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k – (W) → W
Status Affected:
N, OV, C, DC, Z
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) → dest
Status Affected:
N, OV, C, DC, Z
Encoding:
0000
1000
kkkk
kkkk
Description:
W is subtracted from the eight-bit
literal ‘k’. The result is placed in
W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
Example 1:
SUBLW
0x02
Before Instruction
W
C
=
=
1
?
=
=
=
=
Example 2:
1
1
0
0
SUBLW
=
=
=
=
=
=
Example 3:
0
1
1
0
SUBLW
=
=
; result is zero
0x02
=
=
=
=
1
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
SUBWF
REG
Before Instruction
=
=
=
3
2
?
REG
W
C
Z
N
=
=
=
=
=
Example 2:
1
2
1
0
0
; result is positive
SUBWF
REG, W
Before Instruction
REG
W
C
3
?
After Instruction
W
C
Z
N
Cycles:
After Instruction
Before Instruction
W
C
1
REG
W
C
After Instruction
W
C
Z
N
ffff
Words:
Example 1:
2
?
ffff
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is
‘1’, the result is stored back in
register ‘f’ (default). If = ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
; result is positive
0x02
11da
Description:
Decode
Before Instruction
W
C
0101
Q Cycle Activity:
Q1
After Instruction
W
C
Z
N
Encoding:
f [,d [,a]]
FF
0
0
1
; (2’s complement)
; result is negative
=
=
=
2
2
?
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 3:
2
0
1
1
0
; result is zero
SUBWF
REG
Before Instruction
REG
W
C
=
=
=
0x01
0x02
?
After Instruction
REG
W
C
Z
N
© 2007 Microchip Technology Inc.
=
=
=
=
=
0xFFh ;(2’s complement)
0x02
0x00 ; result is negative
0x00
0x01
DS39599G-page 293
PIC18F2220/2320/4220/4320
SUBWFB
Subtract W from f with Borrow
Syntax:
[ label ] SUBWFB
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – (W) – (C) → dest
Status Affected:
N, OV, C, DC, Z
Encoding:
Description:
0101
1
Cycles:
1
Q Cycle Activity:
Q1
10da
ffff
ffff
REG, 1, 0
Before Instruction
REG
W
C
=
=
=
REG
W
C
Z
N
=
=
=
=
=
Example 2:
0x19
0x0D
0x01
(0001 1001)
(0000 1101)
0x0C
0x0D
0x01
0x00
0x00
(0000 1011)
(0000 1101)
; result is positive
SUBWFB REG, 0, 0
Before Instruction
REG
W
C
=
=
=
0x1B
0x1A
0x00
(0001 1011)
(0001 1010)
0x1B
0x00
0x01
0x01
0x00
(0001 1011)
After Instruction
REG
W
C
Z
N
=
=
=
=
=
Example 3:
SUBWFB
; result is zero
REG, 1, 0
Before Instruction
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
DS39599G-page 294
SUBWFB
After Instruction
Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default). If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Words:
Decode
f [,d [,a]]
Example 1:
REG
W
C
=
=
=
0x03
0x0E
0x01
(0000 0011)
(0000 1101)
(1111 0100)
; [2’s comp]
(0000 1101)
After Instruction
REG
=
0xF5
W
C
Z
N
=
=
=
=
0x0E
0x00
0x00
0x01
; result is negative
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
SWAPF
Swap f
Syntax:
[ label ] SWAPF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Affected:
None
Encoding:
0011
Description:
ffff
ffff
The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’,
the result is placed in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
10da
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
SWAPF
REG
Before Instruction
REG
=
0x53
After Instruction
REG
=
0x35
© 2007 Microchip Technology Inc.
DS39599G-page 295
PIC18F2220/2320/4220/4320
TBLRD
Table Read
TBLRD
Table Read (cont’d)
Syntax:
[ label ]
Example1:
TBLRD
Operands:
None
Operation:
if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT,
TBLPTR - No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT,
(TBLPTR) +1 → TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT,
(TBLPTR) -1 → TBLPTR;
if TBLRD +*,
(TBLPTR) +1 → TBLPTR,
(Prog Mem (TBLPTR)) → TABLAT
TBLRD ( *; *+; *-; +*)
Before Instruction
Status Affected:None
Encoding:
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *=3 +*
Description:
This instruction is used to read the
contents of Program Memory (P.M.). To
address the program memory, a pointer
called Table Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 Mbyte address range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLRD instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
DS39599G-page 296
*+ ;
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0x34
=
=
0x34
0x00A357
After Instruction
TABLAT
TBLPTR
Example2:
TBLRD
+* ;
Before Instruction
TABLAT
TBLPTR
MEMORY(0x01A357)
MEMORY(0x01A358)
=
=
=
=
0xAA
0x01A357
0x12
0x34
=
=
0x34
0x01A358
After Instruction
TABLAT
TBLPTR
No
No operation
operation (Write TABLAT)
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TBLWT
Table Write
TBLWT Table Write (Continued)
Syntax:
[ label ]
Words: 1
TBLWT ( *; *+; *-; +*)
Operands:
None
Cycles: 2
Operation:
if TBLWT*,
(TABLAT) → Holding Register,
TBLPTR - No Change;
if TBLWT*+,
(TABLAT) → Holding Register,
(TBLPTR) +1 → TBLPTR;
if TBLWT*-,
(TABLAT) → Holding Register,
(TBLPTR) -1 → TBLPTR;
if TBLWT+*,
(TBLPTR) +1 → TBLPTR,
(TABLAT) → Holding Register
Q Cycle Activity:
Status Affected: None
Encoding:
Description:
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *=3 +*
This instruction uses the 3 LSBs of
TBLPTR to determine which of the 8
holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program
Memory (P.M.). (Refer to Section 6.0
“Flash Program Memory” for
additional details on programming
Flash memory.)
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 MBtye address
range. The LSb of the TBLPTR selects
which byte of the program memory
location to access.
TBLPTR[0] = 0:Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
© 2007 Microchip Technology Inc.
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
No
operation
No
operation
(Read
TABLAT)
No
operation
No
operation
(Write to
Holding
Register )
Example1:
TBLWT
*+;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(0x00A356)
=
=
0x55
0x00A356
=
0xFF
After Instructions (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(0x00A356)
Example 2:
TBLWT
=
=
0x55
0x00A357
=
0x55
+*;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389A
=
0xFF
=
0xFF
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389B
=
0xFF
=
0x34
DS39599G-page 297
PIC18F2220/2320/4220/4320
TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
Syntax:
[ label ] TSTFSZ f [,a]
Syntax:
[ label ] XORLW k
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
skip if f = 0
Operation:
(W) .XOR. k → W
Status Affected:
None
Status Affected:
N, Z
Encoding:
Encoding:
0110
Description:
011a
ffff
ffff
If ‘f’ = 0, the next instruction,
fetched during the current instruction execution is discarded and a
NOP is executed, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’,
then the bank will be selected as
per the BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
No
operation
0000
1010
kkkk
kkkk
Description:
The contents of W are XOR’ed
with the 8-bit literal ‘k’. The result
is placed in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
literal ‘k’
Process
Data
Write to W
Example:
XORLW 0xAF
Before Instruction
W
=
0xB5
After Instruction
W
=
0x1A
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
NZERO
ZERO
TSTFSZ
:
CNT
:
Before Instruction
PC = Address (HERE)
After Instruction
If CNT
PC
If CNT
PC
DS39599G-page 298
=
=
≠
=
0x00,
Address (ZERO)
0x00,
Address (NZERO)
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) .XOR. (f) → dest
Status Affected:
N, Z
Encoding:
0001
10da
f [,d [,a]]
ffff
ffff
Description:
Exclusive OR the contents of W
with register ‘f’. If ‘d’ is ‘0’, the result
is stored in W. If ‘d’ is ‘1’, the result
is stored back in the register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register ‘f’
Process
Data
Write to
destination
Example:
XORWF
REG
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
© 2007 Microchip Technology Inc.
DS39599G-page 299
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 300
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
25.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Programmers
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
25.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Visual device initializer for easy register
initialization
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2007 Microchip Technology Inc.
DS39599G-page 301
PIC18F2220/2320/4220/4320
25.2
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
25.3
MPLAB C18 and MPLAB C30
C Compilers
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
25.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
25.5
MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
25.6
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS39599G-page 302
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
25.7
MPLAB ICE 2000
High-Performance
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
25.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
25.9
MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single stepping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
25.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2007 Microchip Technology Inc.
DS39599G-page 303
PIC18F2220/2320/4220/4320
25.11 PICSTART Plus Development
Programmer
25.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
25.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
DS39599G-page 304
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to VSS ............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2007 Microchip Technology Inc.
DS39599G-page 305
PIC18F2220/2320/4220/4320
FIGURE 26-1:
PIC18F2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
PIC18F2X20/4X20
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 26-2:
PIC18F2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0V
5.5V
Voltage
5.0V
PIC18F2X20/4X20
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
25 MHz
Frequency
DS39599G-page 306
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 26-3:
PIC18LF2220/2320/4220/4320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
PIC18LF2X20/4X20
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
© 2007 Microchip Technology Inc.
DS39599G-page 307
PIC18F2220/2320/4220/4320
26.1
DC Characteristics: Supply Voltage
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
VDD
D001
Characteristic
Min
Typ
Max
Units
Conditions
Supply Voltage
PIC18LF2X20/4X20
2.0
—
5.5
V
PIC18F2X20/4X20
4.2
—
5.5
V
HS, XT, RC and LP Osc mode
D002
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
V
D003
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
0.7
V
D004
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
—
—
VBOR
Brown-out Reset Voltage — Date codes from 0351xxx to 0417xxx, inclusive
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
PIC18LF2X20/4X20 Industrial Low Voltage (-40°C to +125°C)
D005A
D005B
N/A
N/A
N/A
V
BORV1:BORV0 = 10
2.45
2.72
2.99
V
BORV1:BORV0 = 01
3.80
4.22
4.64
V
BORV1:BORV0 = 00
4.09
4.54
4.99
V
Reserved
PIC18F2X20/4X20 Industrial (-40°C to +85°C)
D005C
Legend:
Note 1:
2:
BORV1:BORV0 = 11
BORV1:BORV0 = 1x
N/A
N/A
N/A
V
Reserved
BORV1:BORV0 = 01
3.80
4.22
4.64
V
(Note 2)
BORV1:BORV0 = 00
4.09
4.54
4.99
V
(Note 2)
PIC18F2X20/4X20 Extended (-40°C to +125°C)
BORV1:BORV0 = 1x
N/A
N/A
N/A
V
Reserved
BORV1:BORV0 = 01
3.80
4.22
4.64
V
(Note 2)
BORV1:BORV0 = 00
4.09
4.54
4.99
V
(Note 2)
Shading of rows is to assist in readability of the table.
This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 40 MHz for any VDD at which the BOR allows
execution.
DS39599G-page 308
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.1
DC Characteristics: Supply Voltage
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
VBOR
D005D
D005F
D005G
D005H
D005J
D005K
Legend:
Note 1:
2:
Characteristic
Min
Typ
Max
Units
Conditions
Brown-out Reset Voltage — Date codes above 0417xxx
PIC18LF2X20/4X20 Industrial Low Voltage (-10°C to +85°C)
BORV1:BORV0 = 11
N/A
N/A
N/A
V
BORV1:BORV0 = 10
2.50
2.72
2.94
V
BORV1:BORV0 = 01
3.88
4.22
4.56
V
BORV1:BORV0 = 00
4.18
4.54
4.90
V
Reserved
PIC18LF2X20/4X20 Industrial Low Voltage (-40°C to -10°C)
BORV1:BORV0 = 11
N/A
N/A
N/A
V
BORV1:BORV0 = 10
2.34
2.72
3.10
V
BORV1:BORV0 = 01
3.63
4.22
4.81
V
BORV1:BORV0 = 00
3.90
4.54
5.18
V
Reserved
PIC18F2X20/4X20 Industrial (-10°C to +85°C)
BORV1:BORV0 = 1x
N/A
N/A
N/A
V
Reserved
BORV1:BORV0 = 01
3.88
4.22
4.56
V
(Note 2)
BORV1:BORV0 = 00
4.18
4.54
4.90
V
(Note 2)
PIC18F2X20/4X20 Industrial (-40°C to -10°C)
BORV1:BORV0 = 1x
N/A
N/A
N/A
V
Reserved
BORV1:BORV0 = 01
N/A
N/A
N/A
V
Reserved
BORV1:BORV0 = 00
3.90
4.54
5.18
V
(Note 2)
PIC18F2X20/4X20 Extended (-10°C to +85°C)
BORV1:BORV0 = 1x
N/A
N/A
N/A
V
Reserved
BORV1:BORV0 = 01
3.88
4.22
4.56
V
(Note 2)
BORV1:BORV0 = 00
4.18
4.54
4.90
V
(Note 2)
PIC18F2X20/4X20 Extended (-40°C to -10°C, +85°C to +125°C)
BORV1:BORV0 = 1x
N/A
N/A
N/A
V
Reserved
BORV1:BORV0 = 01
N/A
N/A
N/A
V
Reserved
BORV1:BORV0 = 00
3.90
4.54
5.18
V
(Note 2)
Shading of rows is to assist in readability of the table.
This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
When BOR is on and BORV<1:0> = 0x, the device will operate correctly at 40 MHz for any VDD at which the BOR allows
execution.
© 2007 Microchip Technology Inc.
DS39599G-page 309
PIC18F2220/2320/4220/4320
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
Power-down Current (IPD)(1)
PIC18LF2X20/4X20
PIC18LF2X20/4X20
All devices
Extended devices
Supply Current (IDD)
PIC18LF2X20/4X20
All devices
Extended devices
2:
3:
4:
0.5
μA
-40°C
0.5
μA
+25°C
0.2
1.7
μA
+85°C
0.1
0.5
μA
-40°C
0.1
0.5
μA
+25°C
0.3
1.7
μA
+85°C
VDD = 2.0V
(Sleep mode)
0.1
2.0
μA
-40°C
0.1
2.0
μA
+25°C
0.4
6.5
μA
+85°C
11.2
50
μA
+125°C
VDD = 3.0V
(Sleep mode)
VDD = 5.0V
(Sleep mode)
(2,3)
PIC18LF2X20/4X20
Legend:
Note 1:
0.1
0.1
11
25
μA
-40°C
13
25
μA
+25°C
14
25
μA
+85°C
34
40
μA
-40°C
28
40
μA
+25°C
25
40
μA
+85°C
77
80
μA
-40°C
62
80
μA
+25°C
53
80
μA
+85°C
50
80
μA
+125°C
VDD = 2.0V
VDD = 3.0V
FOSC = 31 kHz
(RC_RUN mode,
internal oscillator source)
VDD = 5.0V
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39599G-page 310
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
100
220
μA
-40°C
110
220
μA
+25°C
120
220
μA
+85°C
180
330
μA
-40°C
180
330
μA
+25°C
170
330
μA
+85°C
Supply Current (IDD)(2,3)
PIC18LF2X20/4X20
PIC18LF2X20/4X20
All devices
Extended devices
PIC18LF2X20/4X20
PIC18LF2X20/4X20
All devices
Extended devices
Legend:
Note 1:
2:
3:
4:
340
550
μA
-40°C
330
550
μA
+25°C
310
550
μA
+85°C
410
650
μA
+125°C
350
600
μA
-40°C
360
600
μA
+25°C
370
600
μA
+85°C
580
900
μA
-40°C
580
900
μA
+25°C
560
900
μA
+85°C
1.1
1.8
mA
-40°C
1.1
1.8
mA
+25°C
1.0
1.8
mA
+85°C
1.2
1.8
mA
+125°C
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHz
(RC_RUN mode,
internal oscillator source)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz
(RC_RUN mode,
internal oscillator source)
VDD = 5.0V
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
DS39599G-page 311
PIC18F2220/2320/4220/4320
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
Supply Current (IDD)(2,3)
PIC18LF2X20/4X20
PIC18LF2X20/4X20
All devices
4:
-40°C
+25°C
5.1
11
μA
+85°C
6.9
11
μA
-40°C
6.3
11
μA
+25°C
6.8
15
μA
+85°C
12
16
μA
-40°C
10
16
μA
+25°C
10
22
μA
+85°C
25
75
μA
+125°C
49
150
μA
-40°C
52
150
μA
+25°C
56
150
μA
+85°C
Extended devices
3:
μA
μA
Extended devices
All devices
2:
8
8
PIC18LF2X20/4X20
PIC18LF2X20/4X20
Legend:
Note 1:
4.7
4.6
73
180
μA
-40°C
77
180
μA
+25°C
+85°C
77
180
μA
130
300
μA
-40°C
130
300
μA
+25°C
130
300
μA
+85°C
350
435
μA
+125°C
VDD = 2.0V
VDD = 3.0V
FOSC = 31 kHz
(RC_IDLE mode,
internal oscillator source)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHz
(RC_IDLE mode,
internal oscillator source)
VDD = 5.0V
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39599G-page 312
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
Supply Current (IDD)(2,3)
PIC18LF2X20/4X20
PIC18LF2X20/4X20
All devices
4:
-40°C
μA
+25°C
150
275
μA
+85°C
220
375
μA
-40°C
220
375
μA
+25°C
210
375
μA
+85°C
390
800
μA
-40°C
400
800
μA
+25°C
380
800
μA
+85°C
+125°C
410
800
μA
150
250
μA
-40°C
150
250
μA
+25°C
160
250
μA
+85°C
340
350
μA
-40°C
300
350
μA
+25°C
280
350
μA
+85°C
Extended devices
3:
μA
275
Extended devices
All devices
2:
275
PIC18LF2X20/4X20
PIC18LF2X20/4X20
Legend:
Note 1:
140
140
0.72
1.0
mA
-40°C
0.63
1.0
mA
+25°C
0.57
1.0
mA
+85°C
0.53
1.0
mA
+125°C
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz
(RC_IDLE mode,
internal oscillator source)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHZ
(PRI_RUN,
EC oscillator)
VDD = 5.0V
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
DS39599G-page 313
PIC18F2220/2320/4220/4320
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
Supply Current (IDD)(2,3)
PIC18LF2X20/4X20
PIC18LF2X20/4X20
All devices
3:
4:
μA
-40°C
600
μA
+25°C
460
600
μA
+85°C
0.80
1.0
mA
-40°C
0.78
1.0
mA
+25°C
0.77
1.0
mA
+85°C
1.6
2.0
mA
-40°C
VDD = 2.0V
VDD = 3.0V
2.0
mA
+25°C
1.5
2.0
mA
+85°C
Extended devices
1.5
2.0
mA
+125°C
Extended devices
6.3
9.0
mA
+125°C
VDD = 4.2V
7.9
10.0
mA
+125°C
VDD = 5.0V
All devices
2:
600
1.5
All devices
Legend:
Note 1:
440
450
9.5
12
mA
-40°C
9.7
12
mA
+25°C
9.9
12
mA
+85°C
11.9
15
mA
-40°C
12.1
15
mA
+25°C
12.3
15
mA
+85°C
FOSC = 4 MHz
(PRI_RUN,
EC oscillator)
VDD = 5.0V
FOSC = 25 MHZ
(PRI_RUN,
EC oscillator)
VDD = 4.2V
FOSC = 40 MHZ
(PRI_RUN,
EC oscillator)
VDD = 5.0V
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39599G-page 314
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
Supply Current (IDD)(2,3)
PIC18LF2X20/4X20
PIC18LF2X20/4X20
All devices
Extended devices
4:
-40°C
+25°C
38
60
μA
+85°C
58
80
μA
-40°C
59
80
μA
+25°C
+85°C
60
100
μA
110
180
μA
-40°C
110
180
μA
+25°C
110
180
μA
+85°C
125
300
μA
+125°C
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 5.0V
180
μA
-40°C
180
μA
+25°C
140
180
μA
+85°C
220
280
μA
-40°C
230
280
μA
+25°C
230
280
μA
+85°C
410
525
μA
-40°C
420
525
μA
+25°C
430
525
μA
+85°C
Extended devices
450
800
μA
+125°C
Extended devices
2.2
3.0
mA
+125°C
VDD = 4.2V
2.7
3.5
mA
+125°C
VDD = 5.0V
All devices
3:
μA
μA
140
PIC18LF2X20/4X20
2:
50
50
140
PIC18LF2X20/4X20
Legend:
Note 1:
37
37
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 5.0V
FOSC = 25 MHZ
(PRI_IDLE,
EC oscillator)
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
DS39599G-page 315
PIC18F2220/2320/4220/4320
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
Supply Current (IDD)(2,3)
All devices
All devices
PIC18LF2X20/4X20
PIC18LF2X20/4X20
All devices
PIC18LF2X20/4X20
PIC18LF2X20/4X20
All devices
Legend:
Note 1:
2:
3:
4:
3.1
4.1
mA
-40°C
3.2
4.1
mA
+25°C
3.3
4.1
mA
+85°C
4.4
5.1
mA
-40°C
4.6
5.1
mA
+25°C
4.6
5.1
mA
+85°C
9
15
μA
-40°C
10
15
μA
+25°C
13
18
μA
+85°C
22
30
μA
-40°C
21
30
μA
+25°C
20
35
μA
+85°C
50
80
μA
-40°C
50
80
μA
+25°C
+85°C
45
85
μA
5.1
9
μA
-40°C
5.8
9
μA
+25°C
7.9
11
μA
+85°C
7.9
12
μA
-40°C
8.9
12
μA
+25°C
10.5
14
μA
+85°C
13
20
μA
-40°C
16
20
μA
+25°C
18
25
μA
+85°C
VDD = 4.2 V
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 32 kHz(4)
(SEC_RUN mode,
Timer1 as clock)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 32 kHz(4)
(SEC_IDLE mode,
Timer1 as clock)
VDD = 5.0V
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39599G-page 316
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD)
D022
(ΔIWDT)
D022A
Watchdog Timer
3:
4:
-40°C
+25°C
2.7
4.0
μA
+85°C
4.6
μA
-40°C
4.6
μA
+25°C
3.1
4.8
μA
+85°C
3.0
10.0
μA
-40°C
3.3
10.0
μA
+25°C
3.9
10.0
μA
+85°C
Extended devices only
4.0
13.0
μA
+125°C
Brown-out Reset
35
50
μA
42
60
μA
Extended devices only
46
65
μA
Low-Voltage Detect
31
45
μA
Extended devices only
2:
μA
μA
2.3
(ΔILVD)
Legend:
Note 1:
3.8
3.8
2.7
(ΔIBOR)
D022B
1.5
2.2
33
50
μA
42
60
μA
46
65
μA
-40°C to +85°C
-40°C to +125°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
-40°C to +85°C
-40°C to +125°C
VDD = 3.0V
VDD = 5.0V
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
© 2007 Microchip Technology Inc.
DS39599G-page 317
PIC18F2220/2320/4220/4320
26.2
DC Characteristics: Power-Down and Supply Current
PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
D025
Device
Timer1 Oscillator
(ΔIOSCB)
A/D Converter
D026
(ΔIAD)
Extended devices only
Legend:
Note 1:
2:
3:
4:
Typ
Max
Units
Conditions
2.1
2.2
μA
-40°C
1.8
2.2
μA
+25°C
2.1
2.2
μA
+85°C
2.2
3.8
μA
-40°C
2.6
3.8
μA
+25°C
2.9
3.8
μA
+85°C
3.0
6.0
μA
-40°C
3.2
6.0
μA
+25°C
VDD = 2.0V
32 kHz on Timer1(4)
VDD = 3.0V
32 kHz on Timer1(4)
VDD = 5.0V
32 kHz on Timer1(4)
3.4
7.0
μA
+85°C
1.0
2.0
μA
-40°C to +85°C
1.0
2.0
μA
-40°C to +85°C
VDD = 3.0V
1.0
2.0
μA
-40°C to +85°C
VDD = 5.0V
1.0
8.0
μA
-40°C to +125°C
VDD = 5.0V
VDD = 2.0V
A/D on, not converting
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
DS39599G-page 318
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.3
DC Characteristics: PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Max
Units
Conditions
with TTL Buffer
VSS
0.15 VDD
V
VDD < 4.5V
—
0.8
V
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger Buffer
RC3 and RC4
VSS
VSS
0.2 VDD
0.3 VDD
V
V
Input Low Voltage
I/O Ports:
D030
D030A
D031
D032
MCLR
VSS
0.2 VDD
V
D032A
OSC1 and T1OSI
VSS
0.2 VDD
V
LP, XT, HS, HSPLL
modes(1)
D033
OSC1
VSS
0.2 VDD
V
EC mode(1)
0.25 VDD + 0.8V
VDD
V
VDD < 4.5V
2.0
VDD
V
4.5V ≤ VDD ≤ 5.5V
0.8 VDD
0.7 VDD
VDD
VDD
V
V
0.8 VDD
VDD
V
1.6
VDD
V
LP, XT, HS, HSPLL
modes(1)
0.8 VDD
VDD
V
EC mode(1)
VIH
Input High Voltage
I/O Ports:
D040
with TTL Buffer
D040A
D041
with Schmitt Trigger Buffer
RC3 and RC4
D042
MCLR
D042A
OSC1 and T1OSI
D043
OSC1
IIL
Input Leakage Current(2,3)
D060
I/O Ports
—
±0.2
μA
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061
MCLR, RA4
—
±1.0
μA
Vss ≤ VPIN ≤ VDD
OSC1
—
±1.0
μA
Vss ≤ VPIN ≤ VDD
50
400
μA
VDD = 5V, VPIN = VSS
D063
D070
Note 1:
2:
3:
4:
IPU
Weak Pull-up Current
IPURB
PORTB Weak Pull-up Current
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Parameter is characterized but not tested.
© 2007 Microchip Technology Inc.
DS39599G-page 319
PIC18F2220/2320/4220/4320
26.3
DC Characteristics: PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Symbol
No.
VOL
D080
Characteristic
D080A
OSC2/CLKO
(RC mode)
D083A
VOH
D090
D090A
OSC2/CLKO
(RC mode)
D092A
D150
VOD
Units
Conditions
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
—
0.6
V
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
—
0.6
V
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
—
0.6
V
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
VDD – 0.7
—
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
VDD – 0.7
—
V
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
VDD – 0.7
—
V
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
VDD – 0.7
—
V
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
—
8.5
V
RA4 pin
Output High Voltage(3)
I/O Ports
D092
Max
Output Low Voltage
I/O Ports
D083
Min
Open-Drain High Voltage
Capacitive Loading Specs
on Output Pins
D100(4) COSC2
OSC2 Pin
—
15
pF
In XT, HS and LP modes
when external clock is
used to drive OSC1
D101
CIO
All I/O Pins and OSC2
(in RC mode)
—
50
pF
To meet the AC Timing
Specifications
D102
CB
SCL, SDA
—
400
pF
In I2C mode
Note 1:
2:
3:
4:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Parameter is characterized but not tested.
DS39599G-page 320
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-1:
MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC Characteristics
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
V
Conditions
Internal Program Memory
Programming Specifications
VPP
Voltage on MCLR/VPP pin
9.00
—
13.25
D112
IPP
Current into MCLR/VPP pin
—
—
300
μA
D113
IDDP
Supply Current during
Programming
—
—
1.0
mA
E/W -40°C to +85°C
E/W -40°C to +125°C
D110
(Note 2)
Data EEPROM Memory
D120
ED
Byte Endurance
100K
10K
1M
100K
—
—
D121
VDRW
VDD for Read/Write
VMIN
—
5.5
D122
TDEW
Erase/Write Cycle Time
—
4
—
D123
TRETD
Characteristic Retention
40
—
—
Year Provided no other
specifications are violated
D124
TREF
Number of Total Erase/Write
Cycles before Refresh(1)
1M
100K
10M
1M
—
—
E/W -40°C to +85°C
E/W -40°C to +125°C
E/W -40°C to +85°C
E/W -40°C to +125°C
V
Using EECON to read/write
VMIN = Minimum operating
voltage
ms
Program Flash Memory
D130
EP
Cell Endurance
10K
1K
100K
10K
—
—
D131
VPR
VDD for Read
VMIN
—
5.5
V
VMIN = Minimum operating
voltage
D132
VIE
VDD for Block Erase
4.5
—
5.5
V
Using ICSP port
D132A VIW
VDD for Externally Timed Erase
or Write
4.5
—
5.5
V
Using ICSP port
D132B VPEW
VDD for Self-Timed Write
VMIN
—
5.5
V
VMIN = Minimum operating
voltage
D133
TIE
ICSP Block Erase Cycle Time
—
4
—
ms
VDD > 4.5V
D133A
TIW
ICSP Erase or Write Cycle Time
(externally timed)
1
—
—
ms
VDD > 4.5V
D133A TIW
D134
Self-Timed Write Cycle Time
TRETD Characteristic Retention
—
2
—
40
—
—
ms
Year Provided no other
specifications are violated
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
2: Required only if Low-Voltage Programming is disabled.
© 2007 Microchip Technology Inc.
DS39599G-page 321
PIC18F2220/2320/4220/4320
TABLE 26-2:
COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
D300
VIOFF
Input Offset Voltage
—
±5.0
±10
mV
D301
VICM
Input Common Mode Voltage*
0
—
VDD – 1.5
V
D302
CMRR
Common Mode Rejection Ratio*
55
—
—
dB
300
300A
TRESP
Response Time(1)*
—
150
400
600
ns
ns
301
TMC2OV
Comparator Mode Change to
Output Valid*
—
—
10
μs
*
Note 1:
Comments
PIC18FXX20
PIC18LFXX20
These parameters are characterized but not tested.
Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 26-3:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
VDD/24
—
VDD/32
LSb
—
—
—
—
1/2
1/2
LSb
LSb
D310
VRES
Resolution
D311
VRAA
Absolute Accuracy
D312
VRUR
Unit Resistor Value (R)*
—
2k
—
Ω
310
TSET
Settling Time(1)*
—
—
10
μs
*
Note 1:
Comments
Low Range (VRR = 1)
High Range (VRR = 0)
These parameters are characterized but not tested.
Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.
FIGURE 26-4:
LOW-VOLTAGE DETECT CHARACTERISTICS
VDD
VLVD
(LVDIF set by hardware)
(LVDIF can be
cleared in software)
LVDIF
DS39599G-page 322
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-4:
LOW-VOLTAGE DETECT CHARACTERISTICS
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
VLVD
D420A
Characteristic
D420C
Legend:
†
Typ†
Max
Units
Conditions
LVD Voltage on VDD Transition High-to-Low — Date codes from 0351xxx to 0417xxx, inclusive
PIC18LF2X20/4X20
Industrial Low Voltage (-40°C to +85°C)
LVDL<3:0> = 0000
D420B
Min
N/A
N/A
N/A
V
Reserved
Reserved
LVDL<3:0> = 0001
N/A
N/A
N/A
V
LVDL<3:0> = 0010
2.08
2.26
2.44
V
LVDL<3:0> = 0011
2.26
2.45
2.65
V
LVDL<3:0> = 0100
2.35
2.55
2.76
V
LVDL<3:0> = 0101
2.55
2.77
2.99
V
LVDL<3:0> = 0110
2.64
2.87
3.10
V
LVDL<3:0> = 0111
2.82
3.07
3.31
V
LVDL<3:0> = 1000
3.09
3.36
3.63
V
LVDL<3:0> = 1001
3.29
3.57
3.86
V
LVDL<3:0> = 1010
3.38
3.67
3.96
V
LVDL<3:0> = 1011
3.56
3.87
4.18
V
LVDL<3:0> = 1100
3.75
4.07
4.40
V
LVDL<3:0> = 1101
3.93
4.28
4.62
V
LVDL<3:0> = 1110
4.23
4.60
4.96
V
PIC18F2X20/4X20
Industrial (-40°C to +85°C)
LVDL<3:0> = 1011
3.56
3.87
4.18
V
LVDL<3:0> = 1100
3.75
4.07
4.40
V
LVDL<3:0> = 1101
3.93
4.28
4.62
V
LVDL<3:0> = 1110
4.23
4.60
4.96
V
PIC18F2X20/4X20
Extended (-40°C to +125°C)
LVDL<3:0> = 1011
3.41
3.87
4.33
V
LVDL<3:0> = 1100
3.58
4.07
4.56
V
LVDL<3:0> = 1101
3.77
4.28
4.79
V
LVDL<3:0> = 1110
4.04
4.60
5.15
V
Shading of rows is to assist in readability of the table.
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
© 2007 Microchip Technology Inc.
DS39599G-page 323
PIC18F2220/2320/4220/4320
TABLE 26-4:
LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
VLVD
D420D
Characteristic
Max
Units
Conditions
Industrial Low Voltage (-10°C to +85°C)
N/A
N/A
N/A
V
Reserved
Reserved
LVDL<3:0> = 0001
N/A
N/A
N/A
V
LVDL<3:0> = 0010
2.08
2.26
2.44
V
LVDL<3:0> = 0011
2.26
2.45
2.65
V
LVDL<3:0> = 0100
2.35
2.55
2.76
V
LVDL<3:0> = 0101
2.55
2.77
2.99
V
LVDL<3:0> = 0110
2.64
2.87
3.10
V
LVDL<3:0> = 0111
2.82
3.07
3.31
V
LVDL<3:0> = 1000
3.09
3.36
3.63
V
LVDL<3:0> = 1001
3.29
3.57
3.86
V
LVDL<3:0> = 1010
3.38
3.67
3.96
V
LVDL<3:0> = 1011
3.56
3.87
4.18
V
LVDL<3:0> = 1100
3.75
4.07
4.40
V
LVDL<3:0> = 1101
3.93
4.28
4.62
V
LVDL<3:0> = 1110
4.23
4.60
4.96
V
PIC18LF2X20/4X20
Industrial Low Voltage (-40°C to -10°C)
LVDL<3:0> = 0000
Legend:
†
Typ†
LVD Voltage on VDD Transition High-to-Low — Date codes above 0417xxx
PIC18LF2X20/4X20
LVDL<3:0> = 0000
D420F
Min
N/A
N/A
N/A
V
Reserved
Reserved
LVDL<3:0> = 0001
N/A
N/A
N/A
V
LVDL<3:0> = 0010
1.99
2.26
2.53
V
LVDL<3:0> = 0011
2.16
2.45
2.75
V
LVDL<3:0> = 0100
2.25
2.55
2.86
V
LVDL<3:0> = 0101
2.43
2.77
3.10
V
LVDL<3:0> = 0110
2.53
2.87
3.21
V
LVDL<3:0> = 0111
2.70
3.07
3.43
V
LVDL<3:0> = 1000
2.96
3.36
3.77
V
LVDL<3:0> = 1001
3.14
3.57
4.00
V
LVDL<3:0> = 1010
3.23
3.67
4.11
V
LVDL<3:0> = 1011
3.41
3.87
4.34
V
LVDL<3:0> = 1100
3.58
4.07
4.56
V
LVDL<3:0> = 1101
3.76
4.28
4.79
V
LVDL<3:0> = 1110
4.04
4.60
5.15
V
Shading of rows is to assist in readability of the table.
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
DS39599G-page 324
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-4:
LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED)
PIC18LF2220/2320/4220/4320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F2220/2320/4220/4320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
VLVD
D420G
Characteristic
D420K
Legend:
†
Max
Units
Conditions
Industrial (-10°C to +85°C)
LVDL<3:0> = 1110
D420J
Typ†
LVD Voltage on VDD Transition High-to-Low — Date codes above 0417xxx
PIC18F2X20/4X20
LVDL<3:0> = 1101
D420H
Min
PIC18F2X20/4X20
3.93
4.28
4.62
V
4.23
4.60
4.96
V
Industrial (-40°C to -10°C)
LVDL<3:0> = 1101
3.76
4.28
4.79
V
LVDL<3:0> = 1110
4.04
4.60
5.15
V
PIC18F2X20/4X20
Reserved
Extended (-10°C to +85°C)
LVDL<3:0> = 1101
3.94
4.28
4.62
V
LVDL<3:0> = 1110
4.23
4.60
4.96
V
PIC18F2X20/4X20
Extended (-40°C to -10°C, +85°C to +125°C)
LVDL<3:0> = 1101
3.77
4.28
4.79
V
LVDL<3:0> = 1110
4.05
4.60
5.15
V
Reserved
Shading of rows is to assist in readability of the table.
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
© 2007 Microchip Technology Inc.
DS39599G-page 325
PIC18F2220/2320/4220/4320
26.4
26.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKO
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
I2C only
AA
output access
BUF
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
Start condition
DS39599G-page 326
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
High
Low
High
Low
SU
Setup
STO
Stop condition
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
26.4.2
TIMING CONDITIONS
Note:
The temperature and voltages specified in Table 26-5
apply to all timing specifications unless otherwise
noted. Figure 26-5 specifies the load conditions for the
timing specifications.
TABLE 26-5:
TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
AC CHARACTERISTICS
FIGURE 26-5:
Because of space limitations, the generic
terms “PIC18FXX20” and “PIC18LFXX20”
are used throughout this section to refer
to the PIC18F2220/2320/4220/4320 and
PIC18LF2220/2320/4220/4320 families of
devices specifically and only those
devices.
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Section 26.1 and
Section 26.3.
LF parts operate up to industrial temperatures only.
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464Ω
VSS
© 2007 Microchip Technology Inc.
CL = 50 pF
for all pins except OSC2/CLKO
and including D and E outputs as ports
DS39599G-page 327
PIC18F2220/2320/4220/4320
26.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-6:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
4
3
4
2
CLKO
TABLE 26-6:
Param.
No.
1A
EXTERNAL CLOCK TIMING REQUIREMENTS
Symbol
FOSC
Characteristic
Min
Max
External CLKI Frequency(1)
DC
40
MHz
EC, ECIO (industrial)
DC
25
MHz
EC, ECIO (extended)
DC
4
MHz
RC osc
0.1
1
MHz
XT osc
4
25
MHz
HS osc
4
10
MHz
HS + PLL osc (industrial)
4
6.25
MHz
HS + PLL osc (extended)
5
33
kHz
LP Osc mode
Oscillator Frequency(1)
1
TOSC
External CLKI
Period(1)
Oscillator Period(1)
2
TCY
Instruction Cycle Time(1)
3
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
4
Note 1:
Units
Conditions
25
—
ns
EC, ECIO (industrial)
40
—
ns
EC, ECIO (extended)
250
—
ns
RC osc
1
—
μs
XT osc
40
100
250
250
ns
ns
HS osc
HS + PLL osc (industrial)
160
250
ns
HS + PLL osc (extended)
30
—
μs
LP osc
100
160
—
—
ns
ns
TCY = 4/FOSC (industrial)
TCY = 4/FOSC (extended)
30
—
ns
XT osc
2.5
—
μs
LP osc
10
—
ns
HS osc
—
20
ns
XT osc
—
50
ns
LP osc
—
7.5
ns
HS osc
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39599G-page 328
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-7:
Param
No.
PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
F10
FOSC Oscillator Frequency Range
4
—
10
MHz HS mode only
F11
FSYS
On-Chip VCO System Frequency
16
—
40
MHz HS mode only
F12
tPLL
PLL Start-up Time (Lock Time)
—
—
2
ms
ΔCLK
CLKO Stability (Jitter)
-2
—
+2
%
F13
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 26-8:
INTERNAL RC ACCURACY: PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial, Extended)
PIC18LF1220/1320
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC18F1220/1320
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Min
Typ
Max
Units
Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
F14
PIC18LF2220/2320/4220/4320
-2
+/-1
F15
-5
F16
-10
F17
PIC18F2220/2320/4220/4320
F18
F19
2
%
+25°C
—
5
%
-10°C to +85°C VDD = 2.7-3.3V
—
10
%
-40°C to +85°C VDD = 2.7-3.3V
-2
+/-1
2
%
-5
—
5
%
-10°C to +85°C VDD = 4.5-5.5V
-10
—
10
%
-40°C to +85°C VDD = 4.5-5.5V
+25°C
VDD = 2.7-3.3V
VDD = 4.5-5.5V
INTRC Accuracy @ Freq = 31 kHz(2)
F20
PIC18LF2220/2320/4220/4320 26.562
—
35.938
kHz
-40°C to +85°C VDD = 2.7-3.3V
F21
PIC18F2220/2320/4220/4320 26.562
—
35.938
kHz
-40°C to +85°C VDD = 4.5-5.5V
Legend:
Note 1:
2:
3:
Shading of rows is to assist in readability of the table.
Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
INTRC frequency after calibration.
Change of INTRC frequency as VDD changes.
© 2007 Microchip Technology Inc.
DS39599G-page 329
PIC18F2220/2320/4220/4320
FIGURE 26-7:
CLKO AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKO
13
14
19
12
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
Note:
20, 21
Refer to Figure 26-5 for load conditions.
TABLE 26-9:
Param
No.
New Value
Old Value
CLKO AND I/O TIMING REQUIREMENTS
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
TOSH2CKL OSC1 ↑ to CLKO ↓
—
75
200
ns
(1)
11
TOSH2CKH OSC1 ↑ to CLKO ↑
—
75
200
ns
(1)
12
TCKR
CLKO Rise Time
—
35
100
ns
(1)
13
TCKF
CLKO Fall Time
—
35
100
ns
(1)
14
TCKL2IOV CLKO ↓ to Port Out Valid
—
—
0.5 TCY + 20
ns
(1)
15
TIOV2CKH Port In Valid before CLKO ↑
0.25 TCY + 25
—
—
ns
(1)
(1)
Port In Hold after CLKO ↑
16
TCKH2IOI
17
TOSH2IOV OSC1↑ (Q1 cycle) to Port Out Valid
18
TOSH2IOI
18A
OSC1↑ (Q2 cycle) to Port PIC18FXX20
Input Invalid
PIC18LFXX20
(I/O in hold time)
0
—
—
ns
—
50
150
ns
100
—
—
ns
200
—
—
ns
19
TIOV2OSH Port Input Valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20
TIOR
Port Output Rise Time
—
10
25
ns
TIOF
Port Output Fall Time
20A
21
21A
Note 1:
PIC18FXX20
PIC18LFXX20
—
—
60
ns
PIC18FXX20
—
10
25
ns
PIC18LFXX20
—
—
60
ns
Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
DS39599G-page 330
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 26-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 26-5 for load conditions.
FIGURE 26-9:
BROWN-OUT RESET TIMING
VDD
BVDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
© 2007 Microchip Technology Inc.
36
DS39599G-page 331
PIC18F2220/2320/4220/4320
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol
No.
Characteristic
Min
30
TMCL
MCLR Pulse Width (low)
31
TWDT
Watchdog Timer Time-out Period (no postscaler)
32
TOST
Oscillation Start-up Timer Period
33
TPWRT
Power-up Timer Period
34
TIOZ
I/O High-Impedance from MCLR Low or
Watchdog Timer Reset
35
TBOR
Brown-out Reset Pulse Width
36
TIVRST
Time for Internal Reference Voltage to become
stable
37
TLVD
Low-Voltage Detect Pulse Width
FIGURE 26-10:
Typ
Max
Units
2
—
—
μs
3.48
4.00
4.71
ms
1024 TOSC
—
1024 TOSC
—
57.0
65.5
77.2
ms
—
2
—
μs
200
—
—
μs
—
20
50
μs
200
—
—
μs
Conditions
TOSC = OSC1 period
VDD ≤ BVDD (see
D005A)
VDD ≤ VLVD
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 26-5 for load conditions.
DS39599G-page 332
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
No.
Characteristic
40
TT0H
T0CKI High Pulse Width
41
TT0L
T0CKI Low Pulse Width
42
TT0P
T0CKI Period
No prescaler
Min
Max
Units
0.5 TCY + 20
—
ns
With prescaler
No prescaler
10
—
ns
0.5 TCY + 20
—
ns
With prescaler
With prescaler
45
TT1H
T1CKI
Synchronous, no prescaler
High Time Synchronous,
PIC18FXX20
with prescaler
PIC18LFXX20
Asynchronous
10
—
ns
TCY + 10
—
ns
Greater of:
20 ns or TCY + 40
N
—
ns
0.5 TCY + 20
—
ns
10
—
ns
No prescaler
PIC18FXX20
PIC18LFXX20
46
47
TT1L
T1CKI
Low Time
Synchronous, no prescaler
ns
ns
50
—
ns
0.5 TCY + 5
—
ns
PIC18FXX20
10
—
ns
PIC18LFXX20
25
—
ns
Asynchronous
PIC18FXX20
30
—
ns
PIC18LFXX20
50
—
ns
Greater of:
20 ns or TCY + 40
N
—
ns
TT1P
T1CKI
Input
Period
FT 1
T1CKI Oscillator Input Frequency Range
Synchronous
TCKE2TMRI Delay from External T1CKI Clock Edge to
Timer Increment
FIGURE 26-11:
—
—
Synchronous,
with prescaler
Asynchronous
48
25
30
60
—
ns
DC
50
kHz
2 TOSC
7 TOSC
—
Conditions
N = prescale
value
(1, 2, 4,..., 256)
N = prescale
value
(1, 2, 4, 8)
CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx
(Capture Mode)
50
51
52
CCPx
(Compare or PWM Mode)
53
Note:
54
Refer to Figure 26-5 for load conditions.
© 2007 Microchip Technology Inc.
DS39599G-page 333
PIC18F2220/2320/4220/4320
TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param
Symbol
No.
50
51
TCCL
Characteristic
CCPx Input Low
Time
TCCH
Max
Units
0.5 TCY + 20
—
ns
PIC18FXX20
10
—
ns
PIC18LFXX20
20
—
ns
0.5 TCY + 20
—
ns
10
—
ns
No prescaler
With
prescaler
CCPx Input High
Time
No prescaler
With
prescaler
52
TCCP
CCPx Input Period
53
TCCR
CCPx Output Fall Time
54
TCCF
CCPx Output Fall Time
FIGURE 26-12:
Min
PIC18FXX20
PIC18LFXX20
20
—
ns
3 TCY + 40
N
—
ns
PIC18FXX20
—
25
ns
PIC18LFXX20
—
45
ns
PIC18FXX20
—
25
ns
PIC18LFXX20
—
45
ns
Conditions
N = prescale
value (1,4 or 16)
PARALLEL SLAVE PORT TIMING (PIC18F4X20)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
64
62
63
Note:
Refer to Figure 26-5 for load conditions.
DS39599G-page 334
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X20)
Param.
No.
Symbol
Characteristic
Min
Max
Units
20
—
ns
PIC18FXX20
20
—
ns
PIC18LFXX20
62
TDTV2WRH Data In Valid Before WR ↑ or CS ↑
(setup time)
63
TWRH2DTI
35
—
ns
64
TRDL2DTV RD ↓ and CS ↓ to Data–Out Valid
—
80
ns
65
TRDH2DTI
RD ↑ or CS ↓ to Data–Out Invalid
10
30
ns
66
TIBFINH
Inhibit of the IBF Flag bit being Cleared from
WR ↑ or CS ↑
—
3 TCY
FIGURE 26-13:
WR ↑ or CS ↑ to Data–In
Invalid (hold time)
Conditions
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
bit 6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb In
bit 6 - - - -1
LSb In
74
73
Note:
Refer to Figure 26-5 for load conditions.
© 2007 Microchip Technology Inc.
DS39599G-page 335
PIC18F2220/2320/4220/4320
TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units
70
TSSL2SCH,
TSSL2SCL
SS ↓ to SCK ↓ or SCK ↑ Input
71
TSCH
SCK Input High Time
(Slave mode)
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
SCK Input Low Time
(Slave mode)
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
100
—
ns
1.5 TCY + 40
—
ns
100
—
ns
PIC18FXX20
—
25
ns
PIC18LFXX20
—
45
ns
—
25
ns
—
25
ns
71A
TSCL
72
72A
TCY
73
TDIV2SCH,
TDIV2SCL
Setup Time of SDI Data Input to SCK Edge
73A
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
74
TSCH2DIL,
TSCL2DIL
Hold Time of SDI Data Input to SCK Edge
75
TDOR
SDO Data Output Rise Time
76
TDOF
SDO Data Output Fall Time
78
TSCR
SCK Output Rise Time
(Master mode)
79
TSCF
SCK Output Fall Time (Master mode)
80
TSCH2DOV, SDO Data Output Valid after
TSCL2DOV SCK Edge
Note 1:
2:
PIC18FXX20
PIC18LFXX20
—
Conditions
ns
—
45
ns
—
25
ns
PIC18FXX20
—
50
ns
PIC18LFXX20
—
100
ns
(Note 1)
(Note 1)
(Note 2)
Requires the use of Parameter # 73A.
Only if Parameter # 71A and # 72A are used.
FIGURE 26-14:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
MSb
SDO
bit 6 - - - - - -1
LSb
75, 76
SDI
MSb In
bit 6 - - - -1
LSb In
74
Note:
Refer to Figure 26-5 for load conditions.
DS39599G-page 336
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
71
Symbol
Characteristic
Min
TSCH
SCK Input High Time
(Slave mode)
TSCL
SCK Input Low Time
(Slave mode)
73
TDIV2SCH,
TDIV2SCL
Setup Time of SDI Data Input to SCK Edge
73A
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
74
TSCH2DIL,
TSCL2DIL
Hold Time of SDI Data Input to SCK Edge
75
TDOR
SDO Data Output Rise Time
71A
72
72A
Continuous
Max Units
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
100
—
ns
1.5 TCY + 40
—
ns
100
—
ns
PIC18FXX20
—
25
ns
45
ns
—
25
ns
—
25
ns
45
ns
25
ns
PIC18LFXX20
76
TDOF
SDO Data Output Fall Time
78
TSCR
SCK Output Rise Time
(Master mode)
79
TSCF
SCK Output Fall Time (Master mode)
80
TSCH2DOV, SDO Data Output Valid after
TSCL2DOV SCK Edge
81
PIC18FXX20
PIC18LFXX20
—
PIC18FXX20
—
PIC18LFXX20
TDOV2SCH, SDO Data Output Setup to SCK Edge
TDOV2SCL
Note 1:
2:
TCY
50
ns
100
ns
—
ns
Conditions
(Note 1)
(Note 1)
(Note 2)
Requires the use of Parameter # 73A.
Only if Parameter # 71A and # 72A are used.
FIGURE 26-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
bit 6 - - - - - -1
LSb
77
75, 76
SDI
MSb In
bit 6 - - - -1
LSb In
74
73
Note:
Refer to Figure 26-5 for load conditions.
© 2007 Microchip Technology Inc.
DS39599G-page 337
PIC18F2220/2320/4220/4320
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
71
TSCH
SCK Input High Time (Slave mode)
71A
TSCL
72
SCK Input Low Time (Slave mode)
72A
Min
Max Units Conditions
TCY
—
ns
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
100
—
ns
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
73A
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
ns
74
TSCH2DIL,
Hold Time of SDI Data Input to SCK Edge
—
ns
100
(Note 1)
(Note 1)
(Note 2)
TSCL2DIL
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
—
25
ns
45
ns
—
25
ns
10
50
ns
—
25
ns
45
ns
25
ns
PIC18LFXX20
TDOF
76
SDO Data Output Fall Time
77
TSSH2DOZ SS ↑ to SDO Output High-Impedance
78
TSCR
SCK Output Rise Time (Master mode)
79
TSCF
SCK Output Fall Time (Master mode)
80
TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXX20
TSCL2DOV
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
—
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
83
Note 1:
2:
—
50
ns
100
ns
—
ns
1.5 TCY + 40
Requires the use of Parameter # 73A.
Only if Parameter # 71A and # 72A are used.
FIGURE 26-16:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
bit 6 - - - - - -1
LSb
75, 76
SDI
MSb In
77
bit 6 - - - -1
LSb In
74
Note:
Refer to Figure 26-5 for load conditions.
DS39599G-page 338
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
71
TSCH
71A
TSCL
72
72A
Min
Max Units Conditions
TCY
—
ns
SCK Input High Time
(Slave mode)
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
SCK Input Low Time
(Slave mode)
Continuous
1.25 TCY + 30
—
ns
Single Byte
40
—
ns
(Note 1)
(Note 2)
73A
TB2B
74
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
—
ns
100
—
ns
—
25
ns
45
ns
PIC18LFXX20
76
TDOF
77
TSSH2DOZ SS↑ to SDO Output High-Impedance
SDO Data Output Fall Time
78
TSCR
SCK Output Rise Time
(Master mode)
—
25
ns
10
50
ns
PIC18FXX20
—
25
ns
PIC18LFXX20
—
45
ns
79
TSCF
—
25
ns
80
TSCH2DOV, SDO Data Output Valid after SCK
TSCL2DOV Edge
PIC18FXX20
—
50
ns
PIC18LFXX20
—
100
ns
TSSL2DOV SDO Data Output Valid after SS ↓
Edge
PIC18FXX20
—
50
ns
PIC18LFXX20
—
100
ns
1.5 TCY + 40
—
ns
82
SCK Output Fall Time (Master mode)
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
83
Note 1:
2:
(Note 1)
Requires the use of Parameter # 73A.
Only if Parameter # 71A and # 72A are used.
FIGURE 26-17:
I2C™ BUS START/STOP BITS TIMING
SCL
91
90
93
92
SDA
Start
Condition
Note:
Stop
Condition
Refer to Figure 26-5 for load conditions.
© 2007 Microchip Technology Inc.
DS39599G-page 339
PIC18F2220/2320/4220/4320
TABLE 26-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
No.
90
TSU:STA
Characteristic
Max
Units
Conditions
ns
Only relevant for Repeated
Start condition
ns
After this period, the first
clock pulse is generated
Start Condition
100 kHz mode
4700
—
Setup Time
400 kHz mode
600
—
Start Condition
100 kHz mode
4000
—
Hold Time
400 kHz mode
600
—
Stop Condition
100 kHz mode
4700
—
91
THD:STA
92
TSU:STO
93
THD:STO Stop Condition
Setup Time
Hold Time
FIGURE 26-18:
Min
400 kHz mode
600
—
100 kHz mode
4000
—
400 kHz mode
600
—
ns
ns
I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note:
Refer to Figure 26-5 for load conditions.
DS39599G-page 340
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
Symbol
No.
100
101
102
THIGH
TLOW
TR
Characteristic
Clock High Time
Clock Low Time
Min
Max
Units
Conditions
100 kHz mode
4.0
—
μs
PIC18FXX20 must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
μs
PIC18FXX20 must operate at a
minimum of 10 MHz
MSSP module
1.5 TCY
—
100 kHz mode
4.7
—
μs
PIC18FXX20 must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
μs
PIC18FXX20 must operate at a
minimum of 10 MHz
MSSP module
1.5 TCY
—
SDA and SCL Rise
Time
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
SDA and SCL Fall
Time
100 kHz mode
—
300
ns
400 kHz mode
CB is specified to be from 10 to 400 pF
103
TF
20 + 0.1 CB
300
ns
CB is specified to be from 10 to 400 pF
90
TSU:STA Start Condition Setup 100 kHz mode
Time
400 kHz mode
4.7
—
μs
0.6
—
μs
Only relevant for Repeated
Start condition
91
THD:STA Start Condition Hold
Time
100 kHz mode
4.0
—
μs
400 kHz mode
0.6
—
μs
106
THD:DAT Data Input Hold Time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
μs
100 kHz mode
250
—
ns
107
TSU:DAT Data Input Setup
Time
400 kHz mode
100
—
ns
92
TSU:STO Stop Condition Setup 100 kHz mode
Time
400 kHz mode
4.7
—
μs
0.6
—
μs
109
TAA
Output Valid from
Clock
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
110
TBUF
Bus Free Time
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
—
400
pF
D102
CB
Note 1:
2:
Bus Capacitive Loading
After this period, the first clock pulse is
generated
(Note 2)
(Note 1)
Time the bus must be free before a
new transmission can start
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement, TSU:DAT ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification), before the SCL line
is released.
© 2007 Microchip Technology Inc.
DS39599G-page 341
PIC18F2220/2320/4220/4320
FIGURE 26-19:
MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
SCL
93
91
90
92
SDA
Stop
Condition
Start
Condition
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
No.
90
TSU:STA
Characteristic
Start condition
Setup time
91
THD:STA Start condition
Hold time
92
TSU:STO Stop condition
Setup time
93
THD:STO Stop condition
Hold time
Note 1:
Min
Max
Units
2(TOSC)(BRG + 1)
—
ns
400 kHz mode
2(TOSC)(BRG + 1)
—
Only relevant for
Repeated Start condition
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ns
After this period, the first
clock pulse is generated
100 kHz mode
100 kHz mode
2(TOSC)(BRG + 1)
—
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
100 kHz mode
2(TOSC)(BRG + 1)
—
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
100 kHz mode
2(TOSC)(BRG + 1)
—
400 kHz mode
2(TOSC)(BRG + 1)
—
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
Conditions
ns
ns
Maximum pin capacitance = 10 pF for all I2C pins.
FIGURE 26-20:
MASTER SSP I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
91
107
92
SDA
In
109
109
110
SDA
Out
Note:
DS39599G-page 342
Refer to Figure 26-5 for load conditions.
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
Symbol
No.
100
THIGH
Characteristic
Clock High Time
Max
Units
100 kHz mode 2(TOSC)(BRG + 1)
—
ms
400 kHz mode
2(TOSC)(BRG + 1)
—
ms
mode(1)
2(TOSC)(BRG + 1)
—
ms
100 kHz mode 2(TOSC)(BRG + 1)
—
ms
400 kHz mode 2(TOSC)(BRG + 1)
—
ms
1 MHz
101
TLOW
Clock Low Time
1 MHz
102
103
90
91
106
107
92
109
110
D102
Note 1:
2:
TR
TF
TSU:STA
SDA and SCL
Rise Time
SDA and SCL
Fall Time
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
THD:DAT Data Input
Hold Time
TSU:DAT
Data Input
Setup Time
TSU:STO Stop Condition
Setup Time
TAA
TBUF
CB
Output Valid from
Clock
Bus Free Time
Min
mode(1)
2(TOSC)(BRG + 1)
—
ms
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
100 kHz mode 2(TOSC)(BRG + 1)
—
ms
400 kHz mode 2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
100 kHz mode 2(TOSC)(BRG + 1)
—
ms
400 kHz mode 2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
ms
1 MHz mode(1)
TBD
—
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(1)
TBD
—
ns
100 kHz mode 2(TOSC)(BRG + 1)
—
ms
400 kHz mode 2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
ms
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
(1)
1 MHz mode
—
—
ns
100 kHz mode
4.7
—
ms
400 kHz mode
1.3
—
ms
1 MHz mode(1)
TBD
—
ms
—
400
pF
Bus Capacitive Loading
Conditions
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for
Repeated Start condition
After this period, the first
clock pulse is generated
(Note 2)
Time the bus must be free
before a new transmission
can start
Maximum pin capacitance = 10 pF for all I2C pins.
A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.
© 2007 Microchip Technology Inc.
DS39599G-page 343
PIC18F2220/2320/4220/4320
FIGURE 26-21:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note:
122
Refer to Figure 26-5 for load conditions.
TABLE 26-22: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
120
121
122
Symbol
Characteristic
TCKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
TCKRF
TDTRF
Min
Max
Units
PIC18FXX20
—
40
ns
PIC18LFXX20
—
100
ns
Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXX20
—
20
ns
PIC18LFXX20
—
50
ns
Data Out Rise Time and Fall Time
PIC18FXX20
—
20
ns
PIC18LFXX20
—
50
ns
FIGURE 26-22:
RC6/TX/CK
pin
Conditions
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
RC7/RX/DT
pin
126
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-23: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
No.
Symbol
Characteristic
125
TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time)
126
TCKL2DTL
DS39599G-page 344
Data Hold after CK ↓ (DT hold time)
Min
Max
Units
10
—
ns
15
—
ns
Conditions
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18F2220/2320/4220/4320 (INDUSTRIAL)
PIC18F2220/2320/4220/4320 (EXTENDED)
PIC18LF2220/2320/4220/4320 (INDUSTRIAL)
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
ΔVREF ≥ 3.0V
A01
NR
Resolution
—
—
10
A03
EIL
Integral Linearity Error
—
—
<±1
LSb ΔVREF ≥ 3.0V
A04
EDL
Differential Linearity Error
—
—
<±1
LSb ΔVREF ≥ 3.0V
A06
EOFF
Offset Error
—
—
<±1
LSb ΔVREF ≥ 3.0V
A07
EGN
Gain Error
—
—
<±1
LSb ΔVREF ≥ 3.0V
A10
—
Monotonicity
A20
ΔVREF
Reference Voltage Range
(VREFH – VREFL)
guaranteed
A21
VREFH
A22
VREFL
bit
Conditions
(2)
—
3
—
AVDD – AVSS
V
For 10-bit resolution
Reference Voltage High
AVSS + 3.0V
—
AVDD + 0.3V
V
For 10-bit resolution
Reference Voltage Low
AVSS – 0.3V
—
AVDD – 3.0V
V
For 10-bit resolution
A25
VAIN
Analog Input Voltage
VREFL
—
VREFH
V
A28
AVDD
Analog Supply Voltage
VDD – 0.3
—
VDD + 0.3
V
Tie to VDD
A29
AVSS
Analog Supply Voltage
VSS – 0.3
—
VSS + 0.3
V
Tie to VSS
A30
ZAIN
Recommended Impedance of
Analog Voltage Source
—
—
2.5(4)
kΩ
A40
IAD
A/D Current
from VDD
—
—
180(5)
μA
—
90(5)
μA
—
—
±5(5)
μA
μA
A50
IREF
Note 1:
2:
3:
4:
5:
PIC18FXX20
PIC18LFXX20
VREF Input Current
(3)
—
—
—
±150(5)
Average current during
conversion(1)
During VAIN acquisition.
During A/D conversion
cycle.
When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source.
Assume quiet environment. If adjacent pins have high-frequency signals (analog or digital), ZAIN may need
to be reduced to as low as 1 kΩ to fight crosstalk effects.
For guidance only.
© 2007 Microchip Technology Inc.
DS39599G-page 345
PIC18F2220/2320/4220/4320
FIGURE 26-23:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
A/D CLK
130
132
9
A/D DATA
8
7
...
...
2
1
0
NEW_DATA
OLD_DATA
ADRES
TCY
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be
executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 26-25: A/D CONVERSION REQUIREMENTS
Param
Symbol
No.
130
TAD
Characteristic
A/D Clock Period
PIC18FXX20
PIC18LFXX20
131
TCNV
Note 1:
2:
Min
Max
Units
1.6
20(2)
μs
TOSC based, VREF ≥ 3.0V
3.0
(2)
μs
TOSC based, VREF full range
20
Conditions
PIC18FXX20
2.0
6.0
μs
A/D RC mode
PIC18LFXX20
3.0
9.0
μs
A/D RC mode
11
12
TAD
Conversion Time
(not including acquisition time)(1)
ADRES register may be read on the following TCY cycle.
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
DS39599G-page 346
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
27.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean – 3σ)
respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 27-1:
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
0.5
0.4
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
5.0V
0.3
IDD (mA)
4.5V
4.0V
0.2
3.5V
3.0V
0.1
2.5V
2.0V
0.0
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
FIGURE 27-2:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +85°C
0.7
0.6
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
5.0V
0.5
4.5V
IDD (mA)
0.4
4.0V
0.3
3.5V
3.0V
0.2
2.5V
0.1
2.0V
0.0
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
© 2007 Microchip Technology Inc.
DS39599G-page 347
PIC18F2220/2320/4220/4320
FIGURE 27-3:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
0.7
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.6
5.5V
5.0V
0.5
4.5V
IDD (mA)
0.4
4.0V
0.3
3.5V
3.0V
0.2
2.5V
0.1
2.0V
0.0
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
FIGURE 27-4:
2.0
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1.8
1.6
5.5V
1.4
5.0V
IDD (mA)
1.2
4.5V
1.0
4.0V
0.8
3.5V
3.0V
0.6
2.5V
0.4
2.0V
0.2
0.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
DS39599G-page 348
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-5:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
2.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
2.0
5.5V
5.0V
1.5
IDD (mA)
4.5V
4.0V
1.0
3.5V
3.0V
2.5V
0.5
2.0V
0.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C
FIGURE 27-6:
16
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
14
5.5V
12
5.0V
10
IDD (mA)
4.5V
8
4.0V
6
3.5V
4
3.0V
2
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
© 2007 Microchip Technology Inc.
DS39599G-page 349
PIC18F2220/2320/4220/4320
FIGURE 27-7:
MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C
16
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
14
5.5V
5.0V
12
4.0V
10
IDD (mA)
4.5V
8
3.5V
6
4
3.0V
2
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
FIGURE 27-8:
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
0.035
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.030
5.5V
5.0V
0.025
4.5V
0.020
IDD (mA)
4.0V
3.5V
0.015
3.0V
2.5V
0.010
2.0V
0.005
0.000
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
DS39599G-page 350
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-9:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +85°C
0.045
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.040
5.5V
0.035
5.0V
0.030
IDD (mA)
4.5V
0.025
4.0V
0.020
3.5V
3.0V
0.015
2.5V
0.010
2.0V
0.005
0.000
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
FIGURE 27-10:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
0.100
0.090
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
0.080
5.0V
0.070
IDD (mA)
0.060
4.5V
0.050
4.0V
3.5V
0.040
3.0V
0.030
2.5V
0.020
2.0V
0.010
0.000
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
© 2007 Microchip Technology Inc.
DS39599G-page 351
PIC18F2220/2320/4220/4320
FIGURE 27-11:
TYPICALyp
IDD vs. FOSC OVER VDD PRI_IDLE,
EC MODE, +25°C
_
600
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
500
5.5V
5.0V
400
IDD (μA)
4.5V
4.0V
300
3.5V
3.0V
200
2.5V
2.0V
100
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
FIGURE 27-12:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
600
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
500
5.5V
5.0V
IDD (μA)
400
4.5V
4.0V
300
3.5V
3.0V
200
2.5V
2.0V
100
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
DS39599G-page 352
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-13:
TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C
6.0
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.5
5.0
4.5
5.5V
5.0V
4.0
IDD (mA)
3.5
4.5V
3.0
2.5
4.0V
2.0
3.5V
1.5
1.0
3.0V
0.5
2.5V
2.0V
0.0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
FIGURE 27-14:
MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C
6.0
5.5
5.5V
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
5.0
5.0V
4.5
4.0
4.5V
IDD (mA)
3.5
3.0
4.0V
2.5
2.0
3.5V
1.5
1.0
3.0V
0.5
2.0V
0.0
4
8
2.5V
12
16
20
24
28
32
36
40
FOSC (MHz)
© 2007 Microchip Technology Inc.
DS39599G-page 353
PIC18F2220/2320/4220/4320
FIGURE 27-15:
TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_RUN MODE,
ALL PERIPHERALS DISABLED
3000
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
8 MHz
2500
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
IPD (μA)
2000
1500
4 MHz
1000
2 MHz
500
1 MHz
125 kHz
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-16:
MAXIMUM IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_RUN,
ALL PERIPHERALS DISABLED
3500
8 MHz
3000
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
2500
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
IPD (μA)
2000
4 MHz
1500
1000
2 MHz
1 MHz
500
125 kHz
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39599G-page 354
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-17:
TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_RUN,
ALL PERIPHERALS DISABLED
100
Max (+125°C)
Max (+85°C)
IPD (μA)
Typ (+25°C)
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-18:
TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_IDLE MODE,
ALL PERIPHERALS DISABLED
800
750
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
700
650
8 MHz
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
IPD (μA)
600
550
4 MHz
500
2 MHz
1 MHz
450
125 kHz
400
350
300
250
200
150
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2007 Microchip Technology Inc.
DS39599G-page 355
PIC18F2220/2320/4220/4320
FIGURE 27-19:
MAXIMUM IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_IDLE,
ALL PERIPHERALS DISABLED
800
8 MHz
750
250 kHz and 500 kHz curves are
bounded by 125 kHz and 1 MHz
700
4 MHz
650
2 MHz
1 MHz
125 kHz
600
550
IPD (μA)
500
450
400
350
300
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
250
200
150
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-20:
TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_IDLE,
ALL PERIPHERALS DISABLED
100
IPD (μA)
Max (+125°C)
Max (+85°C)
10
Typ (+25°C)
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39599G-page 356
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-21:
IPD SEC_RUN MODE, -10°C TO +70°C 32.768 kHz XTAL 2 X 22 pF,
ALL PERIPHERALS DISABLED
80
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
70
60
Max (+70°C)
IPD (μA)
50
40
Typ (+25°C)
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
5.0
5.5
VDD (V)
FIGURE 27-22:
IPD SEC_IDLE, -10°C TO +70°C 32.768 kHz 2 X 22 pF,
ALL PERIPHERALS DISABLED
20
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
18
16
14
Max (+70°C)
IPD (μA)
12
10
Typ (+25°C)
8
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
VDD (V)
© 2007 Microchip Technology Inc.
DS39599G-page 357
PIC18F2220/2320/4220/4320
FIGURE 27-23:
TOTAL IPD, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED
100
Max (+125°C)
10
Max (+85°C)
IPD (μA)
1
0.1
Typ (+25°C)
0.01
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
0.001
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-24:
VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V
3.0
2.5
2.0
VOH (V)
Max (+125°C)
1.5
Typ (+25°C)
Min (+125°C)
1.0
0.5
0.0
0
5
10
15
20
25
IOH (-mA)
DS39599G-page 358
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-25:
VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V
5.0
4.5
Max (+125°C)
4.0
Typ (+25°C)
3.5
VOH (V)
3.0
2.5
Min (+125°C)
2.0
1.5
1.0
0.5
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 27-26:
(-40°C TO
+125°C), VDD = 3.0V
VOL vs. IOL OVER TEMPERATURE
(
)
3.0
Max (+125°C)
2.5
Max (+85°C)
VOL (V)
2.0
1.5
Typ (+25°C)
1.0
0.5
Min (+125°C)
0.0
0
5
10
15
20
25
IOL (-mA)
© 2007 Microchip Technology Inc.
DS39599G-page 359
PIC18F2220/2320/4220/4320
FIGURE 27-27:
VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V
1.0
0.9
Max (+125°C)
0.8
0.7
0.6
VOL (V)
Max (+85°C)
0.5
0.4
Typ (+25°C)
0.3
0.2
Min (+125°C)
0.1
0.0
0
5
10
15
20
25
IOL (-mA)
FIGURE 27-28:
Δ IPD TIMER1 OSCILLATOR, -10°C TO +70°C SLEEP MODE,
TMR1 COUNTER DISABLED
5.0
4.5
Max (-10°C to +70°C)
4.0
3.5
IPD (μA)
3.0
Typ (+25°C)
2.5
2.0
1.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39599G-page 360
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-29:
ΔIPD FSCM vs. VDD OVER TEMPERATURE PRI_IDLE, EC OSCILLATOR AT 32 kHz,
-40°C TO +125°C
4.5
4.0
Max (-40°C)
3.5
ΔIPD (μA)
3.0
2.5
Typ (+25°C)
2.0
1.5
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-30:
ΔIPD WDT, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED
14
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
12
ΔIPD (μA)
10
Max (+125°C)
8
6
Max (+85°C)
4
Typ (+25°C)
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2007 Microchip Technology Inc.
DS39599G-page 361
PIC18F2220/2320/4220/4320
FIGURE 27-31:
ΔIPD LVD vs. VDD SLEEP MODE, LVD = 2.00V-2.12V
50
45
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
40
Max (+125°C)
35
Max (+85°C)
IPD (μA)
30
Typ (+25°C)
25
20
15
10
Low-Voltage Detection Range
5
Normal Operating Range
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
5.0
5.5
VDD (V)
FIGURE 27-32:
ΔIPD BOR vs. VDD, -40°C TO +125°C SLEEP MODE,
BOR ENABLED AT 2.00V-2.16V
40
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
35
Max (+125°C)
30
IPD (μA)
25
Typ (+25°C)
20
15
10
Device may be in Reset
5
Device is Operating
0
2.0
2.5
3.0
3.5
4.0
4.5
VDD (V)
DS39599G-page 362
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
FIGURE 27-33:
ΔIPD A/D, -40°C TO +125°C SLEEP MODE, A/D ENABLED (NOT CONVERTING)
10
Max (+125°C)
1
IPD (μA)
Max (+85°C)
0.1
0.01
Typical:
statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C)
Typ (+25°C)
0.001
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-34:
AVERAGE FOSC vs. VDD FOR VARIOUS R’S EXTERNAL RC MODE,
C = 20 pF, TEMPERATURE = +25°C
5.0
Operation above 4 MHz is not recomended
4.5
4.0
5.1K
3.5
Freq (MHz)
3.0
2.5
10K
2.0
1.5
1.0
33K
0.5
100K
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2007 Microchip Technology Inc.
DS39599G-page 363
PIC18F2220/2320/4220/4320
FIGURE 27-35:
AVERAGE FOSC vs. VDD FOR VARIOUS R’S EXTERNAL RC MODE,
C = 100 pF, TEMPERATURE = +25°C
2.0
1.8
1.6
5.1K
1.4
Freq (MHz)
1.2
1.0
10K
0.8
0.6
0.4
33K
0.2
100K
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-36:
AVERAGE FOSC vs. VDD FOR VARIOUS R’S EXTERNAL RC MODE,
C = 300 pF, TEMPERATURE = +25°C
0.8
0.7
0.6
Freq (MHz)
0.5
5.1K
0.4
0.3
10K
0.2
0.1
33K
100K
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39599G-page 364
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
28.0
PACKAGING INFORMATION
28.1
Package Marking Information
28-Lead SPDIP
Example
PIC18F2220-I/SP e3
0710017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
PIC18F2320-E/SO e3
0710017
PIC18F4220-I/P e3
0710017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
DS39599G-page 365
PIC18F2220/2320/4220/4320
Package Marking Information (Continued)
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS39599G-page 366
Example
PIC18F4320
-I/PT e3
0710017
Example
PIC18F4220
-I/ML e3
0710017
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
28.2
Package Details
The following sections give the technical details of the packages.
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© 2007 Microchip Technology Inc.
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DS39599G-page 369
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© 2007 Microchip Technology Inc.
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© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
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© 2007 Microchip Technology Inc.
DS39599G-page 373
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 374
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
APPENDIX A:
REVISION HISTORY
Revision A (June 2002)
Original data sheet for PIC18F2X20/4X20 devices.
Revision B (October 2002)
This revision includes major changes to Section 2.0
“Oscillator Configurations” and Section 3.0
“Power-Managed Modes”, updates to the Electrical
Specifications in Section 26.0 “Electrical Characteristics” and minor corrections to the data sheet text.
Revision C (October 2003)
This revision includes updates to the Electrical Specifications in Section 26.0 “Electrical Characteristics”
and to the DC Characteristics Graphs and Charts in
Section 27.0 “DC and AC Characteristics Graphs
and Tables” and minor corrections to the data sheet
text.
Revision D (October 2006)
This revision includes updates to the packaging
diagrams.
© 2007 Microchip Technology Inc.
Revision E (January 2007)
This revision includes updates to the packaging
diagrams.
Revision F (February 2007)
This revision includes updates to the packaging
diagrams.
Revision G (December 2007)
• Modified OSCTUNE register data and added
OSCTUN2 register data to Section 2.6 “Internal
Oscillator Block” and Table 4-3 and Table 5-1.
• Changed Brown-out Voltage values in
Section 26.1 “DC Characteristics: Supply Voltage PIC18F2220/2320/4220/4320 (Industrial)
PIC18LF2220/2320/4220/4320 (Industrial)”.
• Updated low-voltage detect values in Table 26-4.
• Removed RE3 pin references for
PIC18F2220/2320 devices in Section 1.0
“Device Overview”, Section 5.0 “Memory
Organization”, Section 10.0 “I/O Ports”,
Section 19.0 “10-bit Analog-to-Digital Converter (A/D) Module” and Section 23.0 “Special
Features of the CPU”.
• Made minor changes to Section 17.3.3
“Enabling SPI I/O”; Table 1-2, Table 1-3,
Table 3-3, Table 12-1 and Table 26-2; Figure 12-3
and Figure 16-1; Example 10-1 and
Example 10-2; and Table 21-1 and Table 23-1.
DS39599G-page 375
PIC18F2220/2320/4220/4320
APPENDIX B:
DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F2220
PIC18F2320
PIC18F4220
PIC18F4320
Program Memory (Bytes)
4096
8192
4096
8192
Program Memory (Instructions)
2048
4096
2048
4096
19
19
20
20
Interrupt Sources
I/O Ports
Ports A, B, C, (E)
Ports A, B, C, (E)
Capture/Compare/PWM Modules
2
2
1
1
Enhanced Capture/Compare/
PWM Modules
0
0
1
1
Parallel Communications (PSP)
No
No
Yes
Yes
10-bit Analog-to-Digital Module
10 Input Channels
10 Input Channels
13 Input Channels
13 Input Channels
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
Packages
DS39599G-page 376
28-Pin SPDIP
28-Pin SOIC
Ports A, B, C, D, E Ports A, B, C, D, E
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
APPENDIX C:
CONVERSION
CONSIDERATIONS
This appendix discusses the considerations for converting from previous versions of a device to the ones
listed in this data sheet. Typically, these changes are
due to the differences in the process technology used.
An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
Not Applicable
© 2007 Microchip Technology Inc.
APPENDIX D:
MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Currently Available
DS39599G-page 377
PIC18F2220/2320/4220/4320
APPENDIX E:
MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442.” The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
APPENDIX F:
MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration.” This Application Note is
available as Literature Number DS00726.
This Application Note is available as Literature Number
DS00716.
DS39599G-page 378
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
INDEX
A
A/D ................................................................................... 211
A/D Converter Interrupt, Configuring ....................... 215
Acquisition Requirements ........................................ 216
ADCON0 Register .................................................... 211
ADCON1 Register .................................................... 211
ADCON2 Register .................................................... 211
ADRESH Register ............................................ 211, 214
ADRESL Register .................................................... 211
Analog Port Pins, Configuring .................................. 218
Associated Registers ............................................... 220
Automatic Acquisition Time ...................................... 217
Configuring the Module ............................................ 215
Conversion Clock (Tad) ........................................... 217
Conversion Status (GO/DONE Bit) .......................... 214
Conversions ............................................................. 219
Converter Characteristics ........................................ 345
Operation in Power-Managed Modes ...................... 218
Special Event Trigger (CCP) ............................ 136, 220
Use of the CCP2 Trigger .......................................... 220
Vref+ and Vref- References ..................................... 216
Absolute Maximum Ratings ............................................. 305
AC (Timing) Characteristics ............................................. 326
Load Conditions for Device Timing
Specifications ................................................... 327
Parameter Symbology ............................................. 326
Temperature and Voltage Specifications ................. 327
Timing Conditions .................................................... 327
Access Bank ...................................................................... 65
ACKSTAT Status Flag ..................................................... 185
ADCON0 Register ............................................................ 211
GO/DONE Bit ........................................................... 214
ADCON1 Register ............................................................ 211
ADCON2 Register ............................................................ 211
ADDLW ............................................................................ 263
Addressable Universal Synchronous Asynchronous
Receiver Transmitter. See USART
ADDWF ............................................................................ 263
ADDWFC ......................................................................... 264
ADRESH Register ............................................................ 211
ADRESL Register .................................................... 211, 214
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 264
ANDWF ............................................................................ 265
Assembler
MPASM Assembler .................................................. 302
B
Bank Select Register (BSR) ............................................... 65
Baud Rate Generator ....................................................... 181
BC .................................................................................... 265
BCF .................................................................................. 266
BF Status Flag ................................................................. 185
Block Diagrams
A/D ........................................................................... 214
Analog Input Model .................................................. 215
Baud Rate Generator ............................................... 181
Capture Mode Operation ......................................... 135
Comparator I/O Operating Modes ............................ 222
Comparator Output .................................................. 224
Comparator Voltage Reference ............................... 228
Compare Mode Operation ....................................... 136
© 2007 Microchip Technology Inc.
External Power-on Reset Circuit
(Slow VDD Power-up) ........................................ 44
Fail-Safe Clock Monitor ........................................... 249
Generic I/O Port Operation ...................................... 101
Interrupt Logic ............................................................ 88
Low-Voltage Detect (LVD) ....................................... 232
Low-Voltage Detect (LVD) with External Input ........ 232
MCLR/Vpp/RE3 Pin ................................................. 112
MSSP (I2C Master Mode) ........................................ 179
MSSP (I2C Mode) .................................................... 164
MSSP (SPI Mode) ................................................... 155
On-Chip Reset Circuit ................................................ 43
PIC18F2220/2320 ....................................................... 9
PIC18F4220/4320 ..................................................... 10
PLL ............................................................................ 20
PORTC (Peripheral Output Override) ...................... 107
PORTD and PORTE (Parallel Slave Port) ............... 114
PWM (Enhanced) .................................................... 143
PWM (Standard) ...................................................... 138
RA3:RA0 and RA5 Pins ........................................... 102
RA4/T0CKI Pin ........................................................ 102
RA6 Pin ................................................................... 102
RA7 Pin ................................................................... 102
RB2:RB0 Pins .......................................................... 105
RB3/CCP2 Pin ......................................................... 105
RB4 Pin ................................................................... 105
RB7:RB5 Pins .......................................................... 104
RD4:RD0 Pins ......................................................... 110
RD7:RD5 Pins ......................................................... 109
RE2:RE0 Pins .......................................................... 111
Reads from Flash Program Memory .......................... 75
System Clock ............................................................. 26
Table Read Operation ............................................... 71
Table Write Operation ................................................ 72
Table Writes to Flash Program Memory .................... 77
Timer0 in 16-Bit Mode ............................................. 118
Timer0 in 8-Bit Mode ............................................... 118
Timer1 ..................................................................... 122
Timer1 (16-Bit Read/Write Mode) ............................ 122
Timer2 ..................................................................... 128
Timer3 ..................................................................... 130
Timer3 (16-Bit Read/Write Mode) ............................ 130
USART Receive ....................................................... 204
USART Transmit ...................................................... 202
Watchdog Timer ...................................................... 246
BN .................................................................................... 266
BNC ................................................................................. 267
BNN ................................................................................. 267
BNOV ............................................................................... 268
BNZ .................................................................................. 268
BOR. See Brown-out Reset.
BOV ................................................................................. 271
BRA ................................................................................. 269
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ..............................................44, 237
BSF .................................................................................. 269
BTFSC ............................................................................. 270
BTFSS ............................................................................. 270
BTG ................................................................................. 271
BZ .................................................................................... 272
DS39599G-page 379
PIC18F2220/2320/4220/4320
C
C Compilers
MPLAB C18 ............................................................. 302
MPLAB C30 ............................................................. 302
CALL ................................................................................ 272
Capture (CCP Module) ..................................................... 135
Associated Registers ............................................... 137
CCP Pin Configuration ............................................. 135
CCPR1H:CCPR1L Registers ................................... 135
Software Interrupt ..................................................... 135
Timer1/Timer3 Mode Selection ................................ 135
Capture (ECCP Module) .................................................. 142
Capture/Compare/PWM (CCP) ........................................ 133
Capture Mode. See Capture.
CCP1 ........................................................................ 134
CCPR1H Register ............................................ 134
CCPR1L Register ............................................ 134
CCP2 ........................................................................ 134
CCPR2H Register ............................................ 134
CCPR2L Register ............................................ 134
Compare Mode. See Compare.
Interaction of Two CCP Modules ............................. 134
PWM Mode. See PWM.
Timer Resources ...................................................... 134
Clock Sources .................................................................... 25
Selection Using OSCCON Register ........................... 25
Clocking Scheme/Instruction Cycle .................................... 57
CLRF ................................................................................ 273
CLRWDT .......................................................................... 273
Code Examples
16 x 16 Signed Multiply Routine ................................. 86
16 x 16 Unsigned Multiply Routine ............................. 86
8 x 8 Signed Multiply Routine ..................................... 85
8 x 8 Unsigned Multiply Routine ................................. 85
Changing Between Capture Prescalers ................... 135
Computed GOTO Using an Offset Value ................... 59
Data EEPROM Read ................................................. 83
Data EEPROM Refresh Routine ................................ 84
Data EEPROM Write .................................................. 83
Erasing a Flash Program Memory Row ..................... 76
Fast Register Stack .................................................... 56
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................ 66
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service .................................. 125
Initializing PORTA .................................................... 101
Initializing PORTB .................................................... 104
Initializing PORTC .................................................... 107
Initializing PORTD .................................................... 109
Initializing PORTE .................................................... 111
Loading the SSPBUF (SSPSR) Register ................. 158
Reading a Flash Program Memory Word ................... 75
Saving STATUS, WREG and BSR
Registers in RAM ............................................... 99
Writing to Flash Program Memory ....................... 78–79
Code Protection ....................................................... 237, 252
COMF ............................................................................... 274
Comparator ...................................................................... 221
Analog Input Connection Considerations ................. 225
Associated Registers ............................................... 226
Configuration ............................................................ 221
Effects of a Reset ..................................................... 225
Interrupts .................................................................. 224
Operation ................................................................. 223
Operation in Power-Managed Modes ...................... 225
DS39599G-page 380
Outputs .................................................................... 223
Reference ................................................................ 223
Response Time ........................................................ 223
Comparator Specifications ............................................... 322
Comparator Voltage Reference ....................................... 227
Accuracy and Error .................................................. 228
Associated Registers ............................................... 229
Configuring .............................................................. 227
Connection Considerations ...................................... 228
Effects of a Reset .................................................... 228
Operation in Power-Managed Modes ...................... 228
Compare (CCP Module) .................................................. 136
Associated Registers ............................................... 137
CCP Pin Configuration ............................................. 136
CCPR1 Register ...................................................... 136
Software Interrupt .................................................... 136
Special Event Trigger .......................................136, 220
Timer1/Timer3 Mode Selection ................................ 136
Compare (ECCP Mode) ................................................... 142
Computed GOTO ............................................................... 59
Configuration Bits ............................................................ 237
Configuration Register Protection .................................... 255
Context Saving During Interrupts ....................................... 99
Control Registers
EECON1 and EECON2 ............................................. 72
Conversion Considerations .............................................. 377
CPFSEQ .......................................................................... 274
CPFSGT .......................................................................... 275
CPFSLT ........................................................................... 275
Crystal Oscillator/Ceramic Resonator ................................ 19
Customer Change Notification Service ............................ 389
Customer Notification Service .......................................... 389
Customer Support ............................................................ 389
D
Data EEPROM Code Protection ...................................... 255
Data EEPROM Memory ..................................................... 81
Associated Registers ................................................. 84
EEADR Register ........................................................ 81
EECON1 and EECON2 Registers ............................. 81
Operation During Code-Protect ................................. 84
Protection Against Spurious Write ............................. 83
Reading ..................................................................... 83
Using .......................................................................... 84
Write Verify ................................................................ 83
Writing ........................................................................ 83
Data Memory ..................................................................... 59
General Purpose Registers ....................................... 59
Map for PIC18F2X20/4X20 ........................................ 60
Special Function Registers ........................................ 61
DAW ................................................................................ 276
DC and AC Characteristics
Graphs and Tables .................................................. 347
DC Characteristics ........................................................... 319
Power-Down and Supply Current ............................ 310
Supply Voltage ......................................................... 308
DCFSNZ .......................................................................... 277
DECF ............................................................................... 276
DECFSZ .......................................................................... 277
Development Support ...................................................... 301
Device Differences ........................................................... 376
Device Overview .................................................................. 7
Features (table) ........................................................... 8
New Core Features ...................................................... 7
Other Special Features ................................................ 7
Direct Addressing ............................................................... 67
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
E
I
ECCP ............................................................................... 141
Auto-Shutdown ........................................................ 149
And Automatic Restart ..................................... 151
Capture and Compare Modes .................................. 142
Outputs .................................................................... 142
Standard PWM Mode ............................................... 142
Start-up Considerations ........................................... 151
Effects of Power-Managed Modes on
Various Clock Sources ............................................... 28
Electrical Characteristics .................................................. 305
Enhanced Capture/Compare/PWM (ECCP) .................... 141
Capture Mode. See Capture (ECCP Module).
PWM Mode. See PWM (ECCP Module).
Enhanced CCP Auto-Shutdown ....................................... 149
Enhanced PWM Mode. See PWM (ECCP Module). ........ 143
Equations
I/O Ports ........................................................................... 101
I2C Mode
ACK Pulse ........................................................168, 169
Acknowledge Sequence Timing .............................. 188
Baud Rate Generator .............................................. 181
Bus Collision During a Repeated
Start Condition ................................................. 192
Bus Collision During a Start Condition ..................... 190
Bus Collision During a Stop Condition ..................... 193
Clock Arbitration ...................................................... 182
Clock Stretching ....................................................... 174
Effect of a Reset ...................................................... 189
General Call Address Support ................................. 178
Master Mode ............................................................ 179
Master Mode (Reception, 7-Bit Address) ................. 187
Master Mode Operation ........................................... 180
Master Mode Reception ........................................... 185
Master Mode Repeated Start Condition Timing ....... 184
Master Mode Start Condition Timing ....................... 183
Master Mode Transmission ..................................... 185
Multi-Master Communication, Bus Collision
and Bus Arbitration .......................................... 189
Multi-Master Mode ................................................... 189
Operation ................................................................. 168
Operation in Power-Managed Mode ........................ 189
Read/Write Bit Information (R/W Bit) ................168, 169
Registers ................................................................. 164
Serial Clock (RC3/SCK/SCL) ................................... 169
Slave Mode .............................................................. 168
Addressing ....................................................... 168
Reception ........................................................ 169
Transmission ................................................... 169
Stop Condition Timing ............................................. 188
ID Locations ..............................................................237, 255
INCF ................................................................................ 278
INCFSZ ............................................................................ 279
In-Circuit Debugger .......................................................... 255
In-Circuit Serial Programming (ICSP) .......................237, 255
Indirect Addressing
INDF and FSR Registers ........................................... 66
Operation ................................................................... 66
Indirect Addressing Operation ........................................... 67
Indirect File Operand ......................................................... 59
INFSNZ ............................................................................ 279
Initialization Conditions for all Registers .......................46–49
Instruction Cycle ................................................................ 57
Instruction Flow/Pipelining ................................................. 57
Instruction Format ............................................................ 259
Instruction Set .................................................................. 257
ADDLW .................................................................... 263
ADDWF .................................................................... 263
ADDWFC ................................................................. 264
ANDLW .................................................................... 264
ANDWF .................................................................... 265
BC ............................................................................ 265
BCF ......................................................................... 266
BN ............................................................................ 266
BNC ......................................................................... 267
BNN ......................................................................... 267
BNOV ...................................................................... 268
BNZ ......................................................................... 268
BOV ......................................................................... 271
BRA ......................................................................... 269
BSF .......................................................................... 269
Calculating the Minimum Required
Acquisition Time ...................................... 216
16 x 16 Signed Multiplication Algorithm ..................... 86
16 x 16 Unsigned Multiplication Algorithm ................. 86
A/D Acquisition Time ................................................ 216
A/D Minimum Holding Capacitor .............................. 216
Errata ................................................................................... 5
External Clock Input ........................................................... 21
F
Fail-Safe Clock Monitor ............................................ 237, 249
Interrupts in Power-Managed Modes ....................... 251
POR or Wake from Sleep ........................................ 251
WDT During Oscillator Failure ................................. 249
Fast Register Stack ............................................................ 56
Firmware Instructions ....................................................... 257
Flash Program Memory ...................................................... 71
Associated Registers ................................................. 79
Control Registers ....................................................... 72
Erase Sequence ........................................................ 76
Erasing ....................................................................... 76
Operation During Code-Protect ................................. 79
Reading ...................................................................... 75
TABLAT Register ....................................................... 74
Table Pointer .............................................................. 74
Boundaries Based on Operation ........................ 74
Table Pointer Boundaries .......................................... 74
Table Reads and Table Writes .................................. 71
Unexpected Termination of Write Operation .............. 79
Write Verify ................................................................ 79
Writing to .................................................................... 77
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 278
H
Hardware Multiplier ............................................................ 85
Introduction ................................................................ 85
Operation ................................................................... 85
Performance Comparison .......................................... 85
HSPLL ................................................................................ 20
© 2007 Microchip Technology Inc.
DS39599G-page 381
PIC18F2220/2320/4220/4320
BTFSC ..................................................................... 270
BTFSS ...................................................................... 270
BTG .......................................................................... 271
BZ ............................................................................. 272
CALL ........................................................................ 272
CLRF ........................................................................ 273
CLRWDT .................................................................. 273
COMF ....................................................................... 274
CPFSEQ .................................................................. 274
CPFSGT ................................................................... 275
CPFSLT ................................................................... 275
DAW ......................................................................... 276
DCFSNZ ................................................................... 277
DECF ....................................................................... 276
DECFSZ ................................................................... 277
GOTO ....................................................................... 278
INCF ......................................................................... 278
INCFSZ .................................................................... 279
INFSNZ .................................................................... 279
IORLW ..................................................................... 280
IORWF ..................................................................... 280
LFSR ........................................................................ 281
MOVF ....................................................................... 281
MOVFF ..................................................................... 282
MOVLB ..................................................................... 282
MOVLW .................................................................... 283
MOVWF ................................................................... 283
MULLW .................................................................... 284
MULWF .................................................................... 284
NEGF ....................................................................... 285
NOP ......................................................................... 285
POP .......................................................................... 286
PUSH ....................................................................... 286
RCALL ...................................................................... 287
Reset ........................................................................ 287
RETFIE .................................................................... 288
RETLW ..................................................................... 288
RETURN .................................................................. 289
RLCF ........................................................................ 289
RLNCF ..................................................................... 290
RRCF ....................................................................... 290
RRNCF ..................................................................... 291
SETF ........................................................................ 291
SLEEP ...................................................................... 292
SUBFWB .................................................................. 292
SUBLW .................................................................... 293
SUBWF .................................................................... 293
SUBWFB .................................................................. 294
SWAPF .................................................................... 295
TBLRD ..................................................................... 296
TBLWT ..................................................................... 297
TSTFSZ .................................................................... 298
XORLW .................................................................... 298
XORWF .................................................................... 299
Summary Table ........................................................ 260
INTCON Register
RBIF Bit .................................................................... 104
INTCON Registers ............................................................. 89
Inter-Integrated Circuit. See I2C.
Internal Oscillator Block ..................................................... 22
Internal RC Oscillator
Use with WDT .......................................................... 246
Internet Address ............................................................... 389
DS39599G-page 382
Interrupt Sources ............................................................. 237
A/D Conversion Complete ....................................... 215
Capture Complete (CCP) ......................................... 135
Compare Complete (CCP) ....................................... 136
Interrupt-on-Change (RB7:RB4) .............................. 104
INTx Pin ..................................................................... 99
PORTB, Interrupt-on-Change .................................... 99
TMR0 ......................................................................... 99
TMR1 Overflow ........................................................ 121
TMR2 to PR2 Match ................................................ 128
TMR2 to PR2 Match (PWM) .............................127, 138
TMR3 Overflow .................................................129, 131
USART Receive/Transmit Complete ....................... 195
Interrupts ............................................................................ 87
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) ..................................... 135
Interrupts, Flag Bits
CCP1 Flag (CCP1IF Bit) .......................................... 135
CCP1IF Flag (CCP1IF Bit) ....................................... 136
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ......................................................... 104
INTOSC Frequency Drift .................................................... 40
INTOSC, INTRC. See Internal Oscillator Block.
IORLW ............................................................................. 280
IORWF ............................................................................. 280
IPR Registers ..................................................................... 96
L
LFSR ................................................................................ 281
Look-up Tables .................................................................. 59
Low-Voltage Detect ......................................................... 231
Characteristics ......................................................... 323
Effects of a Reset .................................................... 235
Operation ................................................................. 234
Current Consumption ....................................... 235
Reference Voltage Set Point ........................... 235
Operation During Sleep ........................................... 235
Low-Voltage ICSP Programming ..................................... 255
LVD. See Low-Voltage Detect. ........................................ 231
M
Master Synchronous Serial Port (MSSP). See MSSP.
Master Synchronous Serial Port. See MSSP
Memory Organization ......................................................... 53
Data Memory ............................................................. 59
Program Memory ....................................................... 53
Memory Programming Requirements .............................. 321
Microchip Internet Web Site ............................................. 389
Migration from Baseline to Enhanced Devices ................ 377
Migration from High-End to Enhanced Devices ............... 378
Migration from Mid-Range to Enhanced Devices ............ 378
MOVF .............................................................................. 281
MOVFF ............................................................................ 282
MOVLB ............................................................................ 282
MOVLW ........................................................................... 283
MOVWF ........................................................................... 283
MPLAB ASM30 Assembler, Linker, Librarian .................. 302
MPLAB ICD 2 In-Circuit Debugger .................................. 303
MPLAB ICE 2000 High-Performance
Universal In-Circuit Emulator ................................... 303
MPLAB Integrated Development
Environment Software ............................................. 301
MPLAB PM3 Device Programmer ................................... 303
MPLAB REAL ICE In-Circuit Emulator System ................ 303
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
MPLINK Object Linker/MPLIB Object Librarian ............... 302
MSSP ............................................................................... 155
Control Registers (General) ..................................... 155
Enabling SPI I/O ...................................................... 159
I2C Master Mode ...................................................... 179
I2C Mode
I2C Mode. See I2C
I2C Slave Mode ........................................................ 168
Operation ................................................................. 158
Overview .................................................................. 155
Slave Select Control ................................................ 161
SPI Master Mode ..................................................... 160
SPI Master/Slave Connection .................................. 159
SPI Mode ................................................................. 155
SPI Slave Mode ....................................................... 161
SSPBUF Register .................................................... 160
SSPSR Register ...................................................... 160
TMR2 Output for Clock Shift ............................ 127, 128
Typical Connection .................................................. 159
MULLW ............................................................................ 284
MULWF ............................................................................ 284
N
NEGF ............................................................................... 285
NOP ................................................................................. 285
O
Opcode Field Descriptions ............................................... 258
Oscillator Configuration ...................................................... 19
EC .............................................................................. 19
ECIO .......................................................................... 19
HS .............................................................................. 19
HSPLL ........................................................................ 19
Internal Oscillator Block ............................................. 22
INTIO1 ....................................................................... 19
INTIO2 ....................................................................... 19
LP ............................................................................... 19
RC .............................................................................. 19
RCIO .......................................................................... 19
XT .............................................................................. 19
Oscillator Selection .......................................................... 237
Oscillator Start-up Timer (OST) ............................28, 44, 237
Oscillator Switching ............................................................ 25
Oscillator Transitions .......................................................... 28
Oscillator, Timer1 ..................................................... 121, 131
Oscillator, Timer3 ............................................................. 129
P
Packaging Information ..................................................... 365
Details ...................................................................... 367
Marking ............................................................ 365, 366
Parallel Slave Port (PSP) ......................................... 109, 114
Associated Registers ............................................... 115
CS (Chip Select) .............................................. 113, 114
PORTD .................................................................... 114
RD (Read Input) ............................................... 113, 114
RE0/AN5/RD Pin ...................................................... 113
RE1/AN6/WR Pin ..................................................... 113
RE2/AN7/CS Pin ...................................................... 113
Select (PSPMODE Bit) .................................... 109, 114
WR (Write Input) .............................................. 113, 114
PICSTART Plus Development Programmer .................... 304
PIE Registers ..................................................................... 94
Pin Functions
MCLR/Vpp/RE3 ................................................... 11, 14
OSC1/CLKI/RA7 .................................................. 11, 14
© 2007 Microchip Technology Inc.
OSC2/CLKO/RA6 .................................................11, 14
RA0/AN0 ...............................................................11, 14
RA1/AN1 ...............................................................11, 14
RA2/AN2/Vref-/CVref ............................................11, 14
RA3/AN3/Vref+ .....................................................11, 14
RA4/T0CKI/C1OUT ..............................................11, 14
RA5/AN4/SS/LVDIN/C2OUT ................................11, 14
RB0/AN12/INT0 ....................................................12, 15
RB1/AN10/INT1 ....................................................12, 15
RB2/AN8/INT2 ......................................................12, 15
RB3/AN9/CCP2 ....................................................12, 15
RB4/AN11/KBI0 ....................................................12, 15
RB5/KBI1/PGM .....................................................12, 15
RB6/KBI2/PGC .....................................................12, 15
RB7/KBI3/PGD .......................................................... 12
RB7/PGD ................................................................... 15
RC0/T1OSO/T1CKI ..............................................13, 16
RC1/T1OSI/CCP2 .................................................13, 16
RC2/CCP1/P1A ....................................................13, 16
RC3/SCK/SCL ......................................................13, 16
RC4/SDI/SDA .......................................................13, 16
RC5/SDO ..............................................................13, 16
RC6/TX/CK ...........................................................13, 16
RC7/RX/DT ...........................................................13, 16
RD0/PSP0 ................................................................. 17
RD1/PSP1 ................................................................. 17
RD2/PSP2 ................................................................. 17
RD3/PSP3 ................................................................. 17
RD4/PSP4 ................................................................. 17
RD5/PSP5/P1B ......................................................... 17
RD6/PSP6/P1C ......................................................... 17
RD7/PSP7/P1D ......................................................... 17
RE0/AN5/RD .............................................................. 18
RE1/AN6/WR ............................................................. 18
RE2/AN7/CS .............................................................. 18
RE3 ............................................................................ 18
VDD .......................................................................13, 18
Vss ........................................................................13, 18
Pinout I/O Descriptions
PIC18F2220/2320 ..................................................... 11
PIC18F4220/4320 ..................................................... 14
PIR Registers ..................................................................... 92
PLL Lock Time-out ............................................................. 44
Pointer, FSRn .................................................................... 66
POP ................................................................................. 286
POR. See Power-on Reset.
PORTA
Associated Registers ............................................... 103
LATA Register ......................................................... 101
PORTA Register ...................................................... 101
TRISA Register ........................................................ 101
PORTB
Associated Registers ............................................... 106
LATB Register ......................................................... 104
PORTB Register ...................................................... 104
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 104
TRISB Register ........................................................ 104
PORTC
Associated Registers ............................................... 108
LATC Register ......................................................... 107
PORTC Register ...................................................... 107
TRISC Register ........................................................ 107
DS39599G-page 383
PIC18F2220/2320/4220/4320
PORTD
Associated Registers ............................................... 110
LATD Register .......................................................... 109
Parallel Slave Port (PSP) Function .......................... 109
PORTD Register ...................................................... 109
TRISD Register ........................................................ 109
PORTE
Analog Port Pins ...................................................... 113
Associated Registers ............................................... 113
LATE Register .......................................................... 111
PORTE Register ...................................................... 111
PSP Mode Select (PSPMODE Bit) .......................... 109
RE0/AN5/RD Pin ...................................................... 113
RE1/AN6/WR Pin ..................................................... 113
RE2/AN7/CS Pin ...................................................... 113
TRISE Register ........................................................ 111
Postscaler, WDT
Assignment (PSA Bit) ............................................... 119
Rate Select (T0PS2:T0PS0 Bits) ............................. 119
Power-Managed Modes ..................................................... 29
Entering ...................................................................... 30
Idle Modes .................................................................. 31
Run Modes ................................................................. 36
Sleep Mode ................................................................ 31
Summary (table) ......................................................... 29
Wake from .................................................................. 38
Power-on Reset (POR) .............................................. 44, 237
Power-up Delays ................................................................ 28
Power-up Timer (PWRT) ...................................... 28, 44, 237
Prescaler, Capture ........................................................... 135
Prescaler, Timer0 ............................................................. 119
Assignment (PSA Bit) ............................................... 119
Rate Select (T0PS2:T0PS0 Bits) ............................. 119
Prescaler, Timer2 ............................................................. 139
Product Identification System ........................................... 391
Program Counter
PCL Register .............................................................. 56
PCLATH Register ....................................................... 56
PCLATU Register ....................................................... 56
Program Memory
Instructions ................................................................. 58
Two-Word .......................................................... 58
Interrupt Vector .......................................................... 53
Map and Stack for PIC18F2220/4220 ........................ 53
Map and Stack for PIC18F2320/4320 ........................ 53
Reset Vector .............................................................. 53
Program Memory Code Protection ................................... 253
Program Verification ......................................................... 252
Program Verification and Code Protection
Associated Registers ............................................... 252
Programming, Device Instructions ................................... 257
PSP. See Parallel Slave Port.
Pulse-Width Modulation. See PWM (CCP Module)
and PWM (ECCP Module).
PUSH ............................................................................... 286
PUSH and POP Instructions .............................................. 55
PWM (CCP Module) ......................................................... 138
Associated Registers ............................................... 139
CCPR1H:CCPR1L Registers ................................... 138
Duty Cycle ................................................................ 138
Example Frequencies/Resolutions ........................... 139
Period ....................................................................... 138
Setup for PWM Operation ........................................ 139
TMR2 to PR2 Match ......................................... 127, 138
DS39599G-page 384
PWM (ECCP Module) ...................................................... 143
Associated Registers ............................................... 153
Direction Change in Full-Bridge
Output Mode .................................................... 147
Effects of a Reset .................................................... 152
Full-Bridge Application Example .............................. 147
Full-Bridge Mode ..................................................... 146
Half-Bridge Mode ..................................................... 145
Half-Bridge Output Mode Applications Example ...... 145
Operation in Power-Managed Modes ...................... 152
Operation with Fail-Safe Clock Monitor ................... 152
Output Configurations .............................................. 143
Output Relationships (Active-High State) ................ 144
Output Relationships (Active-Low State) ................. 144
Programmable Dead-Band Delay ............................ 149
Setup for Operation ................................................. 152
Shoot-Through Current ............................................ 149
Start-up Considerations ........................................... 151
Q
Q Clock ............................................................................ 139
R
RAM. See Data Memory.
RC Oscillator ...................................................................... 21
RCIO Oscillator Mode ................................................ 21
RCALL ............................................................................. 287
RCON Register
Bit Status During Initialization .................................... 45
Bits and Positions ...................................................... 45
RCSTA Register
SPEN Bit .................................................................. 195
Reader Response ............................................................ 390
Register File ....................................................................... 59
Registers
ADCON0 (A/D Control 0) ......................................... 211
ADCON1 (A/D Control 1) ......................................... 212
ADCON2 (A/D Control 2) ......................................... 213
CCP1CON (ECCP Control) ..................................... 141
CCPxCON (CCPx Control) ...................................... 133
CMCON (Comparator Control) ................................ 221
CONFIG1H (Configuration 1 High) .......................... 238
CONFIG2H (Configuration 2 High) .......................... 240
CONFIG2L (Configuration 2 Low) ........................... 239
CONFIG3H (Configuration 3 High) .......................... 241
CONFIG4L (Configuration 4 Low) ........................... 241
CONFIG5H (Configuration 5 High) .......................... 242
CONFIG5L (Configuration 5 Low) ........................... 242
CONFIG6H (Configuration 6 High) .......................... 243
CONFIG6L (Configuration 6 Low) ........................... 243
CONFIG7H (Configuration 7 High) .......................... 244
CONFIG7L (Configuration 7 Low) ........................... 244
CVRCON (Comparator Voltage
Reference Control) .......................................... 227
DEVID1 (Device ID 1) .............................................. 245
DEVID2 (Device ID 2) .............................................. 245
ECCPAS (Enhanced Capture/Compare/PWM
Auto-Shutdown Control) .................................. 150
EECON1 (Data EEPROM Control 1) ....................73, 82
INTCON (Interrupt Control) ........................................ 89
INTCON2 (Interrupt Control 2) ................................... 90
INTCON3 (Interrupt Control 3) ................................... 91
IPR1 (Peripheral Interrupt Priority 1) ......................... 96
IPR2 (Peripheral Interrupt Priority 2) ......................... 97
LVDCON (Low-Voltage Detect Control) .................. 233
OSCCON (Oscillator Control) .................................... 27
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
OSCTUN2 (INTRC Oscillator Tuning) ........................ 24
PIE1 (Peripheral Interrupt Enable 1) .......................... 94
PIE2 (Peripheral Interrupt Enable 2) .......................... 95
PIR1 (Peripheral Interrupt Request
(Flag) 1) ............................................................. 92
PIR2 (Peripheral Interrupt Request
(Flag) 2) ............................................................. 93
PWM1CON (PWM Configuration) ............................ 149
RCON (Reset Control) ......................................... 69, 98
RCSTA (Receive Status and Control) ...................... 197
SSPCON1 (MSSP Control 1, I2C Mode) ................. 166
SSPCON1 (MSSP Control 1, SPI Mode) ................. 157
SSPCON2 (MSSP Control 2,
I2C Master Mode) ............................................. 167
SSPSTAT (MSSP Status, I2C Mode) ....................... 165
SSPSTAT (MSSP Status, SPI Mode) ...................... 156
STATUS ..................................................................... 68
STKPTR (Stack Pointer) ............................................ 55
Summary .............................................................. 62–64
T0CON (Timer0 Control) .......................................... 117
T1CON (Timer1 Control) .......................................... 121
T2CON (Timer2 Control) .......................................... 127
T3CON (Timer3 Control) .......................................... 129
TRISE ...................................................................... 112
TXSTA (Transmit Status and Control) ..................... 196
WDTCON (Watchdog Timer Control) ....................... 247
Reset .......................................................................... 43, 287
Resets .............................................................................. 237
RETFIE ............................................................................ 288
RETLW ............................................................................. 288
RETURN .......................................................................... 289
Return Address Stack ........................................................ 54
Return Stack Pointer (STKPTR) ........................................ 54
Revision History ............................................................... 375
RLCF ................................................................................ 289
RLNCF ............................................................................. 290
RRCF ............................................................................... 290
RRNCF ............................................................................. 291
S
SCI. See USART
SCK .................................................................................. 155
SDI ................................................................................... 155
SDO ................................................................................. 155
Serial Clock (SCK) Pin ..................................................... 155
Serial Communication Interface. See USART.
Serial Data In (SDI) Pin .................................................... 155
Serial Data Out (SDO) Pin ............................................... 155
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 291
Shoot-Through Current .................................................... 149
Slave Select (SS) Pin ....................................................... 155
SLEEP .............................................................................. 292
Sleep
OSC1 and OSC2 Pin States ...................................... 28
Software Simulator (MPLAB SIM) .................................... 302
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ............................................ 237
Special Function Registers ................................................ 61
Map ............................................................................ 61
© 2007 Microchip Technology Inc.
SPI Mode
Associated Registers ............................................... 163
Bus Mode Compatibility ........................................... 163
Effects of a Reset .................................................... 163
Master in Power-Managed Modes ........................... 163
Master Mode ............................................................ 160
Master/Slave Connection ......................................... 159
Registers ................................................................. 156
Serial Clock .............................................................. 155
Serial Data In ........................................................... 155
Serial Data Out ........................................................ 155
Slave in Power-Managed Modes ............................. 163
Slave Mode .............................................................. 161
Slave Select ............................................................. 155
SPI Clock ................................................................. 160
SS .................................................................................... 155
SSPOV Status Flag ......................................................... 185
SSPSTAT Register
R/W Bit .............................................................168, 169
Stack Full/Underflow Resets .............................................. 55
SUBFWB ......................................................................... 292
SUBLW ............................................................................ 293
SUBWF ............................................................................ 293
SUBWFB ......................................................................... 294
SWAPF ............................................................................ 295
T
T0CON Register
PSA Bit .................................................................... 119
T0CS Bit .................................................................. 119
T0PS2:T0PS0 Bits ................................................... 119
T0SE Bit .................................................................. 119
TABLAT Register ............................................................... 74
Table Pointer Operations (table) ........................................ 74
Table Reads/Table Writes ................................................. 59
TBLPTR Register ............................................................... 74
TBLRD ............................................................................. 296
TBLWT ............................................................................. 297
Time-out in Various Situations (table) ................................ 45
Time-out Sequence ........................................................... 44
Timer0 .............................................................................. 117
16-Bit Mode Timer Reads and Writes ...................... 119
Associated Registers ............................................... 119
Clock Source Edge Select (T0SE Bit) ..................... 119
Clock Source Select (T0CS Bit) ............................... 119
Interrupt ................................................................... 119
Operation ................................................................. 119
Prescaler. See Prescaler, Timer0.
Switching Prescaler Assignment ............................. 119
Timer1 .............................................................................. 121
16-Bit Read/Write Mode .......................................... 124
Associated Registers ............................................... 125
Interrupt ................................................................... 124
Operation ................................................................. 122
Oscillator ...........................................................121, 123
Oscillator Layout Considerations ............................. 123
Overflow Interrupt .................................................... 121
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 124
Special Event Trigger (CCP) ................................... 136
TMR1H Register ...................................................... 121
TMR1L Register ....................................................... 121
Use as a Real-Time Clock ....................................... 124
DS39599G-page 385
PIC18F2220/2320/4220/4320
Timer2 .............................................................................. 127
Associated Registers ............................................... 128
MSSP Clock Shift ............................................. 127, 128
Operation ................................................................. 127
Postscaler. See Postscaler, Timer2.
PR2 Register .................................................... 127, 138
Prescaler. See Prescaler, Timer2.
TMR2 Register ......................................................... 127
TMR2 to PR2 Match Interrupt .................. 127, 128, 138
Timer3 .............................................................................. 129
Associated Registers ............................................... 131
Operation ................................................................. 130
Oscillator .......................................................... 129, 131
Overflow Interrupt ............................................. 129, 131
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 131
TMR3H Register ...................................................... 129
TMR3L Register ....................................................... 129
Timing Diagrams
A/D Conversion ........................................................ 346
Acknowledge Sequence ........................................... 188
Asynchronous Reception ......................................... 205
Asynchronous Transmission .................................... 203
Asynchronous Transmission (Back to Back) ............ 203
Baud Rate Generator with Clock Arbitration ............ 182
BRG Reset Due to SDA Arbitration During
Start Condition ................................................. 191
Brown-out Reset (BOR) ........................................... 331
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 192
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 192
Bus Collision During a Stop
Condition (Case 1) ........................................... 193
Bus Collision During a Stop
Condition (Case 2) ........................................... 193
Bus Collision During Start
Condition (SCL = 0) ......................................... 191
Bus Collision During Start
Condition (SDA Only) ....................................... 190
Bus Collision for Transmit and Acknowledge ........... 189
Capture/Compare/PWM (CCP) ................................ 333
CLKO and I/O ........................................................... 330
Clock Synchronization .............................................. 175
Clock, Instruction Cycle .............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 335
Example SPI Master Mode (CKE = 1) ..................... 336
Example SPI Slave Mode (CKE = 0) ....................... 337
Example SPI Slave Mode (CKE = 1) ....................... 338
External Clock (All Modes Except PLL) ................... 328
Fail-Safe Clock Monitor (FSCM) .............................. 250
First Start Bit ............................................................ 183
Full-Bridge PWM Output .......................................... 146
Half-Bridge PWM Output .......................................... 145
I2C Bus Data ............................................................ 340
I2C Bus Start/Stop Bits ............................................. 339
I2C Master Mode (Transmission,
7 or 10-Bit Address) ......................................... 186
I2C Slave Mode (Transmission, 10-Bit Address) ...... 173
I2C Slave Mode (Transmission, 7-Bit Address) ........ 171
I2C Slave Mode with SEN = 0 (Reception,
10-Bit Address) ................................................ 172
I2C Slave Mode with SEN = 0 (Reception,
7-Bit Address) .................................................. 170
DS39599G-page 386
I2C Slave Mode with SEN = 1 (Reception,
10-Bit Address) ................................................ 177
I2C Slave Mode with SEN = 1 (Reception,
7-Bit Address) .................................................. 176
Low-Voltage Detect ................................................. 234
Low-Voltage Detect Characteristics ......................... 322
Master SSP I2C Bus Data ........................................ 342
Master SSP I2C Bus Start/Stop Bits ........................ 342
Parallel Slave Port (PIC18F4X20) ........................... 334
Parallel Slave Port (PSP) Read ............................... 115
Parallel Slave Port (PSP) Write ............................... 115
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 151
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 151
PWM Direction Change ........................................... 148
PWM Direction Change at Near
100% Duty Cycle ............................................. 148
PWM Output ............................................................ 138
Repeat Start Condition ............................................ 184
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST), Power-up Timer (PWRT) ........... 331
Slave Mode General Call Address Sequence
(7 or 10-Bit Addressing Mode) ......................... 178
Slave Synchronization ............................................. 161
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 51
SPI Mode (Master Mode) ......................................... 160
SPI Mode (Slave Mode with CKE = 0) ..................... 162
SPI Mode (Slave Mode with CKE = 1) ..................... 162
Stop Condition Receive or Transmit Mode .............. 188
Synchronous Transmission ..................................... 206
Synchronous Transmission (Through TXEN) .......... 207
Time-out Sequence on POR w/
PLL Enabled (MCLR Tied to VDD) ..................... 51
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 1 ....................... 50
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 2 ....................... 50
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 50
Timer0 and Timer1 External Clock .......................... 332
Transition for Entry to SEC_IDLE Mode .................... 34
Transition for Entry to SEC_RUN Mode .................... 36
Transition for Entry to Sleep Mode ............................ 32
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 248
Transition for Wake from PRI_IDLE Mode ................ 33
Transition for Wake from RC_RUN Mode
(RC_RUN to PRI_RUN) ..................................... 35
Transition for Wake from
SEC_RUN Mode (HSPLL) ................................. 34
Transition for Wake from Sleep (HSPLL) .................. 32
Transition to PRI_IDLE Mode .................................... 33
Transition to RC_IDLE Mode ..................................... 35
Transition to RC_RUN Mode ..................................... 37
USART Synchronous Receive (Master/Slave) ........ 344
USART Synchronous Reception
(Master Mode, SREN) ..................................... 208
USART SynchronousTransmission (Master/Slave) . 344
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
Timing Diagrams and Specifications ................................ 328
A/D Conversion Requirements ................................ 346
Capture/Compare/PWM Requirements ................... 334
CLKO and I/O Requirements ................................... 330
DC Characteristics - Internal RC Accuracy .............. 329
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 336
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 337
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 338
Example SPI Slave Mode
Requirements (CKE = 1) .................................. 339
External Clock Requirements .................................. 328
I2C Bus Data Requirements (Slave Mode) .............. 341
Master SSP I2C Bus Data Requirements ................ 343
Master SSP I2C Bus Start/Stop Bits
Requirements ................................................... 342
Parallel Slave Port Requirements
(PIC18F4X20) .................................................. 335
PLL Clock ................................................................. 329
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 332
Timer0 and Timer1 External Clock
Requirements ................................................... 333
USART Synchronous Receive Requirements ......... 344
USART Synchronous Transmission
Requirements ................................................... 344
Top-of-Stack Access .......................................................... 54
TRISE Register
PSPMODE Bit .......................................................... 109
TSTFSZ ............................................................................ 298
Two-Speed Start-up ................................................. 237, 248
Two-Word Instructions
Example Cases .......................................................... 58
TXSTA Register
BRGH Bit ................................................................. 198
Serial Port Enable (SPEN Bit) ................................. 195
Setting Up 9-Bit Mode with Address Detect ............. 204
Synchronous Master Mode ...................................... 206
Associated Registers, Reception ..................... 208
Associated Registers, Transmit ....................... 207
Reception ........................................................ 208
Transmission ................................................... 206
Synchronous Slave Mode ........................................ 209
Associated Registers, Receive ........................ 210
Associated Registers, Transmit ....................... 209
Reception ........................................................ 210
Transmission ................................................... 209
V
Voltage Reference Specifications .................................... 322
W
Watchdog Timer (WDT) ............................................237, 246
Associated Registers ............................................... 247
Control Register ....................................................... 246
During Oscillator Failure .......................................... 249
Programming Considerations .................................. 246
WCOL .............................................................................. 183
WCOL Status Flag ............................................ 183, 185, 188
WWW Address ................................................................ 389
WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 298
XORWF ........................................................................... 299
U
USART ............................................................................. 195
Asynchronous Mode ................................................ 202
Associated Registers, Receive ........................ 205
Associated Registers, Transmit ....................... 203
Receiver ........................................................... 204
Transmitter ....................................................... 202
Baud Rate Generator (BRG) .................................... 198
Associated Registers ....................................... 198
Baud Rate Formula .......................................... 198
Baud Rates, Asynchronous Mode
(BRGH = 0, Low Speed) .......................... 199
Baud Rates, Asynchronous Mode
(BRGH = 1, High Speed) ......................... 200
Baud Rates, Synchronous Mode
(SYNC = 1) .............................................. 201
High Baud Rate Select (BRGH Bit) .................. 198
Operation in Power-Managed Mode ................ 198
Sampling .......................................................... 198
© 2007 Microchip Technology Inc.
DS39599G-page 387
PIC18F2220/2320/4220/4320
NOTES:
DS39599G-page 388
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
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© 2007 Microchip Technology Inc.
DS39599G-page 389
PIC18F2220/2320/4220/4320
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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Device: PIC18F2220/2320/4220/4320
Literature Number: DS39599G
Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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7. How would you improve this document?
DS39599G-page 390
© 2007 Microchip Technology Inc.
PIC18F2220/2320/4220/4320
PIC18F2220/2320/4220/4320 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
−
PART NO.
Device
Device
X
Temperature
Range
/XX
XXX
Package
Pattern
PIC18F2220/2320/4220/4320(1),
PIC18F2220/2320/4220/4320T(1,2);
VDD range 4.2V to 5.5V
Examples:
a)
b)
c)
PIC18LF4320-I/P 301 = Industrial temp.,
PDIP package, Extended VDD limits,
QTP pattern #301.
PIC18LF2220-I/SO = Industrial temp.,
SOIC package, Extended VDD limits.
PIC18F4220-I/P = Industrial temp., PDIP
package, normal VDD limits.
PIC18LF2220/2320/4220/4320(1),
PIC18LF2220/2320/4220/4320T(1,2);
VDD range 2.0V to 5.5V
Temperature
Range
I
=
-40°C to +85°C (Industrial)
Package
PT
SO
SP
P
ML
=
=
=
=
=
TQFP (Thin Quad Flatpack)
SOIC
Skinny Plastic DIP
PDIP
QFN
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2007 Microchip Technology Inc.
Note
1:
F = Standard Voltage Range
LF = Wide Voltage Range
2:
T
= in tape and reel – SOIC
and TQFP packages only.
DS39599G-page 391
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Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
10/05/07
DS39599G-page 392
© 2007 Microchip Technology Inc.