MMA6222AKEG Rev 0, 12/2009 Freescale Semiconductor Technical Data Analog Dual Axis Micromachined Accelerometer MMA6222AKEG MMA6255AKEG MMA621010AKEG The MMA62XXAKEG series of dual axis (X and Y) silicon capacitive, micromachined accelerometers features a full digital signal processing for filtering, trim and data formatting. It has been optimized for analog output and offers an over-damped transducer. 2-AXIS ACCELEROMETER Features • Available in ±20/20g, ±50/50g, or ±100/100g versions. Additional g-ranges between 20 and 100g may be available upon request • Full-scale range is independently specified for each axis • 400 Hz, 4 Pole, 16 µs sample time, additional filter options are available • Ratiometric analog voltage output • Capture/hold input for system-wide synchronization support • 3.3 or 5 V single supply operation • On-chip temperature sensor and voltage regulator • Internal self-test • Minimal external component requirements • Pb-free 20-pin SOIC package • KEG SUFFIX (Pb-free) 20-LEAD SOIC CASE 475A-02 PIN CONNECTIONS Qualified AEC-Q100, Rev. F Grade 2 (-40°C/ +105°C) Typical Applications • Crash Detection (Airbag) • Impact and vibration monitoring • N/C 1 20 N/C N/C 2 19 N/C XOUT 3 18 CREGA VSSA 4 17 CREGA YOUT 5 16 CREF CAP/HOLD 6 15 CREF Shock detection ST 7 14 VCC VPP 8 13 VSS CREG 9 12 STATUS 10 11 SCLK RESET 20-PIN SOIC PACKAGE N/C: NO INTERNAL CONNECTION ORDERING INFORMATION X-Axis g-Level Y-Axis g-Level Temperature Range Package Packaging MMA6222AEG Device Name 20 20 -40 to +105°C 475A-02 Tubes MMA6222AEGR2 20 20 -40 to +105°C 475A-02 Tape & Reel MMA6222AKEG* 20 20 -40 to +105°C 475A-02 Tubes MMA6222AKEGR2* 20 20 -40 to +105°C 475A-02 Tape & Reel MMA6255AEG 50 50 -40 to +105°C 475A-02 Tubes MMA6255AEGR2 50 50 -40 to +105°C 475A-02 Tape & Reel MMA6255AKEG* 50 50 -40 to +105°C 475A-02 Tubes MMA6255AKEGR2* 50 50 -40 to +105°C 475A-02 Tape & Reel MMA621010AEG 100 100 -40 to +105°C 475A-02 Tubes MMA621010AEGR2 100 100 -40 to +105°C 475A-02 Tape & Reel MMA621010AKEG* 100 100 -40 to +105°C 475A-02 Tubes MMA621010AKEGR2* 100 100 -40 to +105°C 475A-02 Tape & Reel *Part number sourced from a different facility. © Freescale Semiconductor, Inc., 2009. All rights reserved. VCC VCC CREG CREGA CREF 100 nF 1 μF 1 μF 100 nF CS_A CS_D SCLK1 SCLK2 SCLK ST I/O MOSI2 DI STATUS I/O MISO2 DO CS SCLK MMA62XXAKEG VSSA XOUT VSS YOUT CS Main MCU Deployment IC ADC VPP/TEST Safing Sensor(s) Filter / Comparator DEPLOY_EN1 DEPLOY_EN2 Note: If one axis of the MMA62XXAKEG sensor is expected to be used as a confirmation of the other axis, Freescale recommends that MMA62XXAKEG used in conjunction with an additional sensing/safing device for each axis. Figure 1-1 Simplified Airbag Application Diagram 1.1 INTRODUCTION The MMA62XXKEG is trimmed to provide the most accurate voltage representation of acceleration at XOUT and YOUT. This is done by adjusting the signal within the DSP to compensate for errors within the digital-to-analog converters. The SPI is disabled when the device is in normal operating mode, and dedicated ST (self-test activation) and STATUS pin functions are assigned. MMA6222AEG 2 Sensors Freescale Semiconductor 1.2 BLOCK DIAGRAM A block diagram illustrating the major components of the design is shown in Figure 1-2. VPP UNIT PROGRAMMABLE DATA ARRAY VCC CREG CREGA VOLTAGE REGULATOR CREGA REFERENCE OSCILLATOR CLOCK MONITOR PRIMARY OSCILLATOR INTERNAL CLOCK CREF CREF ST STATUS VSS SCLK CONTROL LOGIC VSSA RESET CAP/HOLD g-CELL (Y) SD CONVERTER CONTROL IN SINC FILTER STATUS OUT DIGITAL OUT Y IN TEMP. SENSOR SELF-TEST INTERFACE TEMP DSP (SEE FIGURE 1-2) Y OUT DAC YOUT X OUT DAC XOUT X IN g-CELL (X) SD CONVERTER SINC FILTER Figure 1-2 MMA62XXAKEG Block Diagram CONTROL IN DSP CONTROL OUT OFFSET MONITOR Y IN LOW-PASS FILTER X IN OFFSET, GAIN, LINEARITY ADJUST OUTPUT SCALING TO Y DAC TO X DAC TEMP Figure 1-3 MMA62XXAKEG DSP Block Diagram NOTE: Models of signal chain are available upon request MMA6222AKEG Sensors Freescale Semiconductor 3 1.3 PIN FUNCTIONS The pinout for the MMA62XXAKEG device is illustrated in Figure 1-4. Pin functions are described below. When self-test is active, the output becomes more positive in both axes if ST1 is cleared, or more negative in both axes if ST1 is set. N/C 1 20 N/C N/C 2 19 N/C XOUT 3 18 CREGA VSSA 4 17 CREGA YOUT 5 16 CREF CAP/HOLD 6 15 CREF ST 7 14 VCC VPP 8 13 VSS CREG 9 12 STATUS 10 11 SCLK RESET 20-PIN SOIC PACKAGE N/C: NO INTERNAL CONNECTION X: +1g Y: 0g X: 0g Y: +1g X: 0g Y: -1g TO CENTER OF GRAVITATION FIELD X: -1g Y: 0g Response to static orientation within 1g field. Figure 1-4 MMA62XXAKEG Pinout MMA6222AEG 4 Sensors Freescale Semiconductor 1.4 1.4.1 PIN FUNCTION DESCRIPTIONS VCC This pin supplies power to the device. Careful printed wiring board layout and capacitor placement is critical to ensure best performance. An external bypass capacitor between this pin and VSS is required, as described in Section 1.5. 1.4.2 VSS This pin is the power supply return node for the digital circuitry on the MMA62XXKEG device. 1.4.3 VSSA This pin is the power supply return node for analog circuitry on the MMA62XXAKEG device. An external bypass capacitor between this pin and VCC is required, as described in Section 1.5. 1.4.4 CREG This pin is connected to the internal digital circuitry power supply rail. An external filter capacitor must be connected between this pin and VSS, as described in Section 1.5. 1.4.5 CREGA These pins are connected in parallel to the internal analog circuitry power supply rail. One or two external filter capacitors must be connected between these pins and VSSA, as described in Section 1.5. Two pins are provided to support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as described in Section 1.5. 1.4.6 CREF These pins are connected in parallel to an internal reference voltage node utilized by the analog circuitry. One or two external filter capacitors must be connected between these pins and VSSA, as described shown in Section 1.5. Two pins are provided to support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as described in Section 1.5. 1.4.7 VPP This pin should be tied directly to VSS. 1.4.8 SCLK This input may be left unconnected unless it is desired to initiate device reset as described in Section 1.4.9. 1.4.9 RESET This pin may be used to initiate a hardware reset. If RESET is held low and SCLK is held high for 512 μs, the internal reset signal is asserted. An internal pull-up device is connected to this pin. 1.4.10 STATUS This pin provides an indicator of internal status. The STATUS output will be driven to a logic high level should any of the following fault conditions be detected: • Internal parity fault • Over-temperature condition • Internal clock frequency fault • Device reset • Device initialization Immediately following device reset, STATUS is placed in a high impedance state for approximately 800 μs. At the end of this time, STATUS is driven high and a 3ms stabilization delay required by the internal circuitry begins. The STATUS condition may not be cleared during the stabilization delay. Reset is reported by the device so the system can be aware of potential difficulties if unexpected resets occur. Once asserted, the STATUS output will remain high until the ST pin is driven from a logic low to a logic high state. If a fault condition persists, the STATUS output will be driven high again as soon as it is cleared. MMA6222AKEG Sensors Freescale Semiconductor 5 1.4.11 ST This pin performs a dual function. When driven to a logic high level, the internal self-test voltage generator is activated. A low-tohigh transition on this pin will clear the internal STATUS latch. Note that under certain fault conditions, the STATUS latch will be immediately reset, indicating a terminal fault condition. A diagram illustrating operation of the STATUS latch following device initialization is illustrated in Figure 1-5. SELF TEST ENABLE ST VDD D STATUS Q R FAULT DETECT Figure 1-5 ST and STATUS Interaction 1.4.12 CAP/HOLD When this input pin is low, acceleration data is updated by the DSP whenever a data sample becomes available. Upon a low-tohigh transition of CAP/HOLD acceleration data is frozen. Acceleration data is not updated as long as the pin remains at a logic ‘1’ level. This pin may be tied directly to VSS if the hold function is not desired. 1.4.13 XOUT, YOUT Two digital-to-analog converters (DACs) are provided. These converters translate output of the DSP block into voltage levels proportional to the magnitude of the numerical result and ratiometric to VCC. 1.5 EXTERNAL COMPONENTS The connections illustrated in Figure 1-1 are recommended. Careful printed wiring board layout and component placement is essential for best performance. Low ESR capacitors must be connected to CREG and CREGA pins for the best performance. A grounded land area with solder mask should be placed under the package for improved shielding of the device from external effects. If a land area is not provided, no signals should be routed beneath the package. See Figure 1-1. MMA6222AEG 6 Sensors Freescale Semiconductor SECTION 2 PERFORMANCE SPECIFICATION 2.1 MAXIMUM RATINGS Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep input and output voltages within the range VSS ≤ V ≤ VCC. Ref Rating Symbol Value Unit 1 Supply Voltage VCC -0.3 to +7 V (1) 2 CREG, CREGA, CREF VREG -0.3 to +3 V (1) 3 VPP VREG -0.3 to +11 V (1) 4 SCLK, ST, CAP/HOLD VIN -0.3 to VCC + 0.3 V (1) 5 STATUS (high impedance state) VIN -0.3 to VCC + 0.3 V (1) VDAC -0.3 to VCC + 0.3 V (1) I 10 mA (1) 8 Acceleration (without hitting internal g-cell stops) gmax ±800 g (1) 9 Powered Shock (six sides, 0.5 ms duration) gpms ±1500 g (1) 10 Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g (1) 11 Drop Shock (to concrete surface) hDROP 1.2 m (1) VESD VESD VESD ±2000 ±500 ±200 V V V (1) (1) (1) Tstg -40 to +125 °C (1) 6 XOUT, YOUT (DACEN = 0) 7 Current Drain per Pin Excluding VCC and VSS 12 13 14 Electrostatic Discharge Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM) 15 Storage Temperature Range Notes: 1. Verified by characterization, not tested in production. 2.2 OPERATING RANGE The operating ratings are the limits normally expected in the application and define the range of operation. Ref Characteristic Supply Voltage Standard Operating Voltage, 3.3V operating range 16 Standard Operating Voltage, 5V operating range 17 Symbol Min Typ Max Units VCC VCC VL +3.15 +4.75 +3.3 +5.0 VH +3.45 +5.25 V V (1) (1) TA TL -40 ⎯ TH +105 C (2) Operating Temperature Range 18 Notes: 1. Characterized at all values of VL and VH. Production test is conducted at typical voltage unless otherwise noted. 2. Parameters tested 100% at final test. MMA6222AKEG Sensors Freescale Semiconductor 7 2.3 ELECTRICAL CHARACTERISTICS VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Ref Characteristic Symbol Min Typ Max Units ⎯ 9.0 mA (1) 19 Supply Current Drain Analog-only output configuration 20 21 22 23 Power-On Recovery Threshold (See Figure 2-1) VCC CREG CREGA CREF VPOR_N VPOR_N VPOR_N VPOR_N 2.77 1.80 2.18 1.11 ⎯ ⎯ ⎯ ⎯ 3.15 2.32 2.50 1.29 V V V V (2) (2) (2) (2) 24 25 26 27 Power-On Reset Threshold (See Figure 2-1) VCC CREG CREGA CREF VPOR_A VPOR_A VPOR_A VPOR_A 2.77 1.80 2.18 1.11 ⎯ ⎯ ⎯ 2.95 2.10 2.31 1.19 V V V V (2) (2) (2) (2) 28 29 30 31 Hysteresis (VPOR_N - VPOR_A, See Figure 2-1) VCC CREG CREGA CREF VHYST VHYST VHYST VHYST 0 0 0 0 388 300 261 150 mV mV mV mV VDACU ⎯ ⎯ 2.0 V (2) VDD V2.5 VREF 2.42 2.42 1.20 2.50 2.50 1.25 2.58 2.58 1.29 V V V (1) (1) (1) CREG ESR 800 ⎯ 1000 ⎯ ⎯ 200 nF mΩ (2) (2) IDD 32 Minimum Functional Voltage (See Figure 2-1) ⎯ ⎯ ⎯ ⎯ 33 34 35 Internally Regulated Voltages CREG CREGA (3) CREF 36 37 External Filter Capacitor (CREG, CREGA) Value ESR (including interconnect resistance) 38 Power Supply Coupling (4) Analog output 39 40 41 42 Analog Sensitivity (XOUT, YOUT) 20g Range 35g Range 50g Range 100g Range * * * * ASENS ASENS ASENS ASENS ⎯ ⎯ ⎯ ⎯ 23.40 13.40 9.37 4.68 ⎯ ⎯ ⎯ ⎯ mV/V/g mV/V/g mV/V/g mV/V/g (1)(5) (1)(5) (1)(5) (1)(5) 43 44 Sensitivity Error TA = 25°C 40°C ≤ TA ≤ 105°C * * ΔSENS ΔSENS -8 -8 ⎯ ⎯ +8 +8 % % (1)(5) (1)(5) 45 Offset at 0g Analog output (XOUT, YOUT) * AOUT 0.46 × VCC 0.5 × VCC 0.54 × VCC V (1)(5) Notes: 1. 2. 3. 4. 5. (#) (*) * * See Figure 2-2 (2) Parameters tested 100% at final test. Verified by characterization, not tested in production. Tested at VCC = VL and VCC = VH. Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Indicates a FSL significant parameter (CPK > 1.33). Indicates a FSL critical parameter (CPK > 1.67). MMA6222AEG 8 Sensors Freescale Semiconductor 2.3 ELECTRICAL CHARACTERISTICS (CONTINUED) VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Ref Characteristic Symbol Min Typ Max Units gOVER gOVER gOVER gOVER +20.0 +35.0 +50.0 +100.1 +20.9 +36.6 +52.1 +104.3 +22.1 +38.7 +55.3 +110.5 g g g g (3) (3) (3) (3) gUNDER gUNDER gUNDER gUNDER -20.1 -35.1 -50.1 -100.3 -20.9 -36.6 -52.2 -104.5 -22.2 -38.8 -55.4 -110.7 g g g g (3) (3) (3) (3) gSAT -200 — +200 g (3) NLOUT -1 — 1 % FSR (3) 56 Noise (1Hz-1kHz) nSD — — 1.1 mg/√Hz (3) Positive Self Test Output Change (XOUT, YOUT, analog) TA = 25°C 57 58 -40°C ≤ TA ≤ 105°C ΔST ΔST 10 10 — — 18 18 % FS % FS (1) (1) VZX VYX VZY VXY -4 -4 -4 -4 — — — — +4 +4 +4 +4 % % % % (3) (3) (3) (3) AVLOW AVHIGH OFST GERR DNL — VCC - 0.25 -0.2 -0.3 -2 — — — — 0.25 — +0.2 +0.3 +2 V V %FSR %FSR digit (2) (2) (2) (2) (2) INL INL -3 -3.5 — — +3 +3.5 digit digit (2) (3) Output High Voltage STATUS (ILoad = -100 μA) 70 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 71 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VOH VOH 3.25 3.75 — — — — V V (2) (2) Output Low Voltage STATUS (ILoad = 100 μA) 72 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 73 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VOL VOL — — — — 0.4 0.4 V V (2) (2) Output Loading (STATUS) Load Resistance Load Capacitance ZOUT COUT 47 — — — — 35 kΩ pF (3) (3) Output value on overrange 46 47 48 49 20g Range 35g Range 50g Range 100g Range Output value on Underrange 50 51 52 53 20g Range 35g Range 50g Range 100g Range Maximum acceleration without saturation of internal circuitry All ranges 54 55 Nonlinearity 59 60 61 62 Cross-Axis Sensitivity VZX VYX VZY VXY DAC Characteristics (XOUT, YOUT) Minimum Output Level, IOUT = -200 μA Maximum Output Level, IOUT = 200 μA Offset Error Gain Error Differential Nonlinearity Integral Nonlinearity TA = 25°C 68 69 -40°C ≤ TA ≤ 105°C 63 64 65 66 67 74 75 Notes: 1. Parameters tested 100% at final test. 2. Parameters tested 100% at unit probe. 3. Verified by characterization, not tested in production. MMA6222AKEG Sensors Freescale Semiconductor 9 2.3 ELECTRICAL CHARACTERISTICS (CONTINUED) VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Ref Symbol Min Typ Max Units ZOUT COUT 25 — — — — 60 kΩ pF (3) (3) Input High Voltage RESET, SCLK, ST, CAP/HOLD 78 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 79 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VIH VIH 1.5 2.5 — — — — V V (2) (2) Input Low Voltage RESET, SCLK, ST, CAP/HOLD 80 3.15 V ≤ (VCC - VSS) ≤ 3.45 V 81 4.75 V ≤ (VCC - VSS) ≤ 5.25 V VIL VIL — — — — 0.85 1.0 V V (2) (2) IIH RIN -30 190 -50 270 -260 350 μA kΩ (2) (2) IIL 30 50 260 μA (2) 76 77 82 83 84 85 Characteristic Output Loading (XOUT, YOUT) Load Resistance Load Capacitance Input Current High (at VIH) SCLK, ST, CAP/HOLD VPP/TEST (internal pulldown resistor) Low (at VIL) RESET Notes: 2. Parameters tested 100% at unit probe. 3. Verified by characterization, not tested in production. MMA6222AEG 10 Sensors Freescale Semiconductor 2.4 CONTROL TIMING VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified Ref Characteristic Symbol Min Typ Max Units fC(LPF) 380 400 420 Hz fC(LPF) 335 353 371 Hz OLPF — 4 — 1 (7) tXY —— — 10 ms (1) 90 Internal Oscillator Frequency fOSC 3.8 4.0 4.2 MHz (1) 91 Clock Monitor Threshold fMON 3.6 — 4.4 MHz (7) tCSRES 486 512 538 μs (7) nPOLES fC — 5 1 10 — 20 unit kHz (1) (7) BWGCELL — 3 — kHz (1) DSP Low-Pass Filter (Note 9) Cutoff frequency (Note 10) 86 Filter Option $0C, $1F DSP Low-Pass Filter Cutoff frequency (-3dB, referenced to 0 Hz) 87 Filter $0C, $1F Filter Order Filter $00 - $12 88 Power-On Recovery Time 89 Power applied to XOUT, YOUT valid 92 Chip Select to Internal Reset (See Figure 2-3) 93 94 DAC Low-Pass Filter Number of Poles Cutoff Frequency 95 Sensing Element Rolloff Frequency (-3 dB) Notes: 1. 2. 3. 4. 7. 9. 10. (7) (7) Parameters tested 100% at final test. Parameters tested 100% at unit probe. Verified by characterization, not tested in production. (*) Indicates a FSL critical parameter (CPK > 1.67). (#) Indicates a FSL significant parameter (CPK > 1.33). Functionality verified 100% via scan. Timing characteristic is directly determined by internal oscillator frequency. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Low-pass filter characteristics match those of other Freescale accelerometer devices. Cutoff frequencies shown are -4dB referenced to 0 Hz response, to correspond with previous specifications. MMA6222AKEG Sensors Freescale Semiconductor 11 5.5V VPOR_N VPOR_A VDACU VCC POR tXY XOUT/YOUT DAC OUTPUT UNCERTAIN Figure 2-1 Power-Up Timing Figure 2-2 Power Supply Coupling - DAC Outputs MMA6222AEG 12 Sensors Freescale Semiconductor CS tCSRES INTERNAL RESET SCLK Figure 2-3 CS Reset Timing MMA6222AKEG Sensors Freescale Semiconductor 13 PACKAGE DIMENSIONS MMA6222AEG 14 Sensors Freescale Semiconductor PACKAGE DIMENSIONS MMA6222AKEG Sensors Freescale Semiconductor 15 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http:/www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. MMA6222AKEG Rev. 0 12/2009