Document Number: MMA655X Rev. 3, 03/2012 Freescale Semiconductor Data Sheet: Technical Information Single-Axis SPI Inertial Sensor MMA655x, a SafeAssure solution, is a SPI-based, single-axis, medium-g, overdamped lateral accelerometer designed for use in Automotive Airbag systems. Features • ±105g or ±120g full-scale range • 3.3V or 5V single supply operation • SPI-compatible serial interface • 12-bit digital signed or unsigned SPI data output • Programmable arming function • Twelve low-pass filter options, ranging from 50 Hz to 1000 Hz • Optional offset cancellation with > 6s averaging period and < 0.25 LSB/s slew rate • Pb-Free 16-Pin QFN, 6 by 6 Package Referenced Documents • AECQ100, Revision G, dated May 14, 2007 (http://www.aecouncil.com/) ORDERING INFORMATION Device Axis Range Shipping MMA6555KW X 105g Tubes MMA6556KW X 120g Tubes MMA6555KWR2 X 105g Tape & Reel MMA6556KWR2 X 120g Tape & Reel For user register array programming, please consult your Freescale representative. © 2011, 2012 Freescale Semiconductor, Inc. All rights reserved. MMA655x Bottom View 16 LEAD QFN 6 mm by 6 mm CASE 2086-01 VCC VCC CS VREG SCLK VREGA MOSI MISO C1 C3 C2 MMA655x VSSA VSS ARM VPP/TEST Figure 1. Application Diagram Table 1. External Component Recommendations Ref Des Type Description Purpose C1 Ceramic 0.1 μF, 10%, 10V Minimum, X7R VCC Power Supply Decoupling C2 Ceramic 1 μF, 10%, 10V Minimum, X7R Voltage Regulator Output Capacitor (CVREG) C3 Ceramic 1 μF, 10%, 10V Minimum, X7R Voltage Regulator Output Capacitor (CVREGA) MMA655x 2 Sensor Freescale Semiconductor, Inc. VCC VREG VREGA Odd Register SPI Odd Register Array VREG VREGA VCC CS SPI Self Test Analog Regulator Digital 8 MHz 1 MHz Clock Oscillator Monitor Regulator VREGA OTP Array Memory SPI Mismatch Verification SCLK I/O MOSI MISO VREG Clock & bias Generator Over-Damped X-Axis g-Cell Voltage Monitoring VSS ΣΔ Converter Even Register Array Even Register SPI Clock CRC Generation Offset Monitor IIR SINC Filter Offset Low-Pass Filter Compensation Linear Interpolation Cancellation Output Scaling ARM ARM xxxxxxx xxxxxxx X: 0 g X: +1 g xxxxxxx xxxxxxx xxxxxxx xxxxxxx Figure 2. Internal Block Diagram X: 0 g xxxxxxx xxxxxxx X: -1 g X: 0 g X: 0 g EARTH GROUND Figure 3. Device Orientation Diagram MMA655x(K)W AWLYWWZ Data Code Legend: A: Assembly Location WL: Wafer Lot Number (g-cell Lot Number) Y: Year WW: Work Week Z: Assembly Lot Number Figure 4. Part Marking MMA655x Sensor Freescale Semiconductor, Inc. 3 VSSA N/C N/C Pin Connections VSSA 1 16 15 14 13 VREGA 1 12 CS 17 VSS 2 11 MOSI VREG 3 10 SCLK 9 VCC 5 6 7 8 N/C ARM/PCM TEST/VPP MISO VSS 4 Figure 5. Top View, 16 Pin QFN Package Table 2. Pin Descriptions Pin Pin Name Formal Name 1 VREGA Analog Supply 2 VSS Digital GND 3 VREG Digital Supply 4 VSS Digital GND This pin is the power supply return node for the digital circuitry. 5 N/C No Connect No Connection Definition This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between this pin and VSSA. Reference Figure 1. This pin is the power supply return node for the digital circuitry. This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 1. 6 ARM/ PCM Arm Output / PCM Output The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.6. When the arming output is selected, ARM can be configured as an open drain, active low output with a pullup current; or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a digital output with a PCM signal proportional to the acceleration data. Reference Section 3.1.10 and Section 3.1.11. If unused, this pin must be left unconnected. 7 TEST / VPP Programming Voltage This pin provides the power for factory programming of the OTP registers. This pin must be connected to VSS in the application. 8 MISO SPI Data Out This pin functions as the serial data output for the SPI port. 9 VCC Supply This pin supplies power to the device. An external capacitor must be connected between this pin and VSS. Reference Figure 1. 10 SCLK SPI Clock This input pin provides the serial clock to the SPI port. An internal pulldown device is connected to this pin. 11 MOSI SPI Data In This pin functions as the serial data input to the SPI port. An internal pulldown device is connected to this pin. 12 CS Chip Select This input pin provides the chip select for the SPI port. An internal pullup device is connected to this pin. 13 VSSA Analog GND This pin is the power supply return node for analog circuitry. 14 NC No Connect Not internally connected. This pin can be unconnected or connected to VSS in the application. 15 NC No Connect Not internally connected. This pin can be unconnected or connected to VSS in the application. 16 VSSA Analog GND This pin is the power supply return node for analog circuitry 17 PAD Die Attach Pad Corner Pads This pin is the die attach flag, and is internally connected to VSS. Reference Section 5 for die attach pad connection details. The corner pads are internally connected to VSS. MMA655x 4 Sensor Freescale Semiconductor, Inc. 2 Electrical Characteristics 2.1 Maximum Ratings Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. # Rating Symbol Value Unit 1 Supply Voltage VCC -0.3 to +7.0 V (3) 2 VREG, VREGA VREG -0.3 to +3.0 V (3) 3 SCLK, CS, MOSI,VPP/TEST VIN -0.3 to VCC + 0.3 V (3) 4 ARM VIN -0.3 to VCC + 0.3 V (3) 5 MISO (high impedance state) VIN -0.3 to VCC + 0.3 V (3) 6 Powered Shock (six sides, 0.5 ms duration) gpms ±1500 g (5,18) 7 Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g (5,18) 8 Drop Shock (to concrete surface) hDROP 1.2 m (5) 9 10 11 Electrostatic Discharge Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM) VESD VESD VESD ±2000 ±750 ±200 V V V (5) (5) (5) 12 Storage Temperature Range Tstg -40 to +125 °C (5) 13 Thermal Resistance - Junction to Case qJC 2.5 °C/W (14) 2.2 Operating Range The operating ratings are the limits normally expected in the application and define the range of operation. # Characteristic 14 15 Supply Voltage Standard Operating Voltage, 3.3V Standard Operating Voltage, 5.0V 16 Operating Ambient Temperature Range Verified by 100% Final Test 17 Power-on Ramp Rate (VCC) Symbol Min Typ Max VCC VL +3.135 VTYP +3.3 +5.0 VH +5.25 TA TL -40 — VCC_r 0.000033 — Units V V (15) (15) TH +105 C (1) 3300 V/μs (19) MMA655x Sensor Freescale Semiconductor, Inc. 5 2.3 Electrical Characteristics - Power Supply and I/O VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified # Characteristic 18 Supply Current Power Supply Monitor Thresholds (See Figure 9) VCC Undervoltage (Falling) VREG Undervoltage (Falling) VREG Overvoltage (Rising) VREGA Undervoltage (Falling) VREGA Overvoltage (Rising) Power Supply Monitor Hysteresis VCC Undervoltage 24 VREG Undervoltage, VREG Overvoltage 25 VREGA Undervoltage, VREGA Overvoltage 26 19 20 21 22 23 Power Supply RESET Thresholds (See Figure 6, and Figure 9) VREG Undervoltage RESET (Falling) 27 VREG Undervoltage RESET (Rising) 28 VREG RESET Hysteresis 29 30 31 Internally Regulated Voltages VREG VREGA 32 33 External Filter Capacitor (CVREG, CVREGA) Value ESR (including interconnect resistance) 34 35 Power Supply Coupling 50 kHz ≤ fn ≤ 300 kHz 4 MHz ≤ fn ≤ 100 MHz Symbol Min Typ Max Units * IDD 3.0 — 7.0 mA (1) * * * * * VCC_UV_f VREG_UV_f VREG_OV_r VREGA_UV_f VREGA_OV_r 2.74 2.10 2.65 2.20 2.65 — — — — — 3.02 2.25 2.85 2.35 2.85 V V V V V (3,6) (3,6) (3,6) (3,6) (3,6) VHYST VHYST VHYST 65 20 20 100 100 100 110 210 150 mV mV mV (3) (3) (3) * * VREG_UVR_f VREG_UVR_r VHYST 1.764 1.876 80 — — — 2.024 2.152 140 V V mV (3,6) (3,6) (3) * * VREG VREGA 2.42 2.42 2.50 2.50 2.58 2.58 V V (1,3) (1,3) CVREG, CVREGA ESR 700 — 1000 — 1500 400 nF mΩ (19) (19) — — — — 0.004 0.004 LSB/mv (19) LSB/mv (19) Output High Voltage (MISO, PCM) 36 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (ILoad = -1 mA) 37 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (ILoad = -1 mA) * * VOH_3 VOH_5 VCC - 0.2 VCC - 0.4 — — — — V V (2,3) (2,3) Output Low Voltage (MISO, PCM) 38 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (ILoad = 1 mA) 39 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (ILoad = 1 mA) * * VOL_3 VOL_5 — — — — 0.2 0.4 V V (2,3) (2,3) Open Drain Output High Voltage (ARM) 40 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (IARM = -1 mA) 41 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (IARM = -1 mA) * * VODH_3 VODH_5 VCC - 0.2 VCC - 0.4 — — — — V V (2,3) (2,3) Open Drain Output Pulldown Current (ARM) 42 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (VARM = 1.5V) 43 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (VARM = 1.5V) * * IODPD_3 IODPD_5 50 50 — — 100 100 μA μA (2,3) (2,3) Open Drain Output Low Voltage (ARM) 44 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (IARM = 1 mA) 45 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (IARM = 1 mA) * * VODH_3 VODH_5 — — — — 0.2 0.4 V V (2,3) (2,3) Open Drain Output Pullup Current (ARM) 46 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (VARM = 1.5V) 47 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (VARM = 1.5V) * * IODPU_3 IODPU_5 -100 -100 — — -50 -50 μA μA (2,3) (2,3) 48 Input High Voltage CS, SCLK, MOSI * VIH 2.0 — — V (3,6) 49 Input Low Voltage CS, SCLK, MOSI * VIL — — 1.0 V (3,6) 50 Input Voltage Hysteresis CS, SCLK, MOSI * VI_HYST 0.125 — 0.500 V (19) * * IIH IIL -70 30 -50 50 -30 70 μA μA (2,3) (2,3) 51 52 Input Current High (at VIH)(SCLK, MOSI) Low (at VIL)(CS) MMA655x 6 Sensor Freescale Semiconductor, Inc. 2.4 Electrical Characteristics - Sensor and Signal Chain VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified. # Characteristic 53 54 Digital Sensitivity (SPI) 105.5g (12-Bit Output) 120 g (12-Bit Output) 55 56 57 Sensitivity Error TA = 25 C -40 C ≤ TA ≤ 105 C -40 C ≤ TA ≤ 105 C,VCC_UV_f ≤ VCC - VSS ≤ VL 58a 59a 60a 61a Offset at 0 g (No Offset Cancellation) 12 bits, unsigned 12 bits, signed 12 bits, unsigned, VCC_UV_f ≤ VCC - VSS ≤ VL 12 bits, signed, VCC_UV_f ≤ VCC - VSS ≤ VL 62b 63b 64b 65b Offset at 0g (With Offset Cancellation) 12 bits, unsigned 12 bits, signed 12 bits, unsigned, VCC_UV_f ≤ VCC - VSS ≤ VL 12 bits, signed, VCC_UV_f ≤ VCC - VSS ≤ VL Symbol Min Typ Max Units * * SENS SENS — — 18.2 16.0 — — LSB/g LSB/g (1,9) (1,9) * * ΔSENS ΔSENS ΔSENS -4 -5 -5 — — — +4 +5 +5 % % % (1) (1) (3) * * OFFSET OFFSET OFFSET OFFSET 1988 -60 1988 -60 2048 0 — — 2108 +60 1988 -60 LSB LSB LSB LSB (1) (1) (3) (3) * * OFFSET OFFSET OFFSET OFFSET 2047.75 -0.25 2047.75 -0.25 2048 0 — — 2048.25 +0.25 2048.25 +0.25 LSB LSB LSB LSB (9,7) (9,7) (9) (9) OFFTHRPOS OFFTHRNEG — — 100 -100 — — LSB LSB (7) (7) 66 67 Offset Monitor Thresholds Positive Threshold (12 bits signed) Negative Threshold (12 bits signed) 68 69 70 71 Range of Output (SPI, 12 bits, unsigned) Normal Fault Response Code Unused Codes Unused Codes RANGE FAULT UNUSED UNUSED 128 — 1 3969 — 0 — — 3968 — 127 4095 LSB LSB LSB LSB (7) (7) (7) (7) 72 73 74 Range of Output (SPI, 12 bits, signed) Normal Unused Codes Unused Codes RANGE UNUSED UNUSED -1920 -2047 1921 — — — 1920 -1921 2047 LSB LSB LSB (7) (7) (7) NLOUT -1 — 1 % FSR (3) nRMS nP-P — — — — 1 3 LSB LSB (3) (3) * * VZX VYX -4 -4 — — +4 +4 % % (3) (3) * * ΔST105_25 ΔST105_ΔT ΔST105_ΔTΔV ΔST120_25 ΔST120_ΔT ΔST120_ΔTΔV ΔSTMIN 442 414 414 387 363 363 ΔSTNOM 553 553 553 484 484 484 ΔSTMAX 663 690 690 581 605 605 LSB LSB LSB LSB LSB LSB (1) (1) (3) (1) (1) (3) 75 Nonlinearity 76 77 System Output Noise RMS (12 bits, All Ranges, 400 Hz, 3-pole LPF) Peak to Peak (12 bits, All Ranges, 400 Hz, 3-pole LPF) 78 79 Cross-Axis Sensitivity VZX VYX 80 81 82 83 84 85 Self Test Output Change (Ref Section 3.6) 105.5g, TA = 25 C 105.5g, -40 C ≤ TA ≤ 105 C 105.5g, -40 C ≤ TA ≤ 105 C, VCC_UV_f ≤ VCC - VSS ≤ VL 120g, TA = 25 C 120g, -40 C ≤ TA ≤ 105 C 120g, -40 C ≤ TA ≤ 105 C, VCC_UV_f ≤ VCC - VSS ≤ VL Self Test Output Accuracy Δ from Stored Value, including Sensitivity Error -40 C ≤ TA ≤ 105 C (Ref Section 3.6) 86 * * * * ΔSTACC -10 — +10 % (3) 87 Sigma Delta Modulator Range gADCl_Clip 375 400 450 g (19) 88 Acceleration (without hitting internal g-cell stops gg-cell_Clip 500 560 600 g (19) MMA655x Sensor Freescale Semiconductor, Inc. 7 2.5 Dynamic Electrical Characteristics - Signal Chain VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified. # Characteristic Symbol Min Typ Max Units tS tS tINTERP — — — 64/fOSC 128/fOSC tS/2 — — — s s s (7) (7) (7) 89 90 91 DSP Sample Rate (LPF 0,1,2,3,4,5) DSP Sample Rate (LPF 8,9,10,11,12,13) Interpolation Sample Rate 92 93 Data Path Latency (excluding g-cell and Low Pass Filter) TS = 64/fOSC TS = 128/fOSC * * tDataPath_8 tDataPath_16 33.0 51.9 34.8 54.6 36.5 57.4 μs μs (7,16) (7,16) 94 95 96 97 98 99 Low-Pass Filter (ts = 8μs) Cutoff frequency 0: 100 Hz, 4-pole Cutoff frequency 1: 300 Hz, 4-pole Cutoff frequency 2: 400 Hz, 4-pole Cutoff frequency 3: 800 Hz, 4-pole Cutoff frequency 4: 1000 Hz, 4-pole Cutoff frequency 5: 400 Hz, 3-pole * * * * * * fC0(LPF) fC1(LPF) fC2(LPF) fC3(LPF) fC4(LPF) fC5(LPF) 95 285 380 760 950 380 100 300 400 800 1000 400 105 315 420 840 1050 420 Hz Hz Hz Hz Hz Hz (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) 100 101 102 103 104 105 Low-Pass Filter (ts = 16μs) Cutoff frequency 8: 50 Hz, 4-pole Cutoff frequency 9: 150 Hz, 4-pole Cutoff frequency 10: 200 Hz, 4-pole Cutoff frequency 11: 400 Hz, 4-pole Cutoff frequency 12: 500 Hz, 4-pole Cutoff frequency 13: 200 Hz, 3-pole * * * * * * fC8(LPF) fC9(LPF) fC10(LPF) fC11(LPF) fC12(LPF) fC13(LPF) 47.5 142.5 190 380 475 190 50 150 200 400 500 200 52.5 157.5 210 420 525 210 Hz Hz Hz Hz Hz Hz (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) 106 107 108 109 110 111 112 Offset Cancellation (Normal Mode, 12-Bit Output) Offset Averaging Period Offset Slew Rate Offset Update Rate Offset Correction Value per Update Positive Offset Correction Value per Update Negative Offset Correction Threshold Positive Offset Correction Threshold Negative * * * * * * * OFFAVEPER OFFSLEW OFFRATE OFFCORRP OFFCORRN OFFTHP OFFTHN — — — — — — — 6.29146 0.2384 1049 0.25 -0.25 0.125 0.125 — — — — — — — s LSB/s ms LSB LSB LSB LSB (3,7) (3,7) (3,7) (3,7) (3,7) (3,7) (3,7) 113 114 115 116 117 118 Self Test Activation Time (CS rising edge to 90% of ST Final Value) Cutoff frequency 0: 100 Hz, 4-pole Cutoff frequency 1: 300 Hz, 4-pole Cutoff frequency 2: 400 Hz, 4-pole Cutoff frequency 3: 800 Hz, 4-pole Cutoff frequency 4: 1000 Hz, 4-pole Cutoff frequency 5: 400 Hz, 3-pole ST_ACT100 ST_ACT300 ST_ACT400 ST_ACT800 ST_ACT1000 ST_ACT400_3 — — — — — — — — — — — — 7.00 3.00 2.50 1.70 1.60 2.40 ms ms ms ms ms ms (19) (19) (19) (19) (19) (19) 119 Offset Monitor Bypass Time after Self Test Deactivation tST_OMB — 320 — tS (3,7) 120 Time Between Acceleration Data Requests (Same Axis) tACC_REQ 15 — — μs (3,7,20) 121 122 123 Arming Output Activation Time (ARM, IARM = 200μA) Moving Average and Count Arming Modes (2,3,4,5) Unfiltered Mode Activation Delay (Reference Figure 30) Unfiltered Mode Arm Assertion Time (Reference Figure 30) tARM tARM_UF_DLY tARM_UF_ASSERT 0 0 5.00 — — — 1.51 1.51 6.579 μs μs μs (3,12) (3,12) (3) 124 Sensing Element Natural Frequency fgcell 10791 13464 15879 Hz (19) 125 Sensing Element Cutoff Frequency (-3 dB ref. to 0 Hz) fgcell 0.851 1.58 2.29 kHz (19) 126 Sensing Element Damping Ratio ζgcell 2.46 4.31 9.36 — (19) 127 Sensing Element Delay (@100 Hz) fgcell_delay 70 101 187 μs (19) 128 Sensing Element Step Response (0% - 90%) tStep_gcell — — 200 μs (19) 129 Package Resonance Frequency fPackage 100 — — kHz (19) 130 Package Quality Factor qPackage 1 — 5 (19) MMA655x 8 Sensor Freescale Semiconductor, Inc. 2.6 Dynamic Electrical Characteristics - Supply and SPI VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified # Characteristic 131 132 133 Power-On Recovery Time (VCC = VCCMIN to first SPI access) Power-On Recovery Time (Internal POR to first SPI access) SPI Reset Activation Time (CS high to Reset) 134 135 Internal Oscillator Frequency Test Frequency - Divided from Internal Oscillator 136 Serial Interface Timing (See Figure 7, CMISO ≤ 80pF, RMISO ≥ 10kW) Clock (SCLK) period (10% of VCC to 10% of VCC) Symbol Min Typ Max Units tOP tOP tSPI_RESET — — — — — — 10 840 300 ms μs ns (3) (3,7) (7) * fOSC fOSCTST 7.6 0.95 8 1 8.4 1.05 MHz MHz (7) (1) * tSCLK 120 — — ns (3) 137 Clock (SCLK) high time (90% of VCC to 90% of VCC) * tSCLKH 40 — — ns (3) 138 Clock (SCLK) low time (10% of VCC to 10% of VCC) * tSCLKL 40 — — ns (3) 139 Clock (SCLK) rise time (10% of VCC to 90% of VCC) tSCLKR — 15 40 ns (19) 140 Clock (SCLK) fall time (90% of VCC to 10% of VCC) tSCLKF — 15 28 ns (19) 141 CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC) tLEAD 60 — — ns (3) 142 CS asserted to MISO valid (CS = 10% of VCC to MISO = 10/90% of VCC) tACCESS — — 60 ns (3) 143 Data setup time (MOSI = 10/90% of VCC to SCLK = 10% of VCC) * tSETUP 20 — — ns (3) 144 MOSI Data hold time (SCLK = 90% of VCC to MOSI = 10/90% of VCC) * tHOLD_IN 10 — — ns (3) 145 MISO Data hold time (SCLK = 90% of VCC to MISO = 10/90% of VCC) * tHOLD_OUT 0 — — ns (3) 146 SCLK low to data valid (SCLK = 10% of VCC to MISO = 10/90% of VCC) * tVALID — — 35 ns (3) 147 SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC) * tLAG 60 — — ns (3) 148 CS high to MISO disable (CS = 90% of VCC to MISO = Hi Z) * tDISABLE — — 60 ns (3) 149 CS high to CS low (CS = 90% of VCC to CS = 90% of VCC) * tCSN 526 — — ns (3) 150 SCLK low to CS low (SCLK = 10% of VCC to CS = 90% of VCC) * tCLKCS 50 — — ns (3) 151 CS high to SCLK high (CS = 90% of VCC to SCLK = 90% of VCC) tCSCLK 50 — — ns (19) 1. Parameters tested 100% at final test. 2. Parameters tested 100% at wafer probe. 3. Parameters verified by characterization 4. (*) Indicates a critical characteristic. 5. Verified by qualification testing. 6. Parameters verified by pass/fail testing in production. 7. Functionality verified 100% via scan. Timing characteristic is directly determined by internal oscillator frequency. 8. N/A 9. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Response is corrected to 0 Hz response. 10.Low-pass filter cutoff frequencies shown are -3 dB referenced to 0 Hz response. 11.Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible. 12.Time from falling edge of CS to ARM output valid 13.N/A 14.Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad. 15.Device characterized at all values of VL & VH. Production test is conducted at all typical voltages (VTYP) unless otherwise noted. 16.Data Path Latency is the signal latency from g-cell to SPI output disregarding filter group delays. 17.Filter characteristics are specified independently, and do not include g-cell frequency response. 18.Electrostatic Deflection Test completed during wafer probe. 19.Verified by Simulation. 20.Acceleration Data Request timing constraint only applies for proper operation of the Arming Function MMA655x Sensor Freescale Semiconductor, Inc. 9 VCC_UV_r VCC VCC_UV_f VREGA_UV_r VREGA_UV_f VREGA Note: VREGA & VREG rise and fall slopes will be dependent on output capacitance and load current VREG_UVR_r VREG_UVR_f VREG POR DEVRES Flag Cleared by User DEVRES Time Figure 6. Power-Up Timing CS tLEAD tSCLKR tSCLK tSCLKF tCSN tSCLKH tCSCLK SCLK tSCLKL tLAG tACCESS tVALID tHOLD_OUT tCLKCS tDISABLE MISO tHOLD_IN tSETUP MOSI Figure 7. Serial Interface Timing MMA655x 10 Sensor Freescale Semiconductor, Inc. 3 Functional Description 3.1 Customer Accessible Data Array A customer accessible data array allows for each device to be customized. The array consists of an OTP factory programmable block and read/write registers for device programmability and status. The OTP and writable register blocks incorporate independent CRC circuitry for fault detection (reference Section 3.2). The writable register block includes a locking mechanism to prevent unintended changes during normal operation. Portions of the array are reserved for factory-programmed trim values. The customer accessible data is shown in the table below. Table 3. Customer Accessible Data Location Bit Function Type Addr Register 7 6 5 4 3 2 1 0 $00 SN0 SN[7] SN[6] SN[5] SN[4] SN[3] SN[2] SN[1] SN[0] $01 SN1 SN[15] SN[14] SN[13] SN[12] SN[11] SN[10] SN[9] SN[8] $02 SN2 SN[23] SN[22] SN[21] SN[20] SN[19] SN[18] SN[17] SN[16] $03 SN3 SN[31] SN[30] SN[29] SN[28] SN[27] SN[26] SN[25] SN[24] $04 STDEFL STDEFL[7] STDEFL[6] STDEFL[5] STDEFL[4] STDEFL[3] STDEFL[2] STDEFL[1] STDEFL[0] $05 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $06 FCTCFG STMAG 0 0 0 0 0 0 0 PN[2] PN[1] PN[0] F $07 $08 Invalid Address: “Invalid Register Request” PN PN[7] PN[6] PN[5] $0A DEVCTL RES_1 RES_0 OCPHASE[1] OCPHASE[0] OFFCFG_EN Reserved Reserved Reserved $0B DEVCFG OC Reserved ENDINIT SD OFMON A_CFG[2] A_CFG[1] A_CFG[0] $0C AXISCFG ST Reserved Reserved Reserved LPF[3] LPF[2] LPF[1] LPF[0] ARMCFG Reserved Reserved APS[1] AWS_N[0] AWS_P[1] AWS_P[0] $09 PN[3] Invalid Address: “Invalid Register Request” $0D $0E PN[4] Invalid Address: “Invalid Register Request” APS[0] AWS_N[1] R/W $0F $10 Invalid Address: “Invalid Register Request” ARMT_P AT_P[7] AT_P[6] AT_P[5] ARMT_N AT_N[7] AT_N[6] AT_N[5] $11 $12 AT_P[3] AT_P[2] AT_P[1] AT_P[0] AT_N[2] AT_N[1] AT_N[0] 0 OFFSET DEVRES Invalid Address: “Invalid Register Request” $13 $14 AT_P[4] AT_N[4] AT_N[3] Invalid Address: “Invalid Register Request” DEVSTAT UNUSED IDE UNUSED DEVINIT MISOERR $15 COUNT COUNT[7] COUNT[6] COUNT[5] COUNT[4] COUNT[3] COUNT[2] COUNT[1] COUNT[0] $16 OFFCORR OFFCORR[7] OFFCORR[6] OFFCORR[5] OFFCORR[4] OFFCORR[3] OFFCORR[2] OFFCORR[1] OFFCORR[0] R $17 Invalid Address: “Invalid Register Request” $1C Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $1D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type codes F: Factory programmed OTP location R: Read-only register R/W: N/A: Read/write register Not applicable MMA655x Sensor Freescale Semiconductor, Inc. 11 3.1.1 Device Serial Number Registers A unique serial number is programmed into the serial number registers of each device during manufacturing. The serial number is composed of the following information: Bit Range Content S12 - S0 Serial Number S31 - S13 Lot Number Serial numbers begin at 1 for all produced devices in each lot, and are sequentially assigned. Lot numbers begin at 1 and are sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Depending on lot size and quantities, all possible lot numbers and serial numbers may not be assigned. The serial number registers are included in the OTP shadow register array CRC verification. Reference Section 3.2.1 for details regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device operation or performance, and are only used for traceability purposes. 3.1.2 Self Test Deflection Register (STDEFL) This read-only register provides the nominal self test deflection values at ambient temperature. The self test value is a positive deflection value, measured at the factory, and factory programmed for each device. The minimum stored value ($00) equates to the minimum deflection specified in Section 2.4 (ΔSTMIN), and the maximum stored value ($FF) equates to the maximum deflection specified in Section 2.4 (ΔSTMAX). Table 4. Self Test Deflection Register Location Bit Address Register 7 6 5 4 3 2 1 0 $04 STDEFL STDEFL[7] STDEFL[6] STDEFL[5] STDEFL[4] STDEFL[3] STDEFL[2] STDEFL[1] STDEFL[0] When self test is activated, the acceleration reading can be compared to the value in this register. The difference from the measured deflection value, and the nominal deflection value stored in the register shall not fall outside the self test accuracy limits specified in Section 2.4 (ΔSTACC). Reference Section 3.6 for more details on calculating the self test Limits. 3.1.3 Factory Configuration Registers The factory configuration register is a one time programmable, read only registers which contain customer specific device configuration information that is programmed by Freescale. Table 5. Factory Configuration Register Location Bit Address Register 7 6 5 4 3 2 1 0 $06 FCTCFG 1 0 0 0 0 0 0 0 MMA655x 12 Sensor Freescale Semiconductor, Inc. 3.1.4 Part Number Register (PN) The part number register is a one time programmable, read only register which contains two digits of the device part number to identify the axis and range information. The contents of this register have no impact on device operation or performance. Table 6. Part Number Register Location Bit Address Register 7 6 5 4 3 2 1 0 $08 PN PN[7] PN[6] PN[5] PN[4] PN[3] PN[2] PN[1] PN[0] PN Register Value Range Section 2.4 3.1.5 Decimal HEX 255 $FF 105 00 $00 120 Device Control Register (DEVCTL) The device control register is a read-write register which contains device control operations. The upper 2 bits of this register can be written during both initialization and normal operation. Bits 5 through 0 can be programmed during initialization and then are ignored once the ENDINIT bit is set. Table 7. Device Control Register Location Bit Address Register 7 6 $0A DEVCTL RES_1 RES_0 0 0 Reset Value 5 4 3 OCPHASE[1] OCPHASE[0] OFFCFG_EN 0 0 0 2 1 0 Reserved Reserved Reserved 0 0 0 3.1.5.1 Reset Control (RES_1, RES_0) A series of three consecutive register write operations to the reset control bits in the DEVCTL register will cause a device reset. To reset the internal digital circuitry, the following register write operations must be performed in the order shown below. The register write operations must be consecutive SPI commands in the order shown or the device will not be reset. Register Write to DEVCTL RES_1 RES_0 Effect SPI Register Write 1 0 0 No Effect SPI Register Write 2 1 1 No Effect SPI Register Write 3 0 1 Device RESET The response to the Register Write returns ‘0’ for RES_1 and RES_0, and the existing register value bits 5 through 0. A Register Read of RES_1 and RES_0 returns ‘0’ and terminates the reset sequence. If ENDINIT is cleared, the bits 2 through 0 in the DEVCTL register are modified as described in Section 4.4. If ENDINIT is set, a Register Write will not modify bits 2 through 0 and the response to a Register Read or Write will include the last successful written values for these bits. MMA655x Sensor Freescale Semiconductor, Inc. 13 3.1.5.2 Offset Cancellation Phase Control Bits (OCPHASE[1:0]) The offset cancellation phase control bits control the offset cancellation start up phase. These bits can be written at any time ENDINIT is ‘0’ if the OFFCFG_EN bit is set. OFFCFG_EN OCPHASE[1] OCPHASE[0] Writes to OCPHASE[1:0] Offset Cancellation Phase 0 Don’t Care Don’t Care Ignored Continues from the previously written phase (OCPHASE[1:0]) as specified in Section 3.8.4. 1 0 0 Accepted Remains in Start 1 until OFFCFG_EN is cleared or ENDINIT is set 1 0 1 Accepted Remains in Start 2 until OFFCFG_EN is cleared or ENDINIT is set 1 1 0 Accepted Remains in Start 3 until OFFCFG_EN is cleared or ENDINIT is set 1 1 1 Accepted Remains in Normal Mode until OFFCFG_EN is cleared or ENDINIT is set When ENDINIT is set, the OCPHASE[1:0] bits in a write command are ignored and the offset cancellation phase is set to “Normal”. This can only be changed by a device reset. The response to a register read or write of the DEVCTL register once ENDINIT is set will return the last successfully written values of OCPHASE[1:0]. 3.1.5.3 Offset Cancellation Configuration Enable Bit (OFFCFG_EN) The offset cancellation phase configuration enable bit enables modification of the offset cancellation phase control bits (OCPHASE[1:0]) as shown in Section 3.1.5.2 When ENDINIT is set, the OFFCFG_EN bit in a write command is ignored, and the offset cancellation phase is set to “Normal”. This can only be changed by a device reset. The response to a register read or write of the DEVCTL register once ENDINIT is set will return the last successfully written value of OFFCFG_EN. 3.1.5.4 Reserved Bits (DEVCTL[2:0]) Bits 2 through 0 of the DEVCTL register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device operation and performance. 3.1.6 Device Configuration Register (DEVCFG) The device configuration register is a read/write register which contains data for general device configuration. The register can be written during initialization but is locked once the ENDINIT bit is set. This register is included in the writable register CRC check. Refer to Section 3.2.2 for details. Table 8. Device Configuration Register Location Bit Address Register 7 6 5 4 3 2 1 0 $0B DEVCFG OC Reserved ENDINIT SD OFMON A_CFG[2] A_CFG[1] A_CFG[0] 0 0 0 0 0 0 0 0 Reset Value 3.1.6.1 Offset Cancelled Data Selection Bits (OC) The Offset Cancelled Data Selection Bit determines whether the SPI transmitted data is raw data or offset cancelled data. OC SPI Data 0 Offset Cancelled 1 Raw Data If the OC bit is cleared (Offset Cancelled Data), then the Offset Monitor is automatically enabled (OFMON = ‘1’) regardless of the value written to DEVCFG[3]. 3.1.6.2 Reserved Bit (Reserved) Bits 6 of the DEVCFG register is reserved. A write to the reserved bit must always be logic ‘0’ for normal device operation and performance. MMA655x 14 Sensor Freescale Semiconductor, Inc. 3.1.6.3 End of Initialization Bit (ENDINIT) The ENDINIT bit is a control bit used to indicate that the user has completed all device and system level initialization tests, and that the device will operate in normal mode. Once the ENDINIT bit is set, writes to all writable register bits are inhibited except for the DEVCTL register. Once written, the ENDINIT bit can only be cleared by a device reset. The writable register CRC check (reference Section 3.2.2) is only enabled when the ENDINIT bit is set. When ENDINIT is set, the following occurs: • Offset Cancellation is forced to normal mode. OCPHASE[1:0], and OFFCFG_EN remain in their previously set states. • X-Axis Self Test is disabled. ST remains in its previously set state. 3.1.6.4 SD Bit The SD bit determines the format of acceleration data results. If the SD bit is set to a logic ‘1’, unsigned results are transmitted, with the zero-g level represented by a nominal value of 512. If the SD bit is cleared, signed results are transmitted, with the zerog level represented by a nominal value of 0. SD Operating Mode 1 Unsigned Data Output 0 Signed Data Output 3.1.6.5 OFMON Bit The OFMON bit determines if the offset monitor circuit is enabled. If the OFMON bit is set to a logic ‘1’, the offset monitor is enabled. Reference Section 3.8.5. If the OFMON bit is cleared, the offset monitor is disabled. OFMON Operating Mode 1 Offset Monitor Circuit Enabled 0 Offset Monitor Circuit Disabled If the OC bit in the DEVCFG register is cleared (Offset Cancelled Data), then the Offset Monitor is automatically enabled (OFMON = ‘1’) regardless of the value written to DEVCFG[3]. 3.1.6.6 ARM Configuration Bits (A_CFG[2:0]) The ARM Configuration Bits (A_CFG[2:0]) select the mode of operation for the ARM/PCM pins. Table 9. Arming Output Configuration A_CFG[2] A_CFG[1] A-CFG[0] Operating Mode Output Type Reference 0 0 0 Arm Output Disabled Hi Impedance 0 0 1 PCM Output Digital Output Section 3.8.11 0 1 0 Moving Average Mode Active High with Pulldown Current Section 3.8.10.1 0 1 1 Moving Average Mode Active Low with Pullup Current Section 3.8.10.1 1 0 0 Count Mode Active High with Pulldown Current Section 3.8.10.2 1 0 1 Count Mode Active Low with Pullup Current Section 3.8.10.2 1 1 0 Unfiltered Mode Active High with Pulldown Current Section 3.8.10.3 1 1 1 Unfiltered Mode Active Low with Pullup Current Section 3.8.10.3 MMA655x Sensor Freescale Semiconductor, Inc. 15 3.1.7 Axis Configuration Register (AXISCFG) The axis configuration register is a read/write register which contain axis specific configuration information. This register can be written during initialization, but is locked once the ENDINIT bit is set. This registers is included in the writable register CRC check. Refer to Section 3.2.2 for details. Table 10. Axis Configuration Registers Location Bit Address Register 7 6 5 4 3 2 1 0 $0C AXISCFG ST Reserved Reserved Reserved LPF[3] LPF[2] LPF[1] LPF[0] 0 0 0 0 0 0 0 0 Reset Value 3.1.7.1 Self Test Control (ST) The ST bit enables and disables the self test circuitry. Self test circuitry is enabled if a logic ‘1’ is written to ST and the ENDINIT bit has not been set. Enabling the self test circuitry results in a positive acceleration value. Self test deflection values are specified in Section 2.4. ST is always cleared following internal reset. When the self test circuitry is active, the offset cancellation block and the offset monitor status are suspended, and the status bits in the Acceleration Data Request Response will indicate “Self Test Active”. Reference Section 3.8.4 and Section 4.2 for details. When the self test circuitry is disabled by clearing the ST bit, the offset monitor remains disabled until the time tST_OMB specified in Section 2.5 expires. However, the status bits in the Acceleration Data Request Response will immediately indicate that self test is deactivated. When ENDINIT is set, self test is disabled. This can only be changed by a reset. A Register Write will not modify the ST bit and the response to a Register Read or Write will include the last successful written values for these bits. 3.1.7.2 Reserved Bits (Reserved) Bits 6 through 4 of the AXISCFG register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device operation and performance. 3.1.7.3 Low-Pass Filter Selection Bits (LPF[3:0]) The Low Pass Filter selection bit selects a low-pass filter as shown in Table 11. Refer to Section 3.8.3 for details regarding filter configurations. Table 11. Low Pass Filter Selection Bits LPF[3] LPF[2] LPF[1] LPF[0] Low Pass Filter Selected Nominal Sample Rate (μs) 0 0 0 0 100 Hz, 4-pole 8 0 0 0 1 300 Hz, 4-pole 8 0 0 1 0 400 Hz, 4-pole 8 0 0 1 1 800 Hz, 4-pole 8 0 1 0 0 1000 Hz, 4-pole 8 0 1 0 1 400 Hz, 3-pole 8 0 1 1 0 Reserved Reserved 0 1 1 1 Reserved Reserved 1 0 0 0 50 Hz, 4-pole 16 1 0 0 1 150 Hz, 4-pole 16 1 0 1 0 200 Hz, 4-pole 16 1 0 1 1 400 Hz, 4-pole 16 1 1 0 0 500 Hz, 4-pole 16 1 1 0 1 200 Hz, 3-pole 16 1 1 1 0 Reserved Reserved 1 1 1 1 Reserved Reserved Note:Filter characteristics do not include g-cell frequency response. MMA655x 16 Sensor Freescale Semiconductor, Inc. 3.1.8 Arming Configuration Registers (ARMCFG) The arming configuration register contains configuration information for the arming function. The values in this register are only relevant if the arming function is operating in moving average mode, or count mode. This register can be written during initialization but is locked once the ENDINIT bit is set. Refer to Section 3.1.6.3. This register is included in the writable register CRC check. Refer to Section 3.2.2 for details. Table 12. Arming Configuration Register Location Bit Address Register 7 6 5 4 3 2 1 0 $0E ARMCFG Reserved Reserved APS[1] APS[0] AWS_N[1] AWS_N[0] AWS_P[1] AWS_P[0] 0 0 0 0 1 1 1 1 Reset Value 3.1.9 Reserved Bits (Reserved) Bits 7 through 6 of the ARMCFG register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device operation and performance. 3.1.9.1 Arming Pulse Stretch (APS[1:0]) The APS[1:0] bit sets the programmable pulse stretch time for the arming outputs. Refer to Section 3.8.10 for more details regarding the arming function. Pulse stretch times are derived from the internal oscillator, so the tolerance on this oscillator applies. Table 13. Arming Pulse Stretch Definitions APS[1] APS[0] Pulse Stretch Time (Typical Oscillator) 0 0 0 ms 0 1 16.256 ms - 16.384 ms 1 0 65.408 ms - 65.536 ms 1 1 261.888 ms - 262.016 ms 3.1.9.2 Arming Window Size (AWS_x[1:0]) The AWS_x[1:0] bits have different functions depending on the state of the A_CFG bits in the DEVCFG register. If the arming function is set to moving average mode, the AWS bits set the number of acceleration samples used for the arming function moving average. The number of samples is set independently for each axis and polarity. If the arming function is set to count mode, the AWS bits set the sample count limit for the arming function. The sample count limit is set independently for each axis. Refer to Section 3.8.10 for more details regarding the arming function. Table 14. Positive Arming Window Size Definitions (Moving Average Mode) AWS_P[1] AWS_P[0] Positive Window Size 0 0 2 0 1 4 1 0 8 1 1 16 Table 15. Negative Arming Window Size Definitions (Moving Average Mode) AWS_N[1] AWS_N[0] Negative Window Size 0 0 2 0 1 4 1 0 8 1 1 16 MMA655x Sensor Freescale Semiconductor, Inc. 17 Table 16. Arming Count Limit Definitions (Count Mode) 3.1.10 AWS_N[1] AWS_N[0] AWS_P[1] AWS_P[0] Sample Count Limit Don’t Care Don’t Care 0 0 1 Don’t Care Don’t Care 0 1 3 Don’t Care Don’t Care 1 0 7 Don’t Care Don’t Care 1 1 15 Arming Threshold Registers (ARMT_P, ARMT_N) The arming threshold registers contain the positive and negative thresholds to be used by the arming function. Refer to Section 3.8.10 for more details regarding the arming function. The arming threshold registers can be written during initialization but are locked once the ENDINIT bit is set. Refer to Section 3.1.6.3. The arming threshold registers are included in the writable register CRC check. Refer to Section 3.2.2 for details. Table 17. Arming Threshold Registers Location Bit Address Register 7 6 5 4 3 2 1 0 $10 ARMT_P AT_P[7] AT_P[6] AT_P[5] AT_P[4] AT_P[3] AT_P[2] AT_P[1] AT_P[0] $12 ARMT_N AT_N[7] AT_N[6] AT_N[5] AT_N[4] AT_N[3] AT_N[2] AT_N[1] AT_N[0] 0 0 0 0 0 0 0 0 Reset Value The values programmed into the threshold registers are the threshold values used for the arming function as described in Section 3.8.10. The threshold registers hold independent unsigned 8-bit values for each axis and polarity. Each threshold increment is equivalent to one output LSB. Table 18 shows examples of some threshold register values and the corresponding threshold. Table 18. Threshold Register Value Examples Axis Type Programmed Thresholds Positive Threshold (g) Negative Threshold (g) 50 5.50 -2.75 255 0 14.0 Disabled 18.2 50 20 2.75 -1.10 18.2 150 75 8.24 -4.12 Range (g) Sensitivity (LSB/g) Positive (Decimal) Negative (Decimal) 105.5 18.2 100 105.5 18.2 105.5 105.5 If either the positive or negative threshold is programmed to $00, comparisons are disabled for only that polarity. The arming function still operates for the opposite polarity. If both the positive and negative arming thresholds are programmed to $00, the Arming function is disabled, and the output pin is disabled, regardless of the value of the A_CFG bits in the DEVCFG register. MMA655x 18 Sensor Freescale Semiconductor, Inc. 3.1.11 Device Status Register (DEVSTAT) The device status register is a read-only register. A read of this register clears the status flags affected by transient conditions. Reference Section 4.5 for details on the response for each status condition. Table 19. Device Status Register Location Bit Address Register 7 6 5 4 3 2 1 0 $14 DEVSTAT UNUSED IDE UNUSED DEVINIT MISOERR 0 OFFSET DEVRES 3.1.11.1 Unused Bits (UNUSED) The unused bits have no impact on operation or performance. When read these bits may be ‘1’ or ‘0’. 3.1.11.2 Internal Data Error Flag (IDE) The internal data error flag is set if a customer or OTP register data CRC fault or other internal fault is detected as defined in Section 4.5.5. The internal data error flag is cleared by a read of the DEVSTAT register. If the error is associated with a CRC fault in the writable register array, the fault will be re-asserted and will require a device reset to clear. If the error is associated with the data stored in the fuse array, the fault will be re-asserted even after a device reset. 3.1.11.3 Device Initialization Flag (DEVINIT) The device initialization flag is set during the interval between negation of internal reset and completion of internal device initialization. DEVINIT is cleared automatically. The device initialization flag is not affected by a read of the DEVSTAT register. 3.1.11.4 SPI MISO Data Mismatch Error Flag (MISOERR) The MISO data mismatch flag is set when a MISO Data mismatch fault occurs as specified in Section 4.5.2. The MISOERR flag is cleared by a read of the DEVSTAT register. 3.1.11.5 Offset Monitor Error Flags (OFFSET) The offset monitor error flag is set if the acceleration signal reaches the specified offset limit. The offset monitor error flags are cleared by a read of the DEVSTAT register. 3.1.11.6 Device Reset Flag (DEVRES) The device reset flag is set during device initialization following a device reset. The device reset flag is cleared by a read of the DEVSTAT register. 3.1.12 Count Register (COUNT) The count register is a read-only register which provides the current value of a free-running 8-bit counter derived from the primary oscillator. A 10-bit pre-scaler divides the primary oscillator frequency by 1024. Thus, the value in the register increases by one count every 128 μs and the counter rolls over every 32.768 ms. Table 20. Count Register Location Bit Address Register 7 6 5 4 3 2 1 0 $15 COUNT COUNT[7] COUNT[6] COUNT[5] COUNT[4] COUNT[3] COUNT[2] COUNT[1] COUNT[0] 0 0 0 0 0 0 0 0 Reset Value MMA655x Sensor Freescale Semiconductor, Inc. 19 3.1.13 Offset Correction Value Registers (OFFCORR) The offset correction value register is a read-only register which contains the most recent offset correction increment / decrement value from the offset cancellation circuit. The value stored in this register indicate the amount of offset correction being applied to the SPI output data. The values has a resolution of 1 LSB. Table 21. Offset Correction Value Register Location Bit Address Register 7 6 5 4 3 2 1 0 $16 OFFCORR OFFCORR[7] OFFCORR[6] OFFCORR[5] OFFCORR[4] OFFCORR[3] OFFCORR[2] OFFCORR[1] OFFCORR[0] 0 0 0 0 0 0 0 0 Reset Value 3.1.14 Reserved Registers (Reserved) Registers $1C and $1D are reserved. A write to the reserved bits must always be logic ‘0’ for normal device operation and performance. Table 22. Reserved Registers Location Bit Address Register 7 6 5 4 3 2 1 0 $1C Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $1D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reset Value 3.2 Customer Accessible Data Array CRC Verification 3.2.1 OTP Shadow Register Array CRC Verification The OTP shadow register array is verified for errors using a 3-bit CRC. The CRC verification uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = ‘111’. If a CRC error is detected in the OTP array, the IDE bit is set in the DEVSTAT register. 3.2.2 Writable Register CRC Verification The writable registers in the data array are verified for errors using a 3-bit CRC. The CRC verification is enabled only when the ENDINIT bit is set in the DEVCFG register. The CRC verification uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = ‘111’. If a CRC error is detected in the writable register array, the IDE bit is set in the DEVSTAT register. MMA655x 20 Sensor Freescale Semiconductor, Inc. 3.3 Voltage Regulators Separate internal voltage regulators supply the analog and digital circuitry. External filter capacitors are required, as shown in Figure 1. The voltage regulator module includes voltage monitoring circuitry which indicates a device reset until the external supply and all internal regulated voltages are within predetermined limits. A reference generator provides a stable voltage which is used by the ΣΔ converters. VCC BANDGAP REFERENCE VREGA = 2.50 V VOLTAGE REGULATOR BIAS GENERATOR VREGA PRIMARY OSCILLATOR TRIM TRIM REFERENCE GENERATOR VREF = 1.250 V ΣΔ CONVERTER DIGITAL LOGIC DSP TRACKING REGULATOR Tracks VREGA OTP ARRAY VREG = 2.50 V VREG Figure 8. Power Supply Block Diagram VCCUV VCC VREG VREGOV VREGUV MONITOR BANDGAP GROUND LOSS MONITOR VBGMON VREGA SET DEVRES Flag VREGAUV VREGAOV VREG VREF VREFOV VREFUV VPORREF POR Note: No external access to reference voltage Limits verified by characterization only Figure 9. Voltage Monitoring MMA655x Sensor Freescale Semiconductor, Inc. 21 3.3.1 CVREG Failure Detection The digital supply voltage regulator is designed to be unstable with low capacitance. If the connection to the VREG capacitor becomes open, the digital supply voltage will oscillate and cause either an undervoltage, or overvoltage failure within one internal sample time. This failure will result in one of the following: 1. The DEVRES flag in the DEVSTAT register will be set. The device will respond to SPI acceleration requests as defined in Table 27. 2. The device will be held in RESET and be non-responsive to SPI requests. 3.3.2 CVREGA Failure Detection The analog supply voltage regulator is designed to be unstable with low capacitance. If the connection to the VREGA capacitor becomes open, the analog supply voltage will oscillate and cause either an undervoltage, or overvoltage failure within one internal sample time. The DEVRES flag in the DEVSTAT register will be set. The device will respond to SPI acceleration requests as defined in Table 27. 3.3.3 VSS and VSSA Ground Loss Monitor The device detects the loss of ground connection to either VSS or VSSA. A loss of ground connection to VSS will result in a VREG overvoltage failure. A loss of ground connection to VSSA will result in a VREG undervoltage failure. Both failures result in a device reset. 3.3.4 SPI Initiated Reset In addition to voltage monitoring, a device reset can be initiated by a specific series of three write operations involving the RES_1 and RES_0 bits in the DEVCTL register. Reference Section 3.1.5.1. for details regarding the SPI initiated reset. 3.4 Internal Oscillator The device includes a factory trimmed oscillator as specified in Section 2.6. 3.4.1 Oscillator Monitor The COUNT register in the customer accessible array is a read-only register which provides the current value of a free-running 8-bit counter derived from the primary oscillator. A 10-bit pre-scaler divides the primary oscillator by 1024. Thus, the value in the COUNT register increases by one count every 128 μs, and the register rolls over every 32.768 ms. The SPI master can periodically read the COUNT register, and verify the difference between subsequent register reads against the system time base. 1. The SPI access rates and deviations must be taken into account for this oscillator verification method. 3.5 Transducer The transducer is an overdamped mass-spring-damper system described by the following transfer function: 2 ωn H ( s ) = -----------------------------------------------------2 2 s + 2 ⋅ ξ ⋅ ωn ⋅ s + ωn where: ζ= Damping Ratio ωn= Natural Frequency = 2∗Π∗fn Reference Section 2.4 for transducer parameters. MMA655x 22 Sensor Freescale Semiconductor, Inc. 3.6 Self Test Interface When self test is enabled, the self test interface applies a voltage to the g-cell, causing a deflection of the proof mass. Once enabled, offset cancellation is suspended and the deflection results in an acceleration which is superimposed upon the input acceleration. The resulting acceleration readings can be compared either against absolute limits, or the values stored in the Self Test Deflection Registers (Reference Section 3.1.2). The self test interface is controlled through SPI write operations to the DEVCFG register described in Section 3.1.7 only if the ENDINIT bit in the DEVCFG register is cleared. A diagram of the self test interface is shown in Figure 10. SELF-TEST VOLTAGE GENERATOR g-CELL ENDINIT ENDINIT ST Figure 10. Self Test Interface 3.6.1 Raw Self Test Deflection Verification The raw self test deflection can be directly verified against raw self test limits listed in Section 2.4. 3.6.2 Delta Self Test Deflection Verification The raw self test deflection can be verified against the ambient temperature self test deflection value recorded at the time the device was produced. The production self test deflection is stored in the STDEFL register such that the minimum stored value (0x00) is equivalent to ΔSTMIN, and the maximum stored value (0xFF) is equivalent to ΔSTMAX. The Delta Self Test Deflection limits can then be determined by the following equations: ΔSTDEFLx CNTS ΔST ACCMINLIMIT = FLOOR ⋅ ⎛ ΔST MIN + ------------------------------------------ × [ ΔST MAX – ΔST MIN ]⎞ × ( 1 – ΔST ACC ) ⎝ ⎠ 255 ΔSTDEFLx CNTS ΔST ACCMAXLIMIT = CEIL ⋅ ⎛⎝ ΔST MIN + ------------------------------------------ × [ ΔST MAX – ΔST MIN ]⎞⎠ × ( 1 + ΔST ACC ) 255 where: ΔSTACC ΔSTDEFLxCNTS The accuracy of the self test deflection relative to the stored deflection as specified in Section 2.4. The value stored in the STDEFL register. ΔSTMIN The minimum self test deflection at 25C as specified in Section 2.4. ΔSTMAX The maximum self test deflection at 25C as specified in Section 2.4. MMA655x Sensor Freescale Semiconductor, Inc. 23 ΣΔ Converter 3.7 A sigma delta converter provides the interface between the transducer and the DSP. The output of the ΣΔ converter is a data stream at a nominal frequency of 1 MHz. g-CELL α1 = CTOP VX FIRST INTEGRATOR CINT1 z-1 SECOND INTEGRATOR α2 z-1 1 - z-1 CBOT 1-BIT QUANTIZER ΣΔ_OUT 1 - z-1 ADC ΔC = CTOP - CBOT β2 β1 DAC V = ΔC x VX / CINT1 V = ±2 × VREF Figure 11. ΣΔ Converter Block Diagram 3.8 Digital Signal Processing Block A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating the signal processing flow is shown in Figure 12. Arm/PCM Output Section 3.8.9 Section 3.8.10 A ΣΔ_OUT SINC Filter Section 3.8.2 B Low Pass Filter Section 3.8.3 C Compensation D Section 3.8.6 Interpolation Section 3.8.7 E Offset Cancellation Section 3.8.4 F Offset Cancellation Output Scaling Raw Output Scaling I To ARM G To SPI H To SPI Figure 12. Signal Chain Diagram Table 23. Signal Chain Characteristics Description Sample Time (μs) Data Width Bits Over Range Bits Effective Bits A SD 1 1 B SINC Filter 8 14 C Low Pass Filter 8/16 20 4 12 D Compensation 8/16 20 4 E Interpolation 4/8 20 F Offset Cancellation 256 GH SPI Output I PCM Output Rounding Resolution Bits Typical Block Latency Reference 1 3.2μs Section 3.7 13 11.2μs Section 3.8.2 4 Reference Section 3.8.3 Section 3.8.3 12 4 7.875 μs Section 3.8.6 4 12 4 ts / 2 Section 3.8.8 20 4 12 4 N/A Section 3.8.4 4/8 — — 12 — ts / 2 4/8 — — 9 — Section 3.8.11 MMA655x 24 Sensor Freescale Semiconductor, Inc. 3.8.1 DSP Clock The DSP is clocked at 8 MHz, with an effective 6 MHz operating frequency. The clock to the DSP is disabled for 1 clock prior to each edge of the ΣΔ modulator clock to minimize noise during data conversion. 8 MHz OSC 6 MHz Digital 1MHz Modulator Figure 13. Clock Generation 3.8.2 Decimation Sinc Filter The serial data stream produced by the ΣΔ converter is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 8 or 16, depending on the Low Pass Filter selected. 3 1 – z – 16 H ( z ) = ----------------------------------16 × ( 1 – z – 1 ) Figure 14. Sinc Filter Response, tS = 8 μs MMA655x Sensor Freescale Semiconductor, Inc. 25 3.8.3 Low Pass Filter Data from the Sinc filter is processed by an infinite impulse response (IIR) low pass filter. n0 + ( n1 ⋅ z –1 ) + ( n2 ⋅ z –2 ) + ( n3 ⋅ z –3 ) + ( n4 ⋅ z –4 ) H ( z ) = --------------------------------------------------------------------------------------------------------------------------------d0 + ( d1 ⋅ z –1 ) + ( d2 ⋅ z –2 ) + ( d3 ⋅ z –3 ) + ( d4 ⋅ z –4 ) The device provides the option for one of twelve low-pass filters. The filter is selected with the LPF[3:0] bits in the AXISCFG register. The filter selection options are listed in Section 3.1.7.3, Table 11. Response parameters for the low-pass filter are specified in Section 2.4. Filter characteristics are illustrated in the figures on the following pages. Table 24. Low Pass Filter Coefficients Filter Number LPF Value (HEX) Description -3dB Frequency (±5%) Filter Order Sample Time (μs ±5%) Filter Coefficients n0 8 0x08 50 Hz LPF 4 16 9 1 10 2 13 5 0x00 0x09 0x01 0x0A 0x02 0x0D 0x05 100 Hz LPF 150 Hz LPF 300 Hz LPF 200 Hz LPF 400 Hz LPF 200 Hz LPF 400 Hz LPF 4 4 4 4 4 3 3 8 16 8 16 8 16 8 3 12 4 0x0B 0x03 0x0C 0x04 400 Hz LPF 800 Hz LPF 500 Hz LPF 1000 Hz LPF 4 4 4 4 16 8 16 8 d0 1.25237777794924e-09 5.929003009577855 d2 n3 8.349103355433541e-10 d3 -3.929255528257727 n4 2.087307211059861e-10 d4 0.9765022168437554 n0 1.639127731323242e-08 d0 1 n1 6.556510925292969e-08 d1 -3.928921222686768 14.00 26816/fosc 7.00 n2 9.834768482194806e-08 d2 5.789028996785419 n3 6.556510372902331e-08 d3 -3.791257019240902 n4 1.639128257923422e-08 d4 0.9311495074496179 n0 5.124509334564209e-08 d0 1 n1 2.049803733825684e-07 d1 -3.905343055725098 n2 3.074705789151505e-07 d2 5.72004239520561 n3 2.049803958150164e-07 d3 -3.723967810019985 n4 5.124510693742625e-08 d4 0.9092692903507213 6.00 9024/fosc 3.00 5.00 6784/fosc 2.50 n0 2.720393240451813e-06 d0 1 n1 8.161179721355438e-06 d1 -2.931681632995605 n2 8.161180123840722e-06 d2 2.865296718275204 4.80 5632/fosc n3 2.720393634345496e-06 d3 -0.9335933215174919 0 d4 0 n0 7.822513580322266e-07 d0 1 n1 3.129005432128906e-06 d1 -3.811614513397217 n2 4.693508163398543e-06 d2 5.450666051045118 n3 3.129005428784364e-06 d3 -3.465805771100349 n4 7.822513604678875e-07 d4 0.8267667478030489 n0 1.865386962890625e-06 d0 1 n1 -3.765105724334717 n2 1.119232176112846e-05 d2 5.319861050818872 7.4615478515625e-06 -3.34309015036024 d3 n4 1.865386966264658e-06 d4 2.40 2.50 3392/fosc 1.70 d1 n3 7.4615478515625e-06 Self Test Step Response (ms) 1 -3.976249694824219 n4 11 2.08729034056887e-10 n1 8.349134489240434e-10 d1 n2 0 Group Delay 3.20 2688/fosc 1.60 0.7883646729233078 Note: Low Pass Filter figures do not include g-cell frequency response. MMA655x 26 Sensor Freescale Semiconductor, Inc. Figure 15. Low-Pass Filter Characteristics: fC = 100 Hz, Poles = 4, tS = 8 μs MMA655x Sensor Freescale Semiconductor, Inc. 27 Figure 16. Low-Pass Filter Characteristics: fC = 300 Hz, Poles = 4, tS = 8 μs MMA655x 28 Sensor Freescale Semiconductor, Inc. Figure 17. Low-Pass Filter Characteristics: fC = 400 Hz, Poles = 4, tS = 8 μs MMA655x Sensor Freescale Semiconductor, Inc. 29 Figure 18. Low-Pass Filter Characteristics: fC = 400 Hz, Poles = 3, tS = 8 μs MMA655x 30 Sensor Freescale Semiconductor, Inc. Figure 19. Low-Pass Filter Characteristics: fC = 800 Hz, Poles = 4, tS = 8 μs MMA655x Sensor Freescale Semiconductor, Inc. 31 Figure 20. Low-Pass Filter Characteristics: fC = 1000 Hz, Poles = 4, tS = 8 μs MMA655x 32 Sensor Freescale Semiconductor, Inc. 3.8.4 Offset Cancellation The device provides the option to read offset cancelled acceleration data via the SPI by clearing the OC bit in the DEVCFG register (reference Section 3.1.6.1) and in the SPI command (reference Section 4.1). A block diagram of the offset cancellation is shown in Figure 21, and response parameters are specified in Section 2.4 and in Table 25. Downsampled to 256μs LPFOUT T Registers updated every 1.049s Accumulator Shift 4096 samples T1 T2 T3 T4 OFFTHRNEG T5 T6 OFF_ERR 1.049s OFF_ERR OFFTHRPOS Updated every 1.049s 1/8 LSB Increment 1/4 LSB 6.291s Average Offset Inc/Dec OFFCORRP Decrement 1/4 LSB OFF_CORR_VALUE OCOUT OFFCORRN 1/8 LSB Alignment Correction Figure 21. Offset Cancellation Block Diagram In normal operation, the offset cancellation circuit computes a 24,576 sample running average of the acceleration data downsampled to 256 μs. The running average is compared against positive and negative thresholds to determine the offset correction value that will be applied to the acceleration data. During start up, three phases of moving average sizes are used to allow for faster convergence of misuse input signals. Reference Table 25 for offset cancellation timing information during startup and normal operation. The offset cancellation startup phase can also be directly controlled during initialization (ENDINIT = ‘0’) using the OCPHASE[1:0] bits and the OFFCFG_EN bit in the DEVCTL register, as described in Section 3.1.5.2 and Section 3.1.5.3. Table 25. Offset Cancellation Timing Specifications Phase Start Time of Phase (from POR) Typical Time in Phase (ms) # of Samples in Phase Samples Averaged OFF_CORR_VALUE Update Rate (ms) Averaging Period (ms) Maximum Averaging Filter Slew Rate -3dB Frequency (LSB/s) (Hz) Start 1 tOP 524.288 2048 48 2.048 12.288 122.1 36.05 Start 2 tOP + 524.288 524.288 2048 384 16.38 98.304 15.26 4.506 Start 3 tOP + 1048.576 524.288 2048 3072 131.1 786.432 1.907 0.5632 Normal tOP + 1572.864 — — 24576 1049 6291.456 0.2384 0.07040 When the self test circuitry is active, the offset cancellation block and the offset monitor block are suspended, and the offset correction value is constant. Once the self test circuitry is disabled, the offset cancellation block remains suspended for the time tST_OMB to allow the acceleration output to return to it’s nominal offset. 3.8.5 Offset Monitor The device provides the option for an offset monitor circuit. The offset monitor circuit is enabled when the OFMON bit in the DEVCFG register is programmed to a logic ‘1’. The output of the offset cancellation circuit is compared against a high and low threshold. If the offset correction value exceeds either the OFFTHRPOS, or OFFTHRNEG threshold, an Offset Over Range Error condition is indicated. The offset correction value update rate is listed in Table 25: “Maximum Slew Rate”. Because the offset monitor uses this value, the offset monitor will also update at this rate. The time to indicate an Offset Over Range Error is dependent upon the input signal. The offset monitor status remains suspended during self test, because the offset monitor is based on the offset cancellation circuit, which is also suspended during self test. The offset monitor is disabled for 2.1 seconds following reset regardless of the state of the OFMON bit. MMA655x Sensor Freescale Semiconductor, Inc. 33 3.8.6 Signal Compensation The device includes internal OTP and signal processing to compensate for sensitivity error and offset error. This compensation is necessary to achieve the specified parameters in Section 2.4. 3.8.7 Output Scaling The 20 bit digital output from the DSP is clipped and scaled to a 12-bit data word which spans the acceleration range of the device. Figure 22 shows the method used to establish the output acceleration data word from the DSP output. Over Range D19 D18 D17 Signal D16 12-Bit Data Word Noise D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Using Rounding Figure 22. 12-Bit Output Scaling Diagram 3.8.8 Data Interpolation The device includes 2 to 1 data interpolation to minimize the system sample jitter. Each result produced by the digital signal processing chain is delayed one half of a sample time, and the interpolated value of successive samples is provided between sample times. This operation is illustrated below. Sn-3 Sn-2 Sn-1 Sn Internal Sample Rate t ts Sn-3 ts Sn – 3 + Sn – 2 ------------------------------2 Sn-2 ts Sn – 2 + Sn – 1 ------------------------------2 Sn-1 Sn – 1 + Sn -----------------------2 Output Sample Rate t SPI acceleration request occurring in this window receives interpolated sample SPI acceleration request occurring in this window receives true sample. Figure 23. Data Interpolation Timing MMA655x 34 Sensor Freescale Semiconductor, Inc. The effect of this interpolation at the system level is a 50% reduction in sample jitter. Figure 24 shows the resulting output data for an input signal. 80 75 Internally Sampled Values 70 Counts 65 60 Fixed Latency: tS / 2 Earliest Transmission Point of Interpolated Values 55 Earliest Transmission Point of Internally Sampled Values 50 45 Window of Transmission for Interpolated Values (Maximum: tS / 2) Window of Transmission for = Signal Jitter = Sampled Values (Maximum: tS / 2) 40 0 5 10 15 Input Signal Internally Sampled Signal Interpolated Samples 20 25 30 35 40 Time Figure 24. Data Interpolation Example 3.8.9 Acceleration Data Timing The SPI uses a request/response protocol, where a SPI transfer is completed through a sequence of 2 phases. Reference Section 4 for more details regarding the SPI protocol. The device latches the associated data for an acceleration request at the rising edge of CS. The most recent sample available from the DSP (including interpolation) is latched, and transmitted during the subsequent SPI transfer. SCLK CS MOSI Request Accel Request Accel Request Accel Request Accel Accel Response Accel Response Accel Response MISO Axis Data Latched Arm Function updated Data Latched Arm Function updated if applicable Figure 25. Acceleration Data Timing MMA655x Sensor Freescale Semiconductor, Inc. 35 3.8.10 Arming Function The device provides the option for an arming function with 3 modes of operation. The operation of the arming function is selected by the state of the A_CFG bits in the DEVCFG register. Reference Section 4.5 for the operation of the Arming function with exception conditions. Error conditions do not impact prior arming function responses. If an error occurs after an arming activation, the corresponding pulse stretch for the existing arming condition will continue. However, new acceleration reads will not update the arming function regardless of the acceleration value. 3.8.10.1 Arming Function: Moving Average Mode In moving average mode, the arming function runs a moving average on the offset cancelled output. The number of samples used for the moving average (k) is programmable via the AWS_x[1:0] bits in the ARMCFGX register. Reference Section 3.1.8 for register details. ARM_MAn = (OCn + OCn-1 + ... + OCn+1-k)/k Where n is the current sample. The sample rate is determined by the SPI acceleration data sample rate. At the rising edge of CS for an acceleration data SPI request, the moving average is updated with a new sample. Reference Figure 28. The SPI acceleration data sample rate must meet the minimum time between requests (tACC_REQ_x) specified in Section 2.5. The moving average output is compared against positive and negative 8-bit thresholds that are programmed via the ARMT_x registers. Reference Section 3.1.10 for register details. If the moving average equals or exceeds either threshold, an arming condition is indicated, the ARM output is asserted for the associated axis, and the pulse stretch counter is set as described in Section 3.8.10.4. The ARM output is de-asserted only when the pulse stretch counter expires. Figure 28 shows the arming output operation for different SPI conditions. ARMT_P[7:0] AWS_P[1:0] Positive Moving Average Offset Cancellation Pulse Stretch OffCanc_ARM[10:0] AWS_N[1:0] Gating I/O ARM Negative Moving Average ARMT_N[7:0] APS[3:0] Figure 26. Arming Function Block Diagram - Moving Average Mode The moving average window size must be set prior to setting the arming function to moving average mode, or prior to requesting acceleration data via the SPI. If the moving average window size is changed after enabling moving average mode, the arming function must first be disabled by setting the A_CFG bits to “000”. Once the desired moving average window size is set, the moving average mode can be re-enabled. MMA655x 36 Sensor Freescale Semiconductor, Inc. 3.8.10.2 Arming Function: Count Mode In count mode, the arming function compares each offset cancelled sample against positive and negative thresholds that are programmed via the ARMT_x registers. Reference Section 3.1.10 for register details. If the sample equals or exceeds either threshold, a sample counter is incremented. If the sample does not exceed either threshold, the sample counter is reset to zero. The sample rate is determined by the SPI acceleration data sample rate. At the rising edge of CS for an acceleration data SPI request, a new sample is compared against the thresholds. Reference Figure 28. The SPI acceleration data sample rate must meet the minimum time between requests (tACC_REQ_x) specified in Section 2.5. A sample count limit is programmable via the AWS_x[1:0] bits in the ARMCFG register. If the sample count reaches the programmable sample count limit, an arming condition is indicated, the ARM output is asserted for the associated axis, and the pulse stretch counter is set as described in Section 3.8.10.4. The ARM output is de-asserted only when the pulse stretch counter expires. Figure 28 shows the arming output operation for different SPI conditions. AWS_P[1:0] ARMT_P[7:0] Offset Cancellation 1-4 Sample Pulse Stretch OffCanc_ARM[10:0] Counter Gating I/O ARM ARMT_N[7:0] APS[1:0] Figure 27. Arming Function Block Diagram - Count Mode SCLK CS MOSI Request X-Axis Request X-Axis Request X-Axis Request X-Axis X-Axis Response X-Axis Response X-Axis Response X-Axis Response X-Axis Arm Condition Not Present X-Axis Arm Condition Present X-Axis Arm Condition Not Present X-Axis Arm Condition Not Present MISO ARM Data Latched for Arm & SPI tARM Pulse Stretch Time Figure 28. Arming Condition, Moving Average and Count Mode MMA655x Sensor Freescale Semiconductor, Inc. 37 3.8.10.3 Arming Function: Unfiltered Mode On the rising edge of CS for an acceleration request, the most recent available offset cancelled sample for the requested axis is compared against positive and negative thresholds that are programmed via the ARMT_x registers. Reference Section 3.1.10 for register details. If the sample equals or exceeds either threshold, an arming condition is indicated. Once an arming condition is indicated for the ARM output is asserted when CS is asserted and the MISO data includes an acceleration response for that axis. The pulse stretch function is not applied in Unfiltered mode. Figure 29 contains a block diagram of the Arming Function operation in Unfiltered Mode. Figure 30 shows the Arming output operation under the different SPI request conditions. ACFG[2] ACFG[1] CS I/O AXIS Select ARM ARMING FUNCTION Interpolated Sample Rate Figure 29. Arming Function Block Diagram - Unfiltered Mode SCLK CS MOSI Request X-Axis Request X-Axis Request X-Axis Request X-Axis X-Axis Response X-Axis Response X-Axis Response X-Axis Response X-Axis Arm Condition Not Present X-Axis Arm Condition Present X-Axis Arm Condition Not Present X-Axis Arm Condition Not Present MISO ARM X-Axis Data Latched for Arm & SPI tARM_UF_DLY tARM_UF_ASSERT Figure 30. Arming Condition, Unfiltered Mode MMA655x 38 Sensor Freescale Semiconductor, Inc. 3.8.10.4 Arming Pulse Stretch Function A pulse stretch function can be applied to the arming output in moving average mode, or count mode. If the pulse stretch function is not used (APS[1:0] = ‘00’), the arming output is asserted if and only if an arming condition exists for the associated axis after the most recent evaluated sample. The arming output is de-asserted if and only if an arming condition does not exist for the associated axis after the most recent evaluated sample. If the pulse stretch function is used, (APS[1:0] not equal ‘00’), the arming output is controlled only by the value of the pulse stretch timer value. If the pulse stretch timer value is non-zero, the arming output is asserted. If the pulse stretch timer is zero, the arming output is de-asserted. The pulse stretch counter continuously decrements until it reaches zero. The pulse stretch counter is reset to the programmed pulse stretch value if and only if an arming condition exists for the associated axis after the most recent evaluated sample. Reference Figure 28. The desired pulse stretch time is programmable for via the APS[1:0] bits in the ARMCFG register. Exception conditions listed in Section 4.5 do not impact prior arming function responses. If an exception occurs after an arming activation, the corresponding pulse stretch for the existing arming condition will continue. However, new acceleration reads will not reset the pulse stretch counter regardless of the acceleration value. 3.8.10.5 Arming Pin Output Structure The arming output pin structure can be set to active high, or active low with the A_CFG bits in the DEVCFG register as described in Section 3.1.6.6. The active high and active low pin output structures are shown in Figure 31. Open Drain, Active High Open Drain, Active Low VCC Arm Function Gating VCC ARM ARM Arm Function Gating Figure 31. Arming Function - Pin Output Structure MMA655x Sensor Freescale Semiconductor, Inc. 39 3.8.11 PCM Output Function The device provides the option for a PCM output function. The PCM output is enabled by setting the A_CFG bits in the DEVCFG register to the appropriate state as described in Section 3.1.6.6. Selecting the PCM output enables the following functions: • The PCM pin is programmed as a digital output. Reference Section 2.3 for the pin electrical parameters. • The acceleration value output from the offset cancellation block is saturated to 9-bits and converted to an unsigned value. Note, the 9-bit unsigned acceleration value uses the full range of values (0 - 511). • The 9-bit acceleration value is input into a summer clocked at 8MHz. • The carry from the summer circuit is output to the PCM pin. A block diagram of the PCM output is shown in Figure 32. Exception conditions affect the PCM output as listed in Section 4.5. Output Scaling 9 OC[9:1] A CARRY ARM/PCM 9 Bit ADDER Sample updated every 8μS 9 B SUM D fCLK = 8 MHz D Q D Q Q DFF Q DFF Q DFF Q DFF Q CLK QFF D Q CLK QFF D Q CLK QFF CLK QFF CLK QFF CLK Q CLK Q CLK Q CLK Q 9 Figure 32. PCM Output Function Block Diagram 3.9 Serial Peripheral Interface The device includes a Serial Peripheral Interface (SPI) to provide access to the configuration registers and digital data. Reference Section 4 for details regarding the SPI protocol and available commands. MMA655x 40 Sensor Freescale Semiconductor, Inc. 3.10 Device Initialization Following power-up, under-voltage reset, or a SPI reset command sequence, the device proceeds through an internal initialization process as shown below. Figure 33 also shows the device performance for an example external system level initialization procedure. Internal Initialization OTP Copy to Offset Cancellation Offset Cancellation Offset Cancellation Offset Cancellation Mirror Registers Startup Phase 1 Startup Phase 2 Startup Phase 3 Normal Mode tOC_PHASE1 tOC_PHASE2 tOC_PHASE3 External Initialization Delay Read DEVSTAT Verify X-Axis to clear flags Self Test & Verify X-Axis Re-read DEVSTAT ARM Asserted Dly to verify Status Dly Offset Verify Y-Axis Initialize R/W Offset & ARM_Y Registers to DeAsserted Desired State Dly Verify X-Axis Offset & ARM DeAsserted Verify X-Axis Offset & ARM DeAsserted Re-Initialize R/W Registers Normal (if needed) Dly Mode Verify Y-Axis Verify Y-Axis and Self Test & Offset & ARM_Y Set ENDINIT ARM_Y Asserted DeAsserted tSTRISE tOP X_ST Assertion Dependent on Arming Mode X_ARM DeAssertion Dependent on Pulse Stretch and/or Arming Mode tST_OMB Y_ST tSTFALL Assertion Dependent on Arming Mode Y_ARM POR Ready for SPI Command ENDINIT Clear Internal Offset Error Corrected to ‘0’ Activate X-Axis Self Test DeActivate X-Axis Self Test Activate Y-Axis Self Test DeAssertion Dependent on Pulse Stretch and/or Arming Mode DeActivate Y-Axis Self Test Notes:1) X-Axis and Y-Axis Self Test can be enabled and evaluated simultaneously to reduce test time. For failure mode coverage of the arming pins and of potential common axis failures, Freescale recommends independent self test activation. 2) tSTRISE and tSTFALL are dependent on the selected LPF group delay. Figure 33. Initialization Process MMA655x Sensor Freescale Semiconductor, Inc. 41 3.11 Overload Response 3.11.1 Overload Performance The device is designed to operate within a specified range. Acceleration beyond that range (overload) impacts the output of the sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the device that is dependent upon the overload frequency and amplitude. The g-cell is overdamped, providing the optimal design for overload performance. However, the performance of the device during an overload condition is affected by many other parameters, including: • g-cell damping • Non-linearity • Clipping limits • Symmetry Figure 34 shows the g-cell, ADC and output clipping of the device over frequency. The relevant parameters are specified in Section 2.1, and Section 2.6. g-cellRolloff Acceleration (g) Region Clipped by Output LPFRolloff y ed b lipp C ion Reg g-ce ll Determined by g-cell roll-off and ADC clipping to C due y y AD rtion inearit b o t d s i L pe al D NonClip Sign y and ion f g o e r t R e ion Reg Asymm gg-cell_Clip gADC_Clip Determined by g-cell roll-off and full scale range gRange_Norm Region of Interest fLPF Region of No Signal Distortion Beyond Specification fg-Cell 5kHz 10kHz Frequency (kHz) Figure 34. Output Clipping vs. Frequency 3.11.2 Sigma Delta Over Range Response Over range conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits of the DSP. The ΣΔ converter can saturate at levels above those specified in Section 2.1 (GADC_CLIP). The DSP operates predictably under all cases of over range, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. MMA655x 42 Sensor Freescale Semiconductor, Inc. 4 SPI Communications Communication with the device is completed through synchronous serial transfers via SPI. The device is a slave device configured for CPOL = 0, CPHA = 0, MSB first. SPI transfers are completed through a sequence of two phases. During the first phase, the type of transfer and associated control information is transmitted from the SPI master to the device. Data from the device is transmitted during the second phase. Any activity on MOSI or SCLK is ignored when CS is negated. Consequently, intermediate transfers involving other SPI devices may occur between phase one and phase two. Reference Figure 35. SCLK CS MOSI Phase One: Command Phase Two: Response Phase One: Response -Previous Command MISO SCLK CS MOSI T1P1 T2P1 T3P1 T1P2 T2P2 T3P2 MISO Figure 35. SPI Transfer Detail MMA655x Sensor Freescale Semiconductor, Inc. 43 4.1 SPI Command Format Commands are transferred from the SPI master to the device. Valid commands fall into two categories: register operations, and acceleration data requests. Table 26. SPI Command Message Summary MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 AX A OC 0 0 0 0 0 0 0 0 1 SD ARM P Command Type Reference AX= Axis Selection 0 Acceleration Data 1 N/A A = Acceleration Data Request 0 Register Operation 1 Acceleration Data Request OC = Offset Cancelled Data Confirmation 0 Offset Cancelled Data Enabled 1 Raw Acceleration Data Enabled SD = Signed Data Confirmation Signed Data Enabled 0 Unsigned Data Enabled 1 ARM = ARM Function Status Confirmation Disabled / PCM Output Enabled 0 Arming Function Enabled 1 P = Odd Parity 0 AX A OC 0 0 0 0 0 0 0 0 0 SD ARM P Accel Data 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 OC, Signed Data, Disabled/PCM 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 OC, Signed Data, ARM Enabled 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 OC, Unsigned Data, Disabled/PCM 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 OC, Unsigned Data, ARM Enabled 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 Raw, Signed Data, Disabled/PCM 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 Raw, Signed Data, ARM Enabled 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 Raw, Unsigned Data, Disabled/PCM 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 Raw, Unsigned Data, ARM Enabled 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 Invalid Command 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 Invalid Command 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1 Invalid Command 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 Invalid Command 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 Invalid Command 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 Invalid Command 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 Invalid Command 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Invalid Command P AX A D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Command Type Reference A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 Register Read Section 4.4 D7 D6 D5 D4 D3 D2 D1 D0 Register Write Section 4.4 P 0 0 Register Address A4 P 1 A3 A2 A1 A0 0 Register Address Data to be Written to Register P = Odd Parity MMA655x 44 Sensor Freescale Semiconductor, Inc. 4.2 SPI Response Format Table 27. SPI Response Message Summary MSB LSB 15 14 13 12 11 10 9 D15 D14 AX P D11 D10 D1 D0 8 7 6 5 4 3 2 1 0 Response to Valid Acceleration Request CMD A AX Reference Acceleration Data D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D6 D5 D4 D3 D2 AX = Axis Requested 0 Acceleration Data Response 1 N/A P = Odd Parity S[1:0] = Device Status CMD Valid Accel Data Request A AX 1 0 D1 D0 Accel Data 0 0 In Initialization (ENDINIT = ‘0’) 0 1 Normal Data Request 1 0 ST Active 1 1 Internal Error Present / SPI Error AX P S1 S0 0 P 0 1 D11 D10 D9 D8 D7 Reference Acceleration Data 1 0 Accel Data 0 P 1 0 Self Test Active Acceleration Data 1 0 Accel Data 0 P 0 0 Acceleration Data, Initialization in Process (ENDINIT=’0’) 1 1 Accel Data 1 P 0 1 Invalid Accel Request 1 1 Accel Data 1 P 1 0 Invalid Accel Request 1 1 Accel Data 1 P 0 0 Invalid Accel Request Section 4.3 MSB LSB 15 14 13 12 11 10 9 8 D15 D14 AX P D11 D10 D9 D8 0 0 1 P 1 1 1 0 7 6 5 4 3 2 1 0 Response to Valid Register Access CMD Register Write A 0 AX 1 Reference D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Section 4.4.1 New Contents of Register D7 Register Read 0 0 0 1 0 P 1 1 1 D6 D5 D4 D3 D2 D1 D0 0 Section 4.4.2 Contents of Register MSB LSB 15 14 13 12 11 10 9 8 D15 D14 AX P D11 D10 D9 D8 0 0 AX P 1 1 0 0 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Error Responses CMD Invalid Accel Request A x AX Reference x Internal Error Present x x MISO Error x x Section 4.3 Section 4.5.5 Section 4.5.2 0 0 0 P 1 1 0 0 0 0 0 0 0 0 0 0 SPI Error x x Invalid Register Request Section 4.5.1 0 x 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 Section 4.4 Self Test Error 0 x 0 0 AX P 1 1 0 0 0 0 0 0 0 0 0 0 Section 4.5.5 MMA655x Sensor Freescale Semiconductor, Inc. 45 4.3 Acceleration Data Transfers 12-Bit Acceleration data requests are initiated when the Acceleration bit of the SPI command message (A) is set to a logic ‘1’, and bit D[3] of the SPI command message is set to a logic ‘1’. The Axis Selection bit (AX) selects the type of acceleration data requested, as shown in Table 28. Table 28. Acceleration Data Request Axis Selection Bit (AX) Data Type 0 Acceleration Data 1 Invalid Accel Request To verify that the device is configured as expected, each acceleration data request includes the configuration information which impacts the output data. The requested configuration is compared against the data programmed in the writable register block. Details are shown in Table 29. Table 29. Acceleration Data Request Configuration Information Programmable Option Command Message Bit Writable Register Information Raw or Offset Cancelled Data OC DEVCFG[7] (OC) Signed or Unsigned Data SD DEVCFG[4] (SD) Arming Function or PCM Output ARM DEVCFG[2] || DEVCFG[1] (A_CFG[2] || A_CFG[1]) If the data listed in Table 29 does not does not match, an Acceleration Data Request Mismatch failure is detected and no acceleration data is transmitted. Reference Section 4.5.3.1. Acceleration data request commands include a parity bit (P). Odd parity is employed. The number of logic ‘1’ bits in the acceleration data request command must be an odd number. Acceleration data is transmitted on the next SPI message if and only if all of the following conditions are met: • The DEVINIT bit in the DEVSTAT register is not set • The DEVRES bit in the DEVSTAT register is not set • The IDE bit in the DEVSTAT register is not set (Reference Section 4.5.5) • No SPI Error is detected (Reference Section 4.5.1) • No MISO Error is detected (Reference Section 4.5.2) • No Acceleration Data Request Mismatch failure is detected (Reference Section 4.5.3.1) • No Self Test Error is present (reference Section 4.5.5.2) • No Offset Monitor Error is present for the requested channel (reference Section 4.5.6) If the above conditions are met, the device responds with a “valid acceleration data request” response as shown in Table 27. Otherwise, the device responds as specified in Section 4.5. 4.4 Register Access Operations Two types of register access operations are supported; register write, and register read. Register access operations are initiated when the acceleration bit (A) of the command message is set to a logic ‘0’. The operation to be performed is indicated by the Access Selection bit (AX) of the command message. Access Selection Bit (AX) Operation 0 Register Read 1 Register Write Register Access operations include a parity bit (P). Odd parity is employed. The number of logic ‘1’ bits in the Register Access operation must be an odd number. MMA655x 46 Sensor Freescale Semiconductor, Inc. 4.4.1 Register Write Request During a register write request, bits 12 through 8 contain a five-bit address, and bits 7 through 0 contain the data value to be written. Writable registers are defined in Table 3. The response to a register write operation is shown in Table 27. The response is transmitted on the next SPI message if and only if all of the following conditions are met: • No SPI Error is detected (Reference Section 4.5.1) • No MISO Error is detected (Reference Section 4.5.2) • The ENDINIT bit is cleared (Reference Section 3.1.6.3) • This applies to all registers with the exception of the DEVCTL register (Only Bits 6 and 7 can be modified) • No Invalid Register Request is detected (Reference Section 4.5.3.2) If the above conditions are met, the device responds to the register write request as shown in Table 27. Otherwise, the device Responds as specified in Section 4.5. Register write operations do not occur internally until the transfer during which they are requested has been completed. In the event that a SPI Error is detected during a register write transfer, the write operation is not completed. 4.4.2 Register Read Request During a register read request, bits 12 through 8 contain the five-bit address for the register to be read. Bits 7 through 0 must be logic ‘0’. Readable registers are defined in Table 3. The response to a register read operation is shown in Table 27. The response is transmitted on the next SPI message if and only if all of the following conditions are met: • No SPI Error is detected (Reference Section 4.5.1) • No MISO Error is detected (Reference Section 4.5.2) • No Invalid Register Request is detected (Reference Section 4.5.3.2) If the above conditions are met, the device responds to the register read request as shown in Table 27. Otherwise, the device responds as specified in Section 4.5. 4.5 Exception Handling The following sections describe the conditions and the device response for each detectable exception. In the event that multiple exceptions exist, the exception response is determined by the priority listed in Table 30. Table 30. SPI Error Response Priority Effect on Data Error Priority Exception SPI Data Arming Output PCM Output 1 SPI Error Error Response No Update No Effect 2 SPI MISO Error Error Response No Update No Effect 3 Invalid Request Error Response No Update No Effect 4 DEVINIT Bit Set Error Response No Update Disabled 5 DEVRES Error Error Response No Update Disabled 6 CRC Error Error Response No Update No Effect 7 Self Test Error Error Response No Update No Effect 8 Offset Monitor Error Error Response No Update No Effect MMA655x Sensor Freescale Semiconductor, Inc. 47 4.5.1 SPI Error The following SPI conditions result in a SPI error: • SCLK is high when CS is asserted • The number of SCLK rising edges detected while CS is asserted is not equal to 16 • SCLK is high when CS is negated • Command message parity error (MOSI) • Bit 15 of Acceleration Data Request is not equal to ‘0’ • Bits 4 through 11 of an Acceleration Request are not equal to ‘0’ • Bits 3 of an Acceleration Request is not equal to ‘1’ • Bits 0 through 7 of a Register Read Request are not equal to ‘0’ The device responds to a SPI error with a “SPI Error” response as shown in Table 30. This applies to both acceleration data request SPI errors, and Register Access SPI errors. The arming function will not be updated if a SPI Error is detected. The PCM output is not affected by a SPI Error. 4.5.2 SPI Data Output Verification Error The device includes a function to verify the integrity of the data output to the MISO pin. The function reads the data transmitted on the MISO pin and compares it against the data intended to be transmitted. If any one bit doesn’t match, a SPI MISO Mismatch Fault is detected and the MISOERR flag in the DEVSTAT register is set. If a valid SPI acceleration request message is received during the SPI transfer with the MISO mismatch failure, the SPI acceleration request message is ignored and the device responds with a “MISO Error” response during the subsequent SPI message (reference Table 30). The Arming function is not updated if a MISO mismatch failure occurs. The PCM function is not affected by the MISO mismatch failure. If a valid SPI register write request message is received during the SPI transfer with the MISO mismatch failure, the register write is completed as requested, but the device responds with a “MISO Error” response as shown in Table 30, during the subsequent SPI message. If a valid SPI register read request message is received during the SPI transfer with the MISO mismatch failure, the register read is ignored and the device responds with a “MISO Error” response as shown in Table 30, during the subsequent SPI message. If the register read request is for the DEVSTAT register, the DEVSTAT register will not be cleared. In all cases, the MISOERR flag in the DEVSTAT register will remain set until a successful SPI Register Read Request of the DEVSTAT register is completed. SPI DATA OUT SHIFT REGISTER D DATA OUT BUFFER Q D Q MISO R D Q MISO ERR SCLK R Figure 36. SPI Data Output Verification 4.5.3 Invalid Requests 4.5.3.1 Invalid Acceleration Request The following conditions result in an “Invalid Acceleration Request” error: • The Axis Selection bit (AX) in the Command message is set • The SPI “Acceleration Data Request” Command data listed in Section 4.3, Table 28 does not match the internal register settings The device responds to an ”Invalid Acceleration Request” error with an “Invalid Accel Request” response as specified in Table 30 on the subsequent SPI message only. No internal fault is recorded. The arming function will not be updated if an “Acceleration Data Request Mismatch” Error is detected. The PCM output is not affected by the “Acceleration Data Request Mismatch” error. Register operations will be executed as specified in Section 4.4. MMA655x 48 Sensor Freescale Semiconductor, Inc. 4.5.3.2 Invalid Register Request The following conditions result in an “Invalid Register Request” error: • An attempt is made to write to an un-writable register (Writable registers are defined in Section 3.1, Table 3). Attempts to write to registers $07, $09, $0D, $0F, $11, & $13, $18, $19, $1A and $1B will result in an error. • An attempt is made to write to a register while the ENDINIT bit in the DEVCFG register is set • This applies to all registers with the exception of the DEVCTL register (Only Bits 6 and 7 can be modified) • An attempt is made to read an un-readable register (Readable registers are defined in Section 3.1, Table 3). Attempts to read registers $07, $09, $0D, $0F, $11, & $13, $18, $19, $1A and $1B will result in an error. The device responds to an Invalid Register Request” error with an “Invalid Register Request” response as shown in Table 30. 4.5.4 Device Reset Indications If the DEVINIT, or DEVRES bit is set in the DEVSTAT register as described in Section 3.1.11, the device will respond to acceleration data requests with an “Internal Error Present” response until the bits are cleared in the DEVSTAT register. The DEVINIT bit is cleared automatically when device initialization is complete (Reference tOP in Section 2.6). The DEVRES bit is cleared on a read of the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if the DEVINIT or DEVRES bit is set in the DEVSTAT register. The PCM output is disabled if the DEVINIT or DEVRES bit is set. 4.5.5 Internal Error The following errors will result in an internal error, and set the IDE bit in the DEVSTAT register: • OTP CRC Failure • Writable Register CRC Failure • Self Test Error • Invalid internal logic states 4.5.5.1 CRC Error If the IDE bit is set in the DEVSTAT register due to one or more of the following errors, the device will respond to acceleration data requests with an “Internal Error Present” response until the IDE bit is cleared in the DEVSTAT register. • An OTP Shadow Register CRC failure as described in Section 3.2 • A Writable Register CRC failure as described in Section 3.2 The arming function will not be updated on Acceleration Data Request commands if a CRC Error is detected. The PCM output is not affected by the CRC error. If the CRC error is in the writable register array, and the ENDINIT bit in the DEVCFG register has been set, the error can only be cleared by a device reset. The IDE bit will not be cleared on a read of the DEVSTAT register. If the CRC error is in the OTP shadow register array, the error cannot be cleared. Register operations will be executed as specified in Section 4.4. 4.5.5.2 Self Test Error If the IDE bit is set in the DEVSTAT register due to a Self Test activation failure, the device will respond to acceleration data requests with a “Self Test Error” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if a Self Test Error is detected. The PCM output is not affected by the Self Test Error. The IDE bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs, even if the internal failure is removed. If the internal error is still present when the DEVSTAT register is read, the IDE bit will remain set. Register operations will be executed as specified in Section 4.4. 4.5.6 Offset Monitor Error If an offset monitor error is present as described in Section 3.8.5, the OFFSET bit in the DEVSTAT register will be set. The device will respond to an acceleration request with an “Internal Error Present” response until the OFFSET bit is cleared in the DEVSTAT register. The arming function will not be updated. Once the error condition is removed, the OFFSET bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs. The PCM output is not affected by the offset monitor over range condition. Register operations will be executed as specified in Section 4.4. MMA655x Sensor Freescale Semiconductor, Inc. 49 4.6 Initialization SPI Response The first data transmitted by the device following reset is the SPI Error response shown in Table 30. This ensures that an unexpected reset will always be detectable. The device will respond to all acceleration data requests with the “Invalid Acceleration Data Request” response until the DEVRES bit in the DEVSTAT register is cleared via a read of the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands until the DEVRES bit in the DEVSTAT register is cleared. 4.7 Acceleration Data Representation Acceleration values are determined from the 12-bit digital output (DV) using the following equations: Acceleration = Sensitivity LSB × DV Acceleration = Sensitivity × ( DV – 2048 ) LSB For Signed Data For Unsigned Data The linear range of digital values for signed data is -1920 to +1920, and for unsigned data is 128 to 3968. Resulting ranges and some nominal acceleration values are shown in the following table. Table 31. Nominal Acceleration Data Values Nominal Acceleration Unsigned Digital Value Signed Digital Value 105g 120g Unused Unused 3969 - 4095 1921 - 2047 3968 1920 105.49 g 120.00 g 3967 1919 105.44 g 119.94 g • • • • • • • • • • • • • • • • • • 2050 2 0.1099 g 0.1250 g 2049 1 0.0545 g 0.0625 g 2048 0 0 g 0 g 2047 -1 -0.0545 g -0.0625 g 2046 -2 -0.1099 g -0.1250 g • • • • • • • • • • • • • • • • • • 129 -1919 -105.44 g -119.94 g 128 -1920 -105.49 g -120.00 g 1 - 127 -1921 - 2048 Unused Unused 0 0 Fault Fault MMA655x 50 Sensor Freescale Semiconductor, Inc. Figure 37 shows the how the possible output data codes are determined from the input data and the error sources. The relevant parameters are specified in Section 2.4. Figure 37. Acceleration Data Output Vs. Acceleration Input MMA655x Sensor Freescale Semiconductor, Inc. 51 5 Package 5.1 Case Outline Drawing Reference Freescale Case Outline Drawing # 98ASA00090D http://www.freescale.com/files/shared/doc/package_info/98ASA00090D.pdf 5.2 Recommended Footprint Reference Freescale Application Note AN3111, latest revision: http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf Table 1. Revision History Revision number Revision date 3 03/2012 Description of changes • Added SafeAssure logo, changed first paragraph and disclaimer to include trademark information. • Added devices to ordering table: MMA6555KW and MMA6556KW MMA655x 52 Sensor Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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For Literature Requests Only: Freescale Semiconductor Literature Distribution Center 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 [email protected] Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SafeAssure and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] © 2012 Freescale Semiconductor, Inc. All rights reserved. MMA655X Rev. 3 03/2012