AN-1277 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Utilizing the Cyclic Redundancy Check Block of the ADV7850 by Joe Triggs, Mike Corrigan, and Raymond Carter INTRODUCTION DDR2 SDRAM CVBS YC YPbPr AUDIO L/R 5 A CRC is a redundancy check invented by W. Wesley Patterson in 1961 (Peterson, W. W. and Brown, D. T. [January 1961]. "Cyclic Codes for Error Detection". Proceedings of the IRE, Volume 49, Issue: 1, Pages 228 to 235). A CRC detects errors in digital data and is used primarily in data transmission systems. For example, a 32-bit CRC transmits data over Ethernet. THE ADV7850 The ADV7850, the first complete audio/video front-end device developed by Analog Devices, targets the consumer and professional video markets. The device incorporates a fourinput HDMI receiver that supports video resolutions up to 4000p × 2000p at 30 Hz, a video and graphics digitizer capable of operating at up to 170 MHz, a high speed serial video output, a 3D comb video decoder, and an audio codec. In addition to being a comprehensive single-chip audio/video front end, the ADV7850 also incorporates a frame checker that employs a CRC. The frame checker, which does not require any external hardware to operate, is located at the input to the ADV7850 Tx (see Figure 1), allowing the entire video path for an HDMI input to be analyzed. This feature is not available for analog inputs due to least significant bit (LSB) errors introduced by the analog-to-digital converters (ADCs). ADC ADC ADC SDP CVBS 3D COMB SCART B YC SCART SCART R AUDIO L/R HS/VS/DE SCART G GRAPHICS RGB CYCLIC REDUNDANCY CHECKING CLK DATA CP YPbPr 525p/625p Pb/B 720p/1080i 1080p/ UXGA Pb/R RGB Y/G AUDIO L/R HDMI HS/VS/DE CLK DATA ADC I2S INTERFACE DAC HP L/R TMDS DDC HDMI 2 TMDS DDC HDMI 3 HDMI 4 ARC 4 5V HDMI + VGA 5 TMDS DDC TMDS DDC 36 4 DEEP COLOR HDMI Rx DSD/DST HBR MCLK FAST SWITCH HDCP KEYS AUDIO OUTPUT I2 S S/PDIF SCLK SPI INTERFACE MCLK SCLK S/PDIF ARC 5V EDID REG 5 ADV7850 EDID EPROM 11971-001 HDMI 1 OUTPUT MUX Many different CRC implementations exist, but the same basic premise persists; the data transmitter (Tx) calculates and appends a number of check bits (often referred to as a checksum) to the data before it is transmitted. This is implemented by dividing the data to be transmitted by a fixed binary number. The remainder of the division then forms the checksum. The receiver can determine if the check bits agree with the data using an inverse of the transmitter side calculation. If the checksum calculated on the receiver side does not match that calculated on the transmitter side, the receiver concludes that an error occurred in the data transmission and requests a retransmission of the data. CVBS ADC CRC HDMI Tx SCART RGB + CVBS VIDEO INPUT MUX CVBS × 2/YC AUDIO IN MUX The ADV7850, the first complete audio/video front-end device developed by Analog Devices, Inc., targets the professional and consumer video markets. The device incorporates a frame checker block that employs cyclic redundancy checking (CRC). This application note outlines the background of the frame checker function and details how it is utilized. Figure 1. ADV7850 Functional Block Diagram The frame checker in the ADV7850 is designed, utilizing the CRC-16-CCITT polynomial (x16 + x12 + x5 + 1), to analyze each of the data channels coming into the ADV7850 Tx (green = Channel 0, blue = Channel 1, and red = Channel 2) for a user configurable number of frames (up to 254). When the frame checker is enabled, it simultaneously computes a checksum for each channel (see Figure 2) over the specified number of frames (ranging from 300,000 pixels for 480p to 8,000,000 pixels for 4000p × 2000p). When the frame checker has completed its analysis, it reports a set of results for each of the channels (HDMI transfers data on the red, green, and blue channels). For a static input, performing multiple iterations of the CRC provides a consistent result. A single pixel difference between two frames (up to 16,000,000 pixels of data) yields different checksum results. Whether the pixel difference occurs due to noise on the source, noise induced intermittently in the transmission medium, or the incorrect configuration of the ADV7850, any failure is detected. Rev. 0 | Page 1 of 4 AN-1277 Application Note If the remainder stays the same for subsequent frames, the frames are the same and the system is operating at a combination of hardware and software settings that yield optimum system performance. If the checksums for subsequent frames do not match, the frames are inconsistent and the system must be optimized. AFTER n FRAMES, STORE COMPUTED CHECKSUM START NEW CRC COMPUTATION START CRC COMPUTATION VS 16 CRC GREEN CHANNEL 16 CRC BLUE CHANNEL 16 CRC COMPUTED CHECKSUM UTILIZING THE CRC COMPUTED CHECKSUM COMPUTED CHECKSUM To use the frame checker in the ADV7850 to perform a CRC test, these steps must be followed: 11971-002 RED CHANNEL 1. Figure 2. ADV7850 CRC THE CRC IN VIDEO APPLICATIONS 2. A video signal chain does not mimic the typical Ethernet style data transmitter and receiver pair. In a video signal chain, the link is unidirectional; therefore, it is not feasible for a video sink (for example, a television) to request a video source (for example, a Blu-ray™ player) to retransmit an incorrectly received data frame. To account for this asymmetry, a CRC operates in a slightly different manner. The obvious location in the video signal chain to perform the analysis is in the video receiver, given the limitation already outlined. The video receiver can apply a CRC to subsequent frames of incoming video data, with the only caveat being that the incoming video data must be static in its content. Examples of static content include a SMPTE video test pattern and a DVD player menu screen. The CRC is constructed using the known polynomial (for example, x16 + x12 + x5 + 1) as the divisor, the video data for the selected frame or number of frames as the numerator, and the remainder as the means of testing whether the video data has changed. The known polynomial never changes. If the incoming video does not change (as in a static pattern with no bit errors), the remainder is always constant. remainder ≡ x 16 + x 12 + x 5 + 1 Frame(s)ofVideoData 3. 4. 5. 6. 7. 8. Configure the number of frames requiring the CRC analysis (1 to 254) using the CRC_FRAME_NUMBER[7:0] control (see Table 1). Enable the CRC calculation using the CRC_ENABLE bit (see Table 2). Toggle the CRC block reset from high and back to low using the CRC_RESET bit (see Table 3). Depending on the size of the incoming video frame and the number of frames selected for analysis, the calculation takes some time to be completed. Wait a recommended minimum of 500 ms for the test to complete. Using the CRC_RESULT[15:0] (see Table 4) and CRC_READBACK_SEL[1:0] (see Table 5) controls, read back and log the CRC result for each of the HDMI channels: Channel 0, Channel 1, and Channel 2. Toggle the CRC block reset from high and back to low using the CRC_RESET bit (see Table 3). Wait a minimum of 500 ms for the test to complete. Using the CRC_RESULT[15:0] (see Table 4) and CRC_READBACK_SEL[1:0] (see Table 5) controls, read back and log the CRC result for each of the HDMI channels: Channel 0, Channel 1, and Channel 2. After two CRC checksums have been calculated and logged, a comparison can be performed. If the results are consistent, the static video pattern in both frames received by the ADV7850 CRC block are the same. If the results are not consistent, the static video pattern in both frames received by the ADV7850 CRC block differ and there may be a signal integrity or configuration issue. Rev. 0 | Page 2 of 4 Application Note AN-1277 CRC RELATED CONTROLS The following are the controls for the frame checker: CRC_RESET, IO Map, Address 0x2C[6] • • • • • This signal resets the CRC block. CRC_FRAME_NUMBER[7:0] CRC_ENABLE CRC_RESET CRC_RESULT [15:0] CRC_READBACK_SEL[1:0] Table 3. CRC_RESET Bit Descriptions CRC_RESET 0 1 CRC_FRAME_NUMBER[7:0], IO Map, Address 0x2D[7:0] This signal selects the number of video frames over which the CRC is calculated. Description No action (default) Reset the CRC block CRC_RESULT[15:0], IO Map, Address 0x2E[7:0]; Address 0x2F[7:0] This signal reads back the CRC calculation result. Table 1. CRC_FRAME_NUMBER[7:0] Bit Descriptions Table 4. CRC_RESULT[15:0] Bit Description CRC_FRAME_NUMBER[7:0] 0x01 to 0xFE CRC_RESULT[15:0] 0x0000 to 0xFFFF Description Number of frames for CRC calculation (0x07 = default) Description CRC calculation result (0x0000 = default) CRC_ENABLE, IO Map, Address 0x2C[7] CRC_READBACK_SEL[1:0], IO Map, Address 0x2C[5:4] This bit enables the CRC calculation. This signal changes the data source of the CRC calculation result readback. Table 2. CRC_ENABLE Bit Descriptions CRC_ENABLE 0 1 Description CRC calculation disabled (default) CRC calculation enabled Table 5. CRC_READBACK_SEL[1:0] Bit Descriptions CRC_READBACK_SEL[1:0] 00 01 10 Rev. 0 | Page 3 of 4 Description HDMI Channel 0 (default) HDMI Channel 1 HDMI Channel 2 AN-1277 Application Note NOTES ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN11971-0-2/14(0) Rev. 0 | Page 4 of 4