MTV20N50E Designer’s™ Data Sheet TMOS E−FET.™ Power Field Effect Transistor D3PAK for Surface Mount N−Channel Enhancement−Mode Silicon Gate The D3PAK package has the capability of housing the largest chip size of any standard, plastic, surface mount power semiconductor. This allows it to be used in applications that require surface mount components with higher power and lower RDS(on) capabilities. This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage−blocking capability without degrading performance over time. In addition, this advanced TMOS E−FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain−to−source diode with a fast recovery time. Designed for high voltage, high speed switching applications in surface mount PWM motor controls and both ac−dc and dc−dc power supplies. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Robust High Voltage Termination • Avalanche Energy Specified • Source−to−Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Short Heatsink Tab Manufactured − Not Sheared • Specifically Designed Leadframe for Maximum Power Dissipation • Available in 24 mm, 13−inch/500 Unit Tape & Reel, Add −RL Suffix to Part Number © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 1 1 http://onsemi.com TMOS POWER FET 20 AMPERES, 500 VOLTS RDS(on) = 0.240 W D3PAK Surface Mount CASE 433−01 Style 2 N−Channel ® D G S Publication Order Number: MTV20N50E/D MTV20N50E MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 500 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 500 Vdc VGS ±20 ±40 Vdc ID ID 20 14.1 60 Adc PD 250 2.0 3.57 Watts W/°C Watts TJ, Tstg −55 to 150 °C Rating Gate−to−Source Voltage — Continuous Gate−to−Source Voltage — Non−Repetitive (tp ≤ 10 ms) Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 μs) IDM Total Power Dissipation Derate above 25°C Total Power Dissipation @ TC = 25°C (1) Operating and Storage Temperature Range Apk Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 10 mH, RG = 25 Ω ) EAS Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Thermal Resistance — Junction to Ambient (1) RθJC RθJA RθJA 0.5 62.5 35 °C/W TL 260 °C Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds mJ 2000 (1) When surface mounted to an FR4 board using the minimum recommended pad size. Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. http://onsemi.com 2 MTV20N50E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 500 — — 583 — — — — — — 10 100 — — 100 2.0 — 3.0 7.0 4.0 — mV/°C — 0.23 0.24 Ohm — — 4.75 — 6.0 6.0 gFS 11 16.2 — mhos Ciss — 3880 6950 pF Coss — 452 920 Crss — 96 140 td(on) — 29 55 tr — 90 165 td(off) — 97 190 tf — 84 170 QT — 100 132 Q1 — 20 — Q2 — 44 — Q3 — 36 — — — 0.916 0.81 1.1 — trr — 431 — ta — 272 — tb — 159 — QRR — 6.67 — — 4.5 — — 13 — OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 μAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 500 Vdc, VGS = 0 Vdc) (VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C μAdc nAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 μAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 10 Adc) RDS(on) Drain−to−Source On−Voltage (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) Vdc Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 250 Vdc, ID = 20 Adc, VGS = 10 Vdc, RG = 9.1 Ω) Fall Time Gate Charge (See Figure 8) (VDS = 400 Vdc, ID = 20 Adc, VGS = 10 Vdc) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/μs) Reverse Recovery Stored Charge VSD Vdc ns μC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS (1) Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. http://onsemi.com 3 nH nH MTV20N50E TYPICAL ELECTRICAL CHARACTERISTICS 40 7V I D , DRAIN CURRENT (AMPS) 8V 32 6V 24 16 5V 8 0 RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) VGS = 10 V TJ = 25°C 0 2 4 6 8 10 12 14 16 18 24 TJ = −55°C 3 3.5 4 4.5 5 5.5 6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.5 TJ = 100°C 0.4 0.3 25°C 0.2 − 55°C 0.1 0 10 30 20 ID, DRAIN CURRENT (AMPS) 40 0.32 6.5 TJ = 25°C 0.30 0.28 0.26 VGS = 10 V 0.24 15 V 0.22 0.2 0 Figure 3. On−Resistance versus Drain Current and Temperature 10 20 30 ID, DRAIN CURRENT (AMPS) Figure 4. On−Resistance versus Drain Current and Gate Voltage 2.4 10000 VGS = 10 V ID = 10 A VGS = 0 V TJ = 125°C I DSS , LEAKAGE (nA) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 25°C 8 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS = 10 V 2.0 100°C 16 0 2.5 0.6 0 VDS w 10 V 32 20 RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) I D , DRAIN CURRENT (AMPS) 40 1.6 1.2 0.8 1000 100°C 100 10 25°C 0.4 0 −50 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 1 150 Figure 5. On−Resistance Variation with Temperature 0 50 100 150 200 250 300 350 400 450 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 4 5 MTV20N50E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Δt) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I G(AV) ) can be made from a rudimentary analysis of the drive circuit so that At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9000 10000 8000 TJ = 25°C VGS = 0 V TJ = 25°C Ciss 7000 C, CAPACITANCE (pF) C, CAPACITANCE (pF) VGS = 0 V VDS = 0 V 6000 5000 Ciss Crss 4000 3000 Ciss 1000 Coss 100 2000 1000 0 10 5 5 0 VGS Crss Coss Crss 10 15 20 10 25 10 100 10 VDS VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7a. Capacitance Variation Figure 7b. High Voltage Capacitance Variation http://onsemi.com 5 10 500 QT 400 VGS Q1 6 Q2 300 200 4 ID = 20 A TJ = 25°C 2 VDS Q3 0 0 10 20 100 30 40 50 60 70 QG, TOTAL GATE CHARGE (nC) 80 90 0 100 10 tf td(on) 1 10 RG, GATE RESISTANCE (OHMS) 1 Figure 9. Resistive Switching Time Variation versus Gate Resistance 7 20 IS = 20 A dlS/dt = 100 A/μs VDD = 50 V TJ = 25°C 6 5 I S , SOURCE CURRENT (AMPS) QRR, STORED CHARGE ( μ C) tr 100 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 4 3 2 1 0 td(off) VDD = 250 V ID = 20 A VGS = 10 V TJ = 25°C t, TIME (ns) 8 1000 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) MTV20N50E 0 2 4 6 8 10 12 14 16 18 16 TJ = 25°C VGS = 0 V 12 8 4 0 0.5 0.54 0.58 0.62 0.66 0.7 0.74 0.78 0.82 0.86 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 20 ID, DRAIN CURRENT (AMPS) 0 Figure 11. Diode Forward Voltage versus Curre Figure 10. Stored Charge SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (I DM ), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded and the transition time (tr,tf) do not exceed 10 μs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RθJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 6 MTV20N50E SAFE OPERATING AREA 2000 VGS = 20 V SINGLE PULSE TC = 25°C EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 1600 10 1200 100 μs 1 ms 10 ms 1.0 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 ID = 20 A 10 1.0 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 800 400 1000 0 25 Figure 12. Maximum Rated Forward Biased Safe Operating Area r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) 15 Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 P(pk) 0.01 SINGLE PULSE t1 t2 DUTY CYCLE, D = t1/t2 0.001 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 t, TIME (s) Figure 14. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 7 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RθJC(t) 1.0E+00 1.0E+01 MTV20N50E INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.165 4.191 0.118 3.0 0.100 2.54 0.063 1.6 0.190 4.826 0.243 6.172 inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RθJA versus drain pad area is shown in Figure 15. The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: RθJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (°C/W) 100 1.75 Watts Board Material = 0.0625″ G−10/FR−4, 2 oz Copper 80 PD = TJ(max) − TA RθJA TA = 25°C 60 The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device. For a D3PAK device, PD is calculated as follows. 3.0 Watts 40 20 0 PD = 150°C − 25°C = 2.0 Watts 62.5°C/W 5.0 Watts 2 4 6 A, AREA (SQUARE INCHES) 8 10 Figure 16. Thermal Resistance versus Drain Pad Area for the D3PAK Package (Typical) The 62.5°C/W for the D3PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad™. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. http://onsemi.com 8 MTV20N50E SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143, SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or “tombstoning” may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇÇ ÇÇÇÇÇÇ ÇÇ ÇÇÇ ÇÇ ÇÇÇ ÇÇÇ ÇÇÇÇÇÇ SOLDER PASTE OPENINGS STENCIL Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 9 MTV20N50E TYPICAL SOLDER HEATING PROFILE actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 −189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the STEP 1 PREHEAT ZONE 1 RAMP" 200°C STEP 2 STEP 3 VENT HEATING SOAK" ZONES 2 & 5 RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 STEP 5 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 SOAK" SPIKE" STEP 6 VENT 205° TO 219°C PEAK AT SOLDER JOINT 170°C 160°C 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 50°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 10 STEP 7 COOLING MTV20N50E PACKAGE DIMENSIONS CASE 433−01 ISSUE B −T− B S SEATING PLANE C 4 R E Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K L N P Q R S U V W X Y W Y V N 1 P 2 K 3 F U L A 2 PL J D 2 PL G 0.13 (0.005) X H M T INCHES MIN MAX 0.588 0.592 0.623 0.627 0.196 0.200 0.048 0.052 0.058 0.062 0.078 0.082 0.430 BSC 0.105 0.110 0.018 0.022 0.150 0.160 0.058 0.062 0.353 0.357 0.078 0.082 0.053 0.057 0.623 0.627 0.313 0.317 0.028 0.032 0.050 −−− 0.054 0.058 0.050 0.060 0.104 0.108 STYLE 2: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 14.94 15.04 15.82 15.93 4.98 5.08 1.22 1.32 1.47 1.57 1.98 2.08 1.092 BSC 2.67 2.79 0.46 0.56 3.81 4.06 1.47 1.57 8.97 9.07 1.98 2.08 1.35 1.45 15.82 15.93 7.95 8.05 0.71 0.81 1.27 −−− 1.37 1.47 1.27 1.52 2.64 2.74 GATE DRAIN SOURCE DRAIN E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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