Power MOSFET 2 Amps, 50 Volts

MMDF2N05ZR2
Preferred Device
Power MOSFET
2 Amps, 50 Volts
N−Channel SO−8, Dual
EZFETst are an advanced series of power MOSFETs which
contain monolithic back−to−back zener diodes. These zener diodes
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature ultra low RDS(on) and true
logic level performance. They are capable of withstanding high energy
in the avalanche and commutation modes and the drain−to−source
diode has a very low reverse recovery time. EZFET devices are
designed for use in low voltage, high speed switching applications
where power efficiency is important. Typical applications are dc−dc
converters, and power management in portable and battery powered
products such as computers, printers, cellular and cordless phones.
They can also be used for low voltage motor controls in mass storage
products such as disk drives and tape drives.
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2 AMPERES
50 VOLTS
RDS(on) = 300 mW
N−Channel
D
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery
•
•
•
•
•
•
G
Life
Logic Level Gate Drive − Can Be Driven by Logic ICs
Miniature SO−8 Surface Mount Package − Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO−8 Package Provided
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
50
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
VDGR
50
Vdc
Gate−to−Source Voltage − Continuous
VGS
± 15
Vdc
ID
ID
Adc
IDM
2.0
1.7
8.0
PD
2.0
Watts
TJ, Tstg
− 55 to
150
°C
RθJA
62.5
°C/W
TL
260
°C
Drain Current − Continuous @ TA = 25°C
Drain Current − Continuous @ TA = 70°C
Drain Current − Single Pulse (tp ≤ 10 μs)
Total Power Dissipation @ TA = 25°C
(Note 1.)
Operating and Storage Temperature Range
Thermal Resistance − Junction to Ambient
Maximum Temperature for Soldering
Purposes
MARKING
DIAGRAM
SO−8, Dual
CASE 751
STYLE 11
8
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
S
F2N05Z
LYWW
1
F2N05Z
L
Y
WW
= Device Code
= Location Code
= Year
= Work Week
Apk
PIN ASSIGNMENT
Source−1
1
8
Drain−1
Gate−1
2
7
Drain−1
Source−2
3
6
Drain−2
Gate−2
4
5
Drain−2
Top View
1. When mounted on G10/FR−4 glass epoxy board using minimum
recommended footprint.
ORDERING INFORMATION
Device
Package
MMDF2N05ZR2
SO−8
Shipping
2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 3
1
Publication Order Number:
MMDF2N05ZR2/D
MMDF2N05ZR2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
50
−
56
55
−
−
−
−
−
−
2.0
25
−
0.14
0.5
2.0
−
3.0
−5.0
4.0
−
−
−
200
350
300
500
−
2.0
−
Ciss
−
104
−
Coss
−
58
−
Crss
−
16
−
td(on)
−
24
48
tr
−
46
92
td(off)
−
130
260
tf
−
71
142
QT
−
3.3
4.6
Q1
−
0.7
−
Q2
−
1.3
−
Q3
−
1.4
−
−
0.82
1.4
trr
−
66
−
ta
−
23
−
tb
−
43
−
QRR
−
0.08
−
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (Note 3)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 15 Vdc, VGS = 0 Vdc)
(VDS = 15 Vdc, VGS = 0 Vdc, TJ = 55°C)
IDSS
Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0)
IGSS
Vdc
mV/°C
μAdc
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
(Cpk ≥ 2.0) (Note 3)
Static Drain−to−Source On−Resistance
(VGS = 10 Vdc, ID = 1.5 Adc)
(VGS = 5.0 Vdc, ID = 0.6 Adc)
(Cpk ≥ 2.0) (Note 3)
Forward Transconductance
(VDS = 15 Vdc, ID = 2.5 Adc)
VGS(th)
RDS(on)
gFS
Vdc
mV/°C
mΩ
mMhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 15 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 30 Vdc, ID = 0.6 Adc,
VGS = 10 Vdc,
RG = 25 Ω)
Fall Time
Gate Charge
(see figure 8)
(VDS = 25 Vdc, ID = 1.3 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs)
Reverse Recovery Storage Charge
1. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
3. Reflects typical values.
Max limit − Typ
Cpk =
3 x SIGMA
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2
VSD
Vdc
ns
μC
MMDF2N05ZR2
TYPICAL ELECTRICAL CHARACTERISTICS
4
VGS = 10 V
7V
6.5 V
I D , DRAIN CURRENT (AMPS)
3.5 TJ = 25°C
3.5
3
5.5 V
3
2.5
2.5
2
5.0 V
2
100°C
1.5
1.5
1
4.3 V
0.5
0
VDS ≥ 10 V
TJ = 25°C
6.0 V
I D , DRAIN CURRENT (AMPS)
4
0.2
0.6 0.8
0.4
1
1.2
1.4 1.6
1.8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ = −55°C
0.5
3.9 V
0
25°C
1
0
2.5
2
3
1.2
ID = 1.5 A
TJ = 25°C
1.0
0.8
0.6
0.4
0.2
0
5
8.5
6.5
7
7.5
8
9
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
5.5
6
9.5
10
0.65
TJ = 25°C
0.45
VGS = 5.0 V
0.25
10 V
0.05
0
1
1.5
2.5
2
3
3.5
4
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100
2.0
VGS = 10 V
ID = 1 A
VGS = 0 V
1.5
I DSS , LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
0.5
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
1.0
0.5
0
−50
6.5
Figure 2. Transfer Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 1. On−Region Characteristics
3.5
4
5
4.5
5.5
6
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
−25
0
25
50
75
100
125
10
100°C
25°C
1
0.1
0.01
150
TJ = 125°C
0
5
10
15
20
25
30
35
40
45
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation
with Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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50
MMDF2N05ZR2
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
250
C, CAPACITANCE (pF)
200
VDS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
150
Ciss
100
Crss
Coss
50
Crss
0
10
5
0
VGS
5
10
15
20
VDS
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
25
30
40
QT
VGS
9
30
6
20
Q1
Q2
10
3
VDS
Q3
0
0
0.5
ID = 1.3 A
TJ = 25°C
1
1.5
2
2.5
3
Qg, TOTAL GATE CHARGE (nC)
4
3.5
0
1000
VGS = 10 V
TJ = 25°C
td(off)
t, TIME (ns)
12
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MMDF2N05ZR2
100
tf
tr
td(on)
10
1
10
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
2
VGS = 0 V
TJ = 25°C
IS , SOURCE CURRENT (AMPS)
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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MMDF2N05ZR2
di/dt = 300 A/μs
I S , SOURCE CURRENT
Standard Cell Density
trr
High Cell Density
trr
tb
ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
I D , DRAIN CURRENT (AMPS)
100
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
1 ms
10 ms
1
dc
0.1
0.01
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
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100
MMDF2N05ZR2
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1
D = 0.5
0.1
0.2
0.1
0.05
0.02
0.01
Dual SO−8 Thermal RC Network
Chip
0.0106 Ω
0.0431 Ω
0.1643 Ω
0.0253 F
0.1406 F
0.5064 F
0.3507 Ω
0.4302 Ω
0.01
2.9468 F
177.14 F
SINGLE PULSE
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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7
1.0E+02
Ambient
1.0E+03
MMDF2N05ZR2
INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self−align when
subjected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SO−8 POWER DISSIPATION
The power dissipation of the SO−8 is a function of the
input pad size. This can vary from the minimum pad size
for soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient; and the operating
temperature, TA. Using the values provided on the data
sheet for the SO−8 package, PD can be calculated as
follows:
PD =
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 2.0 Watts.
PD = 150°C − 25°C = 2.0 Watts
62.5°C/W
The 62.5°C/W for the SO−8 package assumes the
recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.0 Watts using the
footprint shown. Another alternative would be to use a
ceramic substrate or an aluminum core board such as
Thermal Cladt. Using board material such as Thermal
Clad, the power dissipation can be doubled using the same
footprint.
TJ(max) − TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
SOLDERING PRECAUTIONS
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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MMDF2N05ZR2
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 12 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177−189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
“SPIKE”
205° TO 219°C
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 15. Typical Solder Heating Profile
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MMDF2N05ZR2
PACKAGE DIMENSIONS
SO−8
CASE 751−07
ISSUE V
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
XXXXXX
ALYW
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
STYLE 11:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0_
8_
0.010
0.020
0.228
0.244
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
EZFET is a trademark of Semiconductor Components Industries, LLC (SCILLC).
Thermal Clad is a registered trademark of the Bergquist Company.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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