SC2440A Dual 30V Step-Down Switching Regulator with 2A Switches POWER MANAGEMENT Features Description Wide Input Voltage Range: 2.8V to 30V Two Integrated 2A Switches Up to 2.5MHz per Channel Programmable Constant Switching Frequency Out of Phase Switching Reduces Input Ripple Both Switching Regulators share a single Input Filtering Capacitor, Reducing Cost External Synchronization Cycle-by-Cycle Current-limiting Independent Soft-Start/Enable Pins Independent Hiccup Overload Protection Power Good Indicators Ease Output Sequencing Low Shutdown Current Thermally Enhanced 16-pin TSSOP Lead Free Package Fully WEEE and RoHS Compliant Applications XDSL and Cable Modems Point of Load Applications Security Cameras The SC2440A is a constant frequency dual current-mode step-down regulator with integrated 30V switches. It produces two independent outputs from a common input power supply. Channel switching frequency can be programmed up to 2.5MHz. The two regulators switch in opposite phase, reducing input ripple current. As a result, a smaller input filtering capacitor can be used. Current-mode PWM control simplifies loop compensation. Cycle-by-cycle current limiting and hiccup overload protection reduce power dissipation during overload. The SC2440A is output short-circuit robust. Separate soft-start/enable pins allow independent control of each channel. Output power good indicators ease output sequencing. The SC2440A can be synchronized to an external clock. This eases noise filtering by eliminating beat frequencies and confining switching noise to a narrow band. Typical Application Circuit R6 100k R5 9.31k C5 FB1 PGOOD1 COMP1 BST1 SS1 SW 1 D3 680pF C7 C2 0.1µF R9 C 10 13.3k V IN 12V ± 10% C 15 R7 14.0k C8 O UT 1 D1 U P S 120 C1 10µF 3.3V /1.8A R1 23.3k R2 10k IN ROSC S C 2440A 4.7µF SS2 22nF L1 3.3µH 22nF SYNC 1N 4148 D2 U P S 120 COMP2 L2 SW 2 470pF O UT 2 4.4µH R3 40.2k C4 0.1µF D 4 GND FB2 C3 10µF BST2 1N 4148 PGOOD2 R8 5V /1.8A R4 10k 100k L 1 : S u m id a C R 4 3 L 2 : F alco D 0 4 0 1 2 C 1 , C 3 : M u ra ta G R M 2 1 B R 6 0 J1 0 6 K C 1 5 : M u ra ta G R M 2 1 B R 6 1 E 4 7 5 K Figure 1. 1.3MHz 12V to 5V and 3.3V Step-down Converter C6 C9 10pF Revision 2.4 C 16 0.1µF 10pF © 2014 Semtech Corporation F re e -ru n n in g fre q u e n cy = 9 5 7 kH z (R e v1 trim m e d p a rt, R 9 = 1 8 .7 k) SC2440A Pin Configuration Ordering Information Top View BST1 1 16 F B 1 SW 1 2 15 C O M P 1 IN 3 14 P G O O D 1 SYNC 4 17 13 S S 1 ROSC 5 GND 12 S S 2 IN 6 11 P G O O D 2 10 C O M P 2 SW 2 7 9 FB2 BST2 8 θJA = 40°C/W 16 Pin TSSOP-EDP Marking Information yyww - Date Code xxxxx xxxxx - Semtech Lot Number Device Package SC2440ATETRT(1) (2) TSSOP-16 EDP SC2440AEVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 2,500 devices. (2) Available in lead-free package only. Device is WEEE and RoHS compliant. SC2440A Absolute Maximum Ratings Recommended Operating Conditions IN ………………………………………………… -0.3V to 32V Junction Temperature Range ………………… -40°C to +105°C SW1/2 ……………………………………………… -0.6V to VIN VIN ………………………………………………… 2.8V to 30V BST1/2 …………………………………………… -0.3V to 42V BST1/2 Voltage Above SW1/2 ……………………… -4V to 36V SS1/2, COMP1/2, ROSC …………………………… -0.3V to 3V Thermal Information SYNC …………………………………………………-0.3V to 6V Thermal Resistance, Junction to Ambient(2) ………… 45°C/W SYNC Pin Current ……………………………… -1mA to 5mA Maximum Junction Temperature …………………… +150 °C FB1/2 ……………………………………………… -0.3V to 7V Storage Temperature Range PGOOD1/2 ………………………………………… -0.3V to VIN Peak IR Reflow Temperature (10s to 30s) ……………… -65°C to +150°C …………… +260°C ESD Protection Level ………………………………… 2.5kV (1) Exceeding the above specifications may result in permanent damage to the device or the device may malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless otherwise noted: VIN = 5V, VBST1/2 = 8V, VSYNC = 0, ROSC = 12.1kΩ, TJ = -40°C to 105°C. Typical values are at TJ = 25°C. Parameter Conditions Min Typ Max Units 30 V 2.8 V Input Supply Maximum Operating VIN VIN Start Voltage VIN Rising 2.6 VIN Start Hysteresis 2.7 90 mV Shutdown Supply Current VSS1 = VSS2 = 0, PGOOD1,2 Open 27 40 µA Quiescent Supply Current Not Switching, PGOOD1,2 Open 4.1 5.5 mA 1.000 1.020 V Control Loops Feedback Voltage Feedback Voltage Line Regulation 0.980 VIN = 3V to 30V 0.006 %/V FB Pin Input Bias Current -100 -200 nA Error Amplifier Transconductance 280 µW-1 Error Amplifier Open-loop Gain 53 dB COMP Sourcing Current VFB = 0.8V, VCOMP = 1.2V 16 µA COMP Sinking Current VFB = 1.2V, VCOMP = 1.2V 18 µA VFB = 0.9V 1.7 V 7.5 A/V COMP Maximum Voltage COMP to Switch Current Gain COMP Switching Threshold 0.7 1.0 1.3 V SC2440A Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units 1.2 1.4 1.6 MHz 90 140 ns Oscillator and Synchronization Channel Free-running Frequency Minimum Switch Off-time SYNC Input High Voltage 2 V SYNC Input Low Voltage SYNC Pin Input Current VSYNC = 2V 0.8 V 60 75 µA 2.6 3.8 A 300 460 mV 10 µA Power Switch Switch Current Limit(1) Switch Saturation Voltage 2.0 ISW1 = -2A Switch Leakage Current Switch Minimum Bootstrap Voltage BST Pin Current ISW1 = -2A 1.8 2.4 V ISW1 = -0.5A 20 30 mA ISW1 = -2A 50 80 mA 0.25 0.35 V Soft-start and Hiccup Overload Protection Shutdown SS Threshold Soft-start Charging Current Soft-start Discharging Current VSS1 = VSS2 0.15 VSS = 0 VSS Rising and VSS = 1.5V 1.8 1.0 1.8 µA 2.6 µA In Overload Shutdown, VSS Falling and VSS = 1.5V 0.8 µA VFB = 0, VCOMP = 1.3V, VSS Rising 1.21 V Hiccup Arming SS Voltage VSS Rising 2.1 V Hiccup Retry SS Voltage VSS Falling FB Overload Threshold VSS = 2.3V, VFB Falling SS Switching Threshold 0.7 1.0 1.3 0.72 V V Output Power Good Indicators PGOOD Threshold Below FB VFB Rising PGOOD Output Low Voltage PGOOD Pin Leakage Current 80 100 120 mV VFB = 0.8V, IPGOOD = 250µA 0.2 0.4 V VPGOOD = 5V 0.1 1 µA TJ Rising 160 °C 18 °C Thermal Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis Notes: (1) Switch current limits do not vary with duty cycle. SC2440A Pin Descriptions Pin # Pin Name Pin Function 1, 8 BST1, BST2 Supply pins to the power transistor drivers. Tie to external diode-capacitor bootstrap circuits to generate drive voltages higher than VIN in order to fully enhance the internal power switches. 2, 7 SW1, SW2 Emitters of the internal power NPN transistors. Each SW pin is connected to the corresponding inductor, freewheeling diode and bootstrap capacitor. 3, 6 IN Power transistor collectors and the power supply to the internal control circuitry. Pins 3 and 6 are internally connected. These pins are to be tied to the same power supply and must be closely bypassed. 4 SYNC Driving the SYNC pin with a TTL-compatible clock synchronizes the SC2440A. If the SC2440A is to be synchronized to a channel frequency fSYNC, then program the channel free-running frequency to approximately fSYNC using the ROSC resistor. The applied clock frequency can be fSYNC or 2fSYNC. See Applications Information for details. Tie this pin to ground if not used. 5 ROSC An external resistor from this pin to ground sets the channel free-running frequency. 9, 16 FB2, FB1 Inverting inputs of the error amplifiers. Each FB pin is tied to a resistor divider between the corresponding output and ground. The resistor divider sets the channel output voltage. 10, 15 COMP2, COMP1 Outputs of the error amplifiers. The voltages at these pins control the peak switch currents. RC networks at these pins compensate the control loops. Pulling either pin below 0.8V stops the corresponding regulator. 11, 14 PGOOD2, PGOOD1 Open-collector outputs of power good comparators. Tie to external pull-up resistors from the input or the output of the converter. The PGOOD outputs become valid as soon as VIN rises above 0.9V during power-up. The PGOOD pin is actively pulled low until the corresponding FB pin rises to within 10% of the final regulation voltage. 12, 13 SS2, SS1 A capacitor from either SS pin to ground sets the soft-start interval and provides an overload hiccup function for that channel. Pulling either SS pin below 0.8V with an open-collector or an open-drain transistor shuts off the corresponding regulator. To completely shut off the SC2440A to low current state, pull both SS pins below 0.15V. 17 (Exposed Pad) GND The exposed pad at the bottom of the package is the analog ground of the SC2440A. It also serves as a thermal contact to the circuit board. It is to be connected to the ground plane of the PC board using multiple vias. SC2440A Block Diagram IN ROSC 5 SYNC 2f OSCILLATOR 4 3 SLOPE COMP2 FREQUENCY DIVIDER & SLOPE COMP + S + + ISEN - SLOPE COMP1 PGOOD1 - OC CLK1, f CLK2, f 14 ILIM + - 6.9mW 18mV + OUTPUT READY COMP1 100mV BST1 PWM 1 15 FB1 + PWM - + EA + 16 V1 A1 + - 1.33V DZ S POWER TRANSISTOR Q1 Q R IZ 2 SW1 R R IZ > 0? SS1 13 1V 0.73V & 1.26V SS2 12 REFERENCE & THERMAL SHUTDOWN ENABLE SOFT-START AND OVERLOAD HICCUP CONTROL SHDN VREG INTERNAL REGULATOR Figure 2. SC2440A Block Diagram (Channel 1 Shown) GND 17 SC2440A Block Diagram X3 1.3V FB 0.72V + - + - R X4 _ Q COMP Clamped AND OC=“1” S COMP PULLED LOW X5 VREG S IC 1.8mA Q X1 SS ARM R X2 1V/2.1V DISCHARGE VREG ID 2.7mA Figure 3. Details of the Soft-start and Overload Hiccup Control Circuit SC2440A Typical Characteristics SC2440A Typical Characteristics (Continued) SC2440A General Description The SC2440A is a dual constant frequency peak currentmode step-down switching regulator with integrated 2A high-side transistors. Both regulators share the same voltage reference, oscillator and synchronizing circuit. Turn-on of the power transistors is phase-shifted by 180° for input ripple reduction. The two regulators are otherwise identical, independent and are capable of producing two independent outputs from a common power supply. The free-running frequency of the master oscillator is programmed with an external resistor from the ROSC pin to ground, giving the user the flexibility of setting the switching frequency according to the input to output voltage conversion ratio. The master clock is fed into a frequency divider for phase clocks generation. As a result, each regulator runs at half the master clock rate (Figure 2). The SC2440A can also be synchronized to an external clock. The SC2440A uses peak current-mode control. The inner current loop of current-mode control reduces the double reactive poles of the output LC filter to a single real pole, easing loop compensation. A simple Type-2 compensation network ensures stability with fast transient response. The switch collector current of each channel is sensed with an integrated sense resistor. The sensed current is summed with a slope-compensating ramp before it is compared with the error amplifier output. The PWM comparator trip point determines the switch turn-on pulse width (Figure 2). ILIM is a cycle-by-cycle current-limit comparator that turns off the power switch whenever the sensed-signal exceeds 18mV. Driving the base of the power transistor above the input power supply rail minimizes the power transistor turn-on voltage and maximizes efficiency. An external bootstrap circuit (formed by the capacitor C2 and the diode D3 in Figure 1) generates a voltage higher than VIN at the BST1 pin. The bootstrapped voltage generated becomes the supply voltage for the power transistor driver. The SS pin is a multiple-function pin. An external capacitor connected from the SS pin to ground together with the internal charging and discharging circuits set the soft-start and overload shutoff times for the regulator (Figure 3). The SS pin can also be used to shut off the corresponding 10 regulator. When either SS pin is pulled below 0.8V, the corresponding regulator is turned off. If both SS pins are pulled below 0.15V, then the SC2440A will undergo overall shutdown, drawing less than 40μA from a 5V input. When either SS pin is released, the corresponding soft-start capacitor is charged with a 1.8μA current source (not shown in Figure 3). When either SS voltage exceeds 0.35V, the internal regulator in the SC2440A turns on. VIN quiescent current increases to 4.1mA. An internal fast charge circuit (not shown) quickly charges the soft-start capacitor to 1V. At this juncture, the fast charge circuit turns off and the 1.8μA current source slowly charges the soft-start capacitor. The error amplifier EA in Figure 2 has two non-inverting inputs. The non-inverting input with the lower voltage predominates. One of the non-inverting inputs is biased to a precision 1V reference and the other non-inverting input is tied to the output of the amplifier A1. Amplifier A1 produces an output V1 = 2(VSS – 1.33) if VSS > 1.33V. For VSS < 1.33V, V1 = 0. During start up, COMP is pulled low initially. When VSS exceeds 1.21V, COMP is released. However the effective non-inverting input of EA remains zero. As a result, the regulator output stays at zero as the soft-start capacitor is charged from 1.21V to 1.33V. The regulator output starts to ramp when VSS exceeds 1.33V and VCOMP rises above 1.1V. If the soft-start interval is made sufficiently long, then the FB voltage (hence the output voltage) will track V1 during start up. VSS must be at least 1.88V to ensure regulation. Zener diode DZ clamps COMP to a voltage higher than that corresponding to the cycle-by-cycle switch current limit. Current flow in DZ indicates clamping of COMP. As the load draws more current from the regulator, the current-limit comparator ILIM (Figure 2) limits the switch current on a cycle-by-cycle basis. If the over-current condition persists, then the COMP voltage will continuously increase to its clamp level, eventually setting the overload shutdown latch X3. The COMP pin is immediately pulled low, turning off the corresponding regulator (Figure 3). Overload shutdown can occur during soft-start. However the SS capacitor is always charged to the upper trip voltage of the Schmitt trigger X1 before it can be discharged. The reset input of the discharge latch X2 stays high before the soft-start capacitor is charged to 2.1V. Once the softstart capacitor is charged above 2.1V, X1 output goes high and the reset input of the SS discharge latch X2 goes low, SC2440A General Description (Continued) enabling SS discharge. The net soft-start capacitor discharging current is ID - IC ≈ 1.2µA. The switching regulator remains off until the soft-start capacitor is discharged below 1V. At this moment, the SS discharge latch is reset. The soft-start capacitor is recharged and the converter again undergoes soft-start, delaying converter restart until the hiccup cycle completes, reducing power dissipation in overload. The regulator will go through soft-start, overload shutdown and restart until it is no longer overloaded. Comparator X4 resets latch X3 during initial start-up or before recovering from overload shutdown. Comparator X5 monitors the output voltage after hiccup is armed. If excessive overload causes the converter output voltage to fall below 72% of its set point, then the converter will be shut off immediately, without waiting for VCOMP to rise to its clamp level. The converter restarts after timing out. The output power good comparator indicates that the channel output voltage has risen to within 10% of its set value. Each regulator of the SC2440A has its own output good comparator. The open collector output of the voltage ready comparator will be actively pulled low if the corresponding feedback voltage is below 0.9V. 11 SC2440A Applications Information Setting the Output Voltage the 1MHz fundamental. The regulator output voltage is set with an external resistor divider (Figure 4) with its center tap tied to the FB pin. Switching frequency is also limited by the minimum controllable on time when stepping down from high VIN to low VOUT. This will be described in next section. 5 5 9287 (1) Table 1. Programming the Channel Frequency VO U T SC2440A R1 < 200nA FB R2 Figure 4. R1 and R2 Set the Output Voltage The percentage error due the input bias current of the error amplifier is '9287 Q$ 5°«5 9287 9 Using a smaller R2 (preferably < 20kW) makes the effect of the amplifier input bias current insignificant compared to the VOUT tolerance resulting from the use of 1% resistors. Setting the Operating Frequency The master oscillator in the SC2440A feeds a toggle flipflop which in turn generates the individual channel clocks CLK1 and CLK2 (Figure 2). The phase clocks run at half the master oscillator frequency and are shifted in phase by 180o. The external resistor from the ROSC pin to ground programs the channel free-running frequency fFREE-RUN. Table 1 lists the suggested programming resistors for various channel frequencies. Before choosing the operating frequency, tradeoffs among efficiency, operating duty cycle, component size and EMI must be considered. High frequency operation reduces the size of passive components but switching losses are higher. Lowering the switching frequency improves efficiency, however the required inductor and capacitor are larger. It is also worth noting that a dual DC-DC converter with each channel switching at 1MHz will produce a switching noise spectrum at integer multiples of 12 Channel fFREE-RUN (kHz) ROSC Resistor (kW) 200 118 300 78.7 400 57.6 500 45.3 600 35.7 700 30.9 800 24.9 900 22.1 1000 19.6 1100 17.4 1200 15.4 1300 13.3 1400 12.1 1500 11.0 1600 10.0 1700 9.09 1800 8.25 1900 7.50 2000 6.65 2100 6.19 2200 5.62 2300 4.99 2400 4.53 2500 4.02 Minimum On Time Considerations The switching duty cycle of a DC-DC converter is the ratio of the switch on time to the switching period. For a non-synchronous step-down regulator, the duty cycle D in continuous-conduction mode (CCM) is given by: SC2440A Applications Information (Continued) ' 9287 9' 9,1 9' 9&(6$7 (2) where VCESAT is the switch saturation voltage and VD is voltage drop across the freewheeling diode. For a given output voltage, the switch on time becomes shorter as VIN increases. In peak current-mode control, the PWM modulating ramp is the sensed current ramp of the power switch. This current ramp is absent unless the switch is turned on. The switch is turned off when this ramp intersects the error amplifier output. The propagation delay time required to immediately turn off the switch after it is turned on is the minimum controllable switch on time [tON(MIN)]. The typical minimum on time is plotted against temperature in “Typical Characteristics”. tON(MIN) increases with temperature and is also load-dependent. The power switch in the SC2440A is either not turned on at all or ' for at least tON(MIN). If the required on time (= ) is shorter I than the minimum on time, the regulator will either jitter or skip cycles. Example: Determine the maximum switching frequency of a dual 12V to 1.2V and 3.3V regulator. The regulator needs to work up to 85°C. We only need to consider the 1.2V output because this channel is switching at the lower duty cycle. Assuming that VD = 0.45V, VCESAT = 0.3V and VIN = 13.2V (10% high line), the duty ratio D1 of the 1.2V can be calculated using equation (2). ' To allow for transient headroom and frequency tolerances, the minimum operating switch on time should be at least 237ns (1.3 times the 0.5A minimum on time at 85°C). The maximum operating frequency of the 12V to 1.2V and ' | N+] . 3.3V converter is therefore QV Minimum Off Time Limitation The PWM latch in Figure 2 is reset every period by the clock. The clock also turns off the power transistor to refresh the bootstrap capacitor. This minimum off time limits the at- tainable duty cycle of the regulator at a given switching frequency. Measurement shows that the power transistor is turned off for at least 140ns every switching period to reset the latch and to refresh the bootstrap capacitor. For a step-down converter, duty cycle increases with increas9 ing 287 ratio. If the required duty cycle is higher than the 9,1 attainable maximum, then the output voltage will not be able to reach its set value regardless of the load. Example: Determine the maximum operating frequency of a dual 3.3V to 1.8V and 2.5V switching regulator using the SC2440A. The 2.5V channel is switching at the higher duty cycle. Assuming that VD = 0.45V, VCESAT = 0.3V and VIN = 2.97V (10% low line), the duty ratio D2 of the 2.5V converter can be calculated using equation (2). ' The maximum operating frequency of the 1.8V and the ' N+] . 2.5V converter is therefore QV Transient headroom requires that channel frequency be set below 380kHz. External Synchronization The SC2440A can be synchronized by feeding an external clock to the SYNC pin. The SYNC input buffer is positiveedge triggered and TTL-compatible (VIL < 0.8V and VIH > 2V). The synchronizing frequency can be either 1X or 2X the desired channel switching frequency. 1X Frequency Synchronization If the channels are to be synchronized to run at an external clock frequency fSYNC, then set the free-running channel frequency between 0.95fSYNC and fSYNC to allow for free-running frequency tolerance. The leading edge of the external clock will lock onto one of the channels and turn on its power transistor. With 1X frequency synchronization, the phase difference between the two channels is not exactly 180o. However, setting the nominal free-running channel frequency near fSYNC will minimize the phase deviation from 180o. 13 SC2440A Applications Information (Continued) 2X Frequency Synchronization An external clock with frequency fSYNC ranging from 1.8X to 2.7X fFREE-RUN will synchronize the individual channels I6<1& with 180o out of phase switching. The nominal to free-running channel frequency should be programmed to between 0.475fSYNC and 0.5fSYNC when synchronizing using a 2X frequency clock. Example: Detemine the value of the frequency setting resistor if the SC2440A is to be synchronized to run at 1.03MHz per channel. The required external clock is a TTL-compatible pulse train running at either 1.03MHz (for 1X frequency synchronization) or 2.06MHz (for 2X frequency synchronization). Using the guideline given above, set the nominal freerunning channel frequency to 1MHz (0.97 × 1.03MHz for 1X frequency synchronization or 0.485 × 2.06MHz for 2X frequency synchronization). From Table 1, a 19.6kΩ resistor sets the channel free-running frequency to 1MHz. Inductor Selection and Output Current The inductor ripple current ΔIL for a non-synchronous step-down converter in continuous-conduction mode is ',/ 9287 9' ' I/ (3) where f is the switching frequency and L is the inductance. In current-mode control, the slope of the modulating (sensed switch current) ramp should be steep enough to lessen jitter tendency but not so steep that the large flux swing decreases efficiency. An inductor ripple current ΔIL between 20-30% of the peak inductor current limit is a good compromise. Inductors so chosen are not only small but also have low core losses. Setting DIL = 0.25(2.6) = 0.65A, VD = 0.45V and VCESAT = 0.3V in (3), the inductance can be calculated as: 14 / 9287 9,1 9287 9,1 ',/ I (4) where L is in μH and f is in MHz. Equation (3) shows that for a given VOUT, DIL increases as D decreases. If VIN varies over a wide range, then choose L based on the nominal input voltage. Always verify converter operation at the input voltage extremes. The channel current limit is at least 2A. The maximum load current of a step-down converter is the switch cur', rent limit ILIM minus / . The maximum channel output current is slightly less than 2A. ,2870$; ,/,0 ',/ $ ',/ (5) The available output current can be made to approach ILIM by using a larger inductor. The saturation current of the inductor should be 20-30% higher than the peak current limit. Low-cost powder iron cores are not suitable for high-frequency switching power supplies due to their high core losses. Inductors with ferrite cores are recommended. Interleaved Switching and Input Capacitor A step-down converter draws a pulsed current with peakto-peak amplitude equal to its output current IOUT from the input power supply. An input capacitor placed between the supply and the buck converter filters the AC current and keeps the current drawn from the supply constant. The input capacitance CIN should be high enough to filter the pulsed input current. Its equivalent series resistance (ESR) should be low so that power dissipated in the capacitor does not result in significant temperature rise and degrade reliability. For a single channel step-down converter, the RMS ripple current in the input capacitor is ,506 &,1 ,287 ' ' (6) Power dissipated in the input capacitor is ,506 (65. &,1 SC2440A Applications Information (Continued) ,287 when ' , corre , (65 sponding to the worst-case power dissipation of 287 in CIN. For example, if one power transistor in the SC2440A Equation (6) has a maximum of is switching from zero to 2A and operating at 50% duty cycle while the other channel is disabled, then the input capacitor will carry 1A of RMS ripple current. If both power transistors in the SC2440A were to switch on in phase, the current drawn by the SC2440A would consist of current pulses with amplitude equal to the sum of the channel switch currents. If both channels were delivering full load to their outputs and operating at 50% duty cycle, then the input current would switch from zero to 4A. The RMS ripple current in the input capacitor would then be 2A. Power dissipated in CIN would be (2A)2(ESR), four times the maximum due to one channel alone. The SC2440A produces the highest RMS ripple current in CIN when only one channel is switching at current limit (< 3.4A). The input capacitor therefore should have a RMS ripple current rating of at least 1.7A. Figure 5 compares the RMS ripple currents produced in the input capacitor by (a) two identical step-down converters switching in phase and (b) a dual step-down converter with 180o out of phase switching (as implemented in the SC2440A) as a function of the switching duty cycle D. For simplicity, each individual converter in both cases is assumed to operate at the same duty cycle and deliver the same output current IOUT for a total output current of 2IOUT. Case (a) produces a maximum CIN RMS ripple current of IOUT when D = 0.5. Whereas the corresponding ripple current ,287 in Case (b). At 50% duty cycle, 180o is reduced to out of phase switching nulls CIN ripple current. Figure 5(b) also shows that slight deviation from 180o phase shift has no major impact on input ripple reduction. Interleaved switching therefore generates lower input voltage noise and requires a smaller input ceramic capacitor for filtering. This saves cost for VIN > 25V as high voltage ceramic capacitors are not cheap. Predicting the input capacitor RMS ripple current of a dual step-down converter operating at different duty cycles and delivering different output currents is not easy. However, the aforementioned advantages of interleaved switching are still valid. Figure 5. Normalized CIN RMS Ripple Current as a Function of the Duty Cycle D for the Following Regulators: (a) Two step-down converters switching in phase and at the same duty cycle. Each regulator delivers IOUT to its corresponding output for a total output current of 2IOUT. (b) A 180o out of phase switching dual stepdown regulator. The output currents and the duty cycles of the individual regulators are identical. Each regulator delivers IOUT to its corresponding output for a total output current of 2IOUT. Figure 6 compares the input voltage ripple generated by the DC-DC converter in Figure 1 with either channel or both channels switching. The low-noise advantage of interleaved switching is clearly evident. Multi-layer ceramic capacitors, which have very low ESR (a few mW) and can easily handle high RMS ripple current are the ideal choice for input filtering. A single 4.7mF or 10mF X5R ceramic capacitor is adequate. For high voltage applications, a small ceramic (1mF or 2.2mF) can be placed in parallel with a low ESR electrolytic capacitor to satisfy both the ESR and bulk capacitance requirements. 15 SC2440A Applications Information (Continued) Output Capacitor VIN 200mV/div AC Coupled The output ripple voltage DVOUT of a buck converter can be expressed as '9287 VSW1 5V/div § · ¸ ',/ ¨¨ (65 I& 287 ¸¹ © (7) where COUT is the output capacitance. 400ns/div (a) VIN 200mV/div AC Coupled Inductor ripple current DIL increases as D decreases [Equation (3)]. The output ripple voltage is therefore the highest when VIN is at its maximum. The first term in (7) results from the ESR of the output capacitor while the second term is due to the charging and discharging of COUT by the inductor ripple current. Substituting DIL = 0.65A, f = 550kHz and COUT = 22mF ceramic with ESR = 3mW in (7), '9287 $ P: P: P9 P9 VSW2 5V/div 400ns/div (b) VIN 200mV/div AC Coupled VSW 5V/div P9 Depending upon operating frequency and the type of capacitor, ripple voltage resulting from the charging and discharging of COUT may be higher than that due to the ESR of the output capacitor. A 10mF to 47mF X5R ceramic capacitor is found adequate for output filtering in most applications. Ripple current in the output capacitor is not a concern because the inductor current of a buck converter directly feeds COUT, resulting in very low ripple current. Avoid using Z5U and Y5V ceramic capacitors for output filtering because these types of capacitors have high temperature and voltage coefficients. Freewheeling Diode 400ns/div (c) Figure 6. Input Voltage Ripple Generated by the DCDC Converter in Figure 1. (a) Channel 1 is delivering 1.8A with Channel 2 shut off. The input ripple voltage ≈105mV. (b) Channel 2 is delivering 1.8A with Channel 1 shut off. The input ripple voltage ≈ 130mV. (c) Both Channels are supplying 1.8A to the loads. Interleaved switching reduces the input ripple voltage to about 60mV. 16 Use of Schottky barrier diodes as freewheeling rectifiers reduces diode reverse recovery current spikes, easing high-side current sensing in the SC2440A. These diodes should have an average current rating between 1A and 2A. The reverse blocking voltage of the Schottky diode should be derated by 10%-20% for reliability. The Schottky diode used in a 12V input step-down converter should have a reverse voltage rating of at least 16V (20% derating). For switching regulators operating at low duty cycles (i.e. low output voltage to input voltage conversion ratios), it is beneficial to use freewheeling diodes with somewhat higher average current ratings (thus lower forward voltages). This is because the diode conduction in- SC2440A Applications Information (Continued) terval is much longer than that of the transistor. Converter efficiency will be improved if the voltage drop across the diode is lower. The freewheeling diodes should be placed close to the SW pins of the SC2440A to minimize ringing due to trace inductance. Bootstrapping the Power Transistors To maximize efficiency, the turn-on voltage across the internal power NPN transistors should be minimized. If these transistors are to be driven into saturation, then their bases will have to be driven from a power supply higher in voltage than VIN. The required driver supply voltage (at least 2.4V higher than the SW voltage) is generated with a bootstrap circuit (the diode DBST and the capacitor CBST in Figure 7). The bootstrapped output (the common node between DBST and CBST ) is connected to the BST pin of the SC2440A. The minimum BST to SW voltage required to fully saturate the power transistor is shown in the “Typical Characteristics” (pages 8-9). The minimum required VCBST increases as temperature decreases. The bootstrap circuit reaches equilibrium when the base charge drawn from CBST during transistor on time is equal to the charge replenished during the off interval. Figure 7 summarizes various ways of bootstrapping the SC2440A. A fast switching PN diode (such as 1N4148 or 1N914) and a small (0.1μF – 0.47mF) ceramic capacitor can be used. In Figure 7(a) the power switch is bootstrapped from the output. This is the most efficient configuration and it also results in the least voltage stress at the BST pin. The maximum BST pin voltage is about VIN + VOUT. The minimum VOUT required for this bootstrap configuration is 2.5V. If the output voltage is 2.5V, then DBST will preferably be a small Schottky diode (such as BAT54) to maximize the bootstrap voltage. A 0.33-0.47mF bootstrap capacitor may also be needed to reduce droop. Bench measurement shows DBST DBST BST VIN VOUT SW IN BST CBST SC2440A VIN SC2440A GND + VZ - - VZ + BST CBST VOUT SW IN DZ DBST DZ DBST VIN SC2440A GND (c) DFW (b) (a) BST VOUT SW IN DFW GND CBST DFW VIN CBST SW IN SC2440A GND VOUT DFW (d) Figure 7(a)-(d). Bootstrap Configurations for the SC2440A 17 SC2440A Applications Information (Continued) voltage should not exceed its absolute maximum rating of 42V. To reduce BST voltage stress when stepping down from high VIN (>20V) to low VOUT (<2.5V), a Zener diode can be added in series with DBST. This is shown in Figure 7(d). The Zener voltage can be selected using (9): that using a Schottky bootstrapping diode when VOUT > 2.5V produces no noticeable efficiency benefit. If VIN(MAX) + VOUT > 42V, then a Zener diode DZ can be used in series with DBST to lower the BST voltage [Figure 7(c)]. The following inequality gives a suitable range for the Zener diode voltage VZ: 9287 ! 9= ! 9,10$; 9287 Figures 7(e) and (f ) show how to bootstrap the SC2440A from a second independent power supply VS. In Figure 7(g), the channel 1 output is used as the bootstrap power supply for channel 2. DC-DC regulators using this bootstrap method are shown in Figure 16(a). If channel 1 is out of regulation, then channel 2 will be shut off by PGOOD1. Correct operation of channel 2 thus depends on the readiness of VOUT1. This may be a drawback. (8) The SC2440A can also be bootstrapped from the input [Figure 7(b)]. This configuration is not as efficient as Figure 7(a). However this may be the only option if the output voltage is less than 2.5V and there is no other available supply with voltage higher than 2.5V. Voltage stress at the BST pin can be somewhat higher than 2VIN. The BST pin V S > 2.5V D BST V IN D BST V S > V IN + 2.5V BST BST C BST SC2440A GND V IN V OUT SW IN V OUT SW IN SC2440A D FW GND (e) D FW (f) D B S T1 V IN BST1 C B S T1 IN V O U T1 > 2.5V SW1 GND SC2440A D FW 1 D FW 2 PGOOD1 SW2 SS2 BST2 C B S T2 V O U T2 D B S T2 (g) Figure 7(e)-(g). Bootstrap Configurations for the SC2440A (Continued) 18 (9) 9,10,1 ! 9= ! 9,10$; SC2440A Applications Information (Continued) The minimum CBST value can be estimated as follows: &%67 ! ,2870$; ' I 96 (10) where VS is the voltage applied to the anode of DBST. The inductor current charges the bootstrap capacitor when it pulls the SW node low during the switch off time. (a) If DBST is connected to the converter input, then CBST will be charged as soon as VIN is applied. If the bootstrap diode is tied to the converter output [Figures 7(a), 7(c) and 7(g)], then CBST can only be charged from the regulator output through the inductor. Before the converter starts, there is neither output voltage nor inductor current. Hence it is necessary for the regulator to deliver some inductor current to the output before CBST can be charged. If VIN is not much higher than the programmed VOUT and it ramps up very slowly, then the inductor current will not be high enough for the bootstrap circuit to run, especially at light loads. In order to have some inductor current to charge CBST, the converter output needs to be loaded or VIN needs to be increased. Using a larger soft-start capacitor CSS will also help the bootstrap circuit to run because there will be current in the inductor over a longer period of time. Figures 8(a) and 8(b) show the minimum input voltage required to start and run before dropping out as a function of the load current. The minimum start-up VIN decreases with higher dVIN/dt or larger soft-start capacitor CSS. The lines labeled “dropout” in these graphs show that once started, the bootstrap circuit is able to sustain itself down to zero load. Soft-Start (b) Figure 8. The Minimum Input Voltage to Start and to Run Before Dropout. The regulator is bootstrapped from its output [Figure 7(a)] with 1N4148. The minimum starting VIN decreases when CSS or dVIN/dt increases. (a) VOUT = 5V (b) VOUT = 3.3V Each regulating channel of the SC2440A has its own softstart circuit. Pulling its soft-start pin below 0.8V with an open-collector NPN or an open-drain NMOS transistor turns off the corresponding regulator. The other regulator continues to run. During startup the soft-start capacitors are charged as soon as VIN exceeds its start threshold (2.71V). The converter remains off until IC (see Figure 3) charges the soft-start capacitor above 1.3V. One of the non-inverting inputs of the error amplifier EA is connected to the output of amplifier A1 (Figure 2). The voltage V1 at this non-inverting input rises at twice the soft-start capacitor charging rate. If the converter is to start into a constant current load IOUT by releasing its SS pin with the input power supply already applied, then the sum of IOUT and the COUT charging current will have to be less than the minimum switch cur- 19 SC2440A Applications Information (Continued) Overload / Short-Circuit Protection rent limit. This places a minimum limit on CSS: &66 ! P$ & 287 ,287 (11) where IOUT is in amperes. Starting the SC2440A by turning on a bench power supply will require much larger soft-start capacitors. CSS is best determined empirically because the rise time of a power supply can range from a few milliseconds to a few hundred milliseconds. With the maximum load applied, the output rise is observed using a 22nF for CSS. Adjust CSS until a linear VOUT ramp is achieved. VSW2 5V/div VOUT2 2V/div VSS2 1V/div VCOMP2 1V/div 4ms/div (a) VSW2 5V/div If the regulator output is shorted to ground, then the COMP voltage will rise to its 1.7V upper clamp. The regulator will quickly reach its cycle-by-cycle current limit. As described in the “General Description”, the regulator will shut off and undergo hiccup regardless whether soft-start is completed. The regulator restarts normally after the short at its output is removed. Short-circuit startup waveforms are captured in Figure 9(b). The converter switches only for a short period of time over a hiccup cycle. Short circuit power dissipation is substantially reduced. Power Good Indicators VOUT2 2V/div VSS2 1V/div VCOMP2 1V/div 4ms/div (b) Figure 9. Overload Hiccup of the 5V Output Channel in Figure 1. (a) Overload shutdown is triggered when IOUT2 is increased from 0.5A to 2.8A. The converter attempts to restart after a time out. (b) The regulator output is shorted to ground. The converter switches only for a short duration over a hiccup cycle. As a result, short circuit power dissipation is very low. 20 As described in the “General Description”, comparator ILIM (Figure 2) limits the switch current on a cycle-by-cycle basis, restricting the available regulator output current to the load. This causes the output voltage to fall and the COMP voltage to rise. If overload persists, then COMP will be clamped and the regulator will undergo shutdown and restart (hiccup). Hiccup is triggered when an over-current condition causes clamping of the error amplifier output. The time taken for VCOMP to rise from its regulating voltage to the clamp level is the delay time before shutdown. A very short over-current condition is therefore ignored. Figure 9(a) captures the initial overload shutdown and the subsequent time out and retry. Clamping of the error amplifier output and CSS discharge are evident. The PGOOD pins (Pins 11 and 14) are the open-collector outputs of the power good comparators. These slow comparators are incorporated with a small hysteresis. The FB low-to-high trip voltage of the power good comparators is 90% of the final regulation voltage. A pull-up resistor from each PGOOD pin to the input supply or the regulator output sets the PGOOD logic high voltage. The power good comparator output becomes valid provided that VIN is above 0.9V. In shutdown the power good output is actively pulled low. A power good pull-up resistor tied to the input will therefore increase current drain during shutdown. Tying the power good pull-up resistor to the regulator output is preferred, as this will minimize the shutdown supply current. In shutdown there is no voltage at the switching regulator output or current in the SC2440A Applications Information (Continued) SS1 CONTROL1 20kW PGOOD1 SS1 Q1 CSS1 SC2440A OFF ON 20kW Q1 SC2440A CSS1 PGOOD1 SS2 CONTROL2 20kW Q2 SS2 PGOOD2 CSS2 CSS2 CONTROL1 OFF CONTROL2 OFF PGOOD2 ON ON tD (a) (a) (b) (b) Figure 10. Sequencing the Outputs by (a) Delaying Release of one Channel Relative to the Other and (b) Using the PGOOD of one Channel to Control the Other. PGOOD pull-up resistor. If the PGOOD output high level (= VOUT ) is unacceptably low, then tying the power good pull-up resistor to the input or to a separate power supply will be the only choice. Sequencing the Outputs As mentioned above, pulling either soft-start pin low with an external transistor shuts off the corresponding regulator (Figure 10). Releasing the soft-start pin enables that channel and allows it to start. Delaying the release of the soft-start pin of one channel with respect to the other is a straightforward way of sequencing the outputs. Figure 10(a) shows this method using two external transistors Q1 and Q2. Q1 is turned off first, allowing channel 1 to start. Channel 2 is then enabled after time tD. The PGOOD output of one channel can also be used in conjunction with the soft-start pin of the other channel to delay start of that regulator. This method is depicted in Figure 10(b). SS2 is pulled low and channel 2 is kept off until the channel 1 output rises to 90% of its set voltage. Loop Compensation Each step-down switching regulator in the SC2440A requires a simple Type-2 compensation network (Figure 11) for stable operation. CZ and RZ form a compensating zero. This zero nulls out the effect of two low-frequency poles in the feedback loop and allows the loop amplitude response to cross unity gain at -20 dB/decade. Increasing FB 1V + EA COMP CZ SC2440A CP RZ Figure 11. Compensation Network for Each Regulator. 21 SC2440A Applications Information (Continued) RZ increases the mid-band loop gain and the crossover frequency. However the converter becomes less stable. Using a linear equivalent model and setting the loop gain crossover frequency to one-tenth the switching frequency, RZ can be calculated: 5= I &287 9287 (12) where RZ is in W. CZ can be determined by setting the zero frequency to one-fifth of the loop gain crossover frequency: &= I 5= (13) where CZ is Farads. VOUT1 0.5V/div AC Coupled The capacitor CP from COMP to ground rolls off the loop gain at high frequency. CP is generally not required for stability. In some cases, the addition of a small capacitor (10 to 22pF) from the COMP pin to ground eliminates SW falling edge jitter. RZ and CZ calculated above are based upon a linear equivalent circuit which does not model the non-linear nature of switching regulators very well. It is imperative to verify loop compensation by checking regulator load transient response. With the largest load step pertinent to the application applied, the regulator output voltage and the inductor current are observed. These transient waveforms should not show any ringing or excessive overshoot (see Figures 12(a) and 12(b) for examples of stable load transient waveforms.). If necessary, adjust RZ until a stable transient is obtained. The RZCZ product is to be kept constant during tuning. Board Layout Considerations IL1 0.5A/div 40ms/div (a) VOUT1 0.5V/div AC Coupled In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheelGL (Figure 13). ing diode carry pulse currents with high GW For jitter-free operation, the size of the loop formed by these components should be minimized. Since the power switches are already integrated within the SC2440A, conV IN V OUT IL2 0.5A/div ZL 40ms/div (b) Figure 12. Load Transient Response of the Converter in Figure 1. (a) Channel 1 (3.3V) Load Transient Response, IOUT1 is switched between 0.3A and 1.8A. (d) Channel 2 (5V) Load Transient Response, IOUT2 is switched between 0.3A and 1.8A. 22 Figure 13. Fast Switching Current Paths in a Stepdown Converter. The input capacitor and the freewheeling diode should be placed close to the part for improved switching performance. SC2440A Applications Information (Continued) necting the anodes of both freewheeling diodes close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitors should be placed close to the IN pins. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. Figure 14 shows an example of external component placement around the SC2440A. The input bypass capacitor C15, the output filtering capacitors and the freewheel- (a) ing diodes are grounded on the power ground plane. The feedback resistor dividers, the compensation networks and the soft-start capacitors are to be tied to analog ground. The frequency-setting resistor R9 is placed next to the ROSC pin and is also connected to analog ground. The exposed pad should be soldered to a large power ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using large vias directly under the device. In Figure 14(a) two 12mil vias are placed at the edge of the underside pad. (b) Figure 14. Suggested PCB Layout for the SC2440A (a) Top Layer and (b) Bottom Layer 23 SC2440A Typical Application Circuits (Continued) R6 C6 102k FB1 22pF C 5 R5 14.3k PGOOD1 COMP1 BST1 SS1 SW 1 D3 1nF C2 0.1mF C7 R9 37.4k C 10 V IN 20V -28V C 15 SYNC C8 R7 9.53k OUT1 D1 20B Q 030 C1 22mF 5V /1.8A R1 80.6k R2 20k IN ROSC S C 2440A 4.7mF SS2 22nF L1 12mH 22nF 600kH z 1N 4148 D2 20B Q 030 COMP2 L2 SW 2 1.5nF OUT2 10mH R3 46.4k C4 0.1mF D 4 GND FB2 C3 22mF BST2 1N 4148 PGOOD2 R8 3.3V /1.8A R4 20k 102k L 1 : W u rth 7 4 4 7 7 7 9 1 1 2 L 2 : W u rth 7 4 4 7 7 7 9 1 0 U p d a te d 9 /2 5 /1 3 C9 22pF C 1 , C 3 : M u ra ta G R M 2 1 B R 6 0 J1 0 6 K C 1 5 : M u ra ta G R M 3 1 C R 7 1 H 4 7 5 K (a) F re e -ru n n in g fre q u e n cy = 5 8 0 kH z (S S 3 1 3 R 2 trim m e d p a rt, R 9 = 3 7 .4 k) C9 10pF C 16 0.1mF VIN 5V/div VSYNC 2V/div VSW1 10V/div VSW2 10V/div C6 10pF (b) VOUT1 2V/div VOUT2 2V/div 1.1M H z 400ns/div (c) 4ms/div (d) Figure 15. (a) Synchronized 600kHz 24V to 5V and 3.3V Dual Step-down Converter. The free-running frequency of the regulator is set to 580kHz. (b) Efficiency (c) Switching Waveforms. VIN = 24V, IOUT1 = IOUT2 = 1A. (d) Start-up Waveforms. VIN = 24V, IOUT1 = IOUT2 = 0.5A. 24 SC2440A Typical Application Circuits (Continued) C6 R5 FB1 47pF C5 COMP1 8.87k C7 D3 BST1 3.9nF C2 0.1mF SS1 SW1 22nF R9 57.6k SC2440A ROSC COMP2 47pF SW2 L2 OUT2 4.7mH 0.8V/1.8A C4 0.1mF GND FB2 R22 4.02k D2 B120 C8 C9 5.6nF R21 30.1k 4.7mF SS2 14.7k R2 20k C1 22mF C15 PGOOD1 R7 R1 30.1k 2.5V/1.8A IN C10 22nF OUT1 10mH D1 B120 VIN 12V ± 10% SYNC BAT54 L1 D4 BST2 BAT54 PGOOD2 C3 47mF R3 8.06k R8 100k L1: Coiltronic DR73 L2: Coiltronic DR73 C1: Murata GRM31CR70J226M C3: Murata GRM32ER70J476M C15: Murata GRM31CR71C475M (a) VPGOOD2 2V/div VSS2 1V/div VOUT1 0.5V/div VOUT2 0.5V/div 4ms/div (b) (c) Figure 16. Stepping Down to a Voltage Lower Than the Feedback Voltage. (a) 400kHz 12V to 2.5V and 0.8V Step-down Converter. R3 is a pre-load to shunt the current from R21 and R22 before PGOOD1 releases SS2. (b) Start-up waveform (IOUT1 = IOUT2 = 1A). (c) Channel 2 load regulation is slightly below that of channel 1 because VFB2 is derived from VOUT1. 25 SC2440A Typical Application Circuits (Continued) R6 100k R5 14.3k C5 FB1 PGOOD1 D3 BST1 COMP1 470pF C2 0.1mF C7 SS1 SW1 R9 C10 15.4k R7 10.2k D1 B120 VIN = 5V ± 10% C1 22mF C15 SC2440A 2.5V/1.8A R2 10k 4.7mF D2 B120 D4 1N4148 C8 COMP2 L2 SW2 680pF R8 100k GND FB2 R1 15.0k IN ROSC SS2 22nF OUT1 2.2mH 22nF SYNC BAT54 L1 R3 8.06k C4 0.1mF C3 22mF BST2 PGOOD2 L1, L2: Coiltronic LD1 OUT2 2.2mH 1.8V/1.8A R4 10k C1, C3: Murata GRM21BR60J226M C15: Murata GRM21BR60J475K Figure 17. 1.2MHz 5V to 2.5V and 1.8V Step-down Converter. 1.1MHz 26 SC2440A Outline Drawing – TSSOP-16 EDP 27 SC2440A Land Pattern – TSSOP-16 EDP Contact Information Semtech Corporation Power Mangement Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com 28