RTG4 DDR Memory Controller with Initialization Configuration User Guide

RTG4 DDR Memory Controller
with Initialization
Configuration User Guide
RTG4 DDR Memory Controller with Initialization Configuration User Guide
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 Fabric External Memory DDR Controller Configurator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Memory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Fabric Interface Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 FDDR Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Fabric DDR Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Importing DDR Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Exporting DDR Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
A Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
17
17
18
2
Introduction
The RTG4 FPGA has two DDR memory controller blocks located on the East and West side of the chip
identified as:
•
East FDDR
•
West FDDR
The DDR controllers control off-chip DDR memories.
To fully configure the RTG4 DDR memory controller you must:
1. Use the RTG4 DDR Memory Controller Configurator to configure the DDR Controller, select its
datapath bus interface (AXI or AHB), and select the DDR clock frequency as well as the fabric
datapath clock frequency.
2. Set the register values for the DDR controller registers to match your external DDR memory
characteristics.
3. Instantiate the DDR controller as part of a user application and make datapath connections.
4. Connect the DDR controller's APB configuration interface as defined by the Peripheral
Initialization solution.
3
1 – Fabric External Memory DDR Controller
Configurator
The Fabric External Memory DDR (FDDR) Configurator is used to configure the overall datapath and the
external DDR memory parameters for the Fabric DDR Controller.
Figure 1-1 • FDDR Configurator Overview
Memory Settings
Use Memory Settings to configure your memory options in the MDDR.
•
Memory Type - LPDDR, DDR2, or DDR3
•
Data Width - 32-bit, 16-bit or 8-bit
•
Clock Frequency - Any value (Decimal/Fractional) in the range of 20 MHz to 333MHz
•
SECDED Enabled ECC - ON or OFF
Single Error Correction Double Error Detection (SECDED) ECC feature of DDR/LPDDR.
4
Fabric Interface Settings
FPGA Fabric Interface - This is the data interface between the FDDR and the FPGA design. Since the
FDDR is a memory controller, it is intended to be a slave on an AXI or AHB bus. The Master of the bus
initiates bus transactions, which are in turn interpreted by the FDDR as memory transactions and
communicated to the off-chip DDR Memory. FDDR fabric interface options are:
•
Using an AXI Interface - One master accesses the FDDR through a 64-bit AXI interface.
•
Using a Single AHB Interface - One master accesses the FDDR through a single 32-bit AHB
interface.
•
Using Two AHB Interfaces - Two masters can access the FDDR using two 32-bit AHB
interfaces.
FPGA CLOCK Divisor - Specifies the frequency ratio between the DDR Controller clock (CLK_FDDR)
and the clock controlling the fabric interface (CLK_FIC64). The CLK_FIC64 frequency should be equal to
that of the AHB/AXI subsystem that is connected to the FDDR AHB/AXI bus interface. For example, if
you have a DDR RAM running at 200 MHz and your Fabric/AXI Subsystem runs at 100 MHz you must
select a divisor of 2 (Figure 1-2).
Figure 1-2 • Fabric Interface Settings - AXI Interface and FDDR Clock Divisor Agreement
Use Fabric PLL LOCK - In the case where CLK_BASE is sourced from a Fabric CCC you can connect
the fabric CCC LOCK output to the FDDR FAB_PLL_LOCK input. CLK_BASE is not stable until the
Fabric CCC locks. Therefore, Microsemi recommends that you hold the FDDR in reset (i.e. assert the
CORE_RESET_N input) until CLK_BASE is stable. The LOCK output of the Fabric CCC indicates that
the Fabric CCC output clocks are stable. By checking the Use FAB_PLL_LOCK option, you can expose
the FAB_PLL_LOCK input port of the FDDR. You can then connect the LOCK output of the Fabric CCC
to the FAB_PLL_LOCK input of the FDDR.
IO Drive Strength (DDR2 and DDR3 only)
Select one of the following drive strengths for your DDR I/Os:
•
Half Drive Strength
•
Full Drive Strength
Depending on your DDR Memory type and the I/O Strength you select, Libero SoC sets the DDR I/O
Standard for your FDDR system as follows:
DDR Memory Type
Half Drive Strength
Full Drive Strength
DDR3
SSTL15I
SSTL15II
DDR2
SSTL18I
SSTL18II
IO Standard (LPDDR only)
Select one of the following options:
•
LVCMOS18 (Lowest Power) for LVCMOS 1.8V IO standard.
•
LPDDRI Note: Before you choose this standard, make sure that your board supports this
standard.
5
IO Calibration
Choose one of the following options:
•
On
•
Off
Calibration ON and OFF provide different values for PCODE and NCODE registers. The I/O calibration
block calibrates the I/O drivers to an external resistor. The impedance control is used to identify the
digital values PCODE<5:0> and NCODE<5:0>. These values are fed to the pull-up/pull-down reference
network to match the impedance with an external resistor. Once it matches the PCODE and NCODE
registers, they are latched and sent to the drivers. Users turn on or turn off this feature as per their board
requirements.
Enable Interrupts
The FDDR is capable of raising interrupts when certain predefined conditions are satisfied. Check
Enable Interrupts in the FDDR configurator if you would like to use these interrupts in your application.
This exposes the interrupt signals on the FDDR instance. You can connect these interrupt signals as
your design requires. The following Interrupt signals and their preconditions are available:
•
FIC_INT - Generated when there is an error in the transaction between the Master and the FDDR
•
IO_CAL_INT - Enables you to recalibrate DDR I/O's by writing to DDR controller registers via the
APB configuration interface. When calibration is complete, this interrupt is raised. For details
about I/O recalibration, refer to the Microsemi RTG4 User's Guide.
•
PLL_LOCK_INT - Indicates that the FDDR FPLL has locked
•
PLL_LOCKLOST_INT - Indicates that the FDDR FPLL has lost lock
•
FDDR_ECC_INT - Indicates a single or two-bit error has been detected
Fabric Clock Frequency
Clock frequency (CLK_BASE) calculation based on your current DDR Controller Clock (CLK_FDDR)
frequency and the FDDR CLOCK divisor, displayed in MHz.
Fabric Clock (CLK_BASE) Frequency (in MHz) = CLK_FDDR Clock Frequency / FDDR CLOCK
divisor
Memory Bandwidth
Memory bandwidth calculation based on your current Clock Frequency value in Mbps.
Memory Bandwidth (in Mbps) = 2 * Clock Frequency
Total Bandwidth
Total bandwidth calculation based on your current Fabric Clock Frequency (CLK_BASE), DDR, Data
Width and FDDR CLOCK divisor, in Mbps.
Total Bandwidth (in Mbps) = (2 * Fabric Clock Frequency * DDR Data Width) / FDDR CLOCK Divisor
6
2 – FDDR Controller Configuration
When you use the Fabric DDR Controller to access an external DDR Memory, the DDR Controller must
be configured at runtime. This is done by writing configuration data to dedicated DDR controller
configuration registers. This configuration data is dependent on the characteristics of the external DDR
memory and your application. This section describes how to enter these configuration parameters in the
FDDR controller configurator and how to build the initialization circuitry for the FDDR Controller after the
FDDR controller is configured.
Fabric DDR Control Registers
The Fabric DDR Controller has a set of registers that need to be configured at runtime. The configuration
values for these registers represent different parameters (for example, DDR mode, PHY width, burst
mode, ECC, etc.). For details about the DDR controller configuration registers, refer to the Microsemi
RTG4 User's Guide.
Fabric DDR Registers Configuration
Use the Memory Initialization (Figure 2-1) and Memory Timing (Figure 2-2) tabs to enter parameters that
correspond to your DDR Memory and application. Consult your DDR Memory vendor's datasheet for
values to enter in these two tabs.
Values you enter in these tabs are automatically translated to the appropriate register values. When you
click a specific parameter its corresponding register is described in the Register Description Window
(Figure 1-1 on page 4).
7
Figure 2-1 • FDDR Configuration - Memory Initialization Tab
8
Figure 2-2 • FDDR Configuration - Memory Timing Tab
Importing DDR Configuration Files
In addition to entering DDR Memory parameters using the Memory Initialization and Timing tabs, you can
import DDR register values from a file. To do so, click the Import Configuration button and navigate to
the text file containing DDR register names and values. Figure 2-3 shows the import configuration
syntax.
9
Figure 2-3 • DDR Register Configuration File Syntax
Note: If you choose to import register values rather than entering them using the GUI, you must specify all
necessary register values. Consult the SmartFusion2 User Guide for details.
Exporting DDR Configuration Files
You can also export the current register configuration data into a text file. This file will contain register
values that you imported (if any) as well as those that were computed from GUI parameters you entered
in this dialog.
If you want to undo changes you have made to the DDR register configuration, you can do so with
Restore Default. This deletes all register configuration data and you must either re-import or reenter this
data. The data is reset to the hardware reset values.
Generated Data
Click OK to generate the configuration. Based on your input in the General, Memory Timing and Memory
Initialization tabs, the FDDR Configurator computes values for all DDR configuration registers and
exports these values into your firmware project and simulation files. The exported file syntax is shown in
Figure 2-4.
10
Figure 2-4 • Exported DDR Register Configuration File Syntax
Initialization
This core has a built-in initialization state machine. Upon the assertion/de-assertion of the
INIT_RESET_N (Active Low) signal, the FDDR block is initialized with the user configurations. When the
configuration phase is complete, the INIT_DONE signal is asserted and the FDDR block is ready for
normal operations.
Note: The clock used for initialization should be a 50MHz clock connected to the INIT_CLK_50MHz
signal.
You can have the FDDR initialization start automatically at power up by connecting the INIT_RESET_N
(Active Low) input of the FDDR block to the POWER_ON_RESET_N (Active Low) signal of the
SYSRESET macro.
11
3 – Port Description
FDDR Core Ports
Table 3-1 • FDDR Core Ports
Port Name
Direction Description
CORE_RESET_N
IN
FDDR Controller Reset
CLK_BASE
IN
FDDR Fabric Interface Clock
INIT_CLK_50MHZ
IN
Initialization clock. Must be connected to a 50MHz clock source
INIT_RESET_N
IN
Active Low signal. Assert/de-assert this signal to start the initialization of the
FDDR
INIT_DONE
OUT
Asserted high when the initialization of the FDDR block is complete
Interrupt Ports
This group of ports is exposed when you select the Enable Interrupts option.
Table 3-2 • Interrupt Ports
Port Name
Direction Description
PLL_LOCK_INT
OUT
Asserts when FDDR PLL locks
PLL_LOCKLOST_INT OUT
Asserts when FDDR PLL lock is lost
ECC_INT
OUT
Asserts when an ECC Event occurs
IO_CALIB_INT
OUT
Asserts when I/O calibration is complete
FIC_INT
OUT
Asserts when there is an error in the AHB/AXI protocol on the Fabric interface
APB3 Configuration Interface
Table 3-3 • APB3 Configuration Interface
Port Name
Direction
Description
APB_S_PENABLE
IN
Slave Enable
APB_S_PSEL
IN
Slave Select
APB_S_PWRITE
IN
Write Enable
APB_S_PADDR[10:2]
IN
Address
APB_S_PWDATA[15:0]
IN
Write Data
APB_S_PREADY
OUT
Slave Ready
APB_S_PSLVERR
OUT
Slave Error
APB_S_PRDATA[15:0]
OUT
Read Data
APB_S_PRESET_N
IN
Slave Reset
APB_S_PCLK
IN
Clock
12
DDR PHY Interface
Table 3-4 • DDR PHY Interface
Port Name
Direction
Description
FDDR_CAS_N
OUT
DRAM CASN
FDDR_CKE
OUT
DRAM CKE
FDDR_CLK
OUT
Clock, P side
FDDR_CLK_N
OUT
Clock, N side
FDDR_CS_N
OUT
DRAM CSN
FDDR_ODT
OUT
DRAM ODT
FDDR_RAS_N
OUT
DRAM RASN
FDDR_RESET_N
OUT
DRAM Reset for DDR3
FDDR_WE_N
OUT
DRAM WEN
FDDR_ADDR[15:0]
OUT
Dram Address bits
FDDR_BA[2:0]
OUT
Dram Bank Address
FDDR_DM_RDQS[4:0]
INOUT
Dram Data Mask
FDDR_DQS[4:0]
INOUT
Dram Data Strobe Input/Output - P Side
FDDR_DQS_N[4:0]
INOUT
Dram Data Strobe Input/Output - N Side
FDDR_DQ[35:0]
INOUT
DRAM Data Input/Output
FDDR_FIFO_WE_IN[2:0]
FDDR_FIFO_WE_OUT[2:0]
IN
OUT
FIFO in signal
FIFO out signal
FDDR_DM_RDQS ([3:0]/[1:0]/[0])
INOUT
Dram Data Mask
FDDR_DQS ([3:0]/[1:0]/[0])
INOUT
Dram Data Strobe Input/Output - P Side
FDDR_DQS_N ([3:0]/[1:0]/[0])
INOUT
Dram Data Strobe Input/Output - N Side
FDDR_DQ ([31:0]/[15:0]/[7:0])
INOUT
DRAM Data Input/Output
FDDR_DQS_TMATCH_0_IN
IN
FDDR_DQS_TMATCH_0_OUT
FDDR_DQS_TMATCH_1_IN
FDDR_DQS_TMATCH_1_OUT
OUT
IN
OUT
FIFO in signal
FIFO out signal
FIFO in signal (32-bit only)
FIFO out signal (32-bit only)
FDDR_DM_RDQS_ECC
INOUT
Dram ECC Data Mask
FDDR_DQS_ECC
INOUT
Dram ECC Data Strobe Input/Output - P Side
FDDR_DQS_ECC_N
INOUT
Dram ECC Data Strobe Input/Output - N Side
FDDR_DQ_ECC ([3:0]/[1:0]/[0])
INOUT
DRAM ECC Data Input/Output
FDDR_DQS_TMATCH_ECC_IN
IN
FDDR_DQS_TMATCH_ECC_OUT
OUT
ECC FIFO in signal
ECC FIFO out signal (32-bit only)
Note: Port widths for some ports change depending on the selection of the PHY width. The notation "[a:0]/
[b:0]/[c:0]" is used to denote such ports, where "[a:0]" refers to the port width when a 32-bit PHY
width is selected, "[b:0]" corresponds to a 16-bit PHY width, and "[c:0]" corresponds to an 8-bit PHY
width.
13
AXI Bus Interface
Table 3-5 • AXI Bus Interface
Port Name
Direction
Description
AXI_S_AWREADY
OUT
Write address ready
AXI_S_WREADY
OUT
Write address ready
AXI_S_BID[3:0]
OUT
Response ID
AXI_S_BRESP[1:0]
OUT
Write response
AXI_S_BVALID
OUT
Write response valid
AXI_S_ARREADY
OUT
Read address ready
AXI_S_RID[3:0]
OUT
Read ID Tag
AXI_S_RRESP[1:0]
OUT
Read Response
AXI_S_RDATA[63:0]
OUT
Read data
AXI_S_RLAST
OUT
Read Last This signal indicates the last transfer in a read burst
AXI_S_RVALID
OUT
Read address valid
AXI_S_AWID[3:0]
IN
Write Address ID
AXI_S_AWADDR[31:0]
IN
Write address
AXI_S_AWLEN[3:0]
IN
Burst length
AXI_S_AWSIZE[1:0]
IN
Burst size
AXI_S_AWBURST[1:0]
IN
Burst type
AXI_S_AWLOCK[1:0]
IN
Lock type This signal provides additional information about the atomic
characteristics of the transfer
AXI_S_AWVALID
IN
Write address valid
AXI_S_WID[3:0]
IN
Write Data ID tag
AXI_S_WDATA[63:0]
IN
Write data
AXI_S_WSTRB[7:0]
IN
Write strobes
AXI_S_WLAST
IN
Write last
AXI_S_WVALID
IN
Write valid
AXI_S_BREADY
IN
Write ready
AXI_S_ARID[3:0]
IN
Read Address ID
AXI_S_ARADDR[31:0]
IN
Read address
AXI_S_ARLEN[3:0]
IN
Burst length
AXI_S_ARSIZE[1:0]
IN
Burst size
AXI_S_ARBURST[1:0]
IN
Burst type
AXI_S_ARLOCK[1:0]
IN
Lock Type
AXI_S_ARVALID
IN
Read address valid
AXI_S_RREADY
IN
Read address ready
AXI_S_CORE_RESET_N
IN
FDDR Global Reset
14
AHB0 Bus Interface
Table 3-6 • AHB0 Bus Interface
Port Name
Direction Description
AHB0_S_HREADYOUT
OUT
AHBL slave ready - When high for a write indicates the slave is ready to
accept data and when high for a read indicates that data is valid.
AHB0_S_HRESP
OUT
AHBL response status - When driven high at the end of a transaction
indicates that the transaction has completed with errors. When driven low at
the end of a transaction indicates that the transaction has completed
successfully.
AHB0_S_HRDATA[31:0]
OUT
AHBL read data - Read data from the slave to the master
AHB0_S_HSEL
IN
AHBL slave select - When asserted, the slave is the currently selected AHBL
slave on the AHB bus
AHB0_S_HADDR[31:0]
IN
AHBL address - byte address on the AHBL interface
AHB0_S_HBURST[2:0]
IN
AHBL Burst Length
AHB0_S_HSIZE[1:0]
IN
AHBL transfer size - Indicates the size of the current transfer (8/16/32 byte
transactions only)
AHB0_S_HTRANS[1:0]
IN
AHBL transfer type - Indicates the transfer type of the current transaction.
AHB0_S_HMASTLOCK
IN
AHBL lock - When asserted the current transfer is part of a locked
transaction.
AHB0_S_HWRITE
IN
AHBL write - When high indicates that the current transaction is a write.
When low indicates that the current transaction is a read.
AHB0_S_HREADY
IN
AHBL ready - When high, indicates that the slave is ready to accept a new
transaction.
AHB0_S_HWDATA[31:0]
IN
AHBL write data - Write data from the master to the slave
15
AHB1 Bus Interface
Table 3-7 • AHB1 Bus Interface
Port Name
Direction Description
AHB1_S_HREADYOUT
OUT
AHBL slave ready - When high for a write indicates the slave is ready to accept
data and when high for a read indicates that data is valid.
AHB1_S_HRESP
OUT
AHBL response status - When driven high at the end of a transaction indicates
that the transaction has completed with errors. When driven low at the end of a
transaction indicates that the transaction has completed successfully.
AHB1_S_HRDATA[31:0] OUT
AHBL read data - Read data from the slave to the master
AHB1_S_HSEL
IN
AHBL slave select - When asserted, the slave is the currently selected AHBL
slave on the AHB bus
AHB1_S_HADDR[31:0]
IN
AHBL address - byte address on the AHBL interface
AHB1_S_HBURST[2:0]
IN
AHBL Burst Length
AHB1_S_HSIZE[1:0]
IN
AHBL transfer size - Indicates the size of the current transfer (8/16/32 byte
transactions only)
AHB1_S_HTRANS[1:0]
IN
AHBL transfer type - Indicates the transfer type of the current transaction.
AHB1_S_HMASTLOCK
IN
AHBL lock - When asserted the current transfer is part of a locked transaction.
AHB1_S_HWRITE
IN
AHBL write - When high indicates that the current transaction is a write. When
low indicates that the current transaction is a read.
AHB1_S_HREADY
IN
AHBL ready - When high, indicates that the slave is ready to accept a new
transaction.
AHB1_S_HWDATA[31:0] IN
16
AHBL write data - Write data from the master to the slave
A – Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
Technical Support
Visit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more
information and support. Many answers available on the searchable web resource include diagrams,
illustrations, and links to other resources on the website.
Website
You can browse a variety of technical and non-technical information on the SoC home page, at
www.microsemi.com/soc.
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected].
17
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Sales office listings can be found at
www.microsemi.com/soc/company/contact/default.aspx.
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations
(ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes in the ITAR
drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
©2015 Microsemi Corporation. All rights
reserved. Microsemi and the Microsemi
logo are trademarks of Microsemi
Corporation. All other trademarks and
service marks are the property of their
respective owners.
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense and security, aerospace, and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs, and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world's standard for time; voice
processing devices; RF solutions; discrete components; security technologies and scalable
anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has
approximately 3,400 employees globally. Learn more at www.microsemi.com.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
5-02-00621-0/04.15