AN10789 GreenChip III TEA1751: integrated PFC and flyback controller Rev. 1.1 — 4 September 2013 Application note Document information Info Content Keywords GreenChip III, TEA1751, PFC, flyback, high efficiency, adaptor, notebook, PC Power Abstract The TEA1751 is a member of the new generation of PFC and flyback controller combination ICs, used for efficient switched mode power supplies. It has a high level of integration which allows the design of a cost effective power supply with a very low number of external components. The TEA1751 is fabricated in a Silicon-On-Insulator (SOI) process. The NXP SOI process makes a wide voltage range possible. AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller Revision history Rev Date Description v.1.1 20130904 updated issue • Modifications: v.1 20090210 Section 7 “PCB layout considerations” has been updated. first issue Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 2 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller 1. Introduction The TEA1751 is a combination controller with a PFC and flyback controller integrated in to an SO-16 package. Both controllers operate in Quasi Resonant (QR) / Discontinuous Conduction Mode (DCM) mode with valley detection. The switching is independent for each controller. The PFC output power is on-time controlled for simplicity. It is not necessary to sense the phase of the mains voltage. The flyback output power is Current mode controlled for good suppression of input voltage ripple. The communication circuitry between both controllers is integrated and no adjustment is needed. The voltage and current levels mentioned in this application note are typical values. A detailed description of the pin level spreading can be found in the TEA1751 data sheet. 1.1 Scope This application note describes the functionality and the control functions of TEA1751 and the adjustments needed within the power converter application. For the large signal parts of the PFC and flyback power stages, the design and data for the coil and transformer are dealt with in a separate application note. 1.2 The TEA1751 GreenChip III controller The features of the GreenChip III allow the power supply engineer to design a reliable and cost-effective and efficient switched mode power supply with the minimum number of external components. 1.2.1 Key features • • • • • • PFC and flyback controller integrated in one SO-16 package Switching frequency of PFC and flyback are independent of each other No external hardware required for communication between the two controllers High level of integration, resulting in a very low external component count Mains voltage enable and brownout protection integrated Fast latch reset function implemented 1.2.2 System features • • • • • • • • AN10789 Application note Safe Restart mode for system fault conditions High-voltage start-up current source (5.4 mA) Reduction of HV current source (1 mA) in Safe restart mode Wide VCC range (38 V) MOSFET driver voltage limited Easy controlled start-up behavior and VCC circuit General-purpose input for latched protection Internal IC overtemperature protection All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 3 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller • Two high-voltage spacers between the HV pin and the next active pin • Open pin protection on the VINSENSE, VOSENSE, PFCAUX, FBCTRL and FBAUX pins 1.2.3 PFC features • • • • • • • Dual output voltage boost converter Frequency limitation (125 kHz) to reduce switching losses and EMI Ton controlled Mains input voltage compensation for control loop for good transient response Over current protection (OCP) Soft start and soft stop Open / short detection for PFC feedback loop: no external OVP circuit necessary 1.2.4 Flyback features • • • • • QR / DCM operation with valley switching Frequency limitation (125 kHz) to reduce switching losses and EMI Current mode controlled Overcurrent protection (OCP) Frequency reduction with fixed minimum peak current to maintain high efficiency at low output power levels without audible noise • Soft start • Accurate OverVoltage Protection (OVP) through auxiliary winding • Time-out protection for output overloads and open flyback feedback loop, available as safe restart (TEA1751T) or latched (TEA1751LT) protection AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 4 of 31 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors AN10789 Application note 1.3 Application schematic D1 L2 + 9 BD1 7 C1 D10 + C2 C8 R5 C3 R18 Vout 9,10 1 5 T1 2 L1 4 + + C36 C37 - R6 7,8 D3 GND 1 D2 D4 Q1 C5 Q2 R13 R14 C9 R11 R12 R17 R16 CX1 C6 C10 R10 R15 R1 R2 D5 C4 LF1 R7 6 C14 + C13 R23A 8 PFCAUX 7 VCC R32 C32A 4 R23 FBAUX FBCTRL PFCCOMP 4 3 6 5 2 R32A R30 5 3 R24 R25 R3 D23A 1 HV FBSENSE 16 TEA1751 GND R27 PFCDRIVER VINSENSE 12 10 FBDRIVER PFCSENSE MAINS INLET 13 VOSENSE 11 9 HVS 15 LATCH 14 HVS U1 C15 C17 C16 U2 1 R31 2 C31 U3 C18 RT2 C7 R4 C20 C19 R26 Fig 1. Application schematic R33 AN10789 5 of 31 © NXP B.V. 2013. All rights reserved. CY1 GreenChip III TEA1751: integrated PFC and flyback controller Rev. 1.1 — 4 September 2013 All information provided in this document is subject to legal disclaimers. R8 R9 LF2 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller 2. Pin description Table 1. Pin descriptions Pin Name Functional description 1 VCC Supply voltage: Vstartup = 22 V, Vth(UVLO) = 15 V. At mains switch-on, the capacitor connected to this pin is charged to VCC start by the internal HV current source. When the pin voltage is lower than 0.65 V, the charge current is limited to 1 mA, this to prevent overheating of the IC if the VCC pin is short circuited. When the pin voltage is between 0.65 V and Vth(UVLO), the charge current is 5.4 mA to enable a fast start-up. Between Vth(UVLO) and Vstartup, the charge current is again limited to 1 mA, this to reduce the safe restart duty cycle and as a result the input power during fault conditions. At the moment Vstartup is reached the current source is pinched-off, and VCC is regulated to Vstartup until the flyback starts. See Section 3.2 for a complete description of the start-up sequence. 2 GND Ground connection. 3 FBCTRL Control input for flyback for direct connection of the optocoupler. At a control voltage of 2 V the flyback delivers maximum power. At a control voltage of 1.5 V the flyback enters the frequency reduction mode and the PFC is switched off. At 1.4 V the flyback stops switching. Internal there is a 30 mA current source connected to the pin, which is controlled by the internal logic. This current source can be used to implement a time-out function to detect an open control-loop or a short circuit of the output-voltage. The time-out function can be disabled with a resistor of 100 k between this pin and ground. 4 FBAUX Input from auxiliary winding for transformer demagnetization detection, mains dependent overpower protection (OPP) overvoltage protection (OVP) of the flyback. The combination of the demagnetization detection and the valley detection at pin HV is determining the switch-on moment of the flyback in the valley. A flyback OVP is detected at a current > 300 A into the FBAUX pin. Internal filtering is present to prevent false detection of an OVP. The flyback OPP starts at a current < 100 A out of the FBAUX pin. 5 LATCH General purpose latched protection input. When Vstartup (pin 1) is reached, this pin is charged to a voltage of 1.35 V first before the PFC is enabled. To trigger the latched protection, the pin must be pulled down to below 1.25 V. An internal 80 A current source is connected to the pin, which is controlled by the internal logic. Because of this current source, an NTC resistor for temperature protection can be directly connected to this pin. 6 AN10789 Application note PFCCOMP Frequency compensation pin for the PFC control loop. All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 6 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller Table 1. Pin descriptions …continued Pin Name Functional description 7 VINSENSE Sense input for mains voltage. This pin has 5 functions: • • • mains enable level: Vstart(VINSENSE) = 1.15 V • • fast latch reset: Vflr = 0.75 V mains stop level (brownout): Vstop(VINSENSE) = 0.9 V mains voltage compensation for the PFC control-loop gain bandwidth dual boost switch-over point: Vbst(DUAL) = 2.2 V The mains enable and mains stop level enable and disable the PFC. The voltage at the VINSENSE pin must be an averaged DC value, representing the AC line voltage. The pin is not used for sensing the phase of the mains voltage. 8 PFCAUX Input from an auxiliary winding of the PFC coil for demagnetization timing and valley detection to control the PFC switching. The auxiliary winding must be connected by a 5 k series resistor to prevent damage of the input due to lightning surges. 9 VOSENSE Sense input for output voltage of the PFC. VOSENSE pin, open loop and short detection: Vth(ol)(VOSENSE) =1.15 V Regulation of PFC output voltage: Vreg(VOSENSE) = 2.5 V PFC soft OVP (cycle-by-cycle): Vovp(VOSENSE) = 2.63 V Control output for output voltage of the PFC, - dual boost current: Ibst(DUAL) = 15 A 10 FBSENSE Current sense input for flyback. At this pin, the voltage across the flyback current sense resistor is measured. The setting of the sense level is determined by the FBCTRL voltage, using the equation: V FBSENSE = 0.75 V FBCTRL – 1 V The maximum setting level for VFBSENSE = 0.5 V. Internal there is a 60 A current source connected to the pin, which is controlled by the internal logic. The current source is used to implement a soft start function for the flyback and to enable the flyback. The flyback only starts when the internal current source is able to charge the soft start capacitor to a voltage of more than 0.5 V. Therefore a minimum soft start resistor of 12 k is required to guarantee the enabling of the flyback. 11 PFCSENSE Overcurrent protection input for PFC. This input is used to limit the maximum peak current in the PFC core. The PFCSENSE is a cycle-by-cycle protection, at 0.5 V the PFC MOSFET is switched off. There is an internal 60 A current-source connected to the pin, which is controlled by the internal logic. This current source is used to implement a soft start and soft stop function for the PFC, this to prevent audible noise in PFC burst mode. This pin is also used for enabling of the PFC. The PFC only starts when the internal current source is able to charge the soft start capacitor to a voltage of more than 0.5 V. Therefore a minimum soft start resistor of 12 k is required to guarantee the enabling of the PFC. AN10789 Application note 12 PFCDRIVER Gate driver output for PFC MOSFET. 13 FBDRIVER Gate driver output for flyback MOSFET. All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 7 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller Table 1. Pin descriptions …continued Pin Name Functional description 14 HVS High-voltage safety spacer, not connected 15 HVS High-voltage safety spacer, not connected 16 HV High-voltage input for internal start-up current source (output at pin 1), and valley sensing of the flyback. The combination of the demagnetization detection at the FBAUX pin and the valley detection at the HV pin determine the switch-on moment of the flyback in the valley. 3. System description and calculation 3.1 PFC and flyback start conditions Figure 2 and Figure 3 show the conditions for enabling of the PFC and flyback are given. If start-up problems occur these conditions can be checked to find the cause of the problem. Some of the conditions are dynamic signals (see Figure 4) and should be checked with an oscilloscope. /$7&+!9 /$7&+!9 )%6(16(VRIWVWDUW9 3)&6(16(VRIWVWDUW9 $1' HQDEOH3)& $1' 9,16(16(!9 926(16(!9 926(16(9 )%&75/9 DDD Fig 2. PFC start condition HQDEOHIO\EDFN DDD Fig 3. Flyback start condition 3.2 Start-up sequence At switch-on with a low mains voltage, the TEA1751(L)T power supply has the following start-up sequence (see Figure 4): 1. The HV current source is set to 0.9 mA and the VCC electrolytic capacitor is charged to 0.65 V; this to detect a possible short circuit at pin VCC. 2. At VCC = 0.65 V, the HV current source is set to 5.4 mA and the VCC electrolytic capacitor is fast charged to VTH(UVLO). 3. At VCC = VTH(UVLO), the HV current source is set to 0.9 mA again and the VCC electrolytic capacitor is charged further to Vstartup. 4. At Vstartup, the HV current source is switched off and the 80 A LATCH pin current source is switched on to charge the LATCH pin capacitor. At the same time, the PFCSENSE and FBSENSE soft start current sources are switched on. 5. When the LATCH pin is charged up to 1.35 V the PFC and flyback can start switching, but only when the VINSENSE pin has reached a level of 1.15 V. 6. For the PFC also the soft start capacitor at pin PFCSENSE must be charged up to 0.5 V. The voltage at the VOSENSE pin must be greater than 1.15 V. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 8 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller 7. For the flyback also the soft start capacitor at pin FBSENSE must be charged up to 0.5 V and the voltage at the FBCTRL pin must be less than 4.5 V. Normally, the voltage at the FBCTRL pin is always less than 4.5 V at the first flyback switching cycle, unless the FBCTRL pin is open. At the moment that the flyback starts, the FBCTRL time-out current source is switched on. 8. When the flyback has reached its nominal output voltage, the VCC supply of the IC is taken over by the auxiliary winding. If, for any reason, the flyback feedback loop signal is missing, then the time-out protection at the FBCTRL pin is triggered and both converters the PFC and the flyback are switched off, VCC drops to VTH(UVLO), and the IC continues with step 3 of the start-up cycle. This is the safe restart cycle. IHV Vstartup Vth(UVLO) Vtrip VCC Vstart(VINSENSE) VINSENSE VEN(LATCH) LATCH PROTECTION soft start PFCSENSE PFCDRIVER soft start FBSENSE FBDRIVER Vto(FBCTRL) FBCTRL Vstart(fb) VOSENSE VO charging VCC capacitor Fig 4. starting converters normal operation protection restart 014aaa156 Start-up sequence at low mains voltage The charge time of the soft start capacitors can be chosen by their values independently for the PFC and the flyback. This way it can be realized that the PFC starts before the flyback. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 9 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller 3.3 VCC cycle at safe restart protections In Safe restart mode, the controller goes through the steps 3 to 8 as described in Section 3.2. 3.4 Mains voltage sensing and brownout The mains input voltage is measured through the VINSENSE pin. When the VINSENSE pin has reached the Vstart(VINSENSE) level of 1.15 V the PFC can start switching, but only if the other start conditions are met as well, see Section 3.1. As soon as the voltage at pin VINSENSE drops below the Vstop(VINSENSE) level of 0.89 V, the PFC stops switching. The flyback however, continues switching until the flyback maximum on-time protection, ton(fb)max (40 s) is triggered. When this protection is triggered, the IC stops switching and enters the safe restart mode. The voltage at the VINSENSE pin must be an average DC value, representing the mains input voltage. The system works optimal with a time constant of approximately 150 ms at the VINSENSE pin. The long time constant at the VINSENSE pin prevents a fast restart of the PFC after a mains drop-out, therefore the voltage at the VINSENSE pin is clamped to a level of 100 mV below the Vstart(VINSENSE) level, this to guarantee a fast PFC restart after recovery of the mains input voltage. BD1 R1 mains inlet - CX1 R2 + C1 R3 VINSENSE R4 TEA1751 C20 0014aaa768 Fig 5. VINSENSE circuitry 3.4.1 Discharge of mains input capacitor For safety, according to Ref. 1, the X-capacitors in the EMC input filtering must be discharged with a time constant < 1 s. The R to discharge the X-cap in the input filtering, is determined by the replacement value of R1+ R2. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 10 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller In a typical 90 W adapter application with CX1 = 220 nF, the replacement value of R1 + R2 must be smaller than or equal to the following: 1 R V ---- = ------------------ = 4.55 M C 220 nF (1) 3.4.2 Brownout voltage adjustment The rectified AC input voltage is measured via R1 and R2. Each resistor alternately senses half the sine wave, so both resistors must have the same value. The average voltage sensed at the connection of R1 and R2 is as follows: 2 2 V avg = ---------- V acrms (2) The V (AC) brownout RMS level is calculated as follows: R1 R2 V acbrownout = ---------- V stop VINSENSE 2 ----------------------------------- + R3 R1 + R2 2 2 ------------------- + 1 R4 (3) For a brownout threshold of 68 V (AC) and compliance with Ref. 1. Example values are shown in Table 2. Table 2. VINSENSE component values CX1 R1 R2 R3 R4 220 nF 2 M 2 M 560 k 47 k 330 nF 1.5 M 1.5 M 820 k 47 k 470 nF 1 M 1 M 1.1 M 47 k A value of 3.3 F for capacitor C20, with 47 k at R4, gives the recommended time constant of 150 ms at the VINSENSE pin. 3.5 Internal OTP The IC has an internal temperature protection to protect the IC from overheating by overloads at the VCC pin. When the junction temperature exceeds the thermal shutdown temperature, the IC stops switching. As long as the OTP is active, the VCC capacitor is not recharged from the HV mains. The OTP circuit is supplied from the HV pin if the VCC supply voltage is not sufficient. The OTP is a latched protection. 3.6 LATCH pin The LATCH pin is a general-purpose input pin, which can be used to latch off both converters. The pin sources a bias current Io(LATCH) of 80 A for the direct connection of an NTC. When the voltage on this pin is pulled below 1.25 V, switching of both converters is immediately stopped. VCC starts cycling between the VTH(UVLO) and Vstartup, without a restart. Switching off and then switching on the mains input voltage trigger the fast latch reset circuit, and reset the latch. At start-up, the latch pin first must be charged above 1.35 V, before both converters are enabled. Charging of the LATCH pin starts at Vstartup. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 11 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller No internal filtering is present at the LATCH pin. A 10 nF capacitor must be placed between this pin and IC GROUND pin to prevent false triggering, also when the LATCH pin function is not used. LATCH TEA1751 RT 4 C19 R26 3 U4 1 2 014aaa769 Fig 6. Usage of the LATCH pin protection Latching on application over temperature occurs when the total resistance value of the NTC and its series resistor drops below the following: V prot LATCH 1.25 V R OTP = ------------------------------- = ---------------- = 15.6 k I O LATCH 80 A (4) The optocoupler triggers the latch if the driven optotransistor conducts more than 80 A. 3.7 Fast latch reset Switching off and then switching on the mains input voltage, can reset the latched protection. After the mains input is switched off, the voltage at the VINSENSE pin will drop below VFLR (0.75 V). This triggers the fast latch reset circuit, but does not reset the latched protection. After the mains input is switched on, the voltage at the VINSENSE pin will rise again, and when the level has passed 0.85 V, the latch will be reset. The system restarts again when the VCC pin is charged to Vstartup. See step 4 of Section 3.2. 4. PFC description and calculation The PFC operates in Quasi Resonant (QR) or Discontinuous Conduction Mode (DCM) with valley detection to reduce the switch-on losses. The maximum switching frequency of the PFC is limited to 125 kHz to reduce the switching losses. One or more valleys are skipped, when necessary, to keep the frequency below 125 kHz. The PFC of the TEA1751(L)T is designed as a dual boost converter with two output voltage levels that are dependent on the mains input voltage range. The advantage of such a dual boost is that the overall system efficiency at low mains can be improved due to reduction of the PFC switching losses. In low and medium power adapters (< 120 W) the contribution of PFC switching losses to the total losses are relative high. The dual output voltage is controlled through an internal current source of 15 A at pin VOSENSE. As shown in Figure 7, the mains input voltage measured at pin VINSENSE is used to control the internal current source. This current-source in combination with the resistors at pin VOSENSE sets the lower PFC output voltage. At high mains, the current-source is switched off. Therefore, the maximum PFC output voltage is not effected by the accuracy of the current-source. In a typical adapter with a PFC output voltage of AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 12 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller 385 V (DC) at high mains, the PFC output voltage is 250 V (DC) at low mains. A voltage of 2.2 V at pin VINSENSE corresponds with a mains input voltage of approximately 180 V (AC). The small slope at the transfer function ensures stable switch over of the PFC output voltage without hiccups. 2.2 V VVINSENSE –15µA II(VOSENSE) Fig 7. 014aaa770 Transfer function of VINSENSE voltage to dual boost current at VOSENSE At low output loads, the PFC is switched off to ensure a high efficiency, and a low no-load standby input power. After switch off, the bulk electrolytic capacitor voltage drops to Vac 2. 4.1 PFC output power and voltage control The PFC of the TEA1751(L)T is on-time controlled, therefore it is not necessary to measure the mains phase angle. The on-time is kept constant during the half sine wave to obtain a good power factor (PF), and a class-D Mains Harmonics Reduction (MHR) (see Ref. 2). AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 13 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller ramp oscillator + VM C S voltage comparator Idis V- current multiplier VVINSENSE V/I TRANSDUCER VR V+ VS I2 I2 + - VPFCGATE Q S I1 Vosc VVOSENSE R Vp transconductance amplifier ton limiting circuit VREF PFC OSCILLATOR VALLEY DETECTION VVALLEY ICOMP VPFCAUX R1 C2 compensation network C1 014aaa771 Fig 8. PFC on-time control To stabilize the PFC control loop, a network with one resistor and two capacitors at the PFCCOMP pin is used. The mathematical equation for the transfer function of a boost converter contains the square of the mains input voltage. In a typical application this results in a low regulation bandwidth for low mains input voltages and a high regulation bandwidth at high input voltage, while at high mains input voltages it can be difficult to meet the MHR requirements. The TEA1751(L)T uses the mains input voltage measured through the VINSENSE pin to compensate the control loop gain as function of the mains input voltage. As a result the gain is constant over the entire mains input voltage range. The voltage at the VINSENSE pin must be an average DC value, representing the mains input voltage. The system works optimal with a time constant of approximately 150 ms at the VINSENSE pin. 4.1.1 Setting the PFC output voltage The PFC output voltage is set with a resistor divider between the PFC output voltage and the VOSENSE pin. In PFC Normal mode, the PFC output voltage is regulated so that the voltage on the VOSENSE pin is equal to Vreg(VOSENSE) = 2.5 V. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 14 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller D1 Vo(PFC) PFC stage C3 1.5 mA VINSENSE R5 R6 2.2 V VOSENSE TEA1751 C4 R7 Place C4 and R7 as close as possible to the IC 014aaa772 Fig 9. PFC output voltage setting For low no-load input power two resistors of 4.7 M (1 %) can be used between the bulk electrolytic capacitor and the VOSENSE pin. The dimensioning of the Ibst(DUAL) current source (15 A) has been adapted to the usage of these resistor values. With a resistor value of 4.7 M for R5 and R6 and 60 k to 62 k for R7, a universal mains adapter has a PFC output voltage of approximately 380 V to 390 V at high mains and 240 V to 250 V at low mains. The resistor R7 (1 %) between the VOSENSE pin and ground can be calculated with equation: R5 + R6 V reg VOSENSE R7 = ------------------------------------------------------------------ V O PFC – V reg VOSENSE (5) Suppose that the regulated PFC output voltage is 382 V, then: 4.7 M + 4.7 M 2.5 V R7 = ---------------------------------------------------------------------- = 62 k 1 % 382 V – 2.5 V At low mains, the 15 A current source Ibst(DUAL) is active. The lower PFC output voltage can be calculated with Equation 6: R5 + R6 + R7 V O PFC LOW = --------------------------------- V reg VOSENSE – I bst DUAL R7 R7 (6) With 4.7 M for R5 and R6 and 62 k for R7 the lower PFC output voltage is calculated as follows: 4.7 M + 4.7 M + 62 k V O PFC LOW = -------------------------------------------------------------------- 2.5 V – 15 A 62 k = 240 V 62 k The function of the capacitor C4 at the VOSENSE pin is to filter noise and to prevent false triggering of the protections, due to MOSFET switching noise, mains surge events or ESD events. False triggering of the Vovp(VOSENSE) protection can cause audible noise and disturbance of the AC mains input current. False triggering of the Vth(ol)(VOSENSE) protection causes a safe restart cycle. A time constant of 500 ns to 1 ms, at the VOSENSE pin should be sufficient, which results in a value of 10 nF for capacitor C4. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 15 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller Place R7 and C4 as close as possible to the IC between the VOSENSE pin and the IC ground pin. 4.1.2 Calculation of the PFC soft start and stop components The soft start and stop are implemented through the RC network at the PFCSENSE pin. Rss1 must have a minimum value of 12 k as specified. This to ensure that the voltage Vstart(soft)PFC of 0.5 V is reached to enable start-up of the PFC. See Section 3.1 for start-up description. Istartup(soft)PFC ≤ 60 μA S1 SOFT START CONTROL RSS1 11 PFCSENSE CSS1 RSENSE1 OCP 0.5 V 014aaa157 Fig 10. PFC soft start The total soft start or soft stop time is equal to: t softstart = 3Rss1 Css1 Keep the soft start time of the PFC smaller than the soft start time of the flyback to ensure that the PFC starts before the flyback at initial start-up. It is also advised that the soft start time is kept within a range of 2 ms to 5 ms. With C8 = 100 nF and R11 = 12 k, the total soft start time is 3.6 ms. 4.2 PFC demagnetizing and valley detection The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the voltage across the PFC MOSFET. To reduce switching losses and electromagnetic interference (EMI) (valley switching) the next stroke is started if the voltage across the PFC MOSFET is at its minimum. The maximum switching frequency of the PFC is limited to 125 kHz to reduce the switching losses. One or more valleys are skipped, when necessary, to keep the frequency below 125 kHz. If no demagnetization signal is detected on the PFCAUX pin, the controller generates a Zero Current Signal (ZCS), 50 ms after the last PFC gate signal. If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal 4 s after demagnetization was detected. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 16 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller In some applications, the PI filter before the PFC inductor can start oscillating when the PFC switching frequency is close to the third harmonic of the PI filter resonance frequency. This can lead to false PFC valley detection. As a result, the PFC can run in Continuous conduction mode. False detection can be suppressed by placing a diode between the IC ground and the PFCAUX pin. L1 C1 D1 L2 9 7 5 1 C3 C2 Q1 R27 TEA1751 PFCAUX D27 014aaa773 Fig 11. PFCAUX circuitry 4.2.1 Design of the PFCAUX winding and circuit To guarantee valley detection at low ringing amplitudes, the voltage at the PFCAUX pin must be set as high as possible, taking into account its absolute maximum rating of 25 V. The number of turns of the PFCAUX winding can be calculated as follows: V PFC AUX 25 V N a max = ---------------------------- N p = ------------------ N p V L max V L max (7) Where: VPFCAUX is the absolute maximum rating of the PFCAUX pin, and VL(max) is the maximum voltage across the PFC primary winding. The PFC output voltage at the PFCOVP level determines the maximum voltage across the PFC primary winding and can be calculated with equation: V OVP VOSENSE 2.63 V V L max = -------------------------------------- V O PFC = ---------------- V O PFC V reg VOSENSE 2.5 V (8) When a PFC coil with a higher number of auxiliary turns is used, then a resistor voltage divider can be placed between the auxiliary winding and pin PFCAUX. The total resistive value of the divider should be less than 10 k to prevent delay of the valley detection by parasitic capacitance. The polarity of the signal at the PFCAUX pin must be reversed compared to the PFC MOSFET drain signal. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 17 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller To protect the PFCAUX pin against electrical overstress, for example during lighting surge events, put a 5 k resistor between the PFC auxiliary winding and this pin. To prevent incorrect valley switching of the PFC due to external disturbance, the resistor should be placed close to the IC. 4.3 PFC protections 4.3.1 VOSENSE OverVoltage Protection (OVP) At start-up or at the transition from PFC Burst mode to PFC Normal mode, a voltage overshoot can occur at the boost electrolytic capacitor. This overshoot is caused by the relative slow response of the PFC control loop. The PFC control loop response must be relatively slow to guarantee a good power factor and meet the MHR requirements. The OverVoltage Protection (OVP) at the VOSENSE pin limits the overshoot. At the moment that the VOVP(VOSENSE) level of 2.63 V is detected, the PFC MOSFET is switched off immediately, regardless of the on-time setting. The switching of the MOSFET remains blocked until the voltage at the VOSENSE pin drops below 2.63 V again. When the resistor between the VOSENSE pin and ground is open, the OVP is also triggered. The peak voltage at the boost electrolytic capacitor generated by the PFC due to an overshoot and limited by the PFC OVP can be calculated with the equation: V ovp VOSENSE 2.63 V V O PFC_peak = ------------------------------------ V O PFC_nominal = ---------------- V O PFC_nominal V reg VOSENSE 2.5 V (9) 4.3.2 VOSENSE open and short pin detection The VOSENSE pin, which is sensing the PFC output voltage, has integrated protection circuitry to detect an open and short-circuited pin. This pin can also sense if one of the resistors in the voltage divider is open. Therefore the VOSENSE pin is fail-safe. It is not necessary to add an external OVP circuit for the PFC. An internal current source pulls down the pin below the Vth(ol)(VOSENSE) detection level of 1.15 V, when the pin is open. At detection of the Vth(ol)(VOSENSE) level switching of the PFC MOSFET is blocked until the voltage at the VOSENSE pin rises above 1.15 V again. 4.3.3 VINSENSE open pin detection The VINSENSE pin, which senses the mains input voltage, has an integrated protection circuit to detect an open pin. An internal current source pulls down the pin below the Vstop(VINSENSE) level of 0.9 V, when the pin is open. 4.3.4 OverCurrent Protection (OCP) An OverCurrent Protection (OCP) limits the maximum current through the PFC MOSFET and PFC coil. The current is measured via a current sense resistor in series with the MOSFET source. The MOSFET is switched off immediately when the voltage at pin PFCSENSE exceeds the Vsense(PFC)max level of 0.52 V. The OCP is a switching cycle-by-switching cycle protection. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 18 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller To avoid false triggering of the PFC OCP by switching of the flyback, keep a margin of 0.1 V into account. False triggering of the VOVP(VOSENSE) protection can cause disturbance of the AC mains input current. It is also advised that a small capacitor of 100 pF to 220 pF is placed directly at the PFCSENSE pin to any suppress external disturbance. The current sense resistor can be calculated as follows: V sense PFC max – V m arg in 0.52 V – 0.1 V R OCP PFC = ------------------------------------------------------------- = ----------------------------------Ip QR PFC max Ip QR PFC max (10) Where: IpQR(PFC)max is the maximum PFC peak current at the high load and low mains. For the PFC operating in Quasi Resonant mode the maximum peak current can be calculated with equation: Ip QR PFC max Po max 2 2 --------------- 1.1 2 2 Pi max 1.1 = ----------------------------------------- = -----------------------------------------Vac max Vac max (11) Where: • Pomax is the maximum output power of the flyback • 1.1 is a factor to compensate for the dead time between zero current in the PFC inductor at the end of the secondary stroke and the detection of the first valley in QR mode • is the expected efficiency of the total converter at maximum output power • Vacmin is minimum mains input voltage 5. Flyback description and calculation The flyback of the TEA1751(L)T is a variable frequency controller that can operate in Quasi Resonant (QR) or Discontinuous Conduction mode with demagnetization detection and valley switching. The setting of the primary peak current controls the output power; the switching frequency is a result. The primary peak current is set through the voltage at the FBCTRL pin and measured back at the FBSENSE pin with the following relationship: V sense FB 0.75 V FBCTRL – 1 V (12) The flyback controls the operational mode of the PFC. At low output powers, when the primary peak current, Ip 0.25 Ip max the PFC is switched off. Demagnetization of the flyback transformer is detected through pin FBAUX, connected to the auxiliary winding. The valley is detected through the HV pin, which can be connected to the MOSFET drain or to the center tap of the primary winding. The input voltage of the flyback is measured through pin FBAUX and used to implement and OverPower Protection (OPP). The OPP keeps the maximum output power of the flyback constant over the input voltage. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 19 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller The flyback has an accurate OverVoltage Protection (OVP) circuit. The overvoltage is measured, through pin FBAUX. Both controllers are switched off in a latched protection when an overvoltage is detected. 5.1 Flyback output power control An important aspect of the TEA1751(L)T flyback system is, that the setting of the primary peak current controls the output power. The switching frequency is a result of external application parameters and internal IC parameters. External application parameters are the transformer turns ratio, the primary inductance, the drain source capacitance, the input voltage, the output voltage and the feedback signal from the control loop. Internal IC parameters are the oscillator setting, the setting of the peak current and the detection of demagnetization and valley. The output power of flyback can be described with the equation: 1 2 P o = --- L p L p f s 2 (13) At initial start-up, the flyback always starts at the maximum output power. From maximum to minimum output power, the flyback goes through the three operation modes as shown Figure 12. fsw(fb)max PFC off PFC on frequency reduction switching frequency discontinuous with valley switching quasi resonant output power 014aaa158 Fig 12. Operation modes flyback At maximum output power, limited by the flyback current sense resistor, the flyback operates in Quasi Resonant (QR) mode. The next primary switching cycle starts at detection of the first valley. By reducing the peak current, the output power is reduced and as a result the switching frequency goes up. When the maximum flyback switching frequency is reached and the output power still must be reduced, the flyback goes from QR into Discontinuous mode (DCM) with valley switching. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 20 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller In DCM, the output power is reduced by further reduction of the peak current and at the same time skipping of one or more valleys. In this mode, the switching frequency is kept constant. The exact switching frequency however, depends on the detection of the valley but is never higher as the maximum frequency. The minimum flyback peak current: Ip min = 0.25 Ip max . At this point, the flyback enters the Frequency Reduction mode and the PFC is set in Burst mode. In the Frequency Reduction mode, the peak current is kept constant. Increasing the off time reduces the output power. Place a 10 nF noise filter capacitor (C15) as close as possible to the FBTRL pin to avoid disturbance of the flyback by switching of the PFC MOSFET. 5.1.1 Calculation of the flyback current sense resistor The current sense resistor ROCP(fb) can be calculated with Equation 14: V sense fb max 0.52 V R OCP fb = ------------------------------- = ---------------------------Ip QR fb max Ip QR fb max (14) For the flyback operating in Quasi Resonant mode the peak current can be calculated with Equation 15: Ip QR fb max Np Vdc min + ------ V o 2Po max 1.1 Ns = ------------------------------ ---------------------------------------- Vdc min Np ------ V o Ns (15) Where: • Pomax is the maximum output power of the flyback • 1.1 is a factor that compensates for the dead time between zero current in the flyback transformer at the end of the secondary stroke and the detection of the first valley in QR mode • is the expected efficiency of the flyback at maximum output power Vdcmin is minimum bulk electrolytic capacitor voltage in PFC Burst mode as follows: V burst L 1.92 V Vdc min = Vo PFC ----------------------------------- = Vo PFC --------------- V reg VOSENSE 2.5 V • Vo is the output voltage • Np is the number of primary turns of the flyback transformer • Ns is the number of secondary turns of the flyback transformer. 5.1.2 Calculation of the flyback soft start components The soft start is implemented through the RC network at pin FBSENSE. Rss1 must have a minimum value of 12 k as specified. This to ensure that the voltage Vstart(soft)PFC of 0.5 V is reached to enable start-up of the flyback. See Section 3.1 for start-up description. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 21 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller The total soft start or soft stop time is equal to: t softstart = 3Rss Css . Make the soft start time for the flyback larger than the soft start time of the PFC, to ensure that the PFC starts before the flyback at initial start-up. It is also advisable to keep the soft start time in a range of 5 ms to 10 ms. With C10 = 220 nF and R16 = 12 k the total soft start time is 8 ms. 5.2 Flyback control of PFC Burst mode The flyback controls the operation mode of the PFC. At low output powers, when the primary peak current Ip 0.25 Ip max , the PFC is switched off. This is the same point as when the flyback enters the Frequency Reduction mode, see Figure 12 and Section 4.1. On the transition from PFC Normal mode to Burst mode and from Burst mode to Normal mode is a hysteresis of 60 mV on Vhys(FBCTRL). This provides the possibility of smooth transitions for all applications. To guarantee a smooth transition from PFC off to PFC on and to avoid audible noise in flyback transformer, place the 10 nF noise filter capacitor C15 as close as possible to the FBTRL pin . 5.3 Flyback protections 5.3.1 Short circuit on the FBCTRL pin If the pin is shorted to ground, switching of the flyback controller is inhibited. This situation is equal to the minimum, or a no output power situation. 5.3.2 Open the FBCTRL pin As shown in Figure 13. the FBCTRL pin is connected to an internal voltage source of 3.5 V via an internal resistor of 3 k. When the voltage on pin FBCTRL is above 2.5 V, this connection is disabled and the FBCTRL pin is biased with an internal 30 A current source. When the voltage on the FBCTRL pin rises above Vto(FBCTRL) of 4.5 V, a fault is assumed. Switching of the flyback (and also the PFC) is blocked and the controller enters the Safe Restart mode. An internal switch pulls the FBCTRL pin down when the flyback is disabled. 5.3.3 Time-out flyback control-loop A time-out function can be realized to protect for an output short circuit at initial start-up or for an open control loop situation. This can be done by placing a resistor in series with a capacitor between the FBCTRL pin and ground. See Figure 13. Above 2.5 V the switch in series with the resistor of 3 k is opened and pin FBCTRL and thus the RC combination is biased with a 30 A current-source. When the voltage on FBCTRL pin rises above 4.5 V, switching of the flyback (and also the PFC) is blocked and the controller enters the Safe Restart mode. The capacitor can be used to set the time to reach 4.5 V at the FBCTRL pin. The resistor is necessary to separate the relative large time-out capacitor from the control loop response. Use a resistor of at least 30 k. The resistor however, also influences the charge time of the capacitor. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 22 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller The time-out time tto can be calculated with Equation 16: C to V to FBCTRL – I O FBCTRL R to t to = --------------------------------------------------------------------------------------------------I O FBCTRL (16) Otherwise the capacitor can be calculated with Equation 17: I O FBCTRL t to C to = -------------------------------------------------------------------------------V to FBCTRL – I O FBCTRL R to (17) Or the resistor can be calculated with Equation 18: v to FBCTRL t to R to = ---------------------------- – -------I O FBCTRL C to (18) A tto of 37 ms in combination with a Cto of 330 nF leads to a resistor value of: 4.5 V 37 ms R to = --------------- – ------------------ = 37.9 k 39 k 30 A 330 nF When the time-out protection is not required, placing a resistor of 100 k between pin FBCTRL and ground can disable the time-out protection. 2.5 V 3.5 V 30 μA 4.5 V 3 kΩ FBCTRL time-out 014aaa049 a. Circuit diagram 4.5 V 2.5 V VFBCTRL output voltage intended output voltage not reached within time-out time. restart intended output voltage reached within time-out time. 014aaa050 b. Timing diagram Fig 13. Time-out protection AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 23 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller 5.3.4 Overvoltage protection flyback The IC has an internal OverVoltage Protection (OVP) circuit, which switches off both controllers when an overvoltage is detected at the output of the flyback, by a latched protection. The IC can detect an overvoltage at a secondary winding of the flyback by measuring the voltage at the auxiliary winding during the secondary stroke. A series resistor between the auxiliary winding and the FBAUX pin converts this voltage to a current on the FBAUX pin. D5 T1 VCC C13 1 PRIM D23A D10 TEA1751 2 4 R23 FBAUX AUX SEC ROVP = R23 ROPP = R23 + R23A 014aaa774 Fig 14. Flyback OVP and OPP circuit At a current Iovp(FBAUX) of 300 A into the FBAUX pin, the IC detects an overvoltage. An internal integrator filters noise and voltage spikes. The output of the integrator is used as an input for an up-down counter. The counter has been added as an extra filter to prevent false OVP detection, which might occur during ESD or lightning events. If the integrator detects an overvoltage, the counter increases its value by one. If another overvoltage is detected during the next switching cycle, the counter increases its value by one again. If no overvoltage is detected during the next switching cycle, then the counter will subtract its value by two (the minimum value is 0). If the value reaches 8, the IC assumes a true overvoltage, and activates the latched protection. Both converters are switched off immediately and VCC starts cycling between the Vth(UVLO) and Vstartup, without a restart. Switching off and then switching on the mains input voltage, triggers the fast latch reset circuit, and reset the latch. The OVP level can be set by the resistor ROVP: R OVP AUX N ------------ Vo OVP – V clamp FBAUX – Vf D23A Ns = ----------------------------------------------------------------------------------------------------------- = I OVP FBAUX AUX N ------------ Vo OVP – 0.7 typ – Vf D23A Ns ----------------------------------------------------------------------------------------(19) 300 A typ Where: • • • • AN10789 Application note Ns is the number of turns on the secondary winding Naux is the number of turns on the auxiliary winding of the flyback transformer Vclamp(FBAUX) is the positive clamp voltage of the FBAUX pin VfD23A is the forward voltage of D23A at a current of 300 A All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 24 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller For the calculation of the VoOVP level, the tolerances on Iovp(FBAUX) must be taken into account, this to avoid triggering of the OVP during normal operation. 5.3.5 OverPower Protection (OPP) In a quasi-resonant flyback, the maximum output power is dependent on the (mains) input voltage. To compensate for this, an OPP is implemented. During the primary stroke of the flyback the mains voltage is sensed by measuring the current drawn from pin FBAUX. See Figure 14, with a resistor between the flyback auxiliary winding and pin FBAUX the voltage at the auxiliary winding is converted into a current IFBAUX. The IC is using the current information to reduce the setting of the maximum flyback peak current measured through pin FBSENSE. See Figure 15 for the limitation of the maximum VFBSENSE level as a function of IFBAUX. 014aaa096 0.6 VFBSENSE (V) 0.52 0.5 0.4 0.37 0.3 −400 −360 −300 −200 −100 0 IFBAUX (μA) Fig 15. Operation modes flyback See Figure 14, the total OPP resistance determining the IFBAUX current during the primary stroke of the flyback exists of R23 + R23A. First, the OVP resistor R23 has to be calculated before the remaining part of the OPP resistor R23A can be calculated. The value of R23A can be calculated with Equation 20: N -----a- Vo PFC LOW – V clamp FBAUX Np R23A = ----------------------------------------------------------------------------------- = I start OPP FBAUX N -----a- 240 V – 0.8 V Np -------------------------------------------- – R OVP 100 A (20) 6. Summary of calculations See Figure 1 “Application schematic” for component reference numbers. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 25 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller 7. PCB layout considerations A good layout is an important part of the final design. It minimizes many kinds of disturbances and makes the overall performance more robust with less risk of EMI. Guidelines for the improvement of the layout of the PCB are as follows: • Separate large signal grounds from small signal grounds (see Figure 17). A triangular symbol indicates small signal grounds. All other ground symbols are related to large signal grounds. • Make the print area within the indicated large signal loops (see Figure 17) as small as possible. Each indicated large signal loop has its own color. Make the copper tracks as short and wide as possible. • The connection between both MOSFETs (PFC and flyback) and the IC driver outputs must be as short as possible (green line in Figure 17). Use wide tracks. Increase the distance between the copper tracks and/or preferably use a separate guided ground track for both connections minimizing the coupling between the PFCDRIVER and FBDRIVER. A circuit diagram according to Figure 16 can be added if it is impossible to place the MOSFET and the IC close to each other. • The power ground and small signal ground are only connected with one short copper track (make this track as short and as wide as possible). Preferably, it should become one spot (connection between ground 4a and ground 6a, shown as a blue line in Figure 17). • Use a ground shield underneath the IC, connect this ground shield to the GND pin of the IC. • Connect all series connected resistors that are fixed to an IC pin as close as possible to that pin. • Connect heat sinks which are connected to the nearest corresponding ground signal component. Make this connection as short as possible. Connect the heat sink of diode bridge BD1 to ground 1, Q1 to 4, and Q2 to 4b. In typical applications, all three components are often mounted on a single heat sink. If so, make one wide copper track that connects all three grounds to each other. Also combine in this copper track ground 2. • Connect the grounds of 6b to each other. • Make a local "star ground" from grounds 6a, 6b, 6c, and 7. Ground 6a is the middle of the star and is connected to the GND pin (the ground of the IC). • Grounds marked 7 do not have to be a star ground. • Place the Y-capacitor across grounds 1 and 8. Use one copper track, separated from all others for this connection. Alternatively, in a typical application setup, use the heat sinks connection copper track for this purpose. • Place C4, C15 and C7 (in order of priority) as close as possible to the IC. Reduce coupling between the PFC switching signals (PFC driver and PFCAUX) and the flyback sense signals (FBSENSE and FBCTRL) as much as possible. The coupling reduction minimizes the risk of electromagnetic interference and audible noise. • Figure 17 shows an overview of the hierarchy of the different grounds at the bottom. Connect the anode of the TL431 (ground 8) to ground 9 using one special separately connecting copper track. Minimize all other currents in this special track. Make the connection as close as possible to the output. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 26 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller Remark: Use the circuit shown in Figure 16 when the distance between the IC drive output and corresponding MOSFET are relatively large. LQSXW ,& '5,9(5 5FK 'FK 4VZLWFK 4GFK *1' 5GFK 5VHQVH DDD Transistor is mounted close to the MOSFET with wide and short tracks. Fig 16. Switching off the MOSFET when the distance between IC and MOSFET is large AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 27 of 31 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx %' & 5 & & & *1' ' ' /) 5 &; ' 5 4 5 5 & 5 5 5 5 & & 5 E 5 9&& +9 )%6(16( +96 926(16( & E 7($ 5 5 5 E )%$8; 5$ '$ & 5$ &$ E 5 )%&75/ 3)&&203 8 /$7&+ 3)&$8; *1' 3)&'5,9(5 5 ' 9,16(16( 8 +96 ) 3)&6(16( & 5 5 /) PDLQV LQOHW 4 & 5 & 57 & 5 5 & 8 & 5 & 5 & & 5 &< Fig 17. TEA1751 PCB layout considerations D F D D E E DDD AN10789 28 of 31 © NXP B.V. 2013. All rights reserved. ODUJHVLJQDOFXUUHQWORRS ODUJHVLJQDOFXUUHQWORRS ODUJHVLJQDOFXUUHQWORRS GreenChip III TEA1751: integrated PFC and flyback controller Rev. 1.1 — 4 September 2013 All information provided in this document is subject to legal disclaimers. & )%'5,9(5 5 5 5 D F & / 9RXW & ' NXP Semiconductors AN10789 Application note ' / AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller 8. References AN10789 Application note [1] IEC-60950 — Chapter 2.1.1.7 “Discharge of capacitors in equipment” [2] IEC61000-3-2 — All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 29 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller 9. Legal information 9.1 Definitions Draft — The document is a draft version only. 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It shall be operated in a designated test area by personnel that is qualified according to local requirements and labor laws to work with non-insulated mains voltages and high-voltage circuits. The product does not comply with IEC 60950 based national or regional safety standards. NXP Semiconductors does not accept any liability for damages incurred due to inappropriate use of this product or related to non-insulated high voltages. Any use of this product is at customer’s own risk and liability. The customer shall fully indemnify and hold harmless NXP Semiconductors from any liability, damages and claims resulting from the use of the product. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 9.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP B.V. AN10789 Application note All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 4 September 2013 © NXP B.V. 2013. All rights reserved. 30 of 31 AN10789 NXP Semiconductors GreenChip III TEA1751: integrated PFC and flyback controller 10. Contents 1 1.1 1.2 1.2.1 1.2.2 1.2.3 1.2.4 1.3 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.5 3.6 3.7 4 4.1 4.1.1 4.1.2 4.2 4.2.1 4.3 4.3.1 4.3.2 4.3.3 4.3.4 5 5.1 5.1.1 5.1.2 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 6 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 The TEA1751 GreenChip III controller . . . . . . . 3 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 System features . . . . . . . . . . . . . . . . . . . . . . . . 3 PFC features . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Flyback features . . . . . . . . . . . . . . . . . . . . . . . . 4 Application schematic . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 6 System description and calculation. . . . . . . . . 8 PFC and flyback start conditions . . . . . . . . . . . 8 Start-up sequence. . . . . . . . . . . . . . . . . . . . . . . 8 VCC cycle at safe restart protections. . . . . . . . 10 Mains voltage sensing and brownout . . . . . . . 10 Discharge of mains input capacitor. . . . . . . . . 10 Brownout voltage adjustment . . . . . . . . . . . . . 11 Internal OTP . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LATCH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . 12 PFC description and calculation . . . . . . . . . . 12 PFC output power and voltage control . . . . . . 13 Setting the PFC output voltage. . . . . . . . . . . . 14 Calculation of the PFC soft start and stop components . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PFC demagnetizing and valley detection . . . . 16 Design of the PFCAUX winding and circuit . . 17 PFC protections . . . . . . . . . . . . . . . . . . . . . . . 18 VOSENSE OverVoltage Protection (OVP) . . . 18 VOSENSE open and short pin detection . . . . 18 VINSENSE open pin detection . . . . . . . . . . . . 18 OverCurrent Protection (OCP) . . . . . . . . . . . . 18 Flyback description and calculation . . . . . . . 19 Flyback output power control . . . . . . . . . . . . . 20 Calculation of the flyback current sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . 21 Calculation of the flyback soft start components . . . . . . . . . . . . . . . . . . . . . . 21 Flyback control of PFC Burst mode . . . . . . . . 22 Flyback protections. . . . . . . . . . . . . . . . . . . . . 22 Short circuit on the FBCTRL pin . . . . . . . . . . . 22 Open the FBCTRL pin . . . . . . . . . . . . . . . . . . 22 Time-out flyback control-loop . . . . . . . . . . . . . 22 Overvoltage protection flyback . . . . . . . . . . . . 24 OverPower Protection (OPP) . . . . . . . . . . . . . 25 Summary of calculations . . . . . . . . . . . . . . . . 25 PCB layout considerations . . . . . . . . . . . . . . . 26 8 9 9.1 9.2 9.3 10 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 30 30 30 30 31 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 September 2013 Document identifier: AN10789