Migration from T89C51RD2 to AT89C51RD2/ED2 This application note is a guide to assist current T89C51RD2 users in converting existing designs to the AT89C51RD2/ED2 devices. In addition to the functional changes, the electrical characteristics of the AT89C51RD2/ED2 are different including an increase in operating power supply range. Check the datasheet for detailed information. 8051 Microcontrollers To permit an easy migration, this application note compares the features, memory organization/accesses, SFRs and bootloader functionality. Application Note Feature Comparison Description T89C51RD2 64K bytes Program Memory In-System Programming (ISP) (63K bytes user Flash memory and 1K bytes Flash bootloader) 1K byte Flash bootloader mapped in the upper 64K bytes user Flash including serial ISP and Flash API AT89C51RD2/ED2 Full 64K bytes program/code memory 2K bytes ROM bootloader overlapped with user Flash including fast serial ISP and Flash API RAM 256 bytes 256 bytes XRAM 1024 bytes 1792 bytes 2048 bytes 2048 bytes 64 bytes page write byte write (ED2 only) Yes (3) Yes (3) CPU & Programmable separately by peripherals CPU & Programmable separately by peripherals SPI Interface No Yes Keyboard Interface No Yes (8 inputs) Prescaler No Yes Baud Rate Generator No Yes 5 10 40 MHz X1 mode 40 MHz X1 mode 20 MHz X2 mode 20 MHz X2 mode 4.5 to 5.5V (M version) Unique Operating Voltage: 2.7V to 5.5V On-Chip EEPROM data 16-bit Timers X2 Mode Internal Interrupt sources Maximum Frequency @ 5V Power Supply Pinout 2.7 to 3.3V (L version) T89C51RD2 and AT89C51RD2/ED2 are pinout compatible. Rev. 4239B–8051–06/03 1 Memory Organization Code Memory Organization T89C51RD2 has a single 64K bytes code memory area including 63K bytes of program/code Flash memory and the upper 1K bytes dedicated for bootloader (serial ISP and Flash API). The AT89C51RD2/ED2 implements 64K bytes of on-chip program/code memory and a standalone 2K bytes ROM for bootloader (serial ISP and Flash API). By default the microcontroller addresses the 64K bytes of on-chip Flash program/code memory. To address the upper 2K bytes ROM bootloader, the ENBOOT bit in AUXR1 register must be set (to access Flash API from user application for example). Figure 1. Code Memory Organization FFFFh 1K byte Flash Bootloader FFFFh 2K bytes ROM Bootloader FC00h F800h 64K Bytes Flash Memory User Space 63K Bytes Flash Memory User Space 0000h T89C51RD2 On-chip RAM/XRAM Memory 0000h AT89C51RD2/ED2 Both T89C51RD2 and AT89C51RD2/ED2 have 256 bytes of scratch pad RAM. The AT89C51RD2/ED2 has 1792 bytes of internal XRAM, whereas the T89C51RD2 has only 1024 bytes. By default AT89C51RD2/ED2 has 768 bytes of on-chip XRAM selected after reset to ensure software compatibility with T89C51RD2. 2 Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 Migration from T89C51RD2 to AT89C51RD2/ED2 On-chip EEPROM Data Both T89C51RD2 and AT89C51ED2 have 2K bytes of EEPROM for data storage. AT89C51RD2 has no on-chip EEPROM. Thus when migrating from an application using EEPROM data, the AT89C51ED2 device should be used. EEPROM Data Write Access The main difference between the products is the write activation sequence for the onchip EEPROM data. AT89C51RD2/ED2 is single-write byte only access, thus no page write mode is available. Figure 2. Recommended EEPROM Data Write Sequences (1) EEPROM Data Write Sequence Setup EETIM EEPROM Data Write Sequence Save & Disable IT EA = 0 Column Latches Mapping EECON = 02h (EEE = 1) EEBusy Cleared? Data Load DPTR= Address ACC= Data Exec: MOVX @DPTR, A Save & Disable IT EA = 0 EEPROM Data Mapping EECON = 02h (EEE = 1) Last Byte to Load? Data Write DPTR = Address ACC = Data Exec: MOVX @DPTR, A Column Latches Mapping EECON = 00h (EEE = 0) EEPROM Mapping EECON = 00h (EEE = 0) Restore IT Launch Programming EECON= 5Xh EECON= AXh Restore IT Last Byte to Load? EEBusy Cleared? Typ 10 ms T89C51RD2 AT89C51RD2/ED2 Note 1. Due to trouble T15 (see T89C51RD2 erratasheet), the write sequence may be executed 3 times. 3 4239B–8051–06/03 As shown in Figure 2, EEPROM data in AT89C51ED2 is single byte access for read and write accesses. Writing EEPROM data for AT89C51ED2 is simpler than in T89C51RD2: • Load DPTR with the EEPROM address • Load ACC with the EEPROM data • Set EEE bit • Execute MOVX @DPTR, A • Wait for EEBUSY flag to be clear before launching a new writing sequence AT89C51ED2 does not need to setup any write time register as EETIM register for T89C51RD2. Write mechanism on EEPROM data is auto-timed and independent from the microcontroller running frequency. EEPROM Data Read Access The EEP ROM da ta read sequenc e is the same between T89C5 1RD2 and AT89C51RD2/ED2 and does not imply any user software application modification. Figure 3. Recommended EEPROM Data Read Sequence for Both Products EEPROM Data Read Sequence EEBusy Cleared? Save & Disable IT EA= 0 EEPROM Data Mapping EECON = 02h (EEE=1) Data Read DPTR = Address ACC = Data Exec: MOVX A, @DPTR Last Byte to Read? EEPROM Data Mapping EECON = 00h EEE = 0 Restore IT 4 Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 Migration from T89C51RD2 to AT89C51RD2/ED2 Hardware Configuration Byte (HSB) The Hardware Configuration Byte defines the start-up conditions at reset: • enable or disable X2 mode (X2 bit) • enable or disable on-chip XRAM • force bootloader execution after reset (BLJB: Bootloader Jump Bit) For T89C51RD2 HSB is accessible using parallel programmers. The AT89C51RD2/ED2 introduces the capability to change X2 and BLJB bits from ISP or In Application Programming (self-programming), all other bits (XRAM, and LB3:1) remain accessible using parallel programming only (like T89C51RD2). Table 1. Hardware Configuration Byte (HSB) HSB 7 T89C51RD2 AT89C51RD2/ED2 X2 6 5 4 BLJB BLLB - BLJB - - 3 XRAM 2 1 0 LB3 LB2 LB1 LB3 LB2 LB1 AT89C51RD2/ED2 features a new XRAM bit to disable the on-chip XRAM. There is no BLLB bit in the AT89C51RD2/ED2 since bootloader code is in ROM memory and there is no need to protect it from hazardous write sequences. As HSB byte has no software access on T89C51RD2, the AT89C51RD2/ED2 HSB behavior does not require application modification. 5 4239B–8051–06/03 SFR Mapping Table 2 contains an SFR comparison between previous and new products. Table 2. SFR Mapping Bit Addressable 0/8 F8h F0h E8h 1/9 2/A 3/B 4/C 5/D 6/E CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX P5 bit addressable CL CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX E7h CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 00XX X000 X000 0000 X000 0000 X000 0000 X000 0000 X000 0000 D0h PSW 0000 0000 FCON XXXX 0000 EECON xxxx xx00 C8h T2CON 0000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 B8h B0h A8h A0h 98h 90h 88h 80h EFh ACC 0000 0000 CCON C0h FFh F7h 00X0 0000 D8h 7/F B 0000 0000 1111 1111 E0h Non Bit Addressable D7h RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 P4 SPCON SPSTA SPDAT 1111 1111 0001 0100 0000 0000 XXXX XXXX IPL0 SADEN X000 000 0000 0000 DFh CFh P5 byte Addressable C7h 1111 1111 BFh P3 IEN1 IPL1 IPH1 IPH0 1111 1111 XXXX X000 XXXX X000 XXXX X111 X000 0000 IEN0 SADDR CKCON1 0000 0000 0000 0000 XXXX XXX0 P2 AUXR1 WDTRST WDTPRG 1111 1111 XXXX X0X0 XXXX XXXX XXXX X000 SCON SBUF BRL BDRCON KBLS KBE KBF 0000 0000 XXXX XXXX 0000 0000 XXX0 0000 0000 0000 0000 0000 0000 0000 B7h AFh A7h 9Fh P1 97h 1111 1111 TCON TMOD TL0 TL1 TH0 TH1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 0/8 1/9 2/A 3/B AUXR XX00 1000 CKCON0 0000 0000 PCON 00X1 0000 4/C 5/D 6/E 8Fh 87h 7/F Modified Registers New Registers 6 Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 Modified Registers For modified SFR, the reset value may have changed from T89C51RD2. The AT89C51RD2/ED2 introduces several new bits in these SFR in place of reserved bits. Thus, if the software application on T89C51RD2 ignores these bits (logically masked), no code modification is needed to use AT89C51RD2/ED2 devices. Table 3. AUXR Register AUXR Register (SFR:8Eh) AUXR T89C51RD2 Reset value: xxxx xx00b 7 6 5 4 3 2 1 0 - - M0 - XRS1 XRS0 EXTRAM A0 DPU - M0 XRS2 XRS1 XRS0 EXTRAM A0 AT89C51RD2/ED2 Reset value: 0x0x 000’HSB.XRAM’0b AT89C51RD2/ED2 introduces several new bits, for internal XRAM sizing, stretch MOVX and disable weak pull-up (see AT89C51RD2/ED2 datasheet for details). The default configuration is compatible with T89C51RD2, therefore no special modification is needed. Table 4. AUXR1 Register AUXR1 Register (SFR:A2h) AUXR1 T89C51RD2 Reset value: xxxx x0x0b AT89C51RD2/ED2 Reset value: xxxx x0x0b 7 6 5 4 3 2 1 0 - - - - GF3 0 - DPS - - ENBOOT - GF3 0 - DPS AT89C51RD2/ED2 features the ENBOOT bit to map the ROM bootlloader area in the logical addressable space of the microcontroller. This special bit must be set before calling the common API entry point in the bootloader. Thus if the software application calls the API from the bootloader, the API call sequence must be modified (set ENBOOT before the “LJMP 0FFF0h” instruction). Table 5. CKCON0 Register CKCON0 Register (SFR:8Fh) CKCON0 T89C51RD2 Reset value: x000 0000b AT89C51RD2/ED2 Reset value: 0000 0000b 7 6 5 4 3 2 1 0 - WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 SPIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 The CKON register has been renamed to CKON0 register in AT89C51RD2/ED2. It introduces a new bit (SPIX2) to access the X2 mode of the SPI interface. If the application ignores this bit, no code modification is needed. Table 6. EECON Register EECON Register (SFR:D2h) EECON 7 7 6 5 4 3 2 1 0 Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 Table 6. EECON Register EECON Register (SFR:D2h) T89C51RD2 Reset value: 0000 xx00b AT89C51ED2 Reset value: xxxx xx00b EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY - - - - - - EEE EEBUSY The EECON register has been modified in AT89C51RD2/ED2. This implies code modification for write access to the on-chip EEPROM data of AT89C51ED2 device (see Figure 2 for typical write sequence). The on-chip EEPROM data read access operation in AT89C51ED2 is the same as in T89C51RD2 (see Figure 3 for a typical read sequence). Table 7. IEN0 Register IEN0 Register (SFR:A8h) IEN0 T89C51RD2 Reset value: 0000 0000b AT89C51RD2/ED2 Reset value: 0000 0000b 7 6 5 4 3 2 1 0 EA EC ET2 ES ET& EX1 ET0 EXO EA EC ET2 ES ET& EX1 ET0 EXO The IE register has been renamed to IEN0 register in AT89C51RD2/ED2. Table 8. IPL0Register IPL0 Register (SFR:B8h) IPL0 T89C51RD2 Reset value: 0000 0000b AT89C51ED2 Reset value: 0000 0000b 7 6 5 4 3 2 1 0 - PPCL PT2L PLS PT1L PX1L PT0L PX0L - PPCL PT2L PLS PT1L PX1L PT0L PX0L The IPL register has been renamed to IPL0 register in AT89C51RD2/ED2. Table 9. IPH0Register IPH0 Register (SFR:B7h) IPH0 T89C51RD2 Reset value: 0000 0000b AT89C51RD2/ED2 Reset value: 0000 0000b 7 6 5 4 3 2 1 0 - PPCH PT2H PHS PT1H PX1H PT0H PX0H - PPCH PT2H PHS PT1H PX1H PT0H PX0H The IPH register has been renamed to IPH0 register in AT89C51RD2/ED2. New Registers In T89C51RD2, the memory locations of the new registers were previously unused. Thus migrating from T89C51RD2 to the new AT89C51RD2/ED2 does not require code modification for these SFR addresses. Prescaler System The prescaler interface uses the SFR: CKRL (SFR:97h) 8 Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 Baud Rate Generator These registers are used for the Baud Rate Generator: BDRCON (SFR:9Bh), BRL (SFR:9Ah). SPI Interface The SPI interface uses the registers: SPCON (SFR:C3h), SPSTR (SFR:C4h), SPDAT (SFR:C5h). Keyboard Interface These registers control the keyboard interface: KBLS (SFR:9Ch), KBE (SFR:9Dh), KBF (SFR:9Eh). New Interrupt Controller The IPL1 (SFR:B2h), IPH1 (SFR:B3h), IEN1 (SFR: B1h). 9 Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 Bootloader Behavior In-System Programming Features Bootloader Activation Both products have the same boot process (see Figure 4), Serial ISP can be activated in two ways: hardware or software conditions (according to BLJB, and BSB values). Figure 4. Boot Process Hardware RESET Hardware Conditions? BLJB=1 Yes (PSEN = 0, EA = 1, and ALE =1 or not connected) BLJB!= 0 ? ENBOOT=0 (for AT89C51RD2/ED2) Software BSB = 00h ? PC = 0000h SBV = FCh ? USER APPLICATION USER Bootloader Atmel Bootloader PC = [SBV]00h 10 Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 ISP Commands The serial ISP protocol for AT89C51RD2/ED2 is very similar to the T89C51RD2. Table 10 summarizes the ISP commands for T89C51RD2 and AT89C51RD2/ED2, highlighted cells indicate the commands that differ between the two products. Table 10. ISP Commands Comparison Table Command Function Command Command Name Data[0] Data[1] T89C51RD2 Program Nb Data Byte. 00h Bootloader will accept up to 16 (10h) data bytes. The data bytes should be 128 byte page Flash boundary. Program Data 01h AT89C51RD2/ED2 Same as for T89C51RD2 except that the command allows up to 128 (80h) data bytes. 00h Erase block0 (0000h-1FFFh) 20h Erase block1 (2000h-3FFFh) 40h Erase block2 (4000h-7FFFh) 80h Not Implemented Erase block3 (8000h- BFFFh) C0h Erase block4 (C000h- FFFFh) 00h Hardware Reset 01h Ljmp Address (data[2:3]= Address) 03h 04h 03h Write Function 00h Erase SBV & BSB 00h Program SSB level 1 01h Program SSB level 2 00h Program BSB (value to write in data[2]) 01h Program SBV (value to write in data[2]) - Full Chip Erase 05h Same as T89C51RD2 06h 07h 04h Not Implemented 0Ah Program X2 fuse (value to write in data[2]) 08h Data[0:1] = start address 04h Display Function Display Data Data [2:3] = end address Data[4] = 00h -> Display data Program BLJB fuse (value to write in data[2]) Same as T89C51RD2 Blank Check Data[4] = 01h -> Blank check 11 Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 Table 10. ISP Commands Comparison Table (Continued) Command Function Command Command Name Data[0] Data[1] T89C51RD2 00h Manufacturer Id 01h Device Id #1 02h Device Id #2 03h Device Id #3 00h Read SSB 01h Read BSB 02h Read SBV 03h Read Hardware Byte Not Implemented 06h Not Implemented Read Extra Byte 08h 00h Read Bootloader Version Not Implemented 0Bh 00h Not Implemented Read Hardware Byte 00h Read Device Boot ID1 01h Read Device Boot ID2 00h Not Implemented AT89C51RD2/ED2 00h Same as T89C51RD2 Same as T89C51RD2 07h 05h Same as T89C51RD2, but return value is different Read Function 0Eh Same as T89C51RD2 0Fh Read Bootloader Version The commands: “Read Hardware Byte” and “Read Bootloader Version” have a different transmission frame from T89C51RD2 to AT89C51RD2/ED2. The ISP command “Read SSB” is the same, but the returned value is different. In fact the SSB byte has different coding value from T89C51RD2 to AT89C51RD2/ED2. Table 11 shows the coding values for SSB byte in both products. Table 11. Cross Reference SSB Values SSB Value Software Security Level T89C51RD2 AT89C51RD2/ED2 0 0xFF 0xFF 1 0x10 0xFE 2 0x00 0xFC Note: 12 FLIP is a PC software application running under Windows® 9X/2000/XP, Windows NT® and LINUX® that supports both products and makes the ISP protocol differences transparent for the end-user. This software is available from the Atmel web site. Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 In-Application Programming Capabilities (SelfProgramming) The AT89C51RD2/ED2 implements all API from the T89C51RD2 and a set of new functionalities. The API entry point is similar in both products (“LCALL FFF0h”) in the bootloader. The major modification deals with the memory management. It is required to enable the ROM bootloader area before calling the common entry point (see Figure 5). Figure 5. Recommended API Call Sequence API CALL Sequence API CALL Sequence Save & Disable IT EA = 0 Save & Disable IT EA = 0 Setup Parameters DPL, DPH, R1, ACC Setup Parameters DPL, DPH, R1, ACC Call API LCALL FFF0h Map Bootloader ENBOOT=1 API Execution Restore IT Call API LCALL FFF0h API Execution UnMap Bootloader ENBOOT=0 Restore IT T89C51RD2 13 AT89C51RD2/ED2 Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 Table 12 summarizes the API calls for both products, greyed cells highlight API with different behavior from T89C51RD2 to AT89C51RD2/ED2. Table 12. API Call Comparison Table Command Effect Command R1 A DPTR0 DPTR1 Returned Value T89C51RD2 READ MANUF ID 00h XXh 0000h XXh ACC = Manufacturer ID READ DEVICE ID1 00h XXh 0001h XXh ACC = Device ID1 Read Device identifier 1 AT89C51RD2/ED2 Read Manufacturer identifier Same as T89C51RD2 READ DEVICE ID2 00h XXh 0002h XXh ACC = Device ID2 Read Device identifier 2 READ DEVICE ID3 00h XXh 0003h XXh ACC = Device ID3 Read Device identifier 3 DPH = 00h 00h ACC = DPH Erase block 0 DPH = 20h ERASE BLOCK PROGRAM DATA BYTE 01h 02h XXh Byte value to program Erase block 1 DPH = 40h Not implemented Erase block 2 DPH = 80h Erase block 3 DPH = C0h Erase block 4 Address of byte to program ACC = 0: DONE Program one Data Byte in user Flash ACC = FCh Erase Software boot vector and boot status byte. (SBV = FCh and BSB = FFh) Same as T89C51RD2 ERASE BOOT VECTOR 04h XXh XXh XXh DPH = 00h Set SSB level 1 DPL = 00h DPH = 00h PROGRAM SSB Set SSB level 2 DPL = 01h 05h XXh 00h ACC = SSB value DPH = 00h Same as T89C51RD2, but returned values are different See Table 11. Set SSB level 0 DPL = 10h DPH = 00h Set SSB level 1 DPL = 11h PROGRAM BSB 06h New BSB value 0000h XXh none Program boot status byte PROGRAM SBV 06h New SBV value 0001h XXh none Program software boot vector READ SSB 07h XXh 0000h XXh ACC = SSB Read Software Security Byte Same as T89C51RD2 Same as T89C51RD2, but returned values are different. See Table 11. READ HSB 07h XXh 0004h XXh ACC = HSB Read Hardware Byte READ BSB 07h XXh 0001h XXh ACC = BSB Read Boot Status Byte READ SBV 07h XXh 0002h XXh ACC = SBV Read Software Boot Vector 14 Same as T89C51RD2 Migration from T89C51RD2 to AT89C51RD2/ED2 4239B–8051–06/03 Migration from T89C51RD2 to AT89C51RD2/ED2 Table 12. API Call Comparison Table (Continued) Command Effect Command READ BOOT VERSION PROGRAM DATA PAGE PROGRAM X2 FUSE R1 A DPTR0 DPTR1 Returned Value 08h XXXXh XXh XXh ACC = Boot_Version 09h 0Ah Number of byte to program Fuse value 00h or 01h Address of the first byte to program in the Flash memory Address in XRAM of the first data to program 0008h XXh T89C51RD2 AT89C51RD2/ED2 Read bootloader version Not Implemented Program up to 128 bytes in user Flash. ACC = 0: DONE Remark: number of bytes to program is limited such as the Flash write remains in a single 128bytes page. Hence, when ACC is 128, valid values of DPL are 00h, or, 80h. Same as T89C51RD2 Program X2 fuse bit with ACC none Not implemented PROGRAM BLJB FUSE 0Ah READ BOOT ID1 0Eh READ BOOT ID2 READ BOOT VERSION Fuse value Program BLJB fuse bit with ACC 0004h XXh none XXh DPL=00h XXh ACC = ID1 Read boot ID1 0Eh XXh DPL=01h XXh ACC = ID2 Read boot ID2 0Fh XXh XXXXh XXh ACC = Boot_Version 00h or 01h Same as T89C51RD2 Not implemented Read bootloader version 15 4239B–8051–06/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ©Atmel Corporation 2003. All rights reserved. Atmel, the Atmel logo, andcombinations thereof are registered trademarks of Atmel Corporation or its subsidiaries. Windows ® is a registered trademark of Microsoft Corporation. Linux® is a registered trademark of Linus Torvalds. Other terms and product names in this document may be the trademarks of others. Printed on recycled paper. 4239B–8051–06/03 /xM