SMART ARM-based Microcontrollers
AT07892: SAM3A/3U/3X/4E DMA Controller
(DMAC) Driver
APPLICATION NOTE
Introduction
®
®
This driver for Atmel | SMART ARM -based microcontrollers provides an
interface for the configuration and management of the device's Direct
Memory Access DMA Controller (DMAC) functionality.
The DMAC is an AHB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more AMBA buses.
This is a driver for the configuration, enabling, disabling, and use of the
DMAC peripheral.
Devices from the following series can use this module:
•
Atmel | SMART SAM3A
•
Atmel | SMART SAM3U
•
Atmel | SMART SAM3X
•
Atmel | SMART SAM4E
The outline of this documentation is as follows:
•
Prerequisites
•
Module Overview
•
Special Considerations
•
Extra Information
•
Examples
•
API Overview
Atmel-42291B-SAM3A-3U-3X-4E-DMA-Controller-DMAC_AT07892_Application Note-07/2015
Table of Contents
Introduction......................................................................................................................1
1. Software License....................................................................................................... 4
2. Prerequisites..............................................................................................................5
3. Module Overview....................................................................................................... 6
4. Special Considerations.............................................................................................. 7
5. Extra Information....................................................................................................... 8
6. Examples................................................................................................................... 9
7. API Overview........................................................................................................... 10
7.1.
7.2.
Structure Definitions................................................................................................................... 10
7.1.1.
Struct dma_transfer_descriptor_t................................................................................ 10
Function Definitions....................................................................................................................10
7.2.1.
Function dmac_channel_disable()...............................................................................10
7.2.2.
Function dmac_channel_enable()............................................................................... 10
7.2.3.
Function dmac_channel_get_status().......................................................................... 11
7.2.4.
Function dmac_channel_is_enable()........................................................................... 11
7.2.5.
Function dmac_channel_is_transfer_done()............................................................... 12
7.2.6.
Function dmac_channel_keep().................................................................................. 12
7.2.7.
Function dmac_channel_multi_buf_transfer_init().......................................................12
7.2.8.
Function dmac_channel_resume().............................................................................. 13
7.2.9.
Function dmac_channel_set_configuration()...............................................................13
7.2.10. Function dmac_channel_set_ctrlA()............................................................................ 13
7.2.11. Function dmac_channel_set_ctrlB()............................................................................ 14
7.2.12. Function dmac_channel_set_descriptor_addr().......................................................... 14
7.2.13. Function dmac_channel_set_destination_addr().........................................................14
7.2.14.
7.2.15.
7.2.16.
7.2.17.
7.2.18.
Function dmac_channel_set_source_addr()............................................................... 15
Function dmac_channel_single_buf_transfer_init()..................................................... 15
Function dmac_channel_stop_transfer()..................................................................... 16
Function dmac_channel_suspend().............................................................................16
Function dmac_disable()............................................................................................. 16
7.2.19.
7.2.20.
7.2.21.
7.2.22.
7.2.23.
7.2.24.
7.2.25.
7.2.26.
7.2.27.
7.2.28.
Function dmac_disable_interrupt().............................................................................. 16
Function dmac_enable().............................................................................................. 17
Function dmac_enable_interrupt()...............................................................................17
Function dmac_get_interrupt_mask().......................................................................... 18
Function dmac_get_status()........................................................................................ 19
Function dmac_get_writeprotect_status()....................................................................19
Function dmac_init().................................................................................................... 19
Function dmac_set_priority_mode()............................................................................ 19
Function dmac_set_writeprotect()............................................................................... 20
Function dmac_soft_chunk_transfer_request()........................................................... 20
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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7.2.29.
7.3.
Function dmac_soft_set_last_transfer_flag()...............................................................20
7.2.30. Function dmac_soft_single_transfer_request()........................................................... 21
Enumeration Definitions............................................................................................................. 21
7.3.1.
Enum dmac_priority_mode_t.......................................................................................21
8. Extra Information for Direct Memory Access Controller Driver................................ 22
8.1.
8.2.
8.3.
8.4.
Acronyms....................................................................................................................................22
Dependencies.............................................................................................................................22
Errata..........................................................................................................................................22
Module History............................................................................................................................22
9. Examples for Direct Memory Access Controller Driver............................................23
9.1.
9.2.
Quick Start Guide for the DMAC driver...................................................................................... 23
9.1.1.
Use Cases................................................................................................................... 23
9.1.2.
DMAC Basic Usage..................................................................................................... 23
9.1.3.
Setup Steps................................................................................................................. 23
9.1.4.
Usage Steps................................................................................................................ 24
SAM Direct Memory Access Controller - Example Memory to Memory Transfer.......................25
9.2.1.
Purpose....................................................................................................................... 25
9.2.2.
Requirements.............................................................................................................. 25
9.2.3.
Description...................................................................................................................25
9.2.4.
Main Files.................................................................................................................... 25
9.2.5.
Compilation Information...............................................................................................25
9.2.6.
Usage.......................................................................................................................... 25
10. Document Revision History..................................................................................... 27
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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1.
Software License
Redistribution and use in source and binary forms, with or without modification, are permitted provided
that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of Atmel may not be used to endorse or promote products derived from this software without
specific prior written permission.
4. This software may only be redistributed and used in connection with an Atmel microcontroller product.
THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE EXPRESSLY AND SPECIFICALLY
DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGE.
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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2.
Prerequisites
There are no prerequisites for this module.
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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3.
Module Overview
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source
peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each
source/destination pair. In the most basic configuration, the DMAC has one master interface and one
channel. The master interface reads the data from a source and writes it to a destination. Two AMBA
transfers are required for each DMAC data transfer. This is also known as a dual-access transfer.
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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4.
Special Considerations
There are no special considerations for this module.
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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5.
Extra Information
For extra information, see Extra Information for Direct Memory Access Controller Driver. This includes:
•
Acronyms
•
Dependencies
•
Errata
•
Module History
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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6.
Examples
For a list of examples related to this driver, see Examples for Direct Memory Access Controller Driver.
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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7.
API Overview
7.1.
Structure Definitions
7.1.1.
Struct dma_transfer_descriptor_t
DMA transfer descriptor structure, otherwise known as a Linked List Item (LLI).
Table 7-1 Members
Type
Name
Description
uint32_t
ul_ctrlA
Control A register settings
uint32_t
ul_ctrlB
Control B register settings
uint32_t
ul_descriptor_addr
Next descriptor address
uint32_t
ul_destination_addr
Destination buffer address
uint32_t
ul_source_addr
Source buffer address
7.2.
Function Definitions
7.2.1.
Function dmac_channel_disable()
Disable the specified DMA Channel.
void dmac_channel_disable(
Dmac * p_dmac,
uint32_t ul_num)
Table 7-2 Parameters
7.2.2.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
Function dmac_channel_enable()
Enable the specified DMA Channel.
void dmac_channel_enable(
Dmac * p_dmac,
uint32_t ul_num)
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Table 7-3 Parameters
7.2.3.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
Function dmac_channel_get_status()
Get the DMAC Channel handler status.
uint32_t dmac_channel_get_status(
Dmac * p_dmac)
Table 7-4 Parameters
Data direction
Parameter name
Description
[in]
p_dmac
Module hardware register base address pointer
Returns
DMAC Channel handler status register. Refer to the section called "DMAC Channel Handler Status
Register" in the device-specific datasheet for more information.
7.2.4.
Function dmac_channel_is_enable()
Check if the specified DMA Channel is enabled.
uint32_t dmac_channel_is_enable(
Dmac * p_dmac,
uint32_t ul_num)
Table 7-5 Parameters
Data direction
Parameter name
Description
[in]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
Returns
The DMA Channel's enable/disable status.
Table 7-6 Return Values
Return value
Description
0
DMA Channel is disabled
1
DMA Channel is enabled
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7.2.5.
Function dmac_channel_is_transfer_done()
Check if the data transfer occurring on the specified DMA Channel is complete.
uint32_t dmac_channel_is_transfer_done(
Dmac * p_dmac,
uint32_t ul_num)
Note: This function is used in polling mode.
Table 7-7 Parameters
Data direction
Parameter name
Description
[in]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
Returns
The data transfer status.
Table 7-8 Return Values
7.2.6.
Return value
Description
0
Data is transferring
1
Data transfer complete
Function dmac_channel_keep()
Resume the specified DMA Channel from an automatic stall state.
void dmac_channel_keep(
Dmac * p_dmac,
uint32_t ul_num)
Table 7-9 Parameters
7.2.7.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
Function dmac_channel_multi_buf_transfer_init()
Initialize the DMA Channel for a multiple buffer transfer.
void dmac_channel_multi_buf_transfer_init(
Dmac * p_dmac,
uint32_t ul_num,
dma_transfer_descriptor_t * p_desc)
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Table 7-10 Parameters
7.2.8.
Data direction
Parameter name
Description
[in, out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
[in]
p_desc
Pointer to a transfer descriptor
Function dmac_channel_resume()
Resume the specified DMA Channel transfer (restoring its context).
void dmac_channel_resume(
Dmac * p_dmac,
uint32_t ul_num)
Table 7-11 Parameters
7.2.9.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
Function dmac_channel_set_configuration()
Set the DMAC configuration register of the specified DMA Channel.
void dmac_channel_set_configuration(
Dmac * p_dmac,
uint32_t ul_num,
uint32_t ul_cfg)
Table 7-12 Parameters
7.2.10.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
[in]
ul_cfg
Configuration of CFG register
Function dmac_channel_set_ctrlA()
Set the DMA control A of the specified DMA Channel.
void dmac_channel_set_ctrlA(
Dmac * p_dmac,
uint32_t ul_num,
uint32_t ul_ctrlA)
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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Table 7-13 Parameters
7.2.11.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
[in]
ul_ctrlA
Configuration of control A register
Function dmac_channel_set_ctrlB()
Set the DMA control B of the specified DMA Channel.
void dmac_channel_set_ctrlB(
Dmac * p_dmac,
uint32_t ul_num,
uint32_t ul_ctrlB)
Table 7-14 Parameters
7.2.12.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
[in]
ul_ctrlB
Configuration of control B register
Function dmac_channel_set_descriptor_addr()
Set the DMA descriptor address of the specified DMA Channel.
void dmac_channel_set_descriptor_addr(
Dmac * p_dmac,
uint32_t ul_num,
uint32_t ul_desc)
Table 7-15 Parameters
7.2.13.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
[in]
ul_desc
Descriptor address
Function dmac_channel_set_destination_addr()
Set the DMA destination address of the specified DMA Channel.
void dmac_channel_set_destination_addr(
Dmac * p_dmac,
uint32_t ul_num,
uint32_t ul_addr)
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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Table 7-16 Parameters
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
[in]
ul_addr
Destination address
Note: This register must be aligned with the source transfer width.
7.2.14.
Function dmac_channel_set_source_addr()
Set the DMA source address of the specified DMA Channel.
void dmac_channel_set_source_addr(
Dmac * p_dmac,
uint32_t ul_num,
uint32_t ul_addr)
Table 7-17 Parameters
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
[in]
ul_addr
Source address
Note: This register must be aligned with the source transfer width.
7.2.15.
Function dmac_channel_single_buf_transfer_init()
Initialize the DMA Channel for a single buffer transfer.
void dmac_channel_single_buf_transfer_init(
Dmac * p_dmac,
uint32_t ul_num,
dma_transfer_descriptor_t * p_desc)
Table 7-18 Parameters
Data direction
Parameter name
Description
[in, out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
[in]
p_desc
Pointer to a transfer descriptor
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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7.2.16.
Function dmac_channel_stop_transfer()
Stop a DMA transfer occurring on the specified DMA Channel.
void dmac_channel_stop_transfer(
Dmac * p_dmac,
uint32_t ul_num)
Note: Under normal operation, the hardware disables a channel on transfer completion by clearing the
DMAC_CHSR.ENAx register bit. The recommended way for software to disable a channel without losing
data is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register.
Table 7-19 Parameters
7.2.17.
Data direction
Parameter name
Description
[in, out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
Function dmac_channel_suspend()
Suspend the specified DMA Channel and its current context.
void dmac_channel_suspend(
Dmac * p_dmac,
uint32_t ul_num)
Table 7-20 Parameters
7.2.18.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
Function dmac_disable()
Disable the DMA Controller.
void dmac_disable(
Dmac * p_dmac)
Table 7-21 Parameters
7.2.19.
Data direction
Parameter name
Description
[in, out]
p_dmac
Module hardware register base address pointer
Function dmac_disable_interrupt()
Disable DMAC interrupts.
void dmac_disable_interrupt(
Dmac * p_dmac,
uint32_t ul_mask)
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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Table 7-22 Parameters
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_mask
A bitmask of interrupts to be disabled
Where input parameter ul_mask is a bitmask containing one or more of the following:
7.2.20.
Parameter Value
Description
DMAC_EBCIDR_BTC0
Channel 0 Buffer Transfer Completed
DMAC_EBCIDR_BTC1
Channel 1 Buffer Transfer Completed
DMAC_EBCIDR_BTC2
Channel 2 Buffer Transfer Completed
DMAC_EBCIDR_BTC3
Channel 3 Buffer Transfer Completed
DMAC_EBCIDR_CBTC0
Channel 0 Chained Buffer Transfer Completed
DMAC_EBCIDR_CBTC1
Channel 1 Chained Buffer Transfer Completed
DMAC_EBCIDR_CBTC2
Channel 2 Chained Buffer Transfer Completed
DMAC_EBCIDR_CBTC3
Channel 3 Chained Buffer Transfer Completed
DMAC_EBCIDR_ERR0
Channel 0 Access Error
DMAC_EBCIDR_ERR1
Channel 1 Access Error
DMAC_EBCIDR_ERR2
Channel 2 Access Error
DMAC_EBCIDR_ERR3
Channel 3 Access Error
Function dmac_enable()
Enable the DMA Controller.
void dmac_enable(
Dmac * p_dmac)
Table 7-23 Parameters
7.2.21.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
Function dmac_enable_interrupt()
Enable DMAC interrupts.
void dmac_enable_interrupt(
Dmac * p_dmac,
uint32_t ul_mask)
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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Table 7-24 Parameters
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_mask
A bitmask of interrupts to be enabled
Where input parameter ul_mask is a bitmask containing one or more of the following:
7.2.22.
Parameter Value
Description
DMAC_EBCIER_BTC0
Channel 0 Buffer Transfer Completed
DMAC_EBCIER_BTC1
Channel 1 Buffer Transfer Completed
DMAC_EBCIER_BTC2
Channel 2 Buffer Transfer Completed
DMAC_EBCIER_BTC3
Channel 3 Buffer Transfer Completed
DMAC_EBCIER_CBTC0
Channel 0 Chained Buffer Transfer Completed
DMAC_EBCIER_CBTC1
Channel 1 Chained Buffer Transfer Completed
DMAC_EBCIER_CBTC2
Channel 2 Chained Buffer Transfer Completed
DMAC_EBCIER_CBTC3
Channel 3 Chained Buffer Transfer Completed
DMAC_EBCIER_ERR0
Channel 0 Access Error
DMAC_EBCIER_ERR1
Channel 1 Access Error
DMAC_EBCIER_ERR2
Channel 2 Access Error
DMAC_EBCIER_ERR3
Channel 3 Access Error
Function dmac_get_interrupt_mask()
Get the DMAC Interrupt Mask.
uint32_t dmac_get_interrupt_mask(
Dmac * p_dmac)
Table 7-25 Parameters
Data direction
Parameter name
Description
[in]
p_dmac
Module hardware register base address pointer
Returns
DMAC Interrupt mask.
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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7.2.23.
Function dmac_get_status()
Get the DMAC transfer status.
uint32_t dmac_get_status(
Dmac * p_dmac)
Table 7-26 Parameters
Data direction
Parameter name
Description
[in]
p_dmac
Module hardware register base address pointer
Returns
DMAC transfer status. Refer to section called "DMAC Error, Buffer Transfer and Chained Buffer Transfer
Status Register" in the device-specific datasheet for more information.
7.2.24.
Function dmac_get_writeprotect_status()
Get the DMAC register's write protect status.
uint32_t dmac_get_writeprotect_status(
Dmac * p_dmac)
Table 7-27 Parameters
Data direction
Parameter name
Description
[in]
p_dmac
Module hardware register base address pointer
Returns
Write protect status.
7.2.25.
Function dmac_init()
Initialize the DMA controller and disable it.
void dmac_init(
Dmac * p_dmac)
Table 7-28 Parameters
7.2.26.
Data direction
Parameter name
Description
[in, out]
p_dmac
Module hardware register base address pointer
Function dmac_set_priority_mode()
Set the DMA priority mode.
void dmac_set_priority_mode(
Dmac * p_dmac,
dmac_priority_mode_t mode)
Atmel AT07892: SAM3A/3U/3X/4E DMA Controller (DMAC) Driver [APPLICATION NOTE]
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Table 7-29 Parameters
7.2.27.
Data direction
Parameter name
Description
[in, out]
p_dmac
Module hardware register base address pointer
[in]
mode
Priority mode
Function dmac_set_writeprotect()
Enable/Disable the write protect of DMAC registers.
void dmac_set_writeprotect(
Dmac * p_dmac,
uint32_t ul_enable)
Table 7-30 Parameters
7.2.28.
Data direction
Parameter name
Description
[out]
p_dmac
Module hardware register base address pointer
[in]
ul_enable
1 to enable, 0 to disable
Function dmac_soft_chunk_transfer_request()
DMA Channel software chunk request.
void dmac_soft_chunk_transfer_request(
Dmac * p_dmac,
uint32_t ul_num,
uint32_t ul_src_req,
uint32_t ul_dst_req)
Table 7-31 Parameters
7.2.29.
Data direction
Parameter name
Description
[in, out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
[in]
ul_src_req
Request a source transfer
[in]
ul_dst_req
Request a destination transfer
Function dmac_soft_set_last_transfer_flag()
Set the DMA Channel's last transfer flag.
void dmac_soft_set_last_transfer_flag(
Dmac * p_dmac,
uint32_t ul_num,
uint32_t ul_src_flag,
uint32_t ul_dst_flag)
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Table 7-32 Parameters
7.2.30.
Data direction
Parameter name
Description
[in, out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
Channel number
[in]
ul_src_flag
Last source transfer flag
[in]
ul_dst_flag
Last destination transfer flag
Function dmac_soft_single_transfer_request()
DMA Channel software single request.
void dmac_soft_single_transfer_request(
Dmac * p_dmac,
uint32_t ul_num,
uint32_t ul_src_req,
uint32_t ul_dst_req)
Table 7-33 Parameters
Data direction
Parameter name
Description
[in, out]
p_dmac
Module hardware register base address pointer
[in]
ul_num
DMA Channel number (range 0 to 3)
[in]
ul_src_req
Request a source transfer
[in]
ul_dst_req
Request a destination transfer
7.3.
Enumeration Definitions
7.3.1.
Enum dmac_priority_mode_t
Table 7-34 Members
Enum value
Description
DMAC_PRIORITY_FIXED
Fixed priority arbiter
DMAC_PRIORITY_ROUND_ROBIN
Modified round robin arbiter
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8.
Extra Information for Direct Memory Access Controller Driver
8.1.
Acronyms
Below is a table listing the acronyms used in this module, along with their intended meanings.
8.2.
Acronym
Definition
AHB
AMBA High-performance Bus
AMBA
Advanced Microcontroller Bus Architecture
FIFO
First In First Out
LLI
Linked List Item
QSG
Quick Start Guide
Dependencies
This driver has the following dependencies:
•
8.3.
None
Errata
There are no errata related to this driver.
8.4.
Module History
An overview of the module history is presented in the table below, with details on the enhancements and
fixes made to the module since its first release. The current version of this corresponds to the newest
version in the table.
Changelog
Initial document release
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9.
Examples for Direct Memory Access Controller Driver
This is a list of the available Quick Start Guides (QSGs) and example applications for SAM3A/3U/3X/4E
DMA Controller (DMAC) Driver. QSGs are simple examples with step-by-step instructions to configure
and use this driver in a selection of use cases. Note that a QSG can be compiled as a standalone
application or be added to the user application.
•
•
9.1.
Quick Start Guide for the DMAC driver
SAM Direct Memory Access Controller - Example Memory to Memory Transfer
Quick Start Guide for the DMAC driver
This is the quick start guide for the SAM3A/3U/3X/4E DMA Controller (DMAC) Driver, with step-by-step
instructions on how to configure and use the driver for a specific use case. The code examples can be
copied into the main application loop or any other function that will need to control the DMAC module.
9.1.1.
Use Cases
•
9.1.2.
DMAC Basic Usage
DMAC Basic Usage
This use case will demonstrate how to initialize the DMAC module to perform a single memory to memory
transfer.
9.1.3.
Setup Steps
9.1.3.1.
Prerequisites
This module requires the following service
•
System Clock Management (sysclock)
9.1.3.2.
Setup Code
Add these macros and global variable to the top of your application's C-file:
#define DMA_CH 0
#define DMA_BUF_SIZE
32
uint32_t g_dma_buf[6][DMA_BUF_SIZE];
Add this to the main loop or a setup function:
pmc_enable_periph_clk(ID_DMAC);
9.1.3.3.
Workflow
1.
Define the variables needed, in order to perform a data transfer:
uint32_t i;
uint32_t cfg;
dma_transfer_descriptor_t desc;
2.
Prepare the data buffer to be transferred:
for (i = 0; i < DMA_BUF_SIZE; i++) {
g_dma_buf[0][i] = i;
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g_dma_buf[1][i] = 0;
}
3.
Initialize the DMAC module:
dmac_init(DMAC);
4.
Set the priority to round-robin:
dmac_set_priority_mode(DMAC, DMAC_PRIORITY_ROUND_ROBIN);
5.
Enable the DMAC module:
dmac_enable(DMAC);
6.
Configure the channel for:
•
Enable stop on done
•
Enable AHB protection
•
Set the FIFO so that largest defined length AHB burst is performed
cfg = DMAC_CFG_SOD_ENABLE |
DMAC_CFG_AHB_PROT(1) |
DMAC_CFG_FIFOCFG_ALAP_CFG;
dmac_channel_set_configuration(DMAC, DMA_CH, cfg);
9.1.4.
Usage Steps
9.1.4.1.
Usage Code
Configure the DMA source and destination buffer addresses:
desc.ul_source_addr = (uint32_t) g_dma_buf[0];
desc.ul_destination_addr = (uint32_t) g_dma_buf[1];
Configure DMA CTRLA:
•
Set the buffer transfer size to DMA_BUF_SIZE
•
Set the source transfer width to 32-bit
•
Set the destination transfer width to 32-bit
desc.ul_ctrlA = DMAC_CTRLA_BTSIZE(DMA_BUF_SIZE) |
DMAC_CTRLA_SRC_WIDTH_WORD |
DMAC_CTRLA_DST_WIDTH_WORD;
•
•
•
•
•
Configure DMA CTRLB:
Disable source buffer descriptor fetch
Disable destination buffer descriptor Fetch
Enable memory-to-memory transfer
Increment the source address
Increment the destination address
desc.ul_ctrlB = DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE |
DMAC_CTRLB_DST_DSCR_FETCH_DISABLE |
DMAC_CTRLB_FC_MEM2MEM_DMA_FC |
DMAC_CTRLB_SRC_INCR_INCREMENTING |
DMAC_CTRLB_DST_INCR_INCREMENTING;
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Initialize the DMA transfer:
desc.ul_descriptor_addr = 0;
dmac_channel_single_buf_transfer_init(DMAC, DMA_CH, &desc);
Start the DMA transfer:
dmac_channel_enable(DMAC, DMA_CH);
Finally, poll for the DMA transfer to complete:
while (!dmac_channel_is_transfer_done(DMAC, DMA_CH)) {
}
9.2.
SAM Direct Memory Access Controller - Example Memory to Memory Transfer
9.2.1.
Purpose
This example demonstrates how to configure and use DMAC controller for single and multiple memory to
memory data buffer transfers.
9.2.2.
Requirements
This example can be used with SAM evaluation kits that have a DMA Controller.
9.2.3.
Description
This example transfers data in one RAM buffer to another RAM buffer. Two transfer modes will be used:
1. It uses single buffer transfer with polling mode. After transfer is done, the transferred data will be
verified.
2. It uses multiple buffer transfer with interrupt mode. After transfer is done, the transferred data will
be verified.
9.2.4.
Main Files
•
•
•
9.2.5.
dmac.c: Direct Memory Access Controller driver
dmac.h: Direct Memory Access Controller driver header file
dmac_example1.c: Direct Memory Access Controller example application
Compilation Information
®
®
This software is written for GNU GCC and IAR Embedded Workbench for Atmel . Other compilers may
or may not work.
9.2.6.
Usage
1.
2.
Build the program and download it into the evaluation board.
®
On the computer, open and configure a terminal application (e.g., HyperTerminal on Microsoft
®
Windows ) with these settings:
•
115200 baud
•
8 bits of data
•
No parity
•
1 stop bit
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3.
4.
•
No flow control
Start the application.
In the terminal window, the following text should appear:
*
*
*
*
*
*
*
*
*
-- DMAC Example --- xxxxxx-xx
-- Compiled: xxx xx xxxx xx:xx:xx -Test single buffer transfer......
> Test OK
Test multiple buffer transfer......
> Test OK.
Note: Values depend on the board and the chip used.
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10.
Document Revision History
Doc. Rev.
Date
Comments
42291B
07/2015
Updated title of application note and added list of supported devices
42291A
05/2014
Initial document release
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