View detail for l AVR32715: AVR UC3B 32-bit Microcontroller Schematic Checklist

APPLICATION NOTE
Atmel AVR32715: AVR UC3B 32-bit Microcontroller
Schematic Checklist
Atmel AVR UC3 32-bit Microcontroller
Features
•
•
•
•
•
Power circuit
Reset circuit
Clocks and crystal oscillators
USB connection
JTAG and Nexus debug ports
Introduction
A good hardware design comes from a proper schematic. Since Atmel® AVR® UC3B
series devices have a fair number of pins and functions, the schematic for these
devices can be large and quite complex.
This application note describes a common checklist which should be used when
starting and reviewing the schematics for an AVR UC3B series design.
32095E−AVR UC3−08/2013
Table of Contents
1. Power Circuit ........................................................................................ 3 1.1 Single 3.3V Power Supply ................................................................................. 3 1.2 Dual 3.3V and 1.8V Power Supply .................................................................... 4 1.3 ADC Reference Power Supply .......................................................................... 5 1.4 No ADC Power Supply ...................................................................................... 6 2. Reset Circuit ........................................................................................ 7 3. Clocks and Crystal Oscillators ............................................................. 8 3.1 External Clock Source ....................................................................................... 8 3.2 Crystal Oscillator ............................................................................................... 8 4. USB Connection .................................................................................. 9 4.1 Not Used ........................................................................................................... 9 4.2 Device Mode, Powered from Bus Connection ................................................... 9 4.3 Device Mode, Self Powered Connection ......................................................... 10 4.4 Host/OTG Mode, Power from Bus Connection ............................................... 11 5. JTAG and Nexus Debug Ports ........................................................... 12 5.1 JTAG Port Interface ........................................................................................ 12 5.2 Nexus Port Interface ....................................................................................... 13 6. GPIO Pin Used by Default USB DFU Bootloader .............................. 15 7. Suggested Reading ........................................................................... 16 7.1 Device Datasheet ............................................................................................ 16 7.2 Evaluation Kit Schematic ................................................................................ 16 8. Revision History ................................................................................. 17 Atmel AVR32715: AVR UC3B 32-bit Microcontroller Schematic Checklist [APPLICATION NOTE]
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1.
Power Circuit
1.1
Single 3.3V Power Supply
Figure 1-1. Single 3.3V power example schematic.
Common for
pin groups
Close to device
(every pin)
Close to pin
VDDIO
DC/DC converter
4.7µF
100nF
33nF
VDDIN
3.33.3
volt
volt
4.7µF
100nF
33nF
Voltage
regulator
VDDOUT
2.2µF
470pF
VDDCORE
2.2µF
100nF
33nF
2.7nF
VDDPLL
2.2µF
Table 1-1.
33nF
2.7nF
Single 3.3V power supply checklist.
Signal name
Recommended pin connection
Description
VDDIO
3.0V to 3.6V
Decoupling/filtering capacitors
33nF (1)(2), 100nF (1)(3) and 4.7µF (1)
Powers I/O lines and USB transceiver.
3.0V to 3.6V
Decoupling/filtering capacitors
33nF (1)(2), 100nF (1)(3) and 4.7µF (1)
Powers on-chip voltage regulator.
Decoupling/filtering capacitors
470pF (1)(2) and 4.7µF (1)
Output of the on-chip 1.8V voltage regulator.
VDDIN
VDDOUT
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Decoupling/filtering capacitors must be added to guarantee
1.8V stability.
VDDCORE
1.65V to 1.95V
Connected to VDDOUT
Decoupling/filtering capacitors
2.7nF (1)(2), 33nF (1)(3), 100nF (1) and 4.7µF (1)
Powers device, flash logic and on-chip RC.
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
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Signal name
Recommended pin connection
Description
VDDPLL
1.65V to 1.95V
Connected to VDDOUT
Decoupling/filtering capacitors
2.7nF (1)(2), 33nF (1)(3) and 4.7µF (1)
Powers the PLL.
Notes:
1.2
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
1.
These values are given only as a typical example.
2.
Decoupling capacitor should be placed as close as possible to each pin in the signal group, vias should be
avoided.
3.
Decoupling capacitor should be placed close to the device for each pin in the signal group.
Dual 3.3V and 1.8V Power Supply
Figure 1-2. Dual 3.3V and 1.8V power example schematic.
DC/DC converter
Common for
pin groups
Close to device
(every pin)
Close to pin
VDDIO
4.7µF
3.33.3
volt
volt
100nF
33nF
VDDIN
Voltage
regulator
VDDOUT
DC/DC converter
VDDCORE
1.83.3
volt
volt
2.2µF
100nF
2.7nF
VDDPLL
2.2µF
Table 1-2.
33nF
33nF
2.7nF
Dual 3.3V and 1.8V power supply checklist.
Signal name
Recommended pin connection
Description
VDDIO
3.0V to 3.6V
Decoupling/filtering capacitors
33nF (1)(2), 100nF (1)(3) and 4.7µF (1)
Powers I/O lines and USB transceiver.
VDDIN
Connected to ground.
On-chip voltage regulator not in use.
VDDOUT
Connected to ground.
On-chip voltage regulator not in use.
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
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Signal name
Recommended pin connection
Description
VDDCORE
1.65V to 1.95V
Decoupling/filtering capacitors
2.7nF (1)(2), 33nF (1)(3), 100nF (1) and 2.2µF (1)
Powers device, flash logic and on-chip RC.
1.65V to 1.95V
Decoupling/filtering capacitors
2.7nF (1)(2), 33nF (1)(3) and 2.2µF (1)
Powers the PLL.
VDDPLL
Notes:
1.3
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
1.
These values are given only as a typical example.
2.
Decoupling capacitor should be placed as close as possible to each pin in the signal group, vias should be
avoided.
3.
Decoupling capacitor should be placed close to the device for each pin in the signal group.
ADC Reference Power Supply
The following schematic checklist is only necessary if the design is using the internal analog to digital converter.
Figure 1-3. ADC reference power supply example schematic.
Close to device
(every pin)
Close to pin
VDDANA
DC/DC converter
100nF
33nF
ADVREF
3.33.3
volt
volt
Table 1-3.
ADC reference power supply checklist.
Signal name
Recommended pin connection
Description
VDDANA
3.0V to 3.6V
Decoupling/filtering capacitors
33nF (1)(2) and 100nF (1)(3)
Powers on-chip ADC.
2.6V to VDDANA.
Connect with VDDANA.
ADVREF is a pure analog input.
ADVREF
Notes:
Decoupling/filtering capacitors must be added to improve
startup stability and reduce source voltage drop.
1.
These values are given only as a typical example.
2.
Decoupling capacitor should be placed as close as possible to each pin in the signal group, vias should be
avoided.
3.
Decoupling capacitor should be placed close to the device for each pin in the signal group.
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1.4
No ADC Power Supply
The following schematic checklist is only necessary if the design is not using the internal analog to digital converter.
Figure 1-4. No ADC power supply example schematic.
DC/DC converter
VDDANA
3.33.3
volt
volt
ADVREF
Table 1-4.
No ADC power supply checklist.
Signal name
Recommended pin connection
VDDANA
3.0V to 3.6V
ADVREF
Connected to ground.
Description
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2.
Reset Circuit
Figure 2-1. Reset circuit example schematic.
Table 2-1.
Reset circuit checklist.
Signal name
Recommended pin connection
Description
RESET
Can be left unconnected in case no reset
from the system needs to be applied to the
product.
The RESET_N pin is a Schmitt input and integrates a
permanent pull-up resistor to VDDIO.
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3.
Clocks and Crystal Oscillators
3.1
External Clock Source
Figure 3-1. External clock source schematic.
Table 3-1.
3.2
External clock source checklist.
Signal name
Recommended pin connection
Description
XIN
Connected to clock output from external
clock source.
Up to VDDIO volt square wave signal up to 50MHz.
XOUT
Can be left unconnected or used as GPIO.
Crystal Oscillator
Figure 3-2. Crystal oscillator example schematic.
Table 3-2.
Crystal oscillator checklist.
Signal name
XIN
XOUT
Notes:
Recommended pin connection
Biasing capacitor 22pF
(1)(2)
Biasing capacitor 22pF
(1)(2)
Description
External crystal between 0.4MHz and 20MHz.
1.
These values are given only as a typical example. The capacitance C of the biasing capacitors can be
computed based on the crystal load capacitance CL and the internal capacitance Ci of the MCU as follows:
C = 2 (CL – Ci)
The value of CL can be found in the crystal datasheet and the value of Ci can be found in the MCU
datasheet.
2.
Decoupling capacitor should be placed as close as possible to each pin in the signal group, vias should be
avoided.
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4.
USB Connection
4.1
Not Used
When the USB interface is not used, D+ and D- should be connected to ground.
4.2
Device Mode, Powered from Bus Connection
Figure 4-1. USB in device mode, bus powered connection example schematic.
VDD
3.3 volt
regulator
VBUS
VBUS
D-
D+
USB_VBOF
D39 ohm
D+
39 ohm
USB_ID
ID
GND
Table 4-1.
USB bus powered connection checklist.
Signal name
Recommended pin connection
Description
USB_VBOF
Can be left unconnected.
USB power control pin.
VBUS
Directly to connector.
USB power measurement pin.
D-
39Ω series resistor.
Placed as close as possible to pin.
Negative differential data line.
D+
39Ω series resistor.
Placed as close as possible to pin.
Positive differential data line.
USB_ID
Can be left unconnected.
Mini connector USB identification pin.
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4.3
Device Mode, Self Powered Connection
Figure 4-2. USB in device mode, self powered connection example schematic.
USB_VBOF
VBUS
VBUS
D-
D+
D39 ohm
D+
39 ohm
USB_ID
ID
GND
Table 4-2.
USB self powered connection checklist.
Signal name
Recommended pin connection
Description
USB_VBOF
Can be left unconnected.
USB power control pin.
VBUS
Directly to connector.
USB power measurement pin.
D-
39Ω series resistor.
Placed as close as possible to pin.
Negative differential data line.
D+
39Ω series resistor.
Placed as close as possible to pin.
Positive differential data line.
USB_ID
Can be left unconnected.
Mini connector USB identification pin.
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4.4
Host/OTG Mode, Power from Bus Connection
Figure 4-3. USB host and OTG powering connection example schematic.
Table 4-3.
USB host and OTG powering connection checklist.
Signal name
Recommended pin connection
Description
USB_VBOF
GPIO connected to VBUS 5.0V regulator enable
signal.
USB power control pin.
VBUS
Directly to connector.
USB power measurement pin.
D-
39Ω series resistor.
Placed as close as possible to pin.
Negative differential data line.
D+
39Ω series resistor.
Placed as close as possible to pin.
Positive differential data line.
USB_ID
GPIO directly connected to connector,
mandatory in OTG mode.
Mini connector USB identification pin. For OTG
it will be tied to ground in host mode, and left
floating in device mode. Pull-up on GPIO pin
must be enabled.
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5.
JTAG and Nexus Debug Ports
5.1
JTAG Port Interface
Figure 5-1. JTAG port interface example schematic.
Table 5-1.
JTAG port interface checklist.
Signal name
Recommended pin connection
Description
TMS
Test mode select, sampled on rising TCK.
TDO
Test data output, driven on falling TCK.
TCK
Test clock, fully asynchronous to system clock
frequency.
RESET
Device external reset line.
TDI
Test data input, sampled on rising TCK.
EVTO
Event output, not used.
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5.2
Nexus Port Interface
Figure 5-2. Nexus port interface example schematic.
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Table 5-2.
Nexus port interface checklist.
Signal name
Recommended pin connection
Description
TDI
Test data input, sampled on rising TCK.
TMS
Test mode select, sampled on rising TCK.
TCK
Test clock, fully asynchronous to system clock
frequency.
TDO
Test data output, driven on falling TCK.
RESET
Device external reset line.
EVTI
Event input.
MDO[0:5]
Trace data output.
EVTO
Event output.
MCK0
Trace data output clock.
MSE[0:1]
Trace frame control.
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6.
GPIO Pin Used by Default USB DFU Bootloader
All AVR UC3B series devices are shipped with default USB DFU Bootloader. If this Bootloader is going to be used in
the application, a pull up or pull down resistor (depending up on IO Pin Condition level in the user page configuration
word) must be connected to specific GPIO pin. The logic level of this GPIO pin will be used as hardware condition to
enter into the Bootloader mode.
The IO condition pin used in default USB DFU Bootloader (For UC3B Device) is PA13. By default, logic low condition is
used to enter into Bootloader mode. Normally Push button in Atmel AVR UC3B Evaluation kits is used for this purpose.
Following schematic is a typical example for this.
Figure 6-1. Bootloader GPIO pin – pull-up resistor typical example schematic.
VDDIO
10k ohm
PA13
100nF
To know more about the USB DFU Bootloader functionalities and its usage, please refer to the application
note AVR32784: AVR UC3 USB DFU Bootloader.
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7.
Suggested Reading
7.1
Device Datasheet
The device datasheet contains block diagrams of the peripherals and details about implementing firmware for the
device. The datasheet is available on http://www.atmel.com/products/microcontrollers/avr/default.aspx?tab=documents.
7.2
Evaluation Kit Schematic
The evaluation kit EVK1101 contains the full schematic for the board; it can be used as a reference design. The
schematic is available on http://www.atmel.com/products/microcontrollers/avr/default.aspx?tab=tools.
Note that capacitors are soldered on the NEXUS trace data output lines on the EVK1101. This may cause speed
limitations. In order to not have this limitation the capacitors has to be removed.
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8.
Revision History
Doc. rev.
Date
Comments
32095E
08/2013
New document template. Description for VDDPLL is corrected, external oscillator range
is updated, and default bootloader pin is mentioned.
32095D
12/2008
New document template. Bugs fixed.
32095C
09/2008
XIN voltage corrected.
32095B
04/2008
Several updates.
32095A
01/2008
Initial document release.
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