APPLICATION NOTE LIN Switch Module Matrix Decoder with the ATA6612/ATA6613 ATA6612/ATA6613 Features ● Less than 100µA current consumption while still scanning the key pad ● Outstanding EMC and ESD performance ● 8-Kbytes/16-Kbytes flash memory for the application program (ATA6612/ATA6613) ● 36-key (up to 64) push-button keyboard in 6 6 matrix ● 4 (up to 6) high current PWM outputs with programmable PWM frequency ● 2 channels (up to 8-channel) used for 10-bit ADC ● ATA6612/ATA6613 can be adapted to a wide range of applications, with few external components required ● LIN transceiver according to LIN 2.x specification and SAEJ2602-2 ● Integrated linear low-drop voltage regulator with 5V ±2% with temperature and overcurrent- monitoring ● Wake-up via LIN, wake-up input, Kl_15 input on key press or cyclic Possible Applications ● Switch panel door module ● Seat belt indicator ● Steering wheel switches ● Power seat switches ● Climate control dashboard 9135B-AUTO-06/15 1. Description This application note describes a method of connecting a switch matrix or keyboard to the LIN SBC ATA6612/ATA6613, which is particularly suited for complete LIN bus node applications. This application note can be used for all applications using matrix keyboards e.g., remote controls and switching panels transmitting the information via the LIN bus. The ATA6612/ATA6613 consists of two chips in one package; the first one is the LIN system basis chip (LIN SBC) ATA6624, which includes an integrated LIN transceiver, a 5V voltage regulator, and a window watchdog. The second chip is an automotive microcontroller from Atmel®’s series of AVR® 8-bit microcontroller with advanced RISC architecture. The ATA6612 consists of the LIN SBC ATA6624 and the ATmega88 with an 8-Kbytes flash. The ATA6613 consists of the LIN SBC ATA6624 and the ATmega168 with a 16-Kbytes flash. The only difference between integrated microcontrollers is the size of the flash memory. All pins of the LIN System Basis Chip as well as all pins of the AVR microcontroller are bonded out to provide customers the same flexibility for their applications as they have when using the discrete parts. This ensures also that all AVR tools can be used for ATA6612/ATA6613. The ATA6624 has already been approved by many OEMs due to its outstanding EMC and ESD performance. Consequentially the ATA6612/ATA6613 offers the same excellent and impressive behavior in rough environments. Official test reports from the certified test center are available on request. 2. Climate Control Dashboard Figure 2-1. 6 6 Switch Matrix Application Optional resistors for higher switch currents VCC PD7 VS 100nF S6 VCC S13 S14 S15 S16 S17 S18 S22 S23 S24 PB6 VDD2 PB7 PD5 ADC6 PD4 AREF PD3 GND4 LIN ADC7 NTRIG PC2 EN PC3 VS PC5 PC6 1kΩ 220pF LIN WAKE (if needed) WAKE PC1 PC4 36 GND ATA6612/13 PD1 S21 PD6 GND1 PD0 S20 GND2 VDD1 AVDD PC0 S19 PB0 PB4 PB5 33kΩ 10kΩ VBAT VCC MODE 100nF 1 TM S12 WD_OSC S11 NRES S10 TXD S9 P7D 100nF S8 INH 10μH S7 LIN Master pull-up 48 PB1 S5 RXD S4 PB2 S3 PD2 S2 PB3 S1 + PVCC KL_15 + GND 24 S25 S26 S27 S28 S29 100nF S30 10μF 100nF 22μF 10kΩ KL15 PD7 S31 2 S32 S33 S34 S35 S36 ATA6612/ATA6613 [APPLICATION NOTE] 9135B–AUTO–06/15 51kΩ 10kΩ 100nF 47kΩ The keyboard matrix is organized in 6 6 push buttons connected with row and column lines as shown in Figure 2-1 on page 2. Pressing a key connects the key's row and column lines. When pressing the top right key, the column line furthest right is connected to top row line. Matrix keyboards can be scanned in several ways. When only single keys are pressed, a quick method is to first select (drive low) all row lines and read the column result. Then all column lines are selected, and the row result is read. Returned column and row is combined into a unique scan code for the specific key pressed. A typical keypad used in cars consists of nine different and independent switches, some of them including backlight illumination. To meet these requirements the following schematic can be used as a starting point. Figure 2-2. 3 3 LIN Switch Module Matrix Decoder with the ATA6612/ATA6613 Optional resistors for higher switch currents VCC PD7 VS LDR 100nF S3 VCC PB6 VDD2 PB7 PD5 PD6 ADC6 PD4 AREF PD3 GND4 LIN PC0 NTRIG PC2 EN PC3 VS NRES TXD INH RXD PD2 PD1 PD0 PC5 PC6 1kΩ 220pF LIN WAKE (if needed) WAKE PC1 PC4 36 GND ATA6612/13 33kΩ 10kΩ VBAT VCC MODE S6 PB0 GND1 TM S5 GND2 VDD1 AVDD ADC7 S4 P7D PB4 PB5 WD_OSC 100nF 1 PB1 100nF LIN Master pull-up 48 10μH PB2 S2 PB3 S1 + PVCC KL_15 + GND 24 100nF S7 S8 S9 10μF 100nF 22μF 10kΩ KL15 PD7 51kΩ 10kΩ 100nF 47kΩ Using only the internal pull-up resistors of the AVR® will lead to a current of approximately 140µA through the pressed keys. For some automotive applications it is very important to have a higher current through the switches in order to prevent oxides. In this case, lower ohmic external pull-up resistors can be added as shown in Figure 2-2. Depending on the resistor value the current through the switches can be adjusted. For example a 470 resistor will lead to a current of ~10mA. The four LEDs shown in Figure 2-2 are all connected to PWM outputs so that the brightness of each LED can be adapted e.g., to the environment light without much effort. The environment light can be measured using a voltage divider consisting of one LDR connected to an ADC input of the microcontroller. The battery voltage can be monitored by an analog comparator input via a switchable voltage divider. During Sleep and Silent mode this voltage divider will be switched off automatically in order to reduce the current consumption. ATA6612/ATA6613 [APPLICATION NOTE] 9135B–AUTO–06/15 3 Note, the current ability of the internal 5V voltage regulator is limited to 50mA. Exceeding this limit will result in a reset. The worst case scenario in the example above should consider when of keys are pressed at the same time, with all LEDs switched on, together with the normal operating current consumption of the IC including all external voltage dividers. For some applications there is a need for a higher current than the internal voltage regulator can deliver (50mA). In this case, it is possible to boost the maximum current by using an external NPN transistor with its base connected to the VCC pin and its emitter connected to PVCC. If this is done, the regulated output voltage of 5V or 3.3V is available at pin PVCC. In addition to the transistor, two additional components must to be used, a resistor (3.3) and an electrolytic capacitor (2.2µF). Note that the output voltage is no longer short-circuit protected when boosting the output current with an external NPN transistor. The limiting parameter for the output current is the maximum power dissipation of the external NPN transistor. For example, when using a MJD31C soldered on the minimum pad size, as found on the development board, the thermal resistance is 80K/W, meaning the maximum possible output current when VS = 12V is approximately 230mA at room temperature. Exceeding this limit is not recommended as the transistor could be damaged as a result of overtemperature. If a higher output current is required, additional cooling of the external transistor has to be ensured. Current consumption: In order to keep the overall current consumption low, while still being able to detect a pressed key, the ATA6612/ATA6613 can be switched to Silent mode. This mode keeps the 5V power supply active for the microcontroller. The microcontroller itself can be switched into the power down mode, from which it can wake up again via a pin change interrupt. Pin change interrupts are available at all I/O pins. The current consumption of the LIN part in the ATA6612/ATA6613 in the silent mode is typically 57µA and the microcontroller itself takes less than 1µA in the power-down mode. Thus, using the extended power-save mode, an overall current consumption of below 60µA can be achieved while still scanning the key pad. Contact Bounce: When a keyboard button is pressed, the contact bounces for some time before settling in a steady on-state. This must be managed by the software in a way that prevents generation of multiple key presses. A common way to achieve this is to wait a short time after the keypress detection, letting the contact settle, and then read the actual state. This also eliminates errors due to noise spikes on the lines. When all pressed keys at a simultaneous key press must be detected, the rows must be scanned separately. The row lines must be selected (driven low) sequentially, reading the column result for each row, thus getting all pressed keys. Additionally, the separated keys have to be decoupled using an additional diode in order to avoid erroneous evaluation, in particular, a a pressed key where is none. The described method also leads to more flexibility in the worst-case overall current consumption as not all rows are selected at the same time and therefore the current through the switches adjusted by the external pull-up resistors can occur only one at a time. 4 ATA6612/ATA6613 [APPLICATION NOTE] 9135B–AUTO–06/15 Figure 2-3. 3 3 Switch Matrix with Decoupling Diodes for Secure Detection of Multiple Key Presses Optional resistors for higher switch currents 48 S1 S2 S3 100nF 1 PB4 PB3 PB5 AVDD AREF 100nF S4 S5 S6 GND4 PC0 PC1 PC2 S7 S8 S9 ATA6612/ATA6613 [APPLICATION NOTE] 9135B–AUTO–06/15 5 3. General Digital I/O Pins Figure 3-1. I/O Pin Equivalent Schematic Rpu Pxn Logic Cpin see Figure “General Digital I/O” for Details Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. The DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pullup resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tristated when reset condition becomes active even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). Each I/O can sink and source 20mA. Table 3-1. 6 Port Pin Configurations DDxn PORTxn PUD (in MCUCR) I/O Pull-up 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if external pulled low 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output low (sink) 1 1 X Output No Output high (source) ATA6612/ATA6613 [APPLICATION NOTE] 9135B–AUTO–06/15 Comment A/D Converter Figure 4-1. Analog to Digital Converter Block Schematic Operation ADC Conversion Complete IRQ AREF ADPS0 ADPS1 ADPS2 ADIF ADFR ADEC ADEN MUX0 Channel Selection Internal 1.1V Reference 0 ADC DATA Register (ADCH/ADCL) Prescaler MUX Decoder AVCC 16 ADC CTRL and Status Register (ADCSRA) MUX1 MUX2 MUX3 REFS0 ADCAR ADC Multiplexer Select (ADMUX) ADIE ADIF 8 BIT DATA BUS REFS1 4. Conversion Logic Sample and Hold Comparator 10-BIT DAC + GND Bandgap Reference ADC7 ADC6 ADC5 Input MUX ADC Multiplexer Output ADC4 ADC3 ADC2 ADC1 ADC0 The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input pins as well as GND and a fixed bandgap voltage reference can be selected as single-ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering powersaving sleep modes. ATA6612/ATA6613 [APPLICATION NOTE] 9135B–AUTO–06/15 7 The ADC generates a 10-bit result, which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right-adjusted, but can optionally be presented left-adjusted by setting the ADLAR bit in ADMUX. If the result is left-adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. Figure 4-2. Analog Input Circuitry IIH 1 to 100kΩ ADCn CS/H = 14pF IIL VCC/2 The analog input circuitry for single-ended channels is illustrated in Figure 4-2. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on the time the source needs to charge the S/H capacitor (which can vary widely). The user is recommended to only use low impedance sources with slowly varying signals since this minimizes the required charge transfer to the S/H capacitor. Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels to avoid distortion from unpredictable signal convolution. The user is advised to remove high-frequency components with a low-pass filter before applying the signals as inputs to the ADC. 8 ATA6612/ATA6613 [APPLICATION NOTE] 9135B–AUTO–06/15 5. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9135B-AUTO-06/15 Put document in the latest template ATA6612/ATA6613 [APPLICATION NOTE] 9135B–AUTO–06/15 9 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: 9135B–AUTO–06/15 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, AVR®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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