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Atmel MSL3040/41/50/60/80/86/87/88
Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers
with Integrated Boost Controller and Phase Shifted Dimming
APPLICATION NOTE
Description:
The MSL3040/41/50/60/80/86/87/88 LED drivers offer a complete solution to drive up to eight parallel
LED strings at up to 40V. The LED current sinks of the MSL3050, MSL3060, MSL3080, MSL3086,
MSL3087, and MSL3088 control up to 60mA each, and the MSL3040 and MSL3041 current sinks control
up to 120mA each, for up to 19W of LED power. The MSL3050, MSL3060 and MSL3080 allow parallel
driver connection, increasing string current capability. A single resistor sets LED current with string
matching and accuracy within ±3%. Each driver varies by the number of current sinks and features (see
Table 1 below). Basic features include integrated boost regulator controller, PWM circuitry that allows
up to 4095:1 dimming, phase-shifted LED PWM dimming, up to eight LED drive outputs, integrated or
separate duty cycle and frequency control inputs, a 1MHz I2C compatible serial interface and internal
registers for PWM dimming control. Additionally, integrated fault detection circuitry acts on string opencircuit and LED short circuit faults, boost regulator over-voltage faults, and die over-temperature faults.
The proprietary Efficiency Optimizer minimizes power use while maintaining proper LED current, and
supports interconnecting multiple drivers to power more than eight strings while maintaining optimum
efficiency.
Table 1. LED Driver Parts Comparison
PART
MAX
PHASE
RESISTOR SET
NUMBER CURRENT SHIFTED
INTERNAL
LED SHORT
OF LED
PER
STRING
BOOST
CIRCUIT
STRINGS STRING DRIVERS CONTROLLER THRESHOLD
SEPARATE
SYNC
INPUT*** BEST FOR
MSL3086
8
60mA
YES
YES
YES
NO
MONITOR, INDUSTRIAL PANEL
MSL3087*
8
60mA
YES
NO
YES
NO
SMALL TV
MSL3088
8
60mA
YES
YES
NO
YES
SMALL TV
8
60mA
NO
YES
YES
NO
MONITOR, INDUSTRIAL PANEL
4**
120mA
NO
YES
YES
NO
MONITOR, INDUSTRIAL PANEL
2**
240mA
NO
YES
YES
NO
MONITOR, INDUSTRIAL PANEL
1**
480mA
NO
YES
YES
NO
MONITOR, INDUSTRIAL PANEL
4
120mA
YES
YES
YES
NO
MONITOR, AUTOMOTIVE
MSL3080
MSL3040*
MSL3041*
MSL3050*
MSL3060*
4
120mA
YES
YES
YES
YES
MONITOR, AUTOMOTIVE
5
60mA
NO
YES
YES
NO
INDUSTRIAL PANEL
1**
300mA
NO
YES
YES
NO
INDUSTRIAL PANEL
6
60mA
NO
YES
YES
NO
MONITOR, INDUSTRIAL PANEL
3**
120mA
NO
YES
YES
NO
MONITOR, INDUSTRIAL PANEL
2**
180mA
NO
YES
YES
NO
MONITOR, INDUSTRIAL PANEL
1**
360mA
NO
YES
YES
NO
MONITOR, INDUSTRIAL PANEL
*
Future product, contact factory for information.
** Drivers without phase shift allow parallel connection of string drive outputs for increased string current.
*** Drivers with separate SYNC input expect two input control signals, one for dimming duty cycle and one for dimming frequency.
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
1
DBIE-20120802
Table of Contents
1.0 Document Scope.......................................................................................... 3
2.0Hardware.................................................................................................... 4
3.0 Basic Operation............................................................................................ 5
4.0 I²C/SMBus Compatible Serial Interface...................................................... 6
4.1
Overview & Timing............................................................................................................6
4.2I2C Bus Timeout................................................................................................................6
4.3I2C Bit Transfer.................................................................................................................7
4.4I2C START and STOP Conditions.....................................................................................7
4.5I2C START and STOP Conditions.....................................................................................7
4.6I2C Slave Address.............................................................................................................8
4.7I2C Message Format for Writing to the MSL3040/41/50/60/80/86/87/88..........................8
4.8I2C Message Format for Reading Registers.....................................................................9
4.9
Register Map..................................................................................................................10
4.10
Register Details.............................................................................................................. 11
4.11
System Control Register 0x01........................................................................................ 11
4.12
Fault Enable Register 0x02............................................................................................ 11
4.13
String Fault Enable Register 0x03..................................................................................12
4.14
Short Circuit Threshold Control Register 0x04...............................................................12
4.15
Fault Status Register 0x05.............................................................................................12
4.16
String Open Circuit Status Register 0x06.......................................................................13
4.17
String Short Circuit Status Register 0x07.......................................................................13
4.18
String Enable Status Register 0x08................................................................................13
4.19
Boost/Boot-Load Status Register 0x09..........................................................................13
4.20
Efficiency Optimizer DAC Readback Register 0x0C......................................................13
4.21
Efficiency Optimizer Status Register 0x0D.....................................................................13
4.22
PWM Control Register 0x10...........................................................................................14
4.23
PWM Frequency/Phase Registers 0x11 and 0x12.........................................................15
PWM Duty Cycle Registers 0x13 and 0x14....................................................................15
4.24
4.25 Reserved registers 0x20-0x23........................................................................................15
4.26
Sleep Registers 0x7F.....................................................................................................15
4.27
Efficiency Optimizer Control Registers 0x84 and 0x85*.................................................16
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
2
1.0 Document Scope
This MSL3040/41/50/60/80/86/87/88 Programmers Guide is an addendum to the datasheets MSL3040/MSL3041, MSL3050/MSL3060/MSL3080
and MSL3086/MSL3087/MSL3088, and gives detailed information and instructions on how to configure, monitor, and control the LED drivers
through the I2C compatible serial interface. These drivers operate without I2C serial port access; using the serial port allows access to advanced
features, dimming modes, fault detection and monitoring modes, and test and debug features.
All registers are volatile and reset when power is removed, when the driver is turned off by the hardware enable input (EN), or when automatically
shut-off due to an over-temperature event. If a configuration other than the default programmed configuration is used, it must be loaded each time
the driver is turned on. Note that non-standard configurations are available from the factory, contact the factory for information.
Register default values for each driver are listed in the Register Details section where appropriate.
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
3
MSL3040/41/50/60/80/86/87/88 Programmers Guide
2.0 Hardware
Hardware ___________________________________________________________
Figure 1.1: LED Driver Block Diagram
Figure 1. LED Driver Block Diagram
Basic Operation ______________________________________________________
All MSL30xx drivers, except the MSL3087, include a boost regulator controller to make a voltage, VLED, that powers the
LEDs. The boost regulator accepts an input voltage of 5V to 32V and boosts it up to a maximum of 40V (limited by the
voltage stand-off rating of the STRn driver outputs). VLED is controlled by a resistive voltage divider, RTOP and RBOTTOM in
Figure 1 above, connected to the controller feedback input FB. The Efficiency Optimizer monitors LED driver voltage and
drives FB to control the VLED voltage to minimize power use while assuring proper LED current. The MSL3087 controls an
external boost regulator with its Efficiency Optimizer output, FBO, which also allows daisy-chaining with other drivers in
the family to drive additional strings from a single optimized power supply. Provision is made for boost regulator control
loop compensation via the COMP input.
Internally or externally generated PWM dimming signals gate the LED string current-sink outputs STRn (the number of
strings vary for different members of the MSL30xx family, Table 1 on page 1). A single external PWM signal connected to
the PWM input distributes to all strings via the string drive logic (Figure 1), with most drivers phase shifting the dimming
signals (Table 1). The additional SYNC input allows separate frequency control for the MSL3088 and MSL3041. All
drivers allow internal register control of PWM dimming frequency and duty cycle (in the place of external inputs) via the
Atmel
MSL3040/41/50/60/80/86/87/88
Programmers
I2C compatible serial interface. All parts in this family have
a requirement
of minimum on time
of 3µs. Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
Page 2 of 15
4
3.0 Basic Operation
All MSL30xx drivers, except the MSL3087, include a boost regulator controller to make a voltage, VLED, that powers the LEDs. The boost regulator
accepts an input voltage of 5V to 32V and boosts it up to a maximum of 40V (limited by the voltage stand-off rating of the STRn driver outputs).
VLED is controlled by a resistive voltage divider, RTOP and RBOTTOM in Figure 1 above, connected to the controller feedback input FB. The Efficiency
Optimizer monitors LED driver voltage and drives FB to control the VLED voltage to minimize power use while assuring proper LED current. The
MSL3087 controls an external boost regulator with its Efficiency Optimizer output, FBO, which also allows daisy-chaining with other drivers in the
family to drive additional strings from a single optimized power supply. Provision is made for boost regulator control loop compensation via the
COMP input.
Internally or externally generated PWM dimming signals gate the LED string current-sink outputs STRn (the number of strings vary for different
members of the MSL30xx family, Table 1 on page 1). A single external PWM signal connected to the PWM input distributes to all strings via the
string drive logic (Figure 1), with most parts in the family phase shifting the dimming signals (Table 1). The additional SYNC input allows separate
frequency control for the MSL3088 and MSL3041. All drivers allow internal register control of PWM dimming frequency and duty cycle (in the place
of external inputs) via the I2C compatible serial interface. All parts in this family have a requirement of minimum on time of 3µs.
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
5
I²C/SMBus Compatible Serial Interface __________________________________
I²C/SMBus
Compatible Serial Interface __________________________________
Overview and Timing
The I2C Compatible
serial
interface
allows access
to the control and status registers. The Register Map section shows register
Overview
and
Timing
4.0 I²C/SMBus
Serial
Interface
definitions
andinterface
the Register
Details
section
register
functions
default
settings.
The
I2C serial
allows
access
to theshows
controldetailed
and status
registers.
The and
Register
Map
sectionThe
shows register
MSL3040/41/50/60/80/86/87/88
operate
as
I²C/SMBus
slaves
that
send
and
receive
data
to
a master.
the Register Details section shows detailed register functions and default settings.
The The interface is
4.1 definitions
Overview and
& Timing
needed only to allow control andoperate
monitoring
over someslaves
functions
advanced
features,
and
is not required
for basic
MSL3040/41/50/60/80/86/87/88
as I²C/SMBus
thatand
send
and receive
data to
a master.
The interface
is
operation.
When
not
using
the
serial
interface,
connect
SDA
and
SCL
to
GND.
2
The
I
C
serial
interface
allows
access
to
the
control
and
status
registers.
The
Register
Map
section
shows
register
definitions
and
the
needed only to allow control and monitoring over some functions and advanced features, and is not required for basic
Register Details
section
detailed
register
functions and
default SDA
settings.
The
MSL3040/41/50/60/80/86/87/88
operate as I²C/SMBus
operation.
When
notshows
using
the serial
interface,
connect
and
SCL
to GND.
slaves
that send
and receive
data to a
The interface
needed
onlycommunication.
to allow control andThe
monitoring
overuses
somebi-directional
functions and data lin
The serial
interface
is suitable
formaster.
100kHz,
400kHzisand
1MHz
interface
advanced
features,
and is not
required
for basicbidirectional
operation. When
not using the serial
interface,master
connect and
SDA slaves.
and SCL to
GND.
SDA
and
clock
input
SCL
to
achieve
communication
between
The
FLTB fault output
The serial interface is suitable for 100kHz, 400kHz and 1MHz communication. The interface uses bi-directional
data lin
optionally
alerts
the
host
system
to
faults.
During
over
temperature
shutdown
the
serial
interface
is
disabled
and regist
SDA
andinterface
clock input
SCLforto100kHz,
achieve
bidirectional
between
and slaves.
FLTB
The serial
is suitable
400kHz
and 1MHzcommunication
communication. The
interface master
uses bi-directional
data The
line SDA
andfault
clockoutput
settings
are
reset
tohost
theirsystem
default
values.
input
SCL to
achieve
bidirectional
communication
slaves. The shutdown
FLTB fault output
optionally
alerts the
systemand
to registe
optionally
alerts
the
to
faults.between
Duringmaster
over and
temperature
the serial
interface
ishost
disabled
faults. During
temperature
the serial interface is disabled and register settings are reset to their default values.
settings
areover
reset
to their shutdown
default values.
The master, typically a microcontroller, initiates all data transfers, and generates the clock that synchronizes the transf
The
master,
typically
microcontroller,
data transfers,
and generates
the clock only
that synchronizes
the
transfers.
SDAoutput),
operates and doe
SDA
operates
asaboth
input initiates
and anallinitiates
open-drain
output.
SCL operates
as a
slave
input
(master
The
master,
a an
microcontroller,
allasdata
transfers,
andoutput),
generates
the
clock
thatclock-stretching.
synchronizes
the transfe
as both
an inputtypically
and an open-drain
output. SCL operates
only
a slave
input (master
and does
not
perform
Use
not
perform
clock-stretching.
Use
pull-ups
on
SDA,
SCL
and
FLTB.
SDA
operates
as both
an input and an open-drain output. SCL operates only as a slave input (master output), and doe
pull-ups
on SDA, SCL
and FLTB.
not perform clock-stretching. Use pull-ups on SDA, SCL and FLTB.
Figure 4.1: I2C Interface Connections
Figure 2. I2C Interface Connections
Figure 2. I2C Interface Connections
transmission
consists
of a condition
START sent
condition
sentaby
a slave
master,
a 7-bit
address
plus one R/W
bit, an
acknowledg
AAtransmission
consists
of a START
by a master,
7-bit
address
plus slave
one R/W
bit, an acknowledge
bit, none
or many
data
bytes
each
separated
bybytes
an acknowledge
bit, and a STOP
condition
(Figure 4.2,
Figure
4.3
and Figure
4.4). (Figure 3, Figure 4 and Fig
bit,
none
or
many
data
each
separated
by
an
acknowledge
bit,
and
a
STOP
condition
A transmission consists of a START condition sent by a master, a 7-bit slave address plus one R/W bit, an acknowledge
5). none or2 many data bytes each separated by an acknowledge bit, and a STOP condition (Figure 3, Figure 4 and Fig
bit,
Figure 4.2: I C Serial Interface Timing Details
5).
SDA
SDA
tSU:DAT
tLOW
tHD:DAT
tLOW
SCL
SCL tHD:STA
Figure
START
CONDITION
START
CONDITION
3.
I2C Serial
tSU:STA
tHD:STA
tHD:STA
tSU:STO
tBUF
tSU:STO
tHIGH
tR
tHD:STA
tHD:DAT
tSU:DAT
tBUF
tSU:STA
tR
tHIGH
tF
tF
Interface Timing Details
REPEATED START
CONDITION
REPEATED START
CONDITION
STOP
START
CONDITION CONDITION
STOP
START
CONDITION CONDITION
2
I C Serial Interface Timing Details
2
4.2IFigure
C Bus3.Timeout
I2C Bus Timeout
The
2 bus timeout feature (register 0x02 bit D7) allows the MSL3040/41/50/60/80/86/87/88 to reset the serial bus interface if a communication
The
bus
timeout
feature
(register
D7)
allows
theforMSL3040/41/50/60/80/86/87/88
to resetterminates,
the serialSDA
bus interfa
Iceases
C Bus
Timeout
before
a STOP
condition
is sent. If0x02
eitherbit
SCL
or SDA
is low
more than 30ms (typical), then the transaction
releases
and the interface
waits before
for another
START condition.
a communication
ceases
a STOP
condition is sent. If either SCL or SDA is low for more than 30ms (typical), the
The bus timeout feature (register 0x02 bit D7) allows the MSL3040/41/50/60/80/86/87/88 to reset the serial bus interfac
transaction terminates,
SDA areleases
and the interface
another
START
athe
communication
ceases before
STOP condition
is sent. Ifwaits
eitherfor
SCL
or SDA
is lowcondition.
for more than 30ms (typical), the
the transaction terminates, SDA releases and the interface waits for another START condition.
I2C Bit Transfer
2
dataTransfer
bit is transferred during each clock pulse. Ensure SDA is stable while SCL is high.
IOne
C Bit
PageSDA
3 of 15is stable while SCL is high.
One data bit is transferred during each clock pulse. Ensure
Page 3 of 15
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
6
4.3 I2C Bit Transfer
MSL3040/41/50/60/80/86/87/88 Programmers Guid
One data bit is transferred during each clock pulse. Ensure SDA is stable while SCL is high.
MSL3040/41/50/60/80/86/87/88
Programmers Guide
Guide
MSL3040/41/50/60/80/86/87/88 Programmers
Figure 4.3: I2C Bit Transfer
Figure
4.I2I22CCBit
Bit Transfer
Figure
4.
Figure 4. I C Bit Transfer
Transfer
4.4I2C START and STOP Conditions
2
2
SCL and SDA
remain
high when
the interface is free. The master signals a transmission with a START condition by transitioning SDA
IIBoth
C
START
and
STOP
Conditions
STOP
Conditions
I2C
C START
START and
and
STOP
Conditions
from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning
Both
SCLlow
and
SDA
remain
when
interface
is free.
The
master
signals
a transmission
with a condition
START
b
Both
SCL
and
remain
when
interface
is
free.
The master
master
signals
transmission
with aa START
START
conditioncondition
by
SDA
to SDA
high
while
SCLhigh
ishigh
high.
The the
busthe
is then
free.
Bothfrom
SCL
and
SDA
remain
high
when
the
interface
is free.
The
signals
aa transmission
with
by
transitioning
SDAfrom
fromhigh
high
low
while
SCL
is high.
When
the master
has finished
communicating
the
transitioning
to
low
while
SCL
is
When
the master
master
has finished
finished
communicating
with the
thewith
slave,
transitioning SDA
SDA
from
high
to to
low
while
SCL
is high.
high.
When
the
has
communicating
with
slave,
itit slave, it
issues
aaaSTOP
condition
by
transitioning
from
low
to high
high
whilewhile
SCL is
is
high.
The
bus
is then
then
free.
Figure
I2C START
and STOP
ConditionsSDA
issues
STOP
condition
transitioning
SDA
to high
SCL
is The
high.
The
bus is
then free.
issues 4.4:
STOP
condition
byby
transitioning
SDA
fromfrom
low low
to
while
SCL
high.
bus
is
free.
SCL
SCL
SCL
11
1
2
2
2
88
8
99
9
11
1
SDA
SDA
SDA
TRANSMITTER
TRANSMITTER
TRANSMITTER
SDA
SDA
RECEIVER
SDA
RECEIVER
NOT ACKNOWLEDGE
ACKNOWLEDGE
NOT
BYNOT
RECEIVER
ACKNOWLEDGE
BY
RECEIVER
RECEIVER
START
START
CONDITION
CONDITION
START
CONDITION
4.5
2
Figure
5.
Figure
5. II2C
C START
START and
and STOP Conditions
2
BY RECEIVER
ACKNOWLEDGE BY
BY
ACKNOWLEDGE
RECEIVER
RECEIVER
ACKNOWLEDGE BY
RECEIVER
I C Acknowledge Bit
Figure 5. I2C START and STOP Conditions
2 acknowledge bit is a clocked 9th bit which the recipient uses to handshake receipt of each 8-bit byte of data. The master generates
IThe
I2C
C Acknowledge
Acknowledge Bit
the 9th clock pulse, and the recipient holds SDA low during the high period of the clock pulse. When the master is transmitting to the slave,
2 acknowledge bit is a clocked 9th bit which the recipient
receipt
of each
each
8-bitpulls
byteSDA
of data.
data.
The
The
acknowledge
bitbecause
is aBit the slave is the recipient. When the slave
usesistotransmitting
handshake
receipt
of
8-bit
byte
of
The
the
pulls SDA low
to the
master,
the
master
low because
IThe
Cslave
Acknowledge
master
generates
the
high period
period of
of the
the clock
clock pulse.
pulse. When
When the
the
master
generates
the 9th
9th clock pulse, and the recipient holds SDA low during the high
the
master
is the recipient.
The
acknowledge
bit isthe
a clocked
9thslave
bit which
the recipient uses to handshake
receipt of
eachthe
8-bit
byte
master
slave, the
pulls SDA
the recipient.
recipient.
When
slave
is of data. The
master is
is transmitting
transmitting to
to
low because the slave is the
When
the slave
is
2
master
generates
the
9th
clock
pulse,
and
the
recipient
holds
SDA
low
during
the
high
period
of
the
clock
pulse. When
Figure
4.5:
I
C
Acknowledge
transmitting
recipient.
transmitting to
to the
the master,
master, the master pulls SDA low because the master is the recipient.
master is transmitting to the slave, the slave pulls SDA low because the slave is the recipient. When the slave is
transmitting to the master, the master pulls SDA low because the master is the recipient.
Figure 6.
6. II22C
C Acknowledge
Acknowledge
Figure
Figure 6. I2C Acknowledge
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
Page 4 of and
15 Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
7
MSL3040/41/50/60/80/86/87/88
Programmers Guide
Guide
MSL3040/41/50/60/80/86/87/88 Programmers
4.6 I22C Slave Address
I 22C Slave Address
I C Slave Address
The MSL3040/41/50/60/80/86/87/88 have a 7-bit long slave address, 0b1010000, followed by an eighth bit, the R/W bit, that combine to
The
MSL3040/41/50/60/80/86/87/88 have
a 7-bit
long
slave
address,
0b1010000,
followed
by
an
eighth
bit,
the
R/W
bit,
The
have
long
slave
address,
0b1010000,
followed
by an
an
eighth
bit,
the
R/W
bit,
The MSL3040/41/50/60/80/86/87/88
MSL3040/41/50/60/80/86/87/88
have a
a 7-bit
7-bit
long
slave
address,
0b1010000,
followed
by
eighth
bit,
make
2 separate 8-bit read and write addresses
(i.e. the
slave
addresses
are
0xA0 for write
operations
and
0xA1bit,
forthe
readR/W
operations).
that
combine
to
make
2
separate
8-bit
read
and
write
addresses
(i.e.
the
slave
addresses
are
0xA0
for
write
operations
that
combine
to
make
2
separate
8-bit
read
and
write
addresses
(i.e.
the
slave
addresses
are
0xA0
for
write
operations
The
bit is low
for a write
and high8-bit
for a read.
have
the same 0xA0/0xA1
address;
when using
thatR/W
combine
to make
2 separate
read All
andMSL3040/41/50/60/80/86/87/88
write addresses (i.e. the slave
addresses
are 0xA0 slave
for write
operations
and
0xA1
for
read
operations).
The
R/W
bit
is
low for
a
and
high
for
a read.
All
MSL3040/41/50/60/80/86/87/88
have
and
for
operations).
bit
is
for
a write
write
and
high for
for
read.
All MSL3040/41/50/60/80/86/87/88
MSL3040/41/50/60/80/86/87/88
have
multiple
drivers
and communicating
withR/W
them
their
serial and
interfaces,
make
external
provision to route the serial interface
to the
and 0xA1
0xA1
for read
read
operations). The
The
R/W
bitthrough
is low
low for
a
write
high
aa read.
All
have
the
same
0xA0/0xA1
slave
address;
when
using
multiple
drivers
and
communicating
with
them
through
their
serial
the
same
0xA0/0xA1
slave
address;
when
using
multiple
drivers
and
communicating
with
them
through
their
serial
appropriate
driver.
the same 0xA0/0xA1 slave address; when using multiple drivers and communicating with them through their serial
interfaces,
make external
provision to
route the
serial
to
the
appropriate
driver.
interfaces,
serial interface
interface to
to the
the appropriate
appropriate driver.
driver.
interfaces, make
make external
external provision
provision to
to route
route the
the serial
interface
Figure 4.6: I2C Slave Address
SDA
SDA
SDA
A7
=1
A7
A7 == 11
A6
=0
A6
A6 == 00
A5
=1
A5
A5 =
=1
1
A4
=
A4
=0
0
A4 =
0
A5
=0
A5 =0
=0
A5
A6
A6 ==
= 00
0
A6
A7
A7 ==
= 00
0
A7
R/W
W
RR//W
A
AA
2
22
3
33
4
4
4
5
55
6
66
7
77
8
88
9
99
MSB
MSB
MSB
SCL
SCL
SCL
1
11
2
2 Slave Address
Figure
Figure
7.
C
Figure 7.
7. III2C
C Slave
Slave Address
Address
4.7I2C Message Format for Writing to the MSL3040/41/50/60/80/86/87/88
II222C
Format
the
C Message
Message
Format for
for Writing
Writing to
to
the MSL3040/41/50/60/80/86/87/88
MSL3040/41/50/60/80/86/87/88
A write
to the MSL3040/41/50/60/80/86/87/88
contains
the slave address, the R/W bit cleared to 0, and at least 1 byte of information. The
A
contains
the
slave
address,
the
R/W
bit
cleared
to
0,
and
at
least
byte
of
A
write
to
the
MSL3040/41/50/60/80/86/87/88
contains
theaddress
slave address,
address,
the as
R/W
bit cleared
cleared
to 0,
0,
and
atleast
least11
1byte
byteregister
of
first
byteto
of the
information
is the register address byte. The
register
byte is stored
a register
pointer,
and
determines
which
A write
write
to
the MSL3040/41/50/60/80/86/87/88
MSL3040/41/50/60/80/86/87/88
contains
the
slave
the
R/W
bit
to
and
at
of
information.
The
first
byte
of
information
is
the
register
address
byte.
The
register
address
byte
is
stored
as
a
register
the
following
byte
is
written
into.
If
the
MSL3040/41/50/60/80/86/87/88
detect
a
STOP
condition
after
the
register
address
byte
is
received,
information.
The
first
byte
of
information
is
the
register
address
byte.
The
register
address
byte
is
stored
as
a
register
information. The first byte
The register address byte is stored as a register
pointer,
and
determines
which
register
the
byte
is written
written into.
into.
the
MSL3040/41/50/60/80/86/87/88
detect
then
it takes
further action
beyond
setting
thefollowing
register pointer.
pointer,
and
determines
which
register
the
following
into. IfIf
If the
the MSL3040/41/50/60/80/86/87/88
MSL3040/41/50/60/80/86/87/88detect
detectaa
a
pointer,
andno
determines
which
byte is
STOP
after
the
register
then itit takes
takes
no
further
action
beyond
setting
the
register
STOP
condition
after
the
register address
address byte
byte is
is received,
takes no
no further
further action
action beyond
beyond setting
settingthe
theregister
register
STOP condition
condition
after
the
received,
then
Figure 4.7: I2C Writing a Register Pointer
pointer.
pointer.
pointer.
ACKNOWLEDGE
ACKNOWLEDGE
FROM
ACKNOWLEDGE FROM
SLAVE
SLAVE
SLAVE
START
START
START
SDA
SDA
SDA
111
000
111
000
000
000
000
000
A
A
A
D7
D7
ACKNOWLEDGE
ACKNOWLEDGE
FROM
FROM SLAVE
SLAVE
..
SLAVE
SLAVE
ADDRESS,
SLAVE ADDRESS,
ADDRESS,
WRITE
WRITE
ACCESS
WRITE ACCESS
ACCESS
..
..
..
..
..
D0
D0
STOP
STOP
STOP
A
A
SET
SET REGISTER
REGISTER
POINTER
POINTER TO
TO X
X
THE
THE
REGISTER
POINTER
NOW
POINTS TO
TO X;
X; A
A SUBSEQUENT
SUBSEQUENT READ
READ
THEREGISTER
REGISTER POINTER
POINTER NOW
NOW POINTS
ACCESS
X
ACCESS
READS FROM
FROM REGISTER
REGISTER ADDRESS
ACCESS READS
ADDRESS X
2
Figure
Figure 8.
8. III22C
C Writing
Writing a
Register Pointer
Figure
8.
C
Writing
aa Register
Register
Pointer
When no STOP condition is detected, the byte transmitted after the register address byte is a data byte, and is placed into the register
pointed
to by
the register
address
byte. To simplify
writing
to multiple
consecutive
registers,
the register
duringinto
each
When
STOP
condition
is
the
transmitted
after
the
address
byte
is
data
byte,
and
placed
into
When no
no
STOP
condition
address
byte
aa
byte,
When
no
STOP
condition
is detected,
detected,
the byte
byte
transmitted
after
the register
register
address
byte is
ispointer
a data
dataauto-increments
byte,and
andisis
isplaced
placed
into
following
acknowledge
period;
dataaddress
bytes transmitted
a STOP
fill subsequent
registers.
the
pointed
by
register
byte.
simplify
multiple
consecutive
registers,
the
register
the register
register
pointed to
to
by the
writingcondition
to
consecutive
registers,
the
register
pointed
to
by
thefurther
register
address
byte. To
To before
simplify
to multiple
multiple
consecutive
registers,the
theregister
register
pointer
data
bytes
transmitted
before
STOP
pointer auto-increments
auto-increments during
during each
pointer
auto-increments
during
each following
following acknowledge
acknowledge period;
period; further
further data
data bytes
bytes transmitted
transmitted before
beforeaa
aSTOP
STOP
Figure 4.8:fillI2C
Writing Two Data Bytes
condition
condition fill
fill subsequent
subsequent registers.
condition
subsequent
registers.
ACKNOWLEDGE
ACKNOWLEDGE FROM
ACKNOWLEDGE
FROM
SLAVE
SLAVE
SLAVE
START
START
START
SDA
SDA
SDA
111
000
111
000
000
000
000
000
A
A
A
D7
D7
D7
...
SLAVE
SLAVE ADDRESS,
ADDRESS,
SLAVE
ADDRESS,
WRITE
WRITE ACCESS
ACCESS
WRITE
ACCESS
ACKNOWLEDGE
ACKNOWLEDGE FROM
FROM
SLAVE
SLAVE
...
..
..
..
..
D0
D0
A
A
D7
D7
SET
SET REGISTER
REGISTER
POINTER
POINTER TO
TO X
X
..
ACKNOWLEDGE
FROM
ACKNOWLEDGE
ACKNOWLEDGE FROM
FROM
SLAVE
SLAVE
SLAVE
...
...
...
...
...
WRITES
TO
DATA
DATA WRITES
WRITES TO
TO
REGISTER
X
REGISTER
REGISTER X
X
D0
D0
D0
AA
A
D7
D7
D7
ACKNOWLEDGE
FROM
ACKNOWLEDGE
ACKNOWLEDGEFROM
FROM STOP
STOP
STOP
SLAVE
SLAVE
SLAVE
...
...
. ..
. ..
. ..
. ..
D0
D0
D0 AA
A
DATA
WRITES
TO
DATA
DATAWRITES
WRITESTO
TO
REGISTER
REGISTER
REGISTERXX
X++
+11
1
THE
POINTER
NOW
POINTS
TO
2;
SUBSEQUENT
READ
THE REGISTER
REGISTER POINTER
POINTER NOW
NOW POINTS
POINTS TO
TOXX
X++
+2;
2;AA
ASUBSEQUENT
SUBSEQUENTREAD
READ
BEGINS
READING
FROM
REGISTER
ADDRESS
ACCESS
ACCESS BEGINS
BEGINS READING
READING FROM
FROMREGISTER
REGISTERADDRESS
ADDRESSXX
X++
+22
2
2
Figure
C Writing
Writing Two
Two Data
Data Bytes
Figure 9.
9. III22C
C
Writing
Two
Data
Bytes
Figure
9.
Page
Page 55 of
of 15
15
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
8
MSL3040/41/50/60/80/86/87/88 Programmers Guid
MSL3040/41/50/60/80/86/87/88 Programmers Guide
I2C Message Format for Reading Registers
2
4.8 IRead
C Message
Format
for one
Reading
the registers
using
of twoRegisters
techniques.
I2C Message
Format
for Reading
Registers
Read
using
oneone
of two
Readthe
theregisters
registers
using
of techniques.
two techniques.
The first technique begins the same way as a write, by setting the register address pointer as shown in Figure 8, includ
the first
STOP
condition
(note
that
even
though
the
final
objective
is to read
data,
the R/W
bit is 4.7,
first
sent8,asincluding
a write
The
begins
thethe
same
way
as a
write,
by
setting
the
register
address
pointer
as
shown
Figure
including
the
STOP because
The
firsttechnique
technique
begins
same
way
as
a write,
by
setting
the register
address
pointer
asinshown
in
Figure
condition
(note
that
even
though
the
final
objective
is
to
read
data,
the
R/W
bit
is
first
sent
as
a
write
because
the
address
pointer
byte
is
the
address
pointer
byte
is
being
written).
Follow
the
Figure
8
transaction
by
that
shown
in
Figure
10,
with
STAR
the STOP condition (note that even though the final objective is to read data, the R/W bit is first sent as a write becausea new
being
written).
Follow
Figure
4.7 transaction
by that
shown
inR/W
Figure
4.9,
new
START condition
and
the slave
thisinitiated
time
condition
and
the the
slave
this time
with
the
set with
to 1ato
indicate
a read.
Then,
afteraaddress,
the
the
address
pointer
byte
isaddress,
being
written).
Follow
the
Figure
8bit
transaction
by
that
shown
in Figure
10,
with
newslave
START
with the R/W bit set to 1 to indicate a read. Then, after the slave initiated acknowledge bit, clock out as many bytes as desired, separated
condition
and theacknowledges.
slave
address,
timeauto-increments
with the
R/W bit
setseparated
to
1 to indicate
a read.
Then, after
the End
slave
initiated
acknowledge
clock
out The
as this
many
as desired,
master
initiated
acknowledges.
The pointer
by
master initiatedbit,
pointer bytes
during
each masterby
initiated
acknowledge
period.
the transmission
with autoacknowledge
bit,
clock
out
as
many
bytes
as
desired,
separated
by
master
initiated
acknowledges.
The
pointer
autoincrements
during
each
master
initiated
acknowledge
period.
End
the
transmission
with
a
not-acknowledge
followed by
a not-acknowledge followed by a stop condition.
increments
during each master initiated acknowledge period. End the transmission with a not-acknowledge followed by a
stop condition.
stop condition.
Figure
4.9: I2C Reading Register Data with Preset Register Pointer
Figure 10. I2C2 Reading Register Data with Preset Register Pointer
Figure 10. I C Reading Register Data with Preset Register Pointer
The
technique
is illustrated
in Figure
4.10. Set
pointerpointer
as shown
Figure in
4.6Figure
without7 sending
STOP condition,
Thesecond
secondread
read
technique
is illustrated
in Figure
11.the
Setregister
the register
asinshown
withoutasending
a
send
a
repeated
START
condition
after
the
second
acknowledge
bit,
then
send
the
slave
address
again
with
the
R/W
bit
set
1 to again
indicate
The
second
read
technique
is
illustrated
in
Figure
11.
Set
the
register
pointer
as
shown
in
Figure
7towithout
sending a
STOP condition, send a repeated START condition after the second acknowledge bit, then send the slave address
a read. Then clock out the data bytes separated by master initiated acknowledge bits. The register pointer auto-increments during each
STOP
repeated
START
after
thebytes
second
acknowledge
bit,
then send
the slave
address aga
with
thecondition,
R/W bit set send
to 1 toaindicate
a read.
Thencondition
clock out the
data
separated
by master
initiated
acknowledge
bits.
master initiated acknowledge period. End the transmission with a not-acknowledge followed by a stop condition. Use this technique for
The
pointer
each
master
initiated
acknowledge
period.
End the
with aacknowledge
notwithregister
the
bit masters,
setauto-increments
to 1because
to indicate
a read.
Then
clock
outinthe
data
bytestransaction.
separated
bytransmission
master initiated
bi
buses
with R/W
multiple
the during
read
sequence
is performed
one
continuous
acknowledge
by a stop condition.during
Use this
technique
buses with
multiple masters,
because
thetransmission
read
The register followed
pointer auto-increments
each
masterforinitiated
acknowledge
period.
End the
with a not
sequence
is performed
onea continuous
transaction.
Figure 4.10:
I2Cfollowed
ReadinginRegister
Data
Using
a Repeated
acknowledge
by
stop
condition.
Use thisSTART
technique for buses with multiple masters, because the read
sequence is performed in one continuous transaction.
ACKNOWLEDGE
FROM SLAVE
START
ACKNOWLEDGE
FROM SLAVE
START
SDA
SDA
1
0
1
0
0
0
0
0
A
D7
1 SLAVE
0
1 ADDRESS,
0
0
0
0
0
A
WRITE ACCESS
SLAVE ADDRESS,
WRITE ACCESS
ACKNOWLEDGE
FROM SLAVE
REPEATED
START
.
D0
A
.
.
ACKNOWLEDGE
FROM SLAVE
.
.
.
.
. REGISTER
.
.
.
D7SET
POINTER TO X
.
REPEATED
START
1
D0
0
1
A4
ACKNOWLEDGE
FROM SLAVE
NOT ACKNOWLEDGE
STOP
FROM MASTER
ACKNOWLEDGE
FROM SLAVE
A3
A2
A1
A SLAVE1 ADDRESS,
0
1 A4
READ ACCESS
.
.
NOT ACKNOWLEDGE
STO
FROM MASTER
1
A
D7
.
.
.
A3
A2
A1
.
.
REGISTER
1 READ
A D7
ADDRESS X
.
D0
A
.
.
.
.
D0
A
SET REGISTER
SLAVE ADDRESS,
READ REGISTER
THE REGISTER POINTER NOW POINTS TO X + 1; A SUBSEQUENT READ
POINTER TO X
READ READING
ACCESSFROM REGISTER ADDRESS
ADDRESS
ACCESS BEGINS
X+1 X
Figure 11. I2C Reading Register Data Using a Repeated START
THE REGISTER POINTER NOW POINTS TO X + 1; A SUBSEQUENT REA
ACCESS BEGINS READING FROM REGISTER ADDRESS X +
2
Figure 11. I C Reading Register Data Using a Repeated START
Page 6 of 15
Page 6 of 15
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
9
4.9 Register Map
The I2C slave ID is 0xA0 for read and 0xA1 for write. Do not change bits that are not described.
ADDRESS AND
REGISTER NAME
FUNCTION
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
Configuration Registers
0x00
strEnRg
LED String Enables
0x01
sysCtrlRg
System Control
-
eoEn
-
-
actOnBst
OVFlt
actOnStr
SCFlt
actOnStr
OCFlt
-
0x02
fltEnRg
Fault Detect Enable
I2CTimeOutEn
-
-
-
bstOVFltEn
strSCEn
strOCEn
fboOCFltEn
0x03
strFltEnRg
String Fault Enable
-
-
scQualDly
scDbncDly
-
-
fltBDrv
-
-
-
bstOVFltDet
strSCDet
0x04 sCThCtrlRg
SC Threshold control
strEn[7:0]
fltEnStr[7:0]
scThrshLvl[1:0]
Power / Fault Status Registers
0x05
fltStsRg
Fault Status
0x06 strOCStsRg
String Open Circuit Fault Status
0x07 strSCStsRg
String Short Circuit Fault Status
bstStsRg
Boost/Boot-Load Status
fboOCFltDet
strOC[7:0]
strSC[7:0]
0x08 strEnStsRg String Enable Status after auto fault handling
0x09
strOCDet
strEnSts[7:0]
adPwmEn
blRecovDone
blDone
-
-
bstOVFlt
bstPwrGood bstSftStrtDone
Efficiency Optimizer Status
0x0C
eoDacRg
EO DAC Read back
0x0D
eoStsRg
EO Status
-
-
-
fboOCFlt
-
eoDacAct
eoCal
eoInitCal
PWM Control
-
dcMsrMode
phaShft
phaShftpairs
intDuty
intFreq
pwmDrct
syncPol
eoDac[7:0]
PWM Control Registers
0x10 pwmCtrlRg
0x11
0x12
0x13
0x14
0x20
0x21
0x22
0x23
freqPhaRg
Internal Frequency and Phase
dutyCycRg
Internal Duty Cycle
Reserved
Reserved
Reserved
Reserved
freqPha [7:0]
freqPha[15:8]
dutyCyc[7:0]
freqMul[1:0]
-
-
dutyCyc[11:8]
‘0x00’
-
‘0x0’
‘0x00’
-
‘0x0’
Power Management Register
0x7F
sleepRg
Put part to sleep and enable power savings
sleep
slpPwrSv
-
-
-
-
-
-
Efficiency Optimizer Control Registers (MSL3087 only)
0x84
eoCtrl0Rg
EO Control Register 0
hdrmStep[1:0]
aCalDly[1:0]
0x85
eoCtrl1Rg
EO Control Register 1
decrStep[1:0]
incrStep[1:0]
stepDly[1:0]
iCalPWM
aCal100
iSinkConfDly[1:0]
aCalEn
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
iChkDis
10
4.10 Register Details
The following sections describe the MSL3040/41/50/60/80/86/87/88 registers. Factory default settings are listed where appropriate. Where
default values differ between driver types, the defaults for each are listed. Bits labelled “-“ are reserved; do not change them, defective
operation may result. Bits labelled “x” are not used, and so may be written to with any value without adverse effects on operation.
String Enable Register 0x00
ADDRESS AND
REGISTER NAME
0x00
DEFAULT
strEnRg
D7
D6
D5
D4
D3
D2
D1
D0
strEn7
strEn6
strEn5
strEn4
strE3
strEn2
strEn1
strEn0
MSL3040/41
0x0F
0
0
0
0
1
1
1
1
MSL3050
0x1F
0
0
0
1
1
1
1
1
MSL3060
0x3F
0
0
1
1
1
1
1
1
MSL3080/86/87/88
0xFF
1
1
1
1
1
1
1
1
StrEnn: Set String Enable bits to 1 to enable, and clear them to 0 to disable the corresponding LED driver strings. The Efficiency Optimizer
and the fault logic ignore disabled outputs.
4.11 System Control Register 0x01
ADDRESS AND
REGISTER NAME
0x01
sysCtrlRg
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
0x4E
x
eoEn
x
x
actOnBst
OVFlt
actOnStr
SCFlt
actOnStr
OCFlt
x
•eoEn: Efficiency Optimizer Enable; Set to 1 to enable the Efficiency Optimizer to dynamically control the boost regulator output voltage,
Clear to 0 to disable control of the boost regulator output voltage.
•actOnBstOVFlt: Act On Boost Over Voltage Fault; Set to 1 to turn off all LED strings upon detection of a boost over-voltage condition;
this fault is non-latching, strings turn on when the fault goes away. Clear to 0 to ignore boost over-voltage condition. This actOnBstOVFlt
bit is ignored when bstOVFltEn (bit D3 of 0x02) = 0.
•actOnStrSCFlt: Act On String Short Circuit Fault; Set to 1 to turn off LED strings that detect an LED short circuit fault, Clear to 0 to leave
LED strings on that detect an LED short circuit fault. Set the short circuit threshold voltage with the Short Circuit Threshold bits D0 and
D1 of register 0x04. The Efficiency Optimizer ignores outputs that are turned off by an LED short circuit fault. This actOnStrSCFlt bit is
ignored when strSCEn (bit D2 of 0x02) = 0.
•actOnStrOCFlt: Act On String Open Circuit Fault; Set to 1 to stop driving LED strings that are open circuit, Clear to 0 to continue driving
LED strings that are open circuit. Regardless of the state of this bit, the Efficiency Optimizer disregards strings that are open circuit.
When actOnStrOCFlt is low the phase engine does not re-calculate phase shifts when a string open circuit occurs. actOnStrOCFlt bit is
ignored when strOCEn (bit D1 of 0x02) = 0.
4.12 Fault Enable Register 0x02
ADDRESS AND
REGISTER NAME
0x02
fltEnRg
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
0x8F
I2CTime
OutEn
x
x
x
bstOVFltEn
strSCEn
strOCEn
fboOCFltEn
•I2CTimeOutEn: I2C Time Out Enable. Set to 1 to enable I2C bus transaction timeout when the bus is stalled beyond 30ms, Clear to 0 to
disallow I2C bus time out.
•bstOVFltEn: Boost Over-Voltage Fault Enable; Set to 1 to have a boost over-voltage fault pull FLTB low, Clear to 0 to not pull FLTB low
when a boost over-voltage faults occurs. This fault is non-latching.
•StrSCEn: String Short Circuit Fault Enable; Set to 1 to have LED short circuit faults pull FLTB low, Clear to 0 to have LED short circuit
faults not pull FLTB low.
•strOCEn: String Open Circuit Fault Enable; Set to 1 to have string open circuit faults pull FLTB low, Clear to 0 to have string open circuit
faults not pull FLTB low. When this bit is zero and a string open circuit fault occurs, the Efficiency Optimizer attempts to bring the string
back in to current regulation by increasing the boost regulator output voltage up to its highest value, where it remains without indicating
a fault condition. In this state fictitious LED short circuit faults may occur.
•fboOCFltEn: Feedback Out Open Circuit Fault Enable; Set to 1 to have feedback open circuit faults pull FLTB low, Clear to 0 to have
feedback open circuit faults not pull FLTB low. The feedback connection is labelled FBO on the MSL3087, and FB on all others.
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
11
4.13 String Fault Enable Register 0x03
ADDRESS AND
REGISTER NAME
0x03
strFltEnRg
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
0xFF
strFltEn7
strFltEn6
strFltEn5
strFltEn4
strFltEn3
strFltEn2
strFltEn1
strFltEn0
•strFltEnn: Individual string fault enable bits. Set to 1 to enable string fault detection, Clear to 0 to disable string fault detection.
4.14 Short Circuit Threshold Control Register 0x04
ADDRESS AND
REGISTER NAME
0x04
sCThCtrlRg
DEFAULT
D7
D6
D5
D4
D3
D2
0b0000 00__
x
x
scQualDly
scDbncDly
-
x
D1
D0
scThrshLvl[1:0]
•scQualDly: LED Short Circuit Qualification Delay; Clear to 0 for a 256ms short circuit qualification delay, Set to 1 for a 512ms short
circuit qualification delay. An LED short circuit must last for the full qualification delay time to be flagged as a fault.
•scDbncDly: LED Short Circuit De-bounce Delay; Clear to 0 for a 2µs short circuit de-bounce delay, Set to 1 for a 4µs short circuit debounce delay.
•scThrshLvl[1:0]: Short Circuit Threshold Setting; 0b00 = 4.9V, 0b01 = 5.8V, 0b10 = 6.8V, 0b11 = 7.6V. scThrshLvl auto-programs when
EN is taken high. The value scThrshLvl takes is based on the value of the resistor connected from SCTH to GND, RSCTH (Table 2).
MSL3088 has no SCTH input; these bits default to 0b10 = 6.8V.
Table 4.1: Short Circuit Threshold Resistor (RSCTH)
RSCTH
scThrshLvl[1:0]
Threshold Voltage
1.0kΩ (or GND)
0b00
4.9V
27kΩ
0b01
5.8V
68kΩ
0b10
6.8V
330kΩ (or OPEN)
0b11
7.6V
4.15 Fault Status Register 0x05
ADDRESS AND
REGISTER NAME
0x05
fltStsRg
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
Read Only
Clear on
read
fltBDrv
x
x
x
bstOV
FltDet
strSCDet
strOCDet
fboOC
FltDet
• fltBDrv: FLTB Driver; equals 1 when any fault is detected (any bit D0 through D3 is 1). When fltBDrv = 1, the hardware FLTB output is low.
•bstOVFltDet: Boost Over-Voltage Fault Detected; equals 1 when boost over-voltage fault is detected (non-latching).
•strSCDet: String Short Circuit Fault Detected; sets to 1 when any string short circuit fault is detected.
•strOCDet: String Open Circuit Fault Detected; sets to 1 when any string open circuit fault is detected.
•fboOCFltDet: FB Open Circuit Fault Detected; sets to 1 when FB open circuit fault is detected.
Clear faults by reading fault register 0x05 and writing 0xFF to registers 0x06 and 0x07, or by toggling EN low then high.
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
12
4.16 String Open Circuit Status Register 0x06
ADDRESS & REGISTER NAME
0x06
strOCStsRg
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
Read-only Clear on write
strOC7
strOC6
strOC5
strOC4
strOC3
strOC2
strOC1
strOC0
• strOCn: Each bit sets to 1 to indicate that the driver detected an open circuit fault on the corresponding string; read to determine which
strings are faulted. Clear faults by reading fault register 0x05 and writing a ‘1’ to the bit showing a fault, or by toggling EN low then high.
4.17 String Short Circuit Status Register 0x07
ADDRESS & REGISTER NAME
0x07
strSCStsRg
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
Read-only Clear on write
strSC7
strsC6
strSC5
strSC4
strSC3
strSC2
strSC1
strSC0
• strSCn: Each bit sets to 1 to indicate that the driver detected a short circuit fault on the corresponding string; read to determine which
strings are faulted. Clear faults by reading fault register 0x05 and writing a ‘1’ to the bit showing a fault, or by toggling EN low then high.
4.18 String Enable Status Register 0x08
ADDRESS & REGISTER NAME
0x08
strEnSts
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
Read-only
strEnSts7
strEnSts6
strEnSts5
strEnSts4
strEnSts3
strEnSts2
strEnSts1
strEnSts0
•strEnStsn: Each bit sets to 1 to indicate that the corresponding string is turned off due to the enable register 0x00 or due to faults.
4.19 Boost/Boot-Load Status Register 0x09
ADDRESS & REGISTER NAME
0x09
bstStsRg
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
Read-only
-
blRecovD
one
blDone
x
x
bstOVFlt
bstPwr
Good
bstSftStrt
Done
• blRecovDone: Boot-Load Recovery Complete. Sets to 1 when all trim and control registers are ready; signals the boost regulator to begin soft start.
•blDone: Boot-load complete; sets to 1 after the initial register values are loaded.
•bstOVFlt: Boost Over Voltage Fault; sets to 1 when boost controller over-voltage fault is detected (not latching).
•bstPwrGood: Boost Power Good; sets to 1 when boost output power is in regulation.
• bstSftStrtDone: Boost Soft Start Done. Sets to 1 when the boost soft-start is complete; drivers are disabled until bstSftStrDone transitions high.
4.20 Efficiency Optimizer DAC Readback Register 0x0C
ADDRESS & REGISTER NAME
0x0C
eoDacRg
DEFAULT
D7
D6
D5
Read Only
D4
D3
D2
D1
D0
eoDacRg(7:0
•eoDacRg[7:0]: Reports the EO DAC setting, which determines EO (FBO on MSL3087, FB on all other drivers) output current at 1.1µA
per LSB, which in turn controls the boost regulator output voltage.
4.21 Efficiency Optimizer Status Register 0x0D
ADDRESS & REGISTER NAME
0x0D
eoStsRg
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
Read-only
-
-
-
fboOCFlt
-
eoDacAct
eoCal
eoInitCal
• fboOCFlt: Feedback Out Open Circuit Fault; equals 1 when the driver detects an open circuit at feedback (FBO on MSL3087, FB on all
other drivers).
• eoDacAct: Efficiency optimizer DAC active; equals 1 when feedback (FBO on MSL3087, FB on all other drivers) is sourcing current to
the boost regulator feedback node to control the boost regulator output voltage.
• eoCal: Efficiency Optimizer Calibration; equals 1 when the EO is calibrating. The EO automatically re-calibrates VOUT every 1 second.
An EO Calibration will also occur immediately when it detects a loss of string current regulation.
• eoInitCal: Efficiency Optimizer Initial Calibration; equals 1 when the EO is performing an initial calibration. Initial Calibration takes a
maximum of 0.52 seconds.
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
13
4.22 PWM Control Register 0x10
ADDRESS & REGISTER NAME
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
x
dcMsrMode
phaShft
phaShftPairs
intDuty
intFreq
pwmDrct
syncPol
MSL3040
0x72
0
1
1
1
0
0
1
0
0x10
pwmCtrlRg
MSL3041
0x70
0
1
1
1
0
0
0
0
MSL50/60/86/87
0x62
0
1
1
0
0
0
1
0
MSL3080
0x42
0
1
0
0
0
0
1
0
MSL3088
0x60
0
1
1
0
0
0
0
0
• dcMsrMode: Duty Cycle Measure Mode; determines response to a PWM input of less than 20Hz. When dcMsrMode = 1 and the PWM
input is 20Hz or greater, the PWM dimming outputs take the duty cycle of the PWM input signal. When dcMsrMode = 1 and the PWM input
is less than 20Hz the PWM dimming output duty cycle is fixed at 0% when the input is low, and is fixed at 100% when the input is high.
When dcMsrMode = 0 and the PWM input is 20Hz or greater, the PWM dimming signals take the duty cycle of the PWM input signal. When
dcMsrMode = 0 and the PWM input is less than 20Hz, the PWM dimming output duty cycle is fixed at the last valid measured duty cycle
before the input fell to less than 20Hz. This allows a PWM input to set the output duty cycle (with a signal above 20Hz) and then cease
while the outputs continue PWM dimming of the LED strings. When pwmDrct = 1 and phaShft = 1, this bit needs to be set to 1.
• phaShft: Phase Shift; Set to 1 to phase shift the string PWM dimming, Clear to 0 for synchronous PWM dimming. Phase shift control is
valid regardless of the settings of bits D1, D2 and D3 of this register.
• phaShftPairs: Phase Shift in Pairs; Set to 1 to phase shift the string PWM dimming so that adjacent strings operate as pairs, synchronizing
STR0 to STR1, STR2 to STR3, STR4 to STR5 and STR6 to STR7. Clear to 0 for independent string PWM dimming phase.
• intDuty: Internal Duty Cycle; Set to 1 to use registers 0x13 and 0x14 to set the PWM dimming duty cycle, Clear to 0 to use the signal at
the PWM input to set the duty cycle. pwmDrct (Bit D1) = 1 overrides this bit. See Table 3 below.
• intFreq: Internal Frequency; Set to 1 to use registers 0x11 and 0x12 to set the PWM dimming frequency, Clear to 0 to use the signal at
the PWM input (SYNC input for MSL3041 and MSL3088) to set the PWM dimming frequency. pwmDrct (Bit D1) = 1 overrides this bit. See
Table 3 below.
• pwmDrct: PWM Direct; Set to 1 to use the signal at the PWM input to control both the PWM dimming frequency and duty cycle, Clear to 0
to use settings indicated by intDuty (bit D2) and intFreq (bit D3) to determine PWM dimming frequency and duty cycle. See Table 3 below.
• syncPol: Sync Polarity; Set to 1 to synchronize string PWM dimming to the rising edge of the signal at the SYNC input, Clear to 0 to
synchronize to the falling edge. This bit is valid only for the MSL3041 and MSL3088, and ignored by the other drivers.
Table 4.2: Internal/External Frequency and Duty Cycle Selection
MSL3041/50/60/80/86/87
STRING DRIVERS GET
REGISTER BITS
pwmDrct
intDuty
intFreq
DUTY CYCLE
FREQUENCY
INFORMATION FROM
MSL3040/88
STRING DRIVERS GET
DUTY CYCLE
FREQUENCY
INFORMATION FROM
0
0
0
PWM INPUT
PWM INPUT
PWM INPUT
SYNC INPUT
0
0
1
PWM INPUT
0x11, 0x12
PWM INPUT
0x11, 0x12*
0
1
0
0x13, 0x14
PWM INPUT
0x13, 0x14*
SYNC INPUT
0
1
1
0x13, 0x14*
0x11, 0x12*
0x13, 0x14*
0x11, 0x12*
1
x
x
PWM INPUT
PWM INPUT
PWM INPUT
PWM INPUT
*Assure that unused PWM and SYNC inputs are held to logic low.
x = don’t care
NOTE: Regardless of the dimming technique used a minimum on-time of 3µs is required.
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
14
4.23 PWM Frequency/Phase Registers 0x11 and 0x12
ADDRESS & REGISTER NAME
0x11
0x12
DEFAULT
freqPhaRg
D7
D6
D5
D4
D3
0x00
freqPha[7:0]
0x00
freqPha[15:8]
D2
D1
D0
• freqPha[15:0]: PWM Frequency or Phase Setting Registers. When internal frequency is selected via register 0x10, the PWM dimming
frequency equals 20MHz divided by the decimal value of this 16-bit register pair. When using an external signal to set the PWM dimming
frequency (SYNC), this register pair determines the delay time between the edge of the input signal transition and the beginning of the first
enabled string PWM dimming on-time, where the delay time is 50ns times the decimal value of the lower 12-bits; when phase shifting is
enabled, subsequent strings are phase delayed using the first string as the zero-time reference.
4.24 PWM Duty Cycle Registers 0x13 and 0x14
ADDRESS & REGISTER NAME
0x13
0x14
DEFAULT
D7
D6
D5
D4
x
x
0x00
dutyCycRg
D3
D2
D1
D0
dutyCyc[7:0]
0x00
freqMul[1:0]
dutyCyc[11:8]
• dutyCyc: 12-bit PWM Duty Cycle Registers. When internal duty cycle is selected, using register 0x10, PWM dimming duty cycle is a
linear relation where 0x000 = 0% and 0xFFF = 100%. A minimum on-time of 3 µs is required.
• freqMul: SYNC Frequency Multiplier; acts on both internally and externally generated PWM frequency. The PWM control signal
frequency (either applied to PWM or SYNC inputs, or internally generated) is multiplied by the decimal value of these two bits, taken as
LSB = 2^0 and MSB = 2^1, plus 1 to generate the string PWM dimming frequency. This allows synchronized PWM dimming at multiples
of the LCD panel refresh rate. For instance, when freqMul = 0b00 the multiplication factor = 0*(2^1) + 0*(2^0) + 1 = 1.
4.25 Reserved registers 0x20-0x23
These four registers are reserved and should maintain a value of 0x00 for all four bytes.
4.26 Sleep Registers 0x7F
ADDRESS & REGISTER NAME
0x7F
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
0x00
Sleep
slpPwrSv
x
x
-
-
x
x
sleepRg
• sleep and slpPwrSv: Sleep and Sleep Power Save; use these bits together to enter/exit low power sleep mode. When sleep = slpPwrSv
= 1 the driver is asleep and input current is reduced to less than 1.8mA, when sleep = slpPwrSv = 0 the driver operates fully. When
asleep, all the registers maintain their states and the I2C remains active. Table 4 presents low power controls and behaviours.
Table 4. Low Power Controls and Behaviors
EXTERNAL
INPUT
CONTROL BITS
BEHAVIOR
RECOVERY
EN*
sleep
slpPwrSv
LEDS
BOOST
REGULATOR
GATE DRIVER
0
x
x
OFF
OFF
<10µA
1
0
x
ON
ON
<20mA
NA
NA
NA
1
1
0
OFF
ON**
<10mA
520ms
YES
NA
1
1
1
OFF
OFF
<1.8mA
520ms
YES
YES
IVIN
MAX
RECOVERY
TIME
INITITAL
CALIBRATION
CYCLE
SOFT START
520ms
YES
YES
NA = Not Applicable
x = Don’t care
* Taking EN from 0 to 1 returns all register bits to their factory default values.
** VLED goes to VOUT(MAX); this state is available but not recommended.
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
15
4.27 Efficiency Optimizer Control Registers 0x84 and 0x85*
ADDRESS & REGISTER NAME
DEFAULT
D7
D6
D5
D4
0x84
eoCtrl0Rg
0x00
hdrmStep[1:0]
aCalDly[1:0]
0x85
eoCtrl1Rg
0x02
decrStep[1:0]
incrStep[1:0]
D3
D2
stepDly[1:0]
iCaPWM
aCal100
D1
D0
iSinkConfDly[1:0]
aCalEn
iChkDis
*These registers are available only on the MSL3087 and determine how the FBO output controls the external boost regulator.
An initial power supply voltage calibration occurs when the EO is started; the EO is started at power-up, when exiting from sleep or when
EN is taken high.
•hdrmStep: Headroom Step. Bits D6 and D7 of 0x84 set the number of steps the EO takes when raising the boost regulator output
voltage after detecting a current sink error during any calibration cycle; 0b00 = 6 steps, 0b01 = 3 steps, 0b10 = 9 steps and 0b11 = 12
steps. Fewer steps improves efficiency, while more steps offers better immunity from power supply transients and noise. incrStep, bits
D4 and D5 of 0x85, controls the FBO current change of each step.
•aCalDly: Auto-Calibration Delay. Bits D4 and D5 of 0x84 set the time delay between consecutive EO auto-recalibration cycles; 0b00 =
1s, 0b01 = 0.5s, 0b10 = 2s and 0b11 = 4s.
•stepDly: Step Delay. Bits D2 and D3 of 0x84 set the delay time between consecutive boost regulator output voltage corrections; 0b00
= 2ms, 0b01 = 1ms, 0b10 = 4ms and 0b11 = 8ms. Set the correction delay to longer than the power supply settling time.
•iSinkConfDly: Current Sink Confirmation Delay. Bits D0 and D1 of 0x84 set the current sink error confirmation delay time; 0b00 = 0.5µs,
0b01 = 0.25µs, 0b10 = 1µs, 0b11 = 2µs. The current sink error confirmation delay is the time that the current sink error must persist
before the EO recognizes it as a current sink error condition. This prevents erroneous current sink error detection due to noise and other
transients. The driver uses a current sync error to determine that LED string voltage is too low and needs to be increased to maintain
current regulation.
•decrStep: Decrement Step. Bits D6 and D7 control the size of the EO voltage control current changes that happen during Efficiency
Optimizer initial calibration; 0b00 = 3 LSBs, 0b01 = 1 LSB, 0b10 = 2 LSBs and 0b11 = 4 LSB. Each current change equals the
decrStep[1:0] value multiplied by the 1.1µA FBO DAC LSB current value. For example, if decrStep[1:0] = 0b10 then the step setting is 2
LSBs, and each current step is 2 * 1.1µA = 2.2µA. The change in VLED for each step is equal to the change in EO voltage control current
times the value of the top resistor in the boost regulator output voltage divider, RTOP (see datasheet for details).
•incrStep: Increment Step. Bits D4 and D5 of 0x85 control the size of the EO voltage control current correction steps that it takes after
a current sink error is detected. Each correction step current size equals the decimal equivalent of incrStep[1:0] plus 1 multiplied by the
1.1µA FBO DAC LSB current value. For example, if incrStep[1:0] = 0b10 then the step setting is 3, and each current step is 3 * 1.1µA
= 3.3µA. The number of correction steps taken is controlled by hdrmStep, bits D6 and D7 of 0x84. The change in VLED for each step is
equal to the change in EO voltage control current times the value of the top resistor in the boost regulator output voltage divider, RTOP
(see datasheet for details).
•iCalPWM: Initialize Calibration with PWM. Set to 1 to use PWM dimming during EO initial calibration. Clear to 0 to use 100% duty cycle
during EO initial calibration; when initial calibration is complete the driver begins PWM dimming.
•aCal100: Auto Re-Calibration at 100% Duty Cycle. Bit D2 of 0x85; Set to 1 to use 100% duty cycle during auto recalibration. Clear to 0
to use the user controlled PWM dimming during auto recalibration.
•aCalEn: Automatic Re-Calibration Enable. Bit D1 of 0x85; Set to 1 to enable automatic EO boost regulator output voltage recalibration,
Clear to 0 to not auto-recalibrate after initial calibration is complete. EO automatic recalibration periodically minimizes the boost regulator
output voltage after initial calibration to maintain optimal efficiency as the LED string voltage changes with time or temperature. aCalDly
bits D4 and D5 of 0x84 set the delay time between consecutive EO recalibration cycles. Regardless of the aCalEn setting, the EO
always maintains sufficient LED string current sink headroom by raising the boost regulator output voltage should a current regulation
error occur.
•iChkDis: Current Check Disable. Bit D0 of 0x85; Set to 1 to disable current sink error detection for the EO, Clear to 0 to enable current
sink error detection. The EO uses a current sync error to determine that LED string voltage is too low and needs to be increased to
maintain current regulation. Use iChkDis as a debugging or testing tool, not for final production code. Clear eoEn (bit D6 in register 0x01)
to 0 before setting iChkDis to 1. When iChkDis = 1 and eoEn = 1 the EO output forces the string power supply to its minimum output
voltage, possibly causing fictitious string short circuit faults. Setting iChkDis = 1 disables open circuit fault detection of all LED strings.
Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
16
MSL3040/41/50/60/80/86/87/88 Programmers Guide
Figure 4.11. Efficiency Optimizer Initial Calibration Cycle
Figure 12. Efficiency OptimizerInitialCalibrationCycle
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Atmel MSL3040/41/50/60/80/86/87/88 Programmers Guide
4-String 120mA and 5/6/8-String 60mA LED Drivers with Integrated Boost Controller
and Phase Shifted Dimming Boost Controller and Phase Shifted Dimming
17