Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) – Data Sheet Describes Mode 0 Operation • Medium-voltage and Standard-voltage Operation • • • • • • • – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) 5 MHz Clock Rate 64-byte Page Mode and Byte Write Operation Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection Self-timed Write Cycle (5 ms max) High Reliability – Endurance: 100,000 Write Cycles – Data Retention: >100 Years 8-lead PDIP and 8-lead JEDEC SOIC Packages SPI Serial Automotive EEPROMs 128K (16,384 x 8) 256K (32,768 x 8) Description The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable programmable read-only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space saving 8-lead PDIP and 8-lead JEDEC SOIC packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions. AT25128A AT25256A The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write. Block write protection is enabled by programming the status register with top onequarter, top one-half or entire array of write protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Table 1. Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input NC No Connect DC Don't Connect 8-lead PDIP CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 8-lead SOIC CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 8-lead TSSOP CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI Rev. 3404B–SEEPR–9/04 1 Absolute Maximum Ratings* Operating Temperature......................................−40°C to +125°C Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Figure 1. Block Diagram 16384/32768 x 8 2 AT25128A/256A 3404B–SEEPR–9/04 AT25128A/256A Table 2. Pin Capacitance (1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol Test Conditions COUT CIN Note: Max Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. Table 3. DC Characteristics Applicable over recommended operating range from TA = −40°C to +125°C, VCC = +2.7V to +5.5V Symbol Parameter VCC1 Supply Voltage VCC2 Supply Voltage ICC1 Supply Current VCC = 5.0V at 1 MHz, SO = Open, Read ICC2 Supply Current ICC3 Supply Current ISB1 Standby Current Test Condition Min Max Units 2.7 5.5 V 4.5 5.5 V 2.0 3.0 mA VCC = 5.0V at 2 MHz, SO = Open, Read, Write 3.0 5.0 mA VCC = 5.0V at 5 MHz, SO = Open, Read, Write 3.5 6.0 mA VCC = 2.7V, CS = VCC Typ 0.5 12.0 (1) µA 15.0 (1) µA ISB2 Standby Current VCC = 5.0V, CS = VCC IIL Input Leakage VIN = 0V to VCC −3.0 3.0 µA Output Leakage VIN = 0V to VCC −3.0 3.0 µA IOL VIL 2.0 (2) Input Low Voltage −0.6 VCC x 0.3 V (2) Input High Voltage VCC x 0.7 VCC + 0.5 V 0.4 V VIH VOL1 Output Low Voltage VOH1 Output High Voltage VOL2 Output Low Voltage VOH2 Output High Voltage Note: 3.6 ≤ VCC ≤ 5.5V 2.7 ≤ VCC ≤ 3.6V IOL = 3.0 mA IOH = −1.6 mA VCC − 0.8 IOL = 0.15 mA IOH = −100 µA V 0.2 VCC − 0.2 V V 1. Maximum value @+125°C 2. VIL and V IH max are reference only and are not tested. 3 3404B–SEEPR–9/04 Table 4. AC Characteristics Applicable over recommended operating range from TA = −40°C to +125°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5–5.5 2.7–5.5 0 0 5.0 5.0 MHz tRI Input Rise Time 4.5–5.5 2.7–5.5 2 2 µs tFI Input Fall Time 4.5–5.5 2.7–5.5 2 2 µs tWH SCK High Time 4.5–5.5 2.7–5.5 80 80 ns tWL SCK Low Time 4.5–5.5 2.7–5.5 80 80 ns tCS CS High Time 4.5–5.5 2.7–5.5 100 100 ns tCSS CS Setup Time 4.5–5.5 2.7–5.5 100 100 ns tCSH CS Hold Time 4.5–5.5 2.7–5.5 100 100 ns tSU Data In Setup Time 4.5–5.5 2.7–5.5 100 100 ns tH Data In Hold Time 4.5–5.5 2.7–5.5 100 100 ns tHD Hold Setup Time 4.5–5.5 2.7–5.5 100 100 ns tCD Hold Hold Time 4.5–5.5 2.7–5.5 100 100 ns tV Output Valid 4.5–5.5 2.7–5.5 0 0 tHO Output Hold Time 4.5–5.5 2.7–5.5 0 0 tLZ Hold to Output Low Z 4.5–5.5 2.7–5.5 0 0 tHZ Hold to Output High Z tDIS 80 80 ns ns 100 100 ns 4.5–5.5 2.7–5.5 100 100 ns Output Disable Time 4.5–5.5 2.7–5.5 100 100 ns tWC Write Cycle Time 4.5–5.5 2.7–5.5 5 5 ms Endurance(1) 5.0V, 25°C, Page Mode Note: 4 100K Write Cycles 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. AT25128A/256A 3404B–SEEPR–9/04 AT25128A/256A Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128A/256A always operates as a slave. TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128A/256A, and the serial output pin (SO) will remain in a high impedance state un til the falling edge of CS is de tected a gain. This will reinitialize the serial communication. CHIP SELECT: The AT25128A/256A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the SO will remain in a high impedance state. H O LD : Th e H O LD p in is u se d in co n jun ctio n w it h the C S pin to s e le ct th e AT25128A/256A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25128A/256A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. 5 3404B–SEEPR–9/04 Figure 2. SPI Serial Interface AT25128A/256A Functional Description The AT25128A/256A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 5. Instruction Set for the AT25128A/256A 6 Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array AT25128A/256A 3404B–SEEPR–9/04 AT25128A/256A WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The ready/busy and write enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 6. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Table 7. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = “0” indicates the device is not write enabled. Bit 1 = “1” indicates the device is write enabled. Bit 2 (BP0) See Table 8. Bit 3 (BP1) See Table 8. Bits 4–6 are “0”s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 9. Bits 0–7 are “1”s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128A/256A is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table 8. Bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, tWC, RDSR). Table 8. Block Write Protect Bits Status Register Bits Array Addresses Protected Level BP1 BP0 AT25128A AT25256A 0 0 0 None None 1 (1/4) 0 1 3000–3FFF 6000 –7FFF 2 (1/2) 1 0 2000–3FFF 4000–7FFF 3 (All) 1 1 0000–3FFF 0000–7FFF 7 3404B–SEEPR–9/04 The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low. Table 9. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writeable Writeable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writeable Protected X High 0 Protected Protected Protected X High 1 Protected Writeable Writeable READ SEQUENCE (READ): Reading the AT25128A/256A via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the read op-code is transmitted via the SI line followed by the byte address to be read (see Table 10). Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address, allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT25128A/256A, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address and the data (D7–D0) to be programmed (see Table 10). Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The ready/busy status of the device can be determined by initiating a RDSR instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle. The AT25128A/256A is capable of a 64-byte page write operation. After each byte of data is received, the six low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be 8 AT25128A/256A 3404B–SEEPR–9/04 AT25128A/256A overwritten. The AT25128A/256A is automatically returned to the write disable state at the completion of a write cycle. NOTE: If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 10. Address Key Address AT25128A AT25256A AN A13 – A0 A14 – A0 Don’t Care Bits A15 – A14 A15 9 3404B–SEEPR–9/04 Timing Diagrams (for SPI Mode 0 [0, 0]) Figure 3. Synchronous Data Timing t CS VIH CS VIL t CSH t CSS VIH t WH SCK t WL VIL tH t SU VIH SI VALID IN VIL tV VOH SO HI-Z t HO t DIS HI-Z VOL Figure 4. WREN Timing Figure 5. WRDI Timing 10 AT25128A/256A 3404B–SEEPR–9/04 AT25128A/256A Figure 6. RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 7 6 5 11 12 13 14 15 2 1 0 SCK INSTRUCTION SI SO HIGH IMPEDANCE DATA OUT 4 3 MSB Figure 7. WRSR Timing Figure 8. READ Timing 11 3404B–SEEPR–9/04 Figure 9. WRITE Timing Figure 10. HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ SO tLZ 12 AT25128A/256A 3404B–SEEPR–9/04 AT25128A/256A AT25128A Ordering Information Ordering Code Package Operation Range AT25128A-10PA-5.0C AT25128AN-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) AT25128A-10PA-2.7C AT25128AN-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options −5.0 Standard Device (4.5V to 5.5V) −2.7 Low Voltage (2.7V to 5.5V) 13 3404B–SEEPR–9/04 AT25256A Ordering Information Ordering Code Package Operation Range AT25256A-10PA-5.0C AT25256AN-10SA-5.0C 8P3 8S1 Automotive (−40°C to 125°C) AT25256A-10PA-2.7C AT25256AN-10SA-2.7C 8P3 8S1 Automotive (−40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options −5.0 Standard Device (4.5V to 5.5V) −2.7 Low Voltage (2.7V to 5.5V) 14 AT25128A/256A 3404B–SEEPR–9/04 AT25128A/256A Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL A b2 b3 b 4 PLCS Side View L NOM MAX NOTE – – 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 – – 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA L Notes: MIN 0.300 BSC 0.115 0.130 4 0.150 2 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B 15 3404B–SEEPR–9/04 8S1 – JEDEC SOIC C 1 E E1 L N ∅ Top View End View e B COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D Side View MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 10/7/03 R 16 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B AT25128A/256A 3404B–SEEPR–9/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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