View detail for ATSAM4SP32A

Atmel SAM4SP32A
CORTEX-M4 PRIME SoC
PRELIMINARY DATASHEET
Features
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Core
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ARM® Cortex™-M4 with a 2Kbytes cache running at 120MHz
Memory Protection Unit (MPU)
DSP Instruction Set
Thumb®-2 instruction set
Memories
• 2048 Kbytes embedded Flash with optional dual bank and cache memory
• 160 Kbytes embedded SRAM
• 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP
routines
•
System
• Embedded voltage regulator for single supply operation
• Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe
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operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
Detection and optional low-power 32.768 kHz for RTC or device clock
RTC with Gregorian and Persian Calendar mode, waveform generation in low
power modes
RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation
High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz
default frequency for device startup. In-application trimming access for
frequency adjustment
Slow Clock Internal RC oscillator as permanent low-power mode device clock
Two PLLs up to 240 MHz for device clock and for USB
Temperature Sensor
Up to 22 Peripheral DMA (PDC) Channels
Low Power Modes
• Sleep and Backup Modes, down to 1 µA in Backup Mode
• Ultra low-power RTC
•
Peripherals
• USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On•
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Chip Transceiver
2 USARTs with ISO7816, IrDA ®, RS-485, Manchester and Modem Mode
Two 2-wire UARTs
2 Two Wire Interface (I2C compatible), 1 Synchronous Serial Controller (SSC)
2 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and
PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for
Stepper Motor
4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead
Time Generator Counter
43020A-ATPL-09/12
•
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32-bit Real-time Timer and RTC with calendar and alarm features
One Analog Comparator with flexible input selection
32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
Write Protected Registers
I/O
• Up to 38 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
• Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel
Capture Mode
•
PRIME PLC Modem
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Power Line Carrier Modem for 50 and 60 Hz mains
97-carrier OFDM PRIME compliant
Baud rate Selectable: 21400 to 128600 bps
Differential BPSK, QPSK, 8-PSK modulations
Automatic Gain Control and signal amplitude tracking
Embedded on-chip DMAs
Media Access Control
Viterbi decoding and CRC PRIME compliant
128-bit AES encryption
Channel sensing and collision pre-detection
Package
• 128-Lead LQFP
• Pb-free and RoHS compliant
•
Typical Applications
• PRIME Smart Meters
• PRIME Data Concentrator
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
2
Description
The SAM4SP32A is a new evolution of SAM4SD32 Flash microcontroller based on
the high performance 32-bit ARM Cortex-M4 RISC processor with a PRIME Power
Line Communication Modem SoC integrated.
The SAM4SP32A operates at a maximum speed of 120 MHz and features with a
2048 Kbytes of Flash, with optional dual bank implementation and 2Kbytes of cache
memory, 160 Kbytes of SRAM, and 32Kbytes embedded SRAM memory available
for PRIME specification requirements.
The peripheral set mainly includes a Certified PRIME Power line communication
transceiver with a featured Class D power amplifier and a set of hardware
accelerators blocks to execute the heavy tasks of the PRIME protocol without the
interruption of the Cortex-M4 CPU. Furthermore, the SAM4SP32A includes a Full
Speed USB Device port with embedded transceiver, , 2x USARTs, 2x UARTs, 2x
TWIs, an I2S, as well as 1 PWM timer, 2x three channel general-purpose 16-bit
timers (with stepper motor and quadrature decoder logic support), an RTC, a
Synchronous Serial Controller (SSC) and an analog comparator.
The Atmel SAM4SP32A SoC device combines robust and high performances
PRIME PLC Modem with a powerfull Cortex-M4 microcontroller with the best ratio in
terms of reduced power consumption, processing power and peripheral set. This
enables the SAM4SP32A to sustain a wide range of applications including PRIME
Smart Grid and data concentrator solutions.
SAM4SP32A operates from 3.0V to 3.6V
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
3
Table of Contents
1. Block Diagram.................................................................................... 8
2. Package and Pinout ........................................................................... 9
2.1
2.2
128-Lead LQFP Package Outline .................................................................. 9
128-Lead LQFP Pinout ............................................................................... 10
3. Signal Description ............................................................................ 11
4. Pin Description ................................................................................. 15
5. Power Considerations ...................................................................... 26
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Power Supplies .......................................................................................... 26
Voltage Regulator ....................................................................................... 26
Typical Powering Schematics...................................................................... 26
Active Mode ............................................................................................... 29
Low-power Modes ...................................................................................... 29
5.5.1
Backup Mode................................................................................ 29
5.5.2
Wait Mode .................................................................................... 29
5.5.3
Sleep Mode .................................................................................. 30
5.5.4
Low Power Mode Summary Table ................................................. 30
Wake-up Sources ....................................................................................... 32
Fast Startup................................................................................................ 33
6. Input/Output Lines............................................................................ 34
6.1
6.2
6.3
6.4
6.5
General Purpose I/O Lines .......................................................................... 34
System I/O Lines ........................................................................................ 34
6.2.2
Serial Wire JTAG Debug Port (SWJ-DP) Pins ................................ 35
Test Pin...................................................................................................... 35
NRST Pin ................................................................................................... 36
ERASE Pin................................................................................................. 36
7. Processor and Architecture .............................................................. 37
7.1
7.2
7.3
7.4
7.5
7.6
7.7
ARM Cortex-M4 Processor ......................................................................... 37
APB/AHB Bridge......................................................................................... 37
Matrix Master.............................................................................................. 37
Matrix Slaves .............................................................................................. 37
Master to Slave Access............................................................................... 38
Peripherical DMA Controller ........................................................................ 38
Debug and Test Features............................................................................ 39
8. SAM4SP32A Product Mapping ........................................................ 40
9. Memories ......................................................................................... 41
9.1
Embedded Memories .................................................................................. 41
9.1.1
Internal SRAM .............................................................................. 41
9.1.2
Internal ROM ................................................................................ 41
9.1.3
Embedded Flash ........................................................................... 41
9.1.3.1
Flash Overview ............................................................ 41
9.1.3.2
Enhanced Embedded Flash Controller .......................... 43
9.1.3.3
Flash Speed ................................................................ 43
9.1.3.4
Lock Regions ............................................................... 44
9.1.3.5
Security Bit Feature...................................................... 44
9.1.3.6
Calibration Bits............................................................. 44
9.1.3.7
Unique Identifier ........................................................... 44
9.1.3.8
User Signature ............................................................. 44
9.1.3.9
Fast Flash Programming Interface ................................ 44
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
4
9.1.4
9.1.3.10 SAM-BA Boot............................................................... 45
9.1.3.11 GPNVM Bits ................................................................ 45
Boot Strategies ............................................................................. 45
10. System Controller ............................................................................ 46
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
System Controller and Peripherals Mapping ................................................ 47
Power-on-Reset, Brownout and Supply Monitor ........................................... 47
10.2.1 Power-On-Reset ........................................................................... 47
10.2.2 Brownout Detector on VDDCORE.................................................. 47
10.2.3 Supply Monitor on VDDIO ............................................................. 47
Reset Controller.......................................................................................... 47
Supply Controller (SUPC) ........................................................................... 47
Clock Generator ......................................................................................... 48
Power Management Controller .................................................................... 49
Watchdog Timer ......................................................................................... 50
SysTick Timer............................................................................................. 50
Real Time Timer ......................................................................................... 50
Real Time Clock ......................................................................................... 50
General-Purpose Backup Registers............................................................. 50
Nested Vectored Interrupt Controller ........................................................... 50
Chip Identification ....................................................................................... 51
UART ........................................................................................................ 51
PIO Controllers ........................................................................................... 51
Peripheral Identifiers ................................................................................... 53
Peripheral Signal Multiplexing on I/O Lines .................................................. 54
10.17.1 PIO Controller A Multiplexing ......................................................... 54
10.17.2 PIO Controller B Multiplexing ......................................................... 55
10.17.3 PIO Controller C Multiplexing......................................................... 55
11. Embedded Peripherals Overview ..................................................... 56
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
Two Wire Interface (TWI) ............................................................................ 56
Universal Asynchronous Receiver Transceiver (UART) ................................ 56
USART....................................................................................................... 56
Synchronous Serial Controller (SSC)........................................................... 57
Timer Counter (TC)..................................................................................... 57
Pulse Width Modulation Controller (PWM) ................................................... 57
USB Device Port (UDP) .............................................................................. 58
Analog Comparator..................................................................................... 58
Cyclic Redundancy Check Calculation Unit (CRCCU) .................................. 59
PLC Brigde................................................................................................. 59
12. PRIME PLC Transceiver .................................................................. 60
12.1
SAM4SP32A PRIME PHY Layer ................................................................. 61
12.1.1 SAM4SP32A PHY Layer ............................................................... 61
12.1.1.2 Transmission and Reception branches ......................... 62
12.1.1.3 Carrier Detection .......................................................... 62
12.1.1.4 Analog Front End control .............................................. 63
12.1.1.5 Power Supply Sensing: VSENSE and PSENSE ............ 63
12.1.1.6 Gain Control ................................................................ 64
12.1.1.7 Line Impedance Control ............................................... 64
12.1.1.8 TxRx Control................................................................ 65
12.1.2 PHY parameters ........................................................................... 65
12.1.3 PHY Protocal Data Unit (PPDU) Format......................................... 66
12.1.4 PHY Service Specification ............................................................. 66
12.1.5 PHY Layer registers ...................................................................... 68
12.1.5.1 PHY_SFR Register ...................................................... 68
12.1.5.2 SYS_CONFIG Register ................................................ 69
12.1.5.3 PHY_CONFIG Register ................................................ 70
12.1.5.4 ATTENUATION Register .............................................. 71
12.1.5.5 ATT_CHIRP Register ................................................... 72
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
5
12.2
12.1.5.6 ATT_SIGNAL Register ................................................. 73
12.1.5.7 TX_TIME Registers ...................................................... 74
12.1.5.8 TIMER_FRAME Registers ............................................ 75
12.1.5.9 TIMER_BEACON_REF Registers................................. 76
12.1.5.10 RX_LEVEL Registers ................................................... 77
12.1.5.11 RSSI_MIN Register ...................................................... 78
12.1.5.12 RSSI_AVG Register ..................................................... 79
12.1.5.13 RSSI_MAX Register ..................................................... 80
12.1.5.14 CINR_MIN Register ..................................................... 81
12.1.5.15 CINR_AVG Register .................................................... 82
12.1.5.16 CINR_MAX Register .................................................... 83
12.1.5.17 EVM_HEADER Registers............................................. 84
12.1.5.18 EVM_PAYLOAD Registers ........................................... 85
12.1.5.19 EVM_HEADER_ACUM Registers ................................. 86
12.1.5.20 EVM_PAYLOAD_ACUM Registers ............................... 87
12.1.5.21 RMS_CALC Register ................................................... 88
12.1.5.22 VSENSE_CONFIG Register ......................................... 89
12.1.5.23 NUM_FAILS Register ................................................... 90
12.1.5.24 TTRANS Register ........................................................ 91
12.1.5.25 AGC0_KRSSI Register ................................................ 92
12.1.5.26 AGC1 KRSSI Register ................................................. 93
12.1.5.27 ZERO_CROSS_TIME Registers................................... 94
12.1.5.28 ZERO_CROSS_CONFIG Register ............................... 95
12.1.5.29 PSENSECYCLES Registers......................................... 96
12.1.5.30 MEAN Registers .......................................................... 97
12.1.5.31 PMAX Registers........................................................... 98
12.1.5.32 TRANS_PSENSE Register........................................... 99
12.1.5.33 P_TH Registers ......................................................... 100
12.1.5.34 MAXPOT Registers .................................................... 101
12.1.5.35 NUMCYCLES Register............................................... 102
12.1.5.36 A_NUMMILIS Register ............................................... 103
12.1.5.37 EMIT_CONFIG Register............................................. 104
12.1.5.38 AFE_CTL Register ..................................................... 105
12.1.5.39 R Registers................................................................ 106
12.1.5.40 PHY_ERRORS Registers ........................................... 107
12.1.5.41 FFT_MODE Registers ................................................ 108
12.1.5.42 AGC_CONFIG Register ............................................. 109
12.1.5.43 SAT_TH Registers ..................................................... 111
12.1.5.44 AGC1_TH Registers .................................................. 112
12.1.5.45 AGC0_TH Registers .................................................. 113
12.1.5.46 AGC_PADS Register ................................................. 114
SAM4SP32A MAC Layer .......................................................................... 115
12.2.1 Cyclic Redundancy Check (CRC) ................................................ 115
12.2.2 Advanced Encryption Standard (AES).......................................... 117
12.2.3 MAC Layer Registers .................................................................. 118
12.2.3.1 SNA Registers ........................................................... 118
12.2.3.2 VITERBI_BER_HARD Register .................................. 119
12.2.3.3 VITERBI_BER_SOFT Register ................................... 120
12.2.3.4 ERR_CRC32_MAC Registers .................................... 121
12.2.3.5 ERR_CRC8_MAC Registers ...................................... 122
12.2.3.6 ERR_CRC8_AES Registers ....................................... 123
12.2.3.7 ERR_CRC8_MAC_HD Registers................................ 124
12.2.3.8 ERR_CRC8_PHY Registers ....................................... 125
12.2.3.9 FALSE_DET_CONFIG Register ................................. 126
12.2.3.10 FALSE_DET Registers............................................... 127
12.2.3.11 MAX_LEN_DBPSK Register....................................... 128
12.2.3.12 MAX_LEN_DBPSK_VTB Register .............................. 129
12.2.3.13 MAX_LEN_DQPSK Register ...................................... 130
12.2.3.14 MAX_LEN_DQPSK_VTB Registers ............................ 131
12.2.3.15 MAX_LEN_D8PSK Registers ..................................... 132
12.2.3.16 MAX_LEN_D8PSK_VTB Register .............................. 133
12.2.3.17 AES_PAD_LEN Register ............................................ 134
12.2.3.18 AES_DATA_IN Registers ........................................... 135
12.2.3.19 AES_DATA_OUT Registers ....................................... 136
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
6
12.2.3.20 KEY_PERIPH Registers ............................................. 137
12.2.3.21 KEY_PHY Registers .................................................. 138
12.2.3.22 AES_SFR Register .................................................... 139
13. Electrical Characteristics ................................................................ 140
13.1
13.2
13.3
Absolute Maximum Ratings....................................................................... 140
DC Characteristics .................................................................................... 141
Power Consumption ................................................................................. 148
13.3.1 Backup Mode Current Consuption ............................................... 148
13.3.1.1 Configuration A .......................................................... 148
13.3.1.2 Configuration B .......................................................... 148
13.3.2 Sleep and Wait Mode Current Consumption................................. 149
13.3.2.1 Sleep Mode ............................................................... 149
13.3.2.2 Wait Mode ................................................................. 151
13.3.3 Active Mode Power Consumption ................................................ 152
13.3.4 Peripheral Power Consumption in Active Mode ............................ 154
13.4 Oscillator Characteristics .......................................................................... 156
13.4.1 32 kHz RC Oscillator Characteristics ........................................... 156
13.4.2 4/8/12 MHz RC Oscillators Characteristics ................................... 157
13.4.3 32.768 kHz Crystal Oscillator Characteristics ............................... 158
13.4.4 32.768 kHz Crystal Characteristics .............................................. 159
13.4.5 3 to 20 MHz Crystal Oscillator Characteristics .............................. 159
13.4.6 3 to 20 MHz Crystal Characteristics ............................................. 160
13.4.7 Crystal Oscillator Design Considerations Information.................... 161
13.4.7.1 Choosing a Crystal ..................................................... 161
13.4.7.2 Printed Circuit Board (PCB) ........................................ 161
13.5 PLLA, PLLB Characteristics ...................................................................... 162
13.6 USB Transceiver Characteristics ............................................................... 163
13.6.1 Typical Connections .................................................................... 163
13.6.2 Electrical Characteristics ............................................................. 163
13.6.3 Switching Characteristics ............................................................ 164
13.7 Analog Comparator Characteristics ........................................................... 165
13.8 Temperature Sensor ................................................................................. 166
13.9 AC Characteristics .................................................................................... 167
13.9.1 Master Clock Characteristics ....................................................... 167
13.9.2 I/O Characteristics....................................................................... 167
13.9.3 SSC Timings............................................................................... 169
13.9.3.2 SSC Timings.............................................................. 173
13.9.4 SMC Timings .............................................................................. 175
13.9.4.1 Read Timings............................................................. 175
13.9.4.2 Write Timings............................................................. 177
13.9.5 USART in SPI Mode Timings....................................................... 180
13.9.5.2 USART SPI TImings .................................................. 182
13.9.6 Two-wire Serial Interface Characteristics ..................................... 184
13.9.7 Embedded Flash Characteristics ................................................. 186
13.10 Recommended Operating Conditions ........................................................ 189
14. Mechanical Characteristics ............................................................ 190
15. Ordering Information ...................................................................... 191
16. Revision History ............................................................................. 192
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
7
Block Diagram
TST
2
T1
O
U
D
VD
VD
JT
D
AG
IN
SE
L
S/
SW
D
IO
K/
SW
C
LK
TC
TM
TD
I
TD
0
Figure 1-1. SAM4SP32A Block Diagram
Voltage
Regulator
System Controller
PCK0-PCK2
Flash
Unique
Identifier
JTAG & Serial Wire
PLLA
PMC
PLLB
In-Circuit Emulator
24-Bit
SysTick Counter N
RC Osc
12/8/4 MHz
XIN
XOUT
Cortex M-4 Processor
Fmax 120MHz
3-20 MHz
Osc
Osc 32 kHz
ERASE
RC 32 kHz
VDDIO
8 GPBREG
V
I
C
FLASH
2*1024 Kbytes
SRAM
160 KBytes
ROM
16
KBytes
MPU
SUPC
XIN32
XOUT32
DSP
CMCC(2 KB cache)
4-layer AHB Bus Matrix Fmax 120 MHz
RTT
VDDPLL
USB 2.0
Full
Speed
2668
Bytes
FIFO
Transceiver
VDDCORE
DPP
DMM
POR
RTCOUT0
RTCOUT1
RTC
Peripheral
Bridge
32 Kbytes
SRAM
AGC
AGND
AVDD
AVRH
AVRL
PLC_CLOCKIN
PLC_CLOCKOUT
VDDIO
VDDCORE
VDDIN
VDDOUT18
GND
EMIT[1:6]
AFE_HIMP
VNR
DBGI
DBG2
DBG3
DBG4
RSTA
RSTS
AINPLC
INTEST7
INTEST8
INTEST9
INTEST10
INTEST11
INTEST12
RSTC
NRST
WDT
SM
PIOA / PIOB
TWCK0
TWD0
TWI0
TWCK1
TWD1
TWI1
URXD0
UTXD0
UART0
URXD1
UTXD1
UART1
PRIME PLC
TRANSCEIVER
PDC
PDC
PDC
PDC
PDC
RXD0
TXD0
SCK0
RTS0
CTS0
INTEST1
INTEST2
INTEST3
INTEST4
INTEST5
INTEST6
PLC_Bridge
USART0
PDC
GPIO
RXD1
TXD1
SCK1
RTS1
CTS1
PDC
USART1
PIO
PDC
TCLK[0]
TIOA[0:1]
TIOB[0:1]
PWMH[0:3]
PWML[0:3]
PWMFI0
GPIO
1.
PDC
Timer Counter A
TF
TK
RK
SSC
TC[0..2]
PWM
PDC
Analog
Comparator
PIODC[1:0]
PIODCEN1
PIODCEN2
PIODCCLK
ADC Ch.
ADVREF
CRC Unit
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
8
2.
Package and Pinout
2.1
128-Lead LQFP Package Outline
Figure 2-1. Orientation of the 128-Lead Package
65
96
97
64
128
33
1
32
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
9
2.2
128-Lead LQFP Pinout
Table 2-1.
SAM4SP32A 128-Lead LQFP pinout
PC0
65
INTEST7
97
34
GND
66
INTEST10
98
TDO/TRACESWO/
PB5
DBG0
35
VDDIO
67
INTEST12
99
JTAGSEL
AGC
36
PA16/PGMD4
68
INTEST11
100
DBG1
GND
37
NC
69
TDI/PB4
101
DBG2
VDDIO
38
PA15/PGMD3
70
VDDIO
102
GND
AGND
39
INTEST1
71
PA6/PGMNOE
103
VDDIO
8
PB0
40
INTEST2
72
PA5/PGMRDY
104
DBG3
9
AVDD
41
PA24/PGMD12
73
PA4/PGMNCMD
105
TMS/SWDIO/PB6
1
ADVREF
33
2
GND
3
GND
4
5
6
7
10
PB1
42
PC5
74
GND
106
DBG4
11
AGND
43
NC
75
EMIT1
107
RSTA
12
AVDD
44
NC
76
VDDIO
108
RSTS
13
VRH
45
VDDCORE
77
NRST
109
TCK/SWCLK/PB7
14
PB2
46
GND
78
TST
110
GND
15
AINPLC
47
PA25/PGMD13
79
EMIT2
111
VDDOUT18
16
PB3
48
VDDOUT18
80
EMIT3
112
GND
17
VRL
49
NC
81
PA3
113
VDDCORE
18
VDDIN
50
INTEST3
82
EMIT4
114
VDDIN
19
VDDOUT12
51
INTEST4
83
PA2/PGMEN2
115
ERASE/PB12
20
PA17/PGMD5
52
INTEST5
84
GND
116
VDDIN
21
PC26
53
PA10/PGMM2
85
VDDIO
117
DDM/PB10
22
PA18/PGMD6
54
GND
86
EMIT5
118
DDP/PB11
23
PA21/PGMD9
55
PA9/PGMM1
87
VDDIO
119
VDDIO
24
VDDCORE
56
INTEST6
88
VDDIO
120
VDDIO
25
PA19/PGMD7
57
GND
89
NC
121
PLC_CLOCKIN
26
PA22/PGMD10
58
90
EMIT6
122
PB13/DAC0
27
PA23/PGMD11
59
VDDIO
PA8/XOUT32/
PGMM0
91
GND
123
PLC_CLOCKOUT
28
PA20/PGMD8
60
INTEST9
92
VDDIO
124
GND
29
GND
61
93
AFE_HIMP
125
PB8/XOUT
30
VDDIO
62
GND
PA7/XIN32/
PGMNVALID
94
PA1/PGMEN1
126
GND
31
NC
63
INTEST8
95
PA0/PGMEN0
127
PB9/PGMCK/XIN
32
NC
64
VDDIO
96
VNR
128
VDDPLL
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
10
Signal Description
3.
Table 3-1.
Signal Description List
Signal Name
Function
Type
Active
Voltage
Level
Reference
Comments
Power Supplies
VDDIO
Peripherals I/O Lines and USB transceiver
Power Supply
VDDIN
Voltage Regulator Input, ADC, DAC and
Analog Comparator Power Supply
VDDCORE
Power the core, the embedded memories
and the peripherals
3.0V to 3.6V
Power
3.0V to 3.6V
Power
1.08V to 1.32V
Power
VDDPLL
Oscillator and PLL Power Supply
Power
1.08V to 1.32V
VDDOUT18
LDO Output Power Supply
Power
1.8V Ouput
VDDOUT12
Voltage Regulator Output
Power
1.2V Output
AVDD
Analog Converter Power Supply
Power
3.0V to 3.6V
AGND
Analog Ground
Ground
GND
Digital Ground
Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
XOUT32
Slow Clock Oscillator Output
PCK0 - PCK2
Programmable Clock Output
Input
Reset State:
-PIO Input
Output
Input
-Internal Pull-up disabled
Output
-Schmitt Trigger enabled(1)
Output
VDDIO
Reset State:
-PIO Input
-Internal Pull-up enabled
-Schmitt Trigger enabled(1)
PLC_CLOCKIN
External clock Input reference
PLC_CLOCKOUT
External clock Output reference
Input
Output
Analog Input Voltage Reference
AINPLC
Direct-analog input voltage
Analog
AVRH
Analog input high voltage reference
Analog
AVRL
Analog input low voltage reference
Analog
ADVERF
Analog Comparator Reference
Analog
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
11
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Voltage
Level
Reference
Comments
Real Time Clock
RTCOUT0
Programmable RTC waveform output
RTCOUT1
Programmable RTC waveform output
Output
Reset State:
VDDIO
Output
-PIO Input
-Internal Pull-up disabled
-Schmitt Trigger enabled(1)
Serial Wire/JTAG Debug Port - SWJ-DP
TCK/SWCLK
Test Clock/Serial Wire Clock
Input
TDI
Test Data In
Input
TDO/TRACESWO
Test Data Out / Trace Asynchronous Data
Reset State:
- SWJ-DP Mode
Output
Out
TMS/SWDIO
Test Mode Select /Serial Wire Input/Output
JTAGSEL
JTAG Selection
VDDIO
Input/ I/O
Input
- Internal pull-up disabled
- Schmitt Trigger enabled
(1)
Permanent Internal
High
pull-down
Flash Memory
Reset State:
ERASE
Flash and NVM Configuration Bits Erase
Command
Input
High
VDDIO
- Erase Input
- Internal pull-down enabled
- Schmitt Trigger enabled(1)
Reset/Test
NRST
TST
Synchronous Microcontroller Reset
I/O
Permanent Internal
Low
VDDIO
Test Select
Input
pull-up
Permanent Internal
pull-down
PRIME PLC TRANSCEIVER Signal Controller
AGC
Automatic Gain Control
Output
EMITx
PLC Transmission ports
Output
VNR
PLC Zero Crossing Detection Signal
Input
AFE_HIMP
Analog Front-End High-Impedance
Output
RSTA
PLC Asynchronous reset
Input
RSTS
Initialization Signal
Input
See footnote (2)
Internal configuration: 33kΩ
typ. pull-down resistor
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
12
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Voltage
Level
Reference
Comments
PRIME PLC TRANSCEIVER Configuration Pins
DBGx
External Configuration Pins
I/O
INTEST7 – INTEST12
External Configuration Pins
I/O
See Pin Description for details
Universal Asynchronous Receiver Transceiver - UARTx
URXDx
UART Receive Data
Input
UTXDx
UART Transmit Data
Output
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31
Parallel IO Controller A
I/O
PB0 - PB14
Parallel IO Controller B
I/O
PC0 - PC31
Parallel IO Controller C
Reset State:
VDDIO
I/O
- PIO or System IOs(2)
- Internal pull-up enabled
- Schmitt Trigger enabled(1)
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
USARTx Serial Clock
I/O
TXDx
USARTx Transmit Data
I/O
RXDx
USARTx Receive Data
Input
RTSx
USARTx Request To Send
CTSx
USARTx Clear To Send
Output
Input
Synchronous Serial Controller - SSC
TK
SSC Transmit Clock
I/O
RK
SSC Receive Clock
I/O
TF
SSC Transmit Frame Sync
I/O
Timer/Counter - TC
TCLKx
TC Channel x External Clock Input
TIOAx
TC Channel x I/O Line A
I/O
TIOBx
TC Channel x I/O Line B
I/O
Input
Pulse Width Modulation Controller- PWMC
PWMHx
PWM Waveform Output High for channel x
PWMLx
PWM Waveform Output Low for channel x
Output
Only output in complementary
Output
PWMFI0
PWM Fault Input
mode when dead time
insertion is enabled.
Input
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
13
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Voltage
Level
Reference
Comments
PLC Brigde
INTEST1 – INTEST6
External Configuration pins
I/O
Two-Wire Interface- TWI
TWDx
TWIx Two-wire Serial Data
I/O
TWCKx
TWIx Two-wire Serial Clock
I/O
Analog Comparator - ACC
AC0 - AC7
Analog Comparator Inputs
Analog
USB Full Speed Device
DMM
USB Full Speed Data -
DPP
USB Full Speed Data +
Analog,
Digital
Reset State:
VDDIO
- USB Mode
- Internal Pull-down(3)
Note:
1.
2.
3.
Schmitt Triggers can be disabled through PIO registers.
Different configurations allowed depending on external topology and net behavior.
Refer to USB Section of the product Electrical Characteristics for information on Pull-down value in USB
Mode.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
14
4.
Pin Description
Table 4-1.
Pin Description List
Pin
Number
Pin Name
1
2, 3, 5,
29, 34,
46, 54,
57, 61,
74, 84,
91, 102,
110, 112,
124, 126
Functions
ADVREF
Type
Analog
Comments
Analog Voltage Comparator reference
Digital Ground
GND
Power
Automatic Gain Control
4
AGC
Output
6, 30, 58,
64, 70,
76, 85,
88, 87,
92, 103,
119, 120,
VDDIO
Power
7, 11
AGND
Power
•
This digital output is managed by
AGC hardware logic to drive
external circuitry if input signal
attenuation is needed
Digital power supply. Voltage range: 3.0V - 3.6 V
Must be decoupled by external capacitors
Analog ground
PIO Controller B Multiplexing (PB0):
8
9, 12
PB0
PWMH0
AC4
RTCOUT0
AVDD
I/O
Power
•
PWM Waveform Output High for
channel 0
•
•
Analog Comparator Input channel 4
•
See Signal Description for details.
Programmable RTC waveform
output
Analog converter power supply. Voltage range: 3.0V
- 3.6 V
PIO Controller B Multiplexing (PB1):
10
13
PB1
AVRH
PWMH1
AC5
RTCOUT1
I/O
Input
•
PWM Waveform Output High for
channel 1
•
•
Analog Comparator Input channel 5
•
See Signal Description for details.
Programmable RTC waveform
output
Analog input high voltage reference
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
15
Table 4-1.
Pin Description List (Continued)
Pin
Number
Pin Name
Functions
Type
Comments
PIO Controller B Multiplexing (PB2):
14
15
PB2
URXD1
AC6
WKUP12
AINPLC
I/O
Input
•
•
•
UART1 Receive Input Data
Analog Comparator Input channel 6
Wake-up Source 12
•
Fast start up of the Processor
•
Active level: Low
Direct-analog input voltage
PIO Controller B Multiplexing (PB3):
16
PB3
UTXD1
PCK2
AC7
I/O
•
•
•
•
UART1 Transmit Output Data
Programmable clock output 2
Analog Comparator Input channel 7
See Signal Description for details.
17
AVRL
Input
18, 35,
114, 116
VDDIN
P
Voltage Regulator Input, Analog Comparator Power
Supply. Voltage range: 3.0V – 3.6 V
19
VDDOUT12
P
Voltage output regulator of 1.2 volts
Analog input low voltage reference
PIO Controller A Multiplexing (PA17):
20
PA17/PGMD5
TD
PCK1
PWMH3
AC0
I/O
•
Synchronous Serial Controller (SSC)
Transmit Output Data
•
•
Programmable clock output 1
•
•
Analog Comparator Input channel 0
PWM Waveform Output High for
channel 3
See Signal Description for details.
PIO Controller C Multiplexing (PC26):
21
PC26
TIOA4
I/O
•
•
Tmer/Counter Channel 4 I/O Line A
General purpose I/O
PIO Controller A Multiplexing (PA18):
22
PA18/PGMD6
RD
PCK2
AC1
I/O
•
Synchronous Serial Controller (SSC)
Receive Input Data
•
•
•
Programmable clock output 2
Analog Comparator Input channel 1
See Signal Description for details.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
16
Table 4-1.
Pin Description List (Continued)
Pin
Number
Pin Name
Functions
Type
Comments
PIO Controller A Multiplexing (PA21):
23
24, 45,
113
PA21/PGMD9
RXD1
PCK1
I/O
P
VDDCORE
•
•
•
USART1 Receive Input Data
Programmable clock output 1
See Signal Description for details.
Core, embedded memories and the peripherals
power supply: Voltage range of 1.08V to 1.32V
PIO Controller A Multiplexing (PA19):
25
PA19/PGMD7
RK
PWML0
AC2WKUP
9
•
Synchronous Serial Controller (SSC)
I/O Receive Clock
•
PWM Waveform Output Low for
channel 0
•
•
Analog Comparator Input channel 2
I/O
Wake-up Source 9
•
Fast start up of the Processor
•
Active level: Low
PIO Controller A Multiplexing (PA22):
26
PA22/PGMD10
TXD1
I/O
•
USART1 Transmit I/O Data
PIO Controller A Multiplexing (PA23):
27
PA23/PGMD11
SCK1
PWMH0
PIODCLLK
I/O
•
•
USART1 I/O Serial Clock
•
Parallel Capture Mode Input Clock
PWM Waveform Output High for
channel 0
•
Voltage reference: VDDIO
PIO Controller A Multiplexing (PA20):
28
31, 32,
37, 43,
44,
PA20/PGMD8
RF
PWML1
AC3
WKUP10
•
Synchronous Serial Controller (SSC)
I/O Receive Frame Sync
•
PWM Waveform Output Low for
channel 1
•
•
Analog Comparator Input channel 3
I/O
Wake-up Source 10
•
Fast start up of the Processor
•
Active level: Low
No connect
NC
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
17
Table 4-1.
Pin Description List (Continued)
Pin
Number
Pin Name
Functions
Type
Comments
PIO Controller C Multiplexing (PC0):
33
PC0
PWML0
I/O
•
PWM Waveform Output Low for
channel 0
•
General purpose I/O
PIO Controller A Multiplexing (PA16):
36
PA16/PGMD4
TK
TIOB1
PWML2
WKUP15
PIODCEN2
•
Synchronous Serial Controller (SSC)
I/O Transmit Clock
•
Timer/Counter (TC) Channel 1 I/O
Line B
•
PWM Waveform Output Low for
channel 2
•
Wake-up Source 15
I/O
•
•
Fast start up of the Processor
•
Active level: Low
PIO Controller - Parallel Capture
Mode Enable 2
•
Voltage reference: VDDIO
PIO Controller A Multiplexing (PA15):
38
PA15/PGMD3
TF
TIOA1
PWML3
WKUP14
PIODCEN1
•
Synchronous Serial Controller (SSC)
I/O Transmit Frame Sync
•
Timer/Counter (TC) Channel 1 I/O
Line A
•
PWM Waveform Output Low for
channel 3
•
Wake-up Source 14
I/O
•
•
Fast start up of the Processor
•
Active level: Low
PIO Controller - Parallel Capture
Mode Enable 1
•
Voltage reference: VDDIO
39
INTEST1
O
External configuration pin. This pin must connect to
INTEST7 (pin 65)
40
INTEST2
O
External configuration pin. This pin must connect to
INTEST8 (pin 63)
PIO Controller A Multiplexing (PA24):
41
PA24/PGMD12
RTS1
PWMH1
PIODC0
I/O
•
•
USART1 Request To Send
•
PIO Controller-Parallel Capture
Mode Data 0
PWM Waveform Output High for
channel 1
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
18
Table 4-1.
Pin Description List (Continued)
Pin
Number
Pin Name
Functions
Type
Comments
PIO Controller C Multiplexing (PC5):
42
PC5
I/O
•
General purpose I/O
PIO Controller A Multiplexing (PA25):
47
PA25/PGMD13
CTS1
PWMH2
PIODC1
I/O
•
•
USART1 Clear To Send
•
PIO Controller-Parallel Capture
Mode Data 1
PWM Waveform Output High for
channel 2
Power
1.8V LDO Output Power Supply. Just Requires output
capacitor. Not intended for external use
INTEST3
O
External configuration pin. This pin must connect to
INTEST9 (pin 60)
51
INTEST4
O
External configuration pin. This pin must connect to
INTEST10 (pin 66)
52
INTEST5
O
External configuration pin. This pin must connect to
INTEST11 (pin 68)
48, 111
VDDOUT18
50
PIO Controller A Multiplexing (PA10):
53
PA10/PGMM2
UTXD0
I/O
•
UART Transmit Output Data
•
PIO Controller A Multiplexing (PA9):
55
56
PA9/PGMM1
URXD0
PWMFI0
WKUP6
INTEST6
I/O
O
•
•
•
UART Receive Input Data
PWM Fault Input
Wake-up Source 6
•
Fast start up of the Processor
•
Active level: Low
External configuration pin. This pin must connect to
INTEST12 (pin 67)
PIO Controller A Multiplexing (PA8):
59
PA8/ XOUT32/PGMM0
CTS0
WKUP5
XOUT32
•
•
INTEST9
I
Wake-up Source 5
•
•
I/O
•
•
60
USART0 Clear To Send
Fast start up of the Processor
Active level: Low
Slow Clock Oscillator Output
See Signal Description for details.
External configuration pin. This pin must connect to
INTEST3 (pin 50)
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
19
Table 4-1.
Pin Description List (Continued)
Pin
Number
Pin Name
Functions
Type
Comments
PIO Controller A Multiplexing (PA7):
62
PA7/ XIN32/PGMNVALID
RTS0
PWMH3
XIN32
I/O
•
•
USART0 Request To Send
•
•
Slow Clock Oscillator Input
PWM Waveform Output High for
channel 3
See Signal Description for details.
63
INTEST8
I
External configuration pin. This pin must connect to
INTEST2 (pin 40)
65
INTEST7
I
External configuration pin. This pin must connect to
INTEST1 (pin 39)
66
INTEST10
I
External configuration pin. This pin must connect to
INTEST4 (pin 51)
67
INTEST12
I
External configuration pin. This pin must connect to
INTEST6 (pin 56)
68
INTEST11
I
External configuration pin. This pin must connect to
INTEST5 (pin 52)
PIO Controller B Multiplexing (PB4):
69
TDI/PB4
TWD1
PWMH2
TDI
I/O
•
Two-Wire Interface – TWI1 Two-wire
I/O Serial Data
•
PWM Waveform Output High for
channel 2
•
Serial Wire/JTAG Debug Port (SWJDP) Test Data In
•
See Signal Description for details.
PIO Controller A Multiplexing (PA6):
71
PA6/PGMNOE
TXD0
PCK0
I/O
•
•
•
USART0 Transmit I/O Data
Programmable Clock Output
See Signal Description for details.
PIO Controller A Multiplexing (PA5):
72
PA5/PGMRY
RXD0
WKUP4
I/O
•
•
USART0 Receive Input Data
Wake-up Source 4
•
•
Fast start up of the Processor
Active level: Low
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
20
Table 4-1.
Pin Description List (Continued)
Pin
Number
Pin Name
Functions
Type
Comments
PIO Controller A Multiplexing (PA4):
73
75, 79,
80, 82,
86, 90,
PA4/PGMNCMD
TWCK0
TCLK0
WKUP3
•
Two-Wire Interface-TWI0 Twowire I/O Serial Clock
•
Timer/Counter (TC) Channel 0
External Clock Input
•
Wake-up Source 3
I/O
•
Fast start up of the
Processor
•
Active level: Low
PLC Transmission ports.
EMIT(1:6)
•
Output
See Signal Description for
details.
Synchronous PRIME PLC Reset
77
NRST
I/O
•
See Signal Description for
details.
•
See Signal Description for
details.
Test Select
78
TST
81
PA3
I
TWD0
PIO Controller A Multiplexing (PA3):
I/O
•
Two-Wire Interface - TWI0 Twowire I/O Serial Data
PIO Controller A Multiplexing (PA2):
83
PA2/PGMEN2
PWMH2
SCK0
WKUP2
I/O
•
PWM Waveform Output High for
channel 2
•
•
USART0 I/O Serial Clock
Wake-up Source 2
•
Fast start up of the
Processor
•
Active level: Low
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
21
Table 4-1.
Pin Description List (Continued)
Pin
Number
Pin Name
Functions
Type
Comments
Analog Front-End High-Impedance
•
93
AFE_HIMP
Output
This digital output is used by the
chip to select between lowimpedance and high-impedance
transmission branch (when
working with a “two half-H-bridge
branches” analog front end
configuration). This way, the
system adapts its transmission
external circuitry to the net
impedance, improving
transmission behavior. The
polarity of this pin can be inverted
by hardware. Please refer to the
Reference Design for further
information.
PIO Controller A Multiplexing (PA1):
94
PA1/PGMEN1
PWMH1
TIOB0
WKUP1
•
PWM Waveform Output High for
channel 1
•
Timer/Counter (TC) Channel 0 I/O
Line B
•
Wake-up Source 1
•
Fast start up of the
Processor
I/O
•
Active level: Low
PIO Controller A Multiplexing (PA0):
95
PA0/PGMEN0
PWMH0
TIOA0
WKUP0
•
PWM Waveform Output High for
channel 0
•
Timer/Counter (TC) Channel 0 I/O
Line A
•
Wake-up Source 0
I/O
•
Fast start up of the
Processor
•
Active level: Low
PLC Zero Crossing Detection Signal
•
96
VNR
Input
This input detects the zerocrossing of the mains voltage,
needed to determine proper
switching times. Depending on
whether an isolated or a nonisolated power supply is being
used, isolation of this pin should
be taken into account in the
circuitry design. Please refer to
the Reference Design for further
information.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
22
Table 4-1.
Pin Description List (Continued)
Pin
Number
Pin Name
Functions
Type
Comments
PIO Controller B Multiplexing (PB5):
97
TDO/ TRACESWO/PB5
TWCK1
PWML0
WKUP13
TDO
TRACESWO
•
Two-Wire Interface - TWI1 Twowire I/O Serial Clock
•
PWM Waveform Output Low for
channel 0
•
Wake-up Source 13
I/O
•
•
Fast start up of the
Processor
•
Active level: Low
TDO - Test Data Out / Trace
Asynchronous DataOut
(TRACESWO)
•
98
99
DBG0
Input
JTAGSEL
A-I
100
DBG1
Input
101
DBG2
Output
104
DBG3
Input
See Signal Description for
details.
Internal configuration: must connect 33kΩ typ. pullup resistor
Analog input used to select the JTAG boundary
scan when asserted at a high level.
•
See Signal Description for
details.
Internal configuration: must 33kΩ typ. pull-up
resistor
No connect
Internal configuration: must 33kΩ typ. pull-up
resistor
PIO Controller B Multiplexing (PB6):
105
106
TMS/ SWDIO/PB6
DBG4
TMS
SWDIO
•
TMS - Test Mode Input Select /
(SWDIO) Serial Wire I/O
•
See Signal Description for
details.
I/O
Input
No connect
PLC Asynchronous reset
107
RSTA
•
RSTA is a digital input pin used to
perform a hardware reset of the
ASIC
•
RSTA is active high
Input
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
23
Table 4-1.
Pin Description List (Continued)
Pin
Number
Pin Name
Functions
Type
Comments
Initialization Signal
108
RSTS
•
During power-on, D_INIT should
be released before asynchronous
reset signal RSTA, in order to
ensure proper system start up.
Not minimum time is required
between both releases, ∆t>0
•
D_INIT is active high
Input
PIO Controller B Multiplexing (PB7):
109
TCK/SWCLK/ PB7
TCK
SWCLK
•
TCK -Test Clock/(SWCLK) Serial
Wire Clock
•
See Signal Description for
details.
I/O
PIO Controller B Multiplexing (PB12):
115
ERASE/PB12
PWML1
ERASE
I/O
•
PWM Waveform Output Low for
channel 0
•
Flash and NVM Configuration Bits
Erase Command
•
See Signal Description for
details.
PIO Controller B Multiplexing (PB10):
117
DDM/PB10
DMM
A-I/O
•
•
USB Full Speed Data –
See Signal Description for
details.
PIO Controller B Multiplexing (PB11):
118
DDP/PB11
DPP
A-I/O
•
•
USB Full Speed Data +
See Signal Description for
details.
External clock reference
•
121
PLC_CLOCKIN
Input
PLC_CLOCKIN must be
connected to one terminal of a
crystal (when a crystal is being
used) or tied to ground if a
compatible oscillator is being
used
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
24
Table 4-1.
Pin Description List (Continued)
Pin
Number
Pin Name
Functions
Type
Comments
External clock reference
•
123
PLC_CLOCKOUT
125
PB8/XOUT
I/O
PLC_CLOCKOUT must be
connected to one terminal of a
crystal (when a crystal is being
used) or to one terminal of a
compatible oscillator (when a
compatible oscillator is being
used)
PIO Controller B Multiplexing (PB8):
XOUT
Output
•
Main Oscilator Output
PIO Controller B Multiplexing (PB9):
127
128
PB9/PGMCK/XIN
VDDPLL
XIN
Input
Power
•
Main Oscilator Input
Oscillator and PLL Power Supply
•
1.08V to 1.32V
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
25
5.
Power Considerations
5.1
Power Supplies
The SAM4SP32A has several types of power supply pins:
5.2
•
VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage ranges from 1.08V to
1.32V.
•
VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers), USB transceiver, Backup part, 32 kHz
crystal oscillator and oscillator pads. Voltage ranges from 3.0V to 3.6V.
•
VDDIN pin: Voltage Regulator Input, and Analog Comparator Power Supply. Voltage ranges from 3.0V to
3.6V.
•
VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator. Voltage ranges from
1.08V to 1.32V.
•
AVDD pin: PRIME PLC Analog Converter Power Supply. Voltage ranges from 3.0V to 3.6V.
Voltage Regulator
The SAM4SP32A embeds two voltage regulators that are managed by the Supply Controller.
The first internal regulator is designed to supply the internal core of SAM4SP32A It features two operating modes:
•
In Normal mode, the voltage regulator consumes less than 500 μA static current and draws 80 mA of output
current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load
current. In Wait Mode quiescent current is only 5 μA.
•
In Backup mode, the voltage regulator consumes less than 1 μA while its output (VDDOUT12) is driven
internally to GND. The default output voltage is 1.20V and the start-up time to reach Normal mode is less
than 300 μs.
The second internal regulator is designed to supply the internal PRIME PLC Transceiver. Its output (VDDOUT18) is
driven internally to GND and the default output voltage is 1.8V. The VDDOUT18 pin just requires an output capacitor
in the range of 0.1μF-10μF and it is not intended for external use.
For adequate input and output power supply decoupling/bypassing, refer to the “Voltage Regulator” section in the
“Electrical Characteristics” section of the datasheet.
5.3
Typical Powering Schematics
The SAM4SP32A supports a 3.0V-3.6V single supply mode. The internal regulator input is connected to the source
and its output feeds VDDCORE. Figure 5-1 shows the power schematics.
As VDDIN powers the voltage regulator, and the analog comparator, when the user does not want to use the
embedded voltage regulator, it can be disabled by software via the SUPC (note that this is different from Backup
mode).
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Figure 5-1. Single Supply
VDDIO
Main Supply
(3.0V-3.6V)
USB
Transceivers.
Analog
Comparator.
VDDIN
VDDOUT12
VDDCORE
Voltage
Regulator
VDDPLL
Note:
Restrictions
For USB, VDDIO needs to be greater than 3.0V.
Figure 5-2. Core Externally Supplied
VDDIO
Main Supply
(3.0V-3.6V)
Can be the
same supply
PLC Transceiver
Analog Comparator
Supplies
(3.0V-3.6V)
Analog
Comparator
VDDIN
VDDOUT12
VDDCORE Supply
(1.08V-1.32V)
USB
Transceivers.
PRIME PLC
Transceiver
Voltage
Regulator
VDDCORE
VDDPLL
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Figure 5-3. Backup Baterry
PRIME PLC
Analog Comparator
Supplies
(3.0V-3.6V)
Backup
Battery
VDDIO
+
VDDIN
Main Supply
IN
OUT
3.3V
LDO
USB
Transceivers.
Analog
Compa rator
PRIME PLC
Transceiver
VDDOUT12
VDDCORE
Voltage
Regulator
ON/OFF
VDDPLL
PIOx (Output)
External wakeup signal
WAKEUPx
Note: The two diodes provide a “switchover circuit” (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
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5.4
Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal
oscillator or the PLLA. The power management controller can be used to adapt the frequency and to disable the
peripheral clocks.
5.5
Low-power Modes
In low-power mode, the 3.3 Volts power source must be shut down before running in any low-power mode. The
PRIME PLC transceiver peripheral is turned off during a low-power mode configuration.The various low-power modes
of the SAM4SP32A are described below:
5.5.1
Backup Mode
The purpose of backup mode is to achieve the lowest power consumption possible in a system which is performing
periodic wake-ups to perform tasks but not requiring fast startup time.
The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz oscillator (RC or crystal
oscillator selected by software in the Supply Controller) are running. The regulators, PRIME PLC transceiver and the
core supply are off.
Backup mode is based on the Cortex-M4 deep sleep mode with the voltage regulators disabled.
The SAM4SP32A can be awakened from this mode through WUP0-15 pins, the supply monitor (SM), the RTT or RTC
wake-up event.
Backup mode is entered by using bit VROFF of Supply Controller (SUPC_CR) and with the SLEEPDEEP bit in the
Cortex-M4 System Control Register set to 1.
Entering Backup mode:
•
•
Set the SLEEPDEEP bit of Cortex_M4, set to 1.
Set the VROFF bit of SUPC_CR at 1
Exit from Backup mode happens if one of the following enable wake up events occurs:
•
•
•
•
5.5.2
WKUPEN0-15 pins (level transition, configurable debouncing)
Supply Monitor alarm
RTC alarm
RTT alarm
Wait Mode
The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a
powered state for a startup time of less than few hundred μs. Current Consumption in Wait mode is typically few μA
(total current consumption) if the internal voltage regulator is used.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and
memories power supplies are still powered except for the PRIME PLC transceiver which remains turned off. From this
mode, a fast start up is available.
This mode is entered via WAITMODE =1 (Waitmode bit in CKGR_MOR) and with LPM = 1 (Low Power Mode bit in
PMC_FSMR) and with FLPM = 00 or FLPM=01 (Flash Low Power Mode bits in PMC_FSMR).
The Cortex-M4 is able to handle external events or internal events in order to wake-up the core. This is done by
configuring the external lines WUP0-15 as fast startup wake-up pins (refer to 0). RTC or RTT Alarm and USB wake-up
events can be used to wake up the CPU.
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Entering Wait Mode:
•
•
•
•
•
•
Note:
5.5.3
Select the 4/8/12 MHz fast RC oscillator as Main Clock
Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR)
Set the FLPM bitfield in the PMC Fast Startup Mode Register (PMC_FSMR)
Set Flash Wait State at 0
Set the WAITMODE bit = 1 in PMC Main Oscillator Register (CKGR_MOR)
Wait for Master Clock Ready MCKRDY=1 in the PMC Status Register (PMC_SR)
Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN bit and
the effective entry in Wait mode. Depending on the user application, waiting for MOSCRCEN bit to be
cleared is recommended to ensure that the core will not execute unde-sired instructions.
Sleep Mode
The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode, only
the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is application
dependent.
This mode is entered via Wait for Interrupt (WFI) with LPM = 0 in PMC_FSMR.
The processor can be awakened from an interrupt if WFI instruction of the Cortex M4 is used.
5.5.4
Low Power Mode Summary Table
The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake up
sources can be individually configured. Table 5-1shows a summary of the configurations of the low-power modes.
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Table 5-1.
Low Power Mode Configuration Summary
Mode
SUPC, 32
kHz
Oscillator,
RTC, RTT
Backup
Registers,
POR
(Backup
Region)
Regulator
Periphericals
Backup
ON
OFF
OFF (Not
powered)
VROFF = 1
+SLEEPDEEP
bit = 1
WUP0-15
pins SM
alarm RTC
alarm RTT
alarm
Reset
Previous
state
saved
PIOA &
PIOB &
PIOC Inputs
with pull
ups
ON
ON
Powered (Not
clocked)
Waitmode=1
+SLEEPDEEP
bit = 0 +LPM
bit = 1
Any Event
from: Fast
startup
through
WUP0-15
pins RTC
alarm RTT
alarm USB
wake-up
Clocked
back
Previous
state
saved
Unchanged
ON
ON
Powered
(Not clocked)
WFE or WFI
+SLEEPDEEP
bit = 0 +LPM
bit = 0
Entry
mode
=WFI
Interrupt
Only; Any
Enabled
Interrupt
Clocked
back
Previous
state
saved
Unchanged
Core
Memory
Mode
Wait
Mode
Sleep
Mode
(1)
Mode Entry
Potential
Wake Up
Sources
Core at
Wake Up
PIO State
while in
Low
Power
Mode
Wake-up
PIO State
Time
Consumption
(1)
(2) (3)
at Wake Up
(4)
1.5 μA typ
< 0.5 ms
15 μA/ 25 μA
< 10 μs
(6)
(6)
(5)
Note:
1.
2.
3.
4.
5.
6.
7.
When considering wake-up time, the time required to start the PLL is not taken into account. Once started,
the device works with the 4/8/12 MHz fast RC oscillator. The user has to add the PLL start-up time if it is
needed in the system. The wake-up time is defined as the time taken for wake up until the first instruction is
fetched.
The external loads on PIOs are not taken into account in the calculation.
Supply Monitor current consumption is not included.
Total Current consumption.
15 μA on VDDCORE, 25 μA for total current consumption (using internal voltage regulator), 18 μA for total
current consump-tion (without using internal voltage regulator).
Depends on MCK frequency.
In this mode the core is supplied and not clocked but some peripherals can be clocked.
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5.6
Wake-up Sources
The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply
Controller performs a sequence which automatically re-enables the core power supply and the SRAM power supply, if
they are not already enabled.
Figure 5-4. Wake-up Sources
sm_out
rtc_alarm
rtt_alarm
WKUPT0
WKUP0
Core
Supply
Restart
RTTEN
WKUPEN0
WKUPIS0
WKUPDBC
WKUPEN1
WKUPIS1
SLCK
WKUPS
Debouncer
Falling/Rising
Edge
Detector
WKUPT15
WKUP15
RTCEN
Falling/Rising
Edge
Detector
WKUPT1
WKUP1
SMEN
WKUPEN15
WKUPIS15
Falling/Rising
Edge
Detector
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5.7
Fast Startup
The SAM4SP32A allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep
mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM +
RTC + RTT).
The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start-up signal to the Power
Management Controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded
4/8/12 MHz Fast RC oscillator, switches the master clock on this 4 MHz clock and reenables the processor clock.
Figure 5-5. Fast Start-Up Sources
FSTT0
WKUP0
FSTP0
FSTT1
WKUP1
FSTP1
FSTT15
WKUP15
fast_restart
FSTP15
RTTAL
RTT Alarm
RTCAL
RTC Alarm
USBAL
USB Alarm
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6.
Input/Output Lines
The SAM4SP32A has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os.
GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can
be used whether in I/O mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators,
erase or analog inputs.
6.1
General Purpose I/O Lines
GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such as pull-up or pulldown, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming
of these modes is performed independently for each I/O line through the PIO controller user interface. For more
details, refer to the product “PIO Controller” section.
The input/output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM4SP32A embeds high speed pads able to handle up to 45 MHz for PLC bridge clock lines and 35 MHz on
other lines. See AC Characteristics Section of the datasheet for more details. Typical pull-up and pull-down value is
100 kΩ for all I/Os.
Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1 below). It consists of an internal series
resistor termination scheme for impedance matching between the out-put (SAM4SP32A) driver and the PCB trace
impedance preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby
reducing in turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between
devices or between boards. In conclusion ODT helps diminish signal integrity issues.
Figure 6-1. On-Die Termination
Z0 ~ Zout + Rodt
ODT
36 Ohms Typ.
Rodt
Receiver
SAM4 Driver with
Zout ~ 10 Ohms
6.2
PCB Trace
Z0 ~ 50 Ohms
System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset, JTAG, and the like. Described below in Table 6-1 are
the SAM4SP32A system I/O lines shared with PIO lines.
These pins are software configurable as general purpose I/O or system pins. At startup the default function of these
pins is always used.
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Table 6-1.
System I/O Configuration Pin List
SYSTEM_IO
Default function
Constraints for
bit number
after reset
Other Functions
normal start
12
ERASE
PB12
Low level at startup(1)
10
DMM
PB10
-
11
DPP
PB11
-
7
TCK/SWCLK
PB7
-
6
TMS/SWDIO
PB6
-
5
TDO/TRACEESWO
PB5
-
4
TDI
PB4
-
-
PA7
XIN32
-
-
PA8
XOUT32
-
-
PB9
XIN
-
-
PB8
XOUT
-
Configuration
In Matrix User Interface
Registers (Refer to the
System I/O Configuration
Register in the “Bus
Matrix” section of the
datasheet.)
See footnote (2) below
See footnote
(3)
below
Note:
1.
2.
3.
6.2.2
If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash
erase before the user application sets PB12 into PIO mode,
In the product Datasheet Refer to: “Slow Clock Generator” of the “Supply Controller” section.
In the product Datasheet Refer to: “3 to 20 MHZ Crystal Oscillator” information in the “PMC” section
Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin
JTAG connector defined by ARM. For more details about voltage refer-ence and reset state, refer to Table 3-1.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer to
the “Debug and Test” Section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is
not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO mode is
performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up,
triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent
pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must
provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the
SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchro-nous trace can only be
used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to the
“Debug and Test” Section.
6.3
Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the
SAM4SP32A series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be
left unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface
(FFPI) section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product
datasheet.
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6.4
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset
signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the
peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the
reset pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent
pull-up resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.
6.5
ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as
logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal
operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high during less than 100
ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform a Flash erase
operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as
a PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted
erasing. Refer to Peripheral Signal Multiplexing on I/O Lines Also, if the ERASE pin is used as a standard I/O output,
asserting the pin to low does not erase the Flash.
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7.
Processor and Architecture
7.1
ARM Cortex-M4 Processor
•
•
•
•
•
•
•
•
7.2
Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit.
Harvard processor architecture enabling simultaneous instruction fetch with data load/store.
Three-stage pipeline.
Single cycle 32-bit multiply.
Hardware divide.
Thumb and Debug states.
Handler and Thread modes.
Low latency ISR entry and exit.
APB/AHB Bridge
The SAM4SP32A embeds One Peripheral bridge:
The peripherals of the bridge are clocked by MCK.
7.3
Matrix Master
The Bus Matrix of the SAM4SP32A manages 4 masters, which means that each master shall perform an access
concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all
the masters have the same decodings.
Table 7-1.
7.4
List of Bus Matrix Masters
Master 0
Cortex-M4 Instruction/Data
Master 1
Cortex-M4 System
Master 2
Peripheral DMA Controller (PDC)
Master 3
CRC Calculation Unit
Matrix Slaves
The Bus Matrix of the SAM4SP32A manages 5 slaves. Each slave has its own arbiter, allowing a different arbitration
per slave.
Table 7-2.
List of Bus Matrix Slaves
Slave 0
Internal SRAM
Slave 1
Internal ROM
Slave 2
Internal Flash
Slave 3
External Bus Interface
Slave 4
Peripheral Bridge
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7.5
Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing
access from the Cortex-43 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired, and shown
as “-” in the following table.
Table 7-3.
SAM4SP32A Master to Slave Access
Slaves
7.6
Masters
0
1
Cortex-M4
I/D Bus
Cortex-M4 S
Bus
2
3
PDC
CRCCU
X
0
Internal SRAM
-
X
X
1
Internal ROM
X
-
X
X
2
Internal Flash
X
-
-
X
3
External Bus Interface
-
X
X
X
4
Peripherical Bridge
-
X
X
-
Peripherical DMA Controller
•
•
•
Handles data transfer between peripherals and memories
Low bus arbitration overhead
•
One Master Clock cycle needed for a transfer from memory to peripheral
•
Two Master Clock cycles needed for a transfer from peripheral to memory
Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to
High priorities):
Table 7-4.
Peripherical DMA Controller
Instance name
Channel T/R
PWM
Transmit
TWI1
Transmit
TWI0
Transmit
UART1
Transmit
UART0
Transmit
USART1
Transmit
USART0
Transmit
PLC bridge
Transmit
SSC
Transmit
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Table 7-5.
7.7
Peripherical DMA Controller
Instance name
Channel T/R
PIOA
Receive
TWI1
Receive
TWI0
Receive
UART1
Receive
UART0
Receive
USART1
Receive
USART0
Receive
PLC bridge
Receive
SSC
Receive
Debug and Test Features
•
Debug access to all memory and registers in the system, including Cortex-M4 register bank when the core is
running, halted, or held in reset.
•
•
•
•
•
Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
Data Watchpoint and Trace (DWT) unit for implementing watch points, data tracing, and system profiling
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
IEEE®1149.1 JTAG Boundary scan on All Digital Pins
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8.
SAM4SP32A Product Mapping
Figure 8-1. SAM4SP32A Product Mapping
0x00000000
Code
0x00000000
Address memory space
Peripherals
0x40000000
Reserved
Boot Memory
Code
0x00400000
Internal Flash
0x00800000
Internal ROM
0x00C00000
1 MByte
bit band
regiion
SSC
0x20000000
SRAM
Reserved
0x24000000
0x40000000
Reserved
0x40010000
TC0
32 MBytes
bit band alias
0x61000000
23
TC0
TC1
TC0
TC2
TC1
TC3
TC1
TC4
24
+0x80
External RAM
0x60000000
SMC Chip Select 0
TC0
+0x40
Peripherals
0x60000000
21
0x4000C000
Undefined
0x1FFFFFFF
22
0x40008000
0x20100000
0x20400000
Reserved
18
0x40004000
25
0x40014000
External SRAM
26
+0x40
0x62000000
0x63000000
SMC Chip Select 1
0xA0000000
SMC Chip Select 3
TC1
28
TWI0
System
Reserved
TC5
0x40018000
0xE0000000
0x64000000
0x9FFFFFFF
27
+0x80
Reserved
SMC Chip Select 2
19
0x4001C000
TWI1
0xFFFFFFFF
20
0x40020000
0x400E0000
System Controller
PWM
0x40024000
SMC
offset
block
peripheral
USART1
0x400E0400
Reserved
5
0x400E0600
0x40030000
UART0
Reserved
8
0x400E0740
CHIPID
0x40034000
UART1
0x40038000
UDP
0x400E0800
Reserved
6
EFC1
0x40040000
PIOA
0x40044000
Reserved
0x400E0000
PIOC
System Controller
13
0x400E2600
RSTC
Reserved
1
+0x10
SUPC
0x40100000
RTT
0x40200000
Reserved
+0x30
3
+0x50
0x40400000
WDT
32 MBytes
bit band alias
Reserved
4
+0x60
35
0x40048000
12
0x400E1400
34
CRCCU
11
PIOB
0x400E1200
30
ACC
0x400E0E00
0x400E1000
29
0x4003C000
EFC
0x400E0C00
33
Reserved
9
0x400E0A00
15
0x4002C000
PMC
ID
14
0x40028000
MATRIX
1 MByte
bit band
regiion
USART0
10
0x400E0200
31
0x60000000
RTC
2
+0x90
GPBR
0x400E1600
Reserved
0x4007FFFF
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9.
Memories
9.1
Embedded Memories
9.1.1
Internal SRAM
The SAM4SP32A device embeds a total of 160-Kbytes high-speed SRAM.
The SRAM is accessible over System Cortex-M4 bus at address 0x2000 0000. The SRAM is in the bit band region.
The bit band alias region is from 0x2200 0000 to 0x23FF FFFF.
9.1.2
Internal ROM
The SAM4SP32A embeds an Internal ROM, which contains the SAM Boot Assistant (SAM-BA®), In Application
Programming routines (IAP) and Fast Flash Programming Interface (FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
9.1.3
Embedded Flash
9.1.3.1 Flash Overview
Flash size is 2x1024 Kbytes.
The memory is organized in sectors. Each sector has a size of 64 KBytes. The first sector of 64 Kbytes is divided into
3 smaller sectors.
The three smaller sectors are organized to consist of 2 sectors of 8 KBytes and 1 sector of 48 KBytes. Refer to 41
below.
Figure 9-1. Global Flash Organization
Sector size
Sector name
8 KBytes
Small Sector 0
8 KBytes
Small Sector 1
48 KBytes
Larger Sector
64 KBytes
Sector 1
64 KBytes
Sector n
Sector 0
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Each Sector is organized in pages of 512 Bytes. For sector 0:
•
•
•
The smaller sector 0 has 16 pages of 512Bytes
The smaller sector 1 has 16 pages of 512 Bytes
The larger sector has 96 pages of 512 Bytes
From Sector 1 to n:
The rest of the array is composed of 64 KBytes sector of each 128 pages of 512bytes. Refer to Figure 9-2 below.
Figure 9-2. Flash Sector Organization
A sector size is 64 KBytes
Sector 0
•
16 pages of 512 Bytes
Smaller sector 0
16 pages of 512 Bytes
Smaller sector 1
96 pages of 512 Bytes
Larger sector
Sector 1
128 pages of 512 Bytes
Sector n
128 pages of 512 Bytes
SAM4SP32A: the Flash size is 2 x 1024 KBytes
•
Internal Flash0 address is 0x0040_0000
•
Internal Flash1 address is 0x0050_0000
Refer to Figure 9-3 below for the organization of the Flash following its size.
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Figure 9-3. Flash Size
Flash 1 MBytes
2 x 8kBytes
1 x 48kBytes
15 x 64kBytes
Erasing the memory can be performed as follows:
•
Note:
•
•
•
on a 512-byte page inside a sector, of 8K Bytes (1)
EWP and EWPL commands can be only used in 8 KBytes sectors.
on a 4-Kbyte Block inside a sector of 8 KBytes/48 Kbytes/64 Kbytes
on a sector of 8 KBytes/48 KBytes/64 KBytes
on chip
The memory has one additional reprogrammable page that can be used as page signature by the user. It is accessible
through specific modes, for erase, write and read operations. Erase pin assertion will not erase the User Signature
page.
Erase memory by page is possible only in Sector of 8 Kbytes.
(1) EWP and EWPL commands can be only used in sector 8KBytes sectors.
9.1.3.2 Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (HEFC4) manages accesses performed by the masters of the system. It
enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block.
It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the sys-tem about the Flash
organization, thus making the software generic.
9.1.3.3 Flash Speed
The user needs to set the number of wait states depending on the frequency used:
For more details, refer to the “AC Characteristics” sub-section of the product “Electrical Characteristics”.
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9.1.3.4 Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several
consecutive pages, and each lock region has its associated lock bit.
Table 9-1.
Lock bit number
Product
Number of lock bits
Lock region size
SAM4SP32A
256 (128 + 128)
8 Kbytes
If a locked-region’s erase or program command occurs, the command is aborted and the EEFC triggers an interrupt.
The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.1.3.5 Security Bit Feature
The SAM4SP32A features a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When the
security is enabled, any access to the Flash, SRAM, Core Registers and Internal Peripherals either through the ICE
interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code
programmed in the Flash.
This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of the EEFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase
is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal
Peripherals are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it
is safer to connect it directly to GND for the final application.
9.1.3.6 Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and
cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
9.1.3.7 Unique Identifier
SAM4SP32A device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be
changed by the user. The ERASE pin has no effect on the unique identifier.
9.1.3.8 User Signature
Each part contains a User Signature of 512 bytes. It can be used by the user to store user information such as
trimming, keys, etc., that the customer does not want to be erased by asserting the ERASE pin or by software ERASE
command. Read, write and erase of this area are allowed.
9.1.3.9 Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or
through a multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial
programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST and PA0
and PA1are tied low.
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9.1.3.10 SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash
memory.
The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
9.1.3.11 GPNVM Bits
The GPNVM bits of the SAM4SP32A are only available on FLash0. There is no GPNVM bit on Flash1. The GPNVM0
is the security bit. The GPNVM1 is used to select the boot mode (boot always at 0x00) on ROM or FLASH. The
SAM4SP32A embeds an additional GPNVM bit : GPNVM2. This GPNVM bit is used only to swap the Flash0 and
Flash1. If GPNVM bit 2 is:
ENABLE: If the Flash1 is mapped at address 0x0040_0000 (Flash1 and Flash0 are continuous).
DISABLE: If the Flash0 is mapped at address 0x0040_0000 (Flash0 and Flash1 are continuous).
Table 9-2.
9.1.4
General Purpose Non volatile Memory Bits
GPNVMBit[#]
Function
0
Security bit
1
Boot mode selection
2
Flash selection (Flash 0 or Flash 1)
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed
via GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set
General-purpose NVM Bit” of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE
clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.
Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting ERASE clears the GPNVM
Bit 2 and thus selects the boot from bank 0 by default.
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10.
System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power,
resets, clocks, time, interrupts, watchdog, etc
Figure 10-1. System Controller Block Diagram
VDDIO
VDDOUT12
vr_on
vr_mode
Software Controlled
Voltage Regulator
VDDIN
VDDIO
Supply
Controller
Zero-Power
Power-on Reset
PIOA/B/C
Input/Output Bu ffers
ON
Supply
Monitor
(Backup)
PIOx
out
Analog
Compa rator
WKUP0 - WKUP15
ADC Analog
Circuitry
rtc_nreset
SLCK
RTC
ADC Ch.
Gene ral Pu rpose
Ba ckup Registers
DAC Analog
Circuitry
rtc_alarm
ADVREF
VDDIO
rtt_nreset
SLCK
RTT
rtt_alarm
XIN32
XOUT32
Embedded
32 kHz RC
Oscillator
DDM
vddcore_nreset
XTALSEL
Xtal 32 k Hz
Oscillator
DDP
USB
Transeivers
osc32k_ xtal_en
Slow Clock
SLCK
bod_core_on
lcore_brown_out
Brownout
Detector
(Core)
osc32k_ rc_en
SRAM
vddcore_nreset
Backup Power Supply
Reset
Controller
NRST
VDDCORE
proc_nreset
periph_nreset
ice_nreset
Peripherals
Matrix
Peripheral
Bridge
Cortex-M4
FSTT0 - FSTT15
SLCK
E mbedded
12 / 8 / 4 MHz
RC
Os cillator
XIN
XOUT
Main Clo ck
MAINCK
3 - 20 MHz
XTAL Oscillator
MAINCK
Power
Manageme nt
Controller
Master Clock
MCK
PLLACK
PLLA
SLCK
VDDIO
MAINCK
Flash
Watchdog
Timer
PLLBCK
PLLB
Core Power Supply
FSTT0 - FSTT15 are possibleFast Startup sources, generated by WKUP0 -WKUP15 pins,
but are not physical pins.
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10.1
System Controller and Peripherals Mapping
Please refer to SAM4SP32A Product Mapping.
All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2
Power-on-Reset, Brownout and Supply Monitor
The SAM4SP32A embeds three features to monitor, warn and/or reset the chip:
•
•
•
Power-on-Reset on VDDIO
Brownout Detector on VDDCORE
Supply Monitor on VDDIO
10.2.1 Power-On-Reset
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but also during power
down. If VDDIO goes below the threshold voltage, the entire chip is reset. For more information, refer to the Electrical
Characteristics section of the datasheet.
10.2.2 Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the
Supply Controller (SUPC_MR). It is especially recommended to disable it during low-power modes such as wait or
sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to the
Supply Controller (SUPC) and Electrical Characteristics sections of the datasheet.
10.2.3 Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully
programmable with 16 steps for the threshold (between 3.0 V to 3.6 V). It is controlled by the Supply Controller
(SUPC). A sample mode is possible. It allows dividing the supply monitor power consumption by a factor of up to
2048. For more information, refer to the SUPC and Electrical Characteristics sections of the datasheet.
10.3
Reset Controller
The Reset Controller is based on a Power-on-Reset cell, and a Supply Monitor on VDDCORE. The Reset Controller is
capable to return to the software the source of the last reset, either a general reset, a wake-up reset, a software reset,
a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the NRST pin
input/output. It is capable to shape a reset signal for the external devices, simplifying to a minimum connection of a
push-button on the NRST pin to implement a manual reset. The configuration of the Reset Controller is saved as
supplied on VDDIO.
10.4
Supply Controller (SUPC)
The Supply Controller controls the power supplies of each section of the processor and the peripherals (via Voltage
regulator control).
The Supply Controller has its own reset circuitry and is clocked by the 32 kHz Slow Clock generator.
The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power poweron reset allows the Supply Controller to start properly, while the soft-ware-programmable brownout detector allows
detection of either a battery discharge or main voltage loss.
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The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow
Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the Slow Clock
source.
The Supply Controller starts up the device by sequentially enabling the internal power switches and the Voltage
Regulator, then it generates the proper reset signals to the core power supply.
It also enables to set the system in different low-power modes and to wake it up from a wide range of events.
10.5
Clock Generator
The Clock Generator is made up of:
•
•
•
•
One Low-power 32768Hz Slow Clock Oscillator with bypass mode
•
•
One 80 to 240 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller
One Low-power RC Oscillator
One 3-20 MHz Crystal Oscillator, which can be bypassed
One Fast RC Oscillator, factory programmed. Three output frequencies can be selected: 4, 8 or 12 MHz. By
default 4 MHz is selected.
One 80 to 240 MHz programmable PLL (PLLA), provides the clock, MCK to the processor and peripherals.
The PLLA input frequency is from 3 MHz to 32 MHz.
Figure 10-2. Clock Generator Block Diagram
Clock Generator
XTALSEL
On Chip
32k RC OSC
XIN32
XOUT32
XIN
XOUT
Slow Clock
SLCK
Slow Clock
Oscillator
12M Main
Oscillator
Main Clock
MAINCK
On Chip
12/8/4 MHz
RC OSC
MAINSEL
PLL and
Divider B
PLLB Clock
PLLBCK
PLL and
Divider A
PLLA Clock
PLLACK
Status
Control
Power
Management
Controller
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10.6
Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
•
•
•
•
•
•
•
the Processor Clock, HCLK
the Free running processor clock, FCLK
the Cortex SysTick external clock
the Master Clock, MCK, in particular to the Matrix and the memory interfaces
the USB Clock, UDPCK
independent peripheral clocks, typically at the frequency of MCK
three programmable clock outputs: PCK0, PCK1 and PCK2
The Supply Controller selects between the 32 kHz RC oscillator and the crystal oscillator. The unused oscillator is
disabled automatically so that power consumption is optimized.
By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at 4 MHz.
The user can trim the 8 and 12 MHz RC Oscillator frequency by software.
Figure 10-3. Power Management Controller Block Diagram
Processor
Clock
Controller
Sleep Mode
Divider
/8
int
SystTick
FCLK
Master Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
HCK
Prescaler
/1,/2,/4,...,/64
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
Prescaler
/1,/2,/4,...,/64
ON/OFF
pck[..]
USB Clock Controller
ON/OFF
PLLBCK
UDPCK
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The SysTick calibration value is fixed at 12500, which allows the generation of a time base of 1 ms with SysTick clock
at 12.5 MHz (max HCLK/8 = 100 MHz/8 = 12500, so STCALIB = 0x30D4).
10.7
Watchdog Timer
•
•
10.8
Windowed, prevents the processor to be in a deadlock on the watchdog access
SysTick Timer
•
•
•
10.9
16-bit key-protected only-once Programmable Counter
24-bit down counter
Self-reload capability
Flexible System timer
Real Time Timer
•
Real-Time Timer, allowing backup of time with different accuracies
•
32-bit Free-running backup Counter
•
Integrates a 16-bit programmable prescaler running on slow clock
•
Alarm Register capable to generate a wake-up of the system through the Shut Down Controller
10.10 Real Time Clock
•
•
•
•
•
•
•
•
Low power consumption
Full asynchronous design
Two hundred year Gregorian and Persian calendar
Programmable Periodic Interrupt
Trimmable 32.7682 kHz crystal oscillator clock source
Alarm and update parallel load
Control of alarm and update Time/Calendar Data In
Waveform output capability on GPIO pins in low power modes
10.11 General-Purpose Backup Registers
•
Eight 32-bit backup general-purpose registers
10.12 Nested Vectored Interrupt Controller
•
•
•
•
•
Thirty maskable external interrupts
Sixteen priority levels
Processor state automatically saved on interrupt entry, and restored on
Dynamic reprioritizing of interrupts
Priority grouping.
•
selection of pre-empting interrupt levels and non pre-empting interrupt levels.
•
Support for tail-chaining and late arrival of interrupts.
• back-to-back interrupt processing without the overhead of state saving and restoration between
interrupts.
•
Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction
overhead.
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10.13 Chip Identification
•
Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
Table 10-1. SAM4SP32A Chip ID´s Register
Chip Name
SAM4SP32A
Flash Size
RAM Size
(KBytes)
(KBytes)
2*1024
160
Pin Count
CHIPID_CIDR
CHIPID_EXID
128
0X29A7_0EE8
-
JTAG ID: 05B3_203F
10.14 UART
•
Two-pin UART
•
Implemented features are 100% compatible with the standard Atmel USART
•
Independent receiver and transmitter with a common programmable Baud Rate Generator
•
Even, Odd, Mark or Space Parity Generation
•
Parity, Framing and Overrun Error Detection
•
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
•
Support for two PDC channels with connection to receiver and transmitter
10.15 PIO Controllers
•
•
•
3 PIO Controllers, PIOA, PIOB and PIOC controlling a maximum of 37 I/O Lines
Each PIO Controller controls up to 22 programmable I/O Lines
Fully programmable through Set/Clear Registers
Table 10-2. PIO available on SAM4SP32A
Version
Pins
PIOA
22
PIOB
12
PIOC
3
•
•
Multiplexing of four peripheral functions per I/O Line
•
•
•
•
Synchronous output, provides set and clear of several I/O lines in a single write
For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
• Input change interrupt
• Programmable Glitch filter
• Programmable debouncing filter
• Multi-drive option enables driving in open drain
• Programmable pull-up on each I/O line
• Pin data status register, supplies visibility of the level on the pin at any time
• Additional interrupt modes on a programmable event: rising edge, falling edge, low level or high level
• Lock of the configuration by the connected peripheral
Write Protect Registers
Programmable Schmitt trigger inputs
Parallel capture mode
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•
Can be used to interface a CMOS digital image sensor, etc....
•
One clock, 8-bit parallel data and two data enable on I/O lines
•
•
Data can be sampled one time out of two (for chrominance sampling only)
Supports connection of one Peripheral DMA Controller channel (PDC) which offers buffer reception
without processor intervention
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10.16 Peripheral Identifiers
Table 10-3 defines the Peripheral Identifiers of the SAM4SP32A. A peripheral identifier is required for the control of
the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power
Management Controller.
Table 10-3. Peripherical Identifiers
PMC
Instance ID
Instance Name
NVIC Interrupt
Clock Control
Instance Description
0
SUPC
X
Supply Controller
1
RSTC
X
Reset Controller
2
RTC
X
Real Time Clock
3
RTT
X
Real Time Timer
4
WDT
X
Watchdog Timer
5
PMC
X
Power Management Controller
6
EFC0
X
Enhanced Embedded Flash Controller 0
7
EFC1
X
Enhanced Embedded Flash Controller 1
8
UART0
X
X
UART 0
9
UART1
X
X
UART 1
10
SMC
X
X
Static Memory Controller
11
PIOA
X
X
Parallel I/O Controller A
12
PIOB
X
X
Parallel I/O Controller B
13
PIOC
X
X
Parallel I/O Controller C
14
USART0
X
X
USART 0
15
USART1
X
X
USART 1
16
-
-
-
Reserved
17
-
-
-
Reserved
18
-
X
X
Reserved
19
TWI0
X
X
Two Wire Interface 0
20
TWI1
X
X
Two Wire Interface 1
21
-
-
-
Reserved
22
SSC
X
X
Synchronous Serial Controller
23
TC0
X
X
Timer/Counter 0
24
TC1
X
X
Timer/Counter 1
25
-
-
-
Reserved
26
-
-
-
Reserved
27
-
-
-
Reserved
28
-
-
-
Reserved
29
-
Reserved
30
-
Reserved
31
PWM
X
X
Pulse Width Modulation
32
CRCCU
X
X
CRC Calculation Unit
33
ACC
X
X
Analog Comparator
34
UDP
X
X
USB Device Port
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10.17 Peripheral Signal Multiplexing on I/O Lines
The SAM4SP32A features 3 PIO controllers (PIOA, PIOB and PIOC), that multiplex the I/O lines of the peripheral set.
The SAM4SP32A controls up to 22 lines. Each line can be assigned to one of three peripheral functions: A, B or C.
The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A, B and C are
multiplexed on the PIO Controllers. The column “Comments” has been inserted in this table for the user’s own
comments; it may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the tables.
10.17.1 PIO Controller A Multiplexing
Table 10-4. Multiplexing on PIO Controller A (PIOA)
I/O
Peripherical A
Peripherical B
Peripherical C
Extra Function
PA0
PWMH0
TIOA0
A17
WKUP0
PA1
PWMH1
TIOB0
A18
WKUP1
PA2
PWMH2
SCK0
DATRG
WKUP2
PA3
TWD0
NPCS3
PA4
TWCK0
TCLK0
WKUP3
PA5
RXD0
NPCS3
WKUP4
PA6
TXD0
PCK0
PA7
RTS0
PWMH3
PA8
CTS0
ADTRG
Line
System Function
Comment
XIN32
WKUP5
PA9
URXD0
NPCS1
PA10
UTXD0
NPCS2
PWMFI0
WKUP6
PA15
TF
TIOA1
PWML3
WKUP14/PIODCEN1
PA16
TK
PA17
TD
TIOB1
PWML2
WKUP15/PIODCEN2
PCK1
PWMH3
AC0
PA18
RD
PCK2
A14
AC1
PA19
RK
PWML0
A15
AC2/WKUP9
PA20
RF
PWML1
A16
AC3/WKUP10
PA21
RXD1
PCK1
PA22
TXD1
NPCS3
NCS2
PA23
SCK1
PWMH0
A19
PIODCCLK
PA24
RTS1
PWMH1
A20
PIODC0
PA25
CTS1
PWMH2
A23
PIODC1
XOUT32
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10.17.2 PIO Controller B Multiplexing
Table 10-5. Multiplexing on PIO Controller B (PIOB)
I/O
Line
Peripherical A
Peripherical B
Peripherical C
Extra Function
PB0
PWMH0
AC4/RTCOUT0
PB1
PWMH1
AC5/RTCOUT1
PB2
URXD1
PB3
PB4
PB5
NPCS2
AC6/WKUP12
UTXD1
PCK2
AC7
TWD1
PWMH2
TWCK1
PWML0
System Function
TDI
WKUP13
TDO/TRACESWO
PB6
TMS/SWDIO
PB7
TCK/SWCLK
PB8
XOUT
PB9
XIN
PB10
DMM
PB11
PB12
Comment
DPP
PWML1
ERASE
10.17.3 PIO Controller C Multiplexing
Table 10-6. Multiplexing on PIO Controller C (PIOC)
I/O
Peripherical A
Peripherical B
PC0
D0
PWML0
PC5
D5
PC26
A8
Line
Peripherical C
Extra Function
System Function
Comment
TIOA4
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11.
Embedded Peripherals Overview
11.1
Two Wire Interface (TWI)
•
•
•
•
•
•
•
11.2
Compatibility with Atmel two-wire interface, serial memory and I2C compatible devices
One, two or three bytes for slave address
Sequential read/write operations
Bit Rate: Up to 400 kbit/s
General Call Supported in Slave Mode
Connecting to PDC channel capabilities optimizes data transfers in Master Mode only
•
One channel for the receiver, one channel for the transmitter
•
Next buffer support
Universal Asynchronous Receiver Transceiver (UART)
•
11.3
Master, Multi-Master and Slave Mode Operation
Two-pin UART
•
Independent receiver and transmitter with a common programmable Baud Rate Generator
•
Even, Odd, Mark or Space Parity Generation
•
Parity, Framing and Overrun Error Detection
•
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
•
Support for two PDC channels with connection to receiver and transmitter
USART
•
•
•
•
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
•
1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
•
Parity generation and error detection
•
Framing error detection, overrun error detection
•
MSB- or LSB-first
•
Optional break generation and detection
•
By 8 or by-16 over-sampling receiver frequency
•
Hardware handshaking RTS-CTS
•
Receiver time-out and transmitter timeguard
•
Optional Multi-drop Mode with address generation and detection
•
Optional Manchester Encoding
•
Full modem line support on USART1 (DCD-DSR-DTR-RI)
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
•
•
•
NACK handling, error counter with repetition and iteration limit
SPI Mode
•
Master or Slave
•
Serial Clock programmable Phase and Polarity
•
SPI Serial Clock (SCK) Frequency up to MCK/4
IrDA modulation and demodulation
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•
•
Test Modes
•
11.4
11.5
Remote Loopback, Local Loopback, Automatic Echo
Synchronous Serial Controller (SSC)
•
Provides serial synchronous communication links used in audio and telecom applications (with CODECs in
Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader)
•
•
•
Contains an independent receiver and transmitter and a common clock divider
•
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
Offers configurable frame sync and data length
Receiver and transmitter can be programmed to start automatically or on detection of different event on the
frame sync signal
Timer Counter (TC)
•
•
•
•
•
•
11.6
Communication at up to 115.2 Kbps
Two 16-bit Timer Counter Channels
Wide range of functions including:
•
Frequency Measurement
•
Event Counting
•
Interval Measurement
•
Pulse Generation
•
Delay Timing
•
Pulse Width Modulation
•
Up/down Capabilities
Each channel is user-configurable and contains:
•
One external clock input
•
Five internal clock inputs
•
Two multi-purpose input/output signals
Two global registers that act on all three TC Channels
Quadrature decoder
•
Advanced line filtering
•
Position / revolution / speed
2-bit Gray Up/Down Counter for Stepper Motor
Pulse Width Modulation Controller (PWM)
•
•
•
One Four-channel 16-bit PWM Controller, 16-bit counter per channel
Common clock generator, providing Thirteen Different Clocks
•
A Modulo n counter providing eleven clocks
•
Two independent Linear Dividers working on modulo n counter outputs
•
High Frequency Asynchronous clocking mode
Independent channel programming
•
Independent Enable Disable Commands
•
Independent Clock Selection
•
Independent Period and Duty Cycle, with Double Buffering
•
Programmable selection of the output waveform polarity
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•
•
•
Programmable center or left aligned output waveform
•
Independent Output Override for each channel
•
Independent complementary Outputs with 12-bit dead time generator for each channel
•
Independent Enable Disable Commands
•
Independent Clock Selection
•
Independent Period and Duty Cycle, with Double Buffering
Synchronous Channel mode
•
Synchronous Channels share the same counter
•
Mode to update the synchronous channels registers after a programmable number of periods
Connection to one PDC channel
•
•
•
11.7
One programmable Fault Input providing an asynchronous protection of outputs
Stepper motor control (2 Channels)
USB Device Port (UDP)
•
•
•
•
•
•
•
11.8
Provides Buffer transfer without processor intervention, to update duty cycle of synchronous channels
USB V2.0 full-speed compliant,12 Mbits per second.
Embedded USB V2.0 full-speed transceiver
Embedded 2688-byte dual-port RAM for endpoints
Eight endpoints
•
Endpoint 0: 64bytes
•
Endpoint 1 and 2: 64 bytes ping-pong
•
Endpoint 3: 64 bytes
•
Endpoint 4 and 5: 512 bytes ping-pong
•
Endpoint 6 and 7: 64 bytes ping-pong
•
Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints
Suspend/resume logic
Integrated Pull-up on DDP
Pull-down resistor on DDM and DDP when disabled
Analog Comparator
•
•
•
One analog comparator
High speed option vs. low-power option
•
170 μA/xx ns active current consumption/propagation delay
•
20 μA/xx ns active current consumption/propagation delay
Selectable input hysteresis
•
•
0, 15 mV, 30mV (Typ)
Minus input selection:
•
Temperature Sensor
•
ADVREF
•
Plus input selection:
• All analog inputs
•
output selection:
• Internal signal
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•
•
11.9
•
external pin
•
selectable inverter
window function
Interrupt on:
• Rising edge, Falling edge, toggle
• Signal above/below window, signal inside/outside window
Cyclic Redundancy Check Calculation Unit (CRCCU)
•
•
32-bit cyclic redundancy check automatic calculation
CRC calculation between two addresses of the memory
11.10 PLC Brigde
•
Six I/O lines to connect to PRIME PLC Transceiver for external configurations
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12.
PRIME PLC Transceiver
The SAM4SP32A MCU embeds a Certified PRIME Power line communication transceiver with a featured Class D
power amplifier and a set of hardware accelerators blocks to execute the heavy tasks of the PRIME protocol without
the interruption of the Cortex-M4 CPU.
The PRIME PLC Transceiver peripheral integrates:
•
•
•
•
•
•
•
•
•
•
Power Line Carrier Modem for 50 and 60 Hz mains
97-carrier OFDM PRIME compliant
Baud rate Selectable: 21400 to 128600 bps
Differential BPSK, QPSK, 8-PSK modulations
Automatic Gain Control and signal amplitude tracking
Embedded on-chip DMAs
Media Access Control
Viterbi decoding and CRC PRIME compliant
128-bit AES encryption
Channel sensing and collision pre-detection
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12.1
SAM4SP32A PRIME PHY Layer
12.1.1 SAM4SP32A PHY Layer
The physical layer of SAM4SP32A consists of a hardware implementation of the PRIME Physical Layer Entity, which
is an Orthogonal Frequency Division Multiplexing (OFDM) system in the CENELEC A-band. This PHY layer transmits
and receives MPDUs (MAC Protocol Data Unit) between neighbor nodes.
From the transmission point of view, the PHY layer receives its inputs from the MAC (Medium Access Control) layer,
via DMA. At the end of transmission branch, data is output to the physical channel.
On the reception side, the PHY layer receives its inputs from the physical channel, and at the end of reception branch,
the data flows to the MAC layer, via DMA.
A PHY layer block diagram is shown below:
Figure 12-1. SAM4SP32A PHY Layer Block Diagram
MAC
Layer
from
DMA
Convolutional
Encoder
Scrambler
CRC
Interleaver
Cyclic
Prefix
AES
Block
Sub-carrier
Modulator
IFFT
Converter/PAD
to µC
Carrier
Detection
SAM4SP32A
PHY Layer
MAC
Layer
VSENSE
PSENSE
Power
Supply
Sensing
Test
mode
to
DMA
Tx
AES
Block
Sub- carrier
Demodulator
FFT
CRC
Interleaver
Pre-FFT
Syncro
Convolutional
Decoder
Scrambler
Analog
Front - End
Control
AGC0
AGC1
Gain
Control
Line
Impedance
Control
AFE_HIMP
TxRx
Control
AFE_TXRX
Rx
Converter
The diagram can be divided in four sub-blocks: Transmission branch, Emission branch, Analog Front End control and
Carrier Detection.
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12.1.1.2 Transmission and Reception branches
Phy layer takes data to be sent from dedicated DMA channel (PHY_TX). 128-bit AES encryption is done “on the fly”,
and the Clyclic Redundancy Check (CRC) fields are hardware-generated in real time. These CRCs are properly
appended to the transmission data. The rest of the chain is hardware-wired, and performs automatically all the tasks
needed to send data according to PRIME specifications.
In Figure 12-2, the block diagram of the transmission brach Is shown.
Figure 12-2. Transmission branch
Test
mode
from DMA
CRC
Convolutional
Encoder
AES
Block
Scrambler
Cyclic
Prefix
Interleaver
Sub-carrier
Modulator
Converter/PAD
Tx
IFFT
The output is differentially modulated using a BPSK/DQPSK/D8PSK scheme. After modulation, IFFT (Inverse Fourier
Transform) block and cyclic prefix block allows to implement an OFDM scheme.
A Converter and a Power Amplifier Driver is the last block in the transmission branch. This block is responsible for
adjusting the signal to reach the best transmission efficiency, thus reducing consumption and power dissipation.
Test mode: When selected, test mode injects data directly to Sub-carrier modulation block. When in test mode, data
can be injected continuously to the line using only a set of selected frequencies, in order to test channel behavior.
The reception branch performs automatically all the tasks needed to process received data. Phy layer delivers data to
MAC layer through the dedicated DMA channel (PHY_RX).
Figure 12-3. Reception branch
to DMA
CRC
Convolutional
Decoder
Sub- carrier
Demodulator
FFT
AES
Block
Scrambler
Interleaver
Pre- FFT
Syncro
Converter
Rx
12.1.1.3 Carrier Detection
Looking for an easy detection of incoming messages, PRIME specification defines a chirp signal located at the
beginning of the PRIME frames devised to ease synchronization in the receptor. By means of detection techniques,
the receiver can know accurately when the chirp has been completely received and then the correct instant when the
frame begins.
Before starting a transmission, it is also necessary to use carrier detection in order to check if another device is
already emitting, thus avoiding collisions. If any device is emitting, the carrier detection triggers a microcontroller
interruption and sets an internal flag, thus the transmission will be stopped.
The main drawback of this process is that chirp signal length (2.4 milliseconds) is not short enough to guarantee very
low collision ratio.
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To improve this drawback, the OFDM PLC Modem implements two different algorithms to detect the carrier as soon
as possible, aiming to reduce collisions and improving the medium access behavior. By these early detection
techniques, the system achieves low collision ratio, and the communication throughput increases significantly.
12.1.1.4 Analog Front End control
The Phy layer controls the Analog Front End by means of four sub-blocks:
•
•
•
•
Power Supply sensing
Gain control
Line Impedance control
TxRx control
12.1.1.5 Power Supply Sensing: VSENSE and PSENSE
The power supply is continuously monitored to avoid power supply failures that could damage the supply device. This
block senses the power channel using two different inputs:
•
VSENSE: VSENSE detects whether voltage falls below 3.3v during a number of cycles while a
message is being transmitted. This measurement is done after a transitory guard time (TTRANS in
figure below). If a Voltage failure occurs, the transmission is shut down and sending messages again
will be not possible if an internal flag (VFAILURE) is not previously cleared.
Figure 12-4. Transitory guard time in message transmission
Message transmision
TTRANS (no measuring
voltage failures)
•
Measuring possible voltage failures
PSENSE: PSENSE measures the power source current consumption, shutting down the transmission
if the consumption exceeds a defined threshold (stored in MAXPOT phy layer registers, see 12.1.5.34).
This measurement is done after a transitory guard time. As the current measurement varies over time,
an averaging is done taking into account an average parameter (Alpha), a configurable number of
cycles (NUMCYCLES, see 12.1.5.35) and a configurable length of each cycle (A_NUMMILIS, see
12.1.5.36).
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If a power failure occurs, the transmission is shut down and sending messages again will be not
possible if an internal flag (PFAILURE, see 12.1.5.22) is not previously cleared.
The system considers that a power failure has occurs when the value read from MEAN registers (see
12.1.5.30) is above the user-definable value stored in MAXPOT registers.
Figure 12-5. PSENSE parameters
Message transmision
NUM_MILIS NUM_MILIS NUM_MILIS NUM_MILIS NUM_MILIS
TRANS_PSENSE
NUM_CYCLES
New
PSENSE
CYCLES
value
New
PSENSE
CYCLES
value
New
PSENSE
CYCLES
value
New
PSENSE
CYCLES
value
New
MEAN
value
New
PSENSE
CYCLES
value
New
MEAN
value
New
MEAN
value
Psense and Vsense configurations parameters are automatically set by the Phy layer.
See related peripheral registers for more information about Psense and Vsense.
12.1.1.6 Gain Control
This block implements two Automatic Gain Control outputs to adjust the received signal level to a suitable range. Both
of them are set to ‘1’ when the received signal is above two system thresholds in order to activate external attenuators
placed in the external analog front end.
The value of these outputs is set during the beginning of a received message and is hold until the end of the message.
AGC0 and AGC1 follow different algorithms, thus using both of them ensures a more accurate gain control.
See AGC_CONFIG register in for information about AGC configuration.
12.1.1.7 Line Impedance Control
This block modifies the configuration of the Analog Front End by means of AFE-HIMP output. When working with a
suitable external configuration, the system can change the filter conditions in order to adjust its behavior to the line
impedance values. See last SAM4SP32A reference design for further information about Line Impedance topologies.
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12.1.1.8 TxRx Control
This block modifies the configuration of the Analog Front End by means of AFE-TXRX output. Thus is possible to
change filter conditions between transmission/reception.
See reference design for further information about TxRx control.
12.1.2 PHY parameters
As described below, the PHY layer is specified by certain main parameters, which are fixed for each specific
constellation/coding combination. These parameters have to be identical in a network in order to achieve compatibility.
Table 12-1. PRIME Phy main parameters
PRIME Phy parameter
Value
Base Band Clock (Hz)
250000
Subcarrier spacing (Hz)
488,28125
Number of data subcarriers
84 (header), 96 (payload)
Number of pilot subcarriers
13 (header), 1 (payload)
FFT interval (samples)
512
FFT interval (µs)
2048
Cyclic Prefix (samples)
48
Cyclic Prefix (µs)
192
Symbol interval (samples)
560
Symbol interval (µs)
2240
Preamble period (µs)
2048
Table 12-2 shows the PHY data rate during payload transmission, and maximum MSDU length for various modulation
and coding combinations
Table 12-2. Phy parameters depending on the modulation
DBPSK
DQPSK
D8PSK
Convolutional Code (1/2)
On
Off
On
Off
On
Off
Information bits per subcarrier
0,5
1
1
2
1,5
3
Information bits per OFDM symbol
48
96
96
192
144
288
Raw data rate (kbps approx)
21,4
42,9
42,9
85,7
64,3
128,6
MAX MSDU length with 63 symbols
(bits)
3016
6048
6040
12096
9064
18144
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Table 12-3 shows the modulation and coding scheme and the size of the header portion of the PHY frame
Table 12-3. Header parameters
DBPSK
Convolutional Code (1/2)
On
Information bits per subcarrier
0,5
Information bits per OFDM symbol
42
All the parameters of the physical layer such as the base band clock, subcarrier spacing, number of subcarriers...; are
defined in PRIME Specification, and have to be identical in a network in order to achieve compatibility.
12.1.3 PHY Protocal Data Unit (PPDU) Format
Figure 12-6 shows how OFDM symbols are transmitted in a PPDU (Physical layer Protocol Data Unit). The preamble
is used at the beginning of every PPDU for synchronization purposes.
Figure 12-6. PHY layer transmitter block diagram
CRC
Convolutional
Encoder
Scrambler
Interleaver
Sub-carrier
Modulator
IFFT
Cyclix Prefix
Phy layer adaptively modifies attenuation values applied to the whole signal. Also, additional attenuations are applied
to the chirp section of the signal (preamble) and to the rest of the signal itself (header+payload), to smoothly adapt
amplitude values and transitions.
Figure 12-7. PPDU OFDM symbols and duration
2,048 ms
4,48 ms / 2 OFDM symbols
PREAMBLE
HEADER
Header:
• DBPSK
• FEC: ½ always on
2,24 * M ms / M OFDM symbols
PAYLOAD
Payload:
• DBPSK, DQPSK, D8PSK
• FEC: ½ on/off
12.1.4 PHY Service Specification
There is an interface specified in PRIME for the PHY layer, with several primitives relative to both data and control
planes.
PHY layer has a single 20-bit free-running clock measured in 10µs steps. Time measured by this clock is the one to
be used in some PHY primitives to indicate a specific instant in time.
SAM4SP32A includes a hardware implementation of this clock, which consists of a 20-bit register. This register is
read-only and it can be accessed as a 32-bit variable by the ADD8051C3A microcontroller.
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Figure 12-8. Header and payload structure
4 bits
6 bits
6 bits
54 bits
8 bits
6 bits
Protocol
LEN
PAD_LEN
MAC_H
CRC_Ctrl
FLUSHING_H
PHY HEADER, 84 bits
8xM bits
MSDU
8 bits
8xP bits
FLUSHING_D
PAD
PHY PAYLOAD
Prime specifies a complete set of primitives to manage the PHY Layer, and the PHY-SAP (PHY Service Access Point)
from MAC layer. Atmel PRIME stack integrates all this functions, making them transparent to the final user and
simplifying the management.
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12.1.5 PHY Layer registers
Relative addresses in the PLC modem intenrnal memory map given.
12.1.5.1 PHY_SFR Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
PHY_SFR
BCH_ERR
CD
UMD
--
--
TXRX
--
INT_PHY
Name:
PHY_SFR
Address:
0xFE2A
Access:
Read/write
Reset:
0x87
•
--:
•
BCH_ERR: Busy Channel Error Flag.
Reserved bit
This bit is set to ‘0’ by hardware to indicate the presence of an OFDM signal at the
transmission instant. Otherwise, this field value is ‘1’.
This bit is used for returning a result of “Busy Channel” in the PHY_DATA.confirm primitive
(see PRIME specification).
•
CD:
Carrier Detect bit.
This bit is set to ‘1’ by hardware when an OFDM signal is detected, and it is active during the
whole reception.
This bit is used in channel access (CSMA-CA algorithm) for performing channel-sensing.
•
UMD:
Unsupported Modulation Scheme flag.
This flag is set to ‘1’ by hardware every time a header with correct CRC is received, but the
PROTOCOL field in this header indicates a modulation scheme not supported by the
system.
•
TXRX:
Transmission order.
When data to transmit is ready at ADDR_PHY_INI_TX in data memory, the Time value is set
at TX_TIME register and then the emission level is specified at ATTENUATION register,
then TXRX bit has to be set to '0' in order to init transmission.
If this bit is read, only returns '0' when physical transmission has started. Otherwise, it
returns '1'.
The transmission will begin when TIMER_BEACON_REF is equal to TX_TIME.
•
INT_PHY:
Physical Layer interruption
This bit is internally connected to the external microcontroller interrupt /EXT_INT.
It is low-level active. It is set to '0' by physical layer and is cleared by writing '1' in the bit
PHY_SFR(0).
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12.1.5.2 SYS_CONFIG Register
Name
Bit 7
Bit 6
SYS_CONFIG
Bit 5
--
Name:
SYS_CONFIG
Address:
0xFE2C
Access:
Read/write
Reset:
0x04
•
--:
•
CONV_PD: Converter Power Down
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CONV_PD
PHY_PD
PHY_ERR_EN
PHY_ERR
PHY_RST
Reserved bits
The SAM4SP32A microcontroller can activate internal converter power down mode by
setting this bit. When internal converter is in power down mode, the system is unable to
receive.
This bit is high-level active.
•
PHY_PD:
PHY Power Down
This bit shuts down Physical Layer clock. When in PHY power down mode, all the system
blocks involved in communication remain inactive. Thus, the system will be unable to
transmit or receive. The next sequence must be respected to ensure proper power down:
Setting PHY power down mode
1-Set Physical Layer reset (SYS_CONFIG(0)), PHY_RST=’1’
2-Set CONV_PD and PHY_PD fields
Exiting PHY power down mode
1-Clear CONV_PD and PHY_PD fields
2-Clear Physical Layer reset (SYS_CONFIG(0)), PHY_RST=’0’
This bit is high-level active.
•
PHY_ERR_EN:Physical Layer Watchdog enable
This bit enables or disables Physical layer watchdog. Physical layer watchdog is enabled by
default.
This bit is high-level active.
•
PHY_EN:
Physical Layer Error Flag
This flag indicates if a Physical layer error has occurred. Physical layer watchdog has a
200milliseconds sampling period. When Physical layer detects an error, it activates the
Physical layer interrupt and this flag is set.
To restore situation, microcontroller must reset Physical layer by means of PHY_RST bit
(SYS_CONFIG(0)).
•
PHY_RST: Physical Layer Reset
This bit resets the Physical layer. To perform a Physical layer reset cycle, microcontroller
must set this bit to ‘1’ and then must clear it to ‘0’.
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12.1.5.3 PHY_CONFIG Register
Name
Bit
7
PHY_CONFIG
Bit
6
--
Name:
PHY_CONFIG
Address:
0xFE68
Access:
Read/write
Reset:
0x1F
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CINR_MODE
PAD_LEN_AC
AES_EN
CD_MOD1_EN
CD_MOD2_DET
MAC_EN
•
--:
•
CINR_MODE:Carrier to Interference + Noise Ratio mode
Reserved bits
This bit enables/disables CINR mode when set to ‘1’.
•
•
•
•
•
•
‘0’: CINR mode disabled.
• ‘1’: CINR mode enabled.
PAD_LEN_AC: This field allows the system to work with two different representations of the Phy
header PAD_LEN field (PAD_LEN represented before coding or PAD_LEN represented
after coding).
AES_EN:
•
‘0’: PAD_LEN field in PHY header is represented before coding. This is the
suitable value to fulfill PRIME specification.
•
‘1’: PAD_LEN field in PHY header is represented after coding.
This field enables/disables “on the fly” AES encryption and decryption by hardware.
•
‘0’: “on the fly” AES encryption/decryption disabled.
•
‘1’: “on the fly” AES encryption/decryption enabled.
CD_MOD1_EN: This field enables/disables Carrier Detection mode 1.
•
‘0’: Carrier Detection mode 1 disabled.
•
‘1’: Carrier Detection mode 1 enabled.
CD_MOD2_DET: This field enables/disables Carrier Detection mode 2.
•
‘0’: Carrier Detection mode 2 disabled.
•
‘1’: Carrier Detection mode 2 enabled.
MAC_EN: This field enables/disables CRC processing by hardware.
•
‘0’: CRC processing disabled.
•
‘1’: CRC processing enabled.
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12.1.5.4 ATTENUATION Register
Name
Bit 7
ATTENUATION
Name:
ATTENUATION
Address:
0xFE24
Access:
Read/write
Reset:
0xFF
•
ATTENUATION:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
ATTENUATION(7:0)
Global attenuation for the transmitted signal (chirp+signal). The 16-bit signal level
is multiplied by this 8-bit value and the result is truncated to 16 bits.
Attenuation value = 0xFF  the transmitted signal amplitude is not attenuated.
Attenuation value = 0x00  the transmitted signal amplitude is nullified.
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12.1.5.5 ATT_CHIRP Register
Name
Bit 7
ATT_CHIRP
Name:
ATT_CHIRP
Address:
0xFE9B
Access:
Read/write
Reset:
0xFF
•
ATT_CHIRP:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
ATT_CHIRP(7:0)
This register stores the attenuation value for the chirp. The 16-bit chirp data is
multiplied with this 8-bit value and the 24-bit result is truncated to 16 bits.
Attenuation value = 0xFF  the chirp amplitude is not attenuated
Attenuation value = 0x00  the chirp amplitude is nullified
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12.1.5.6 ATT_SIGNAL Register
Name
Bit 7
ATT_SIGNAL
Name:
ATT_SIGNAL
Address:
0xFE9C
Access:
Read/write
Reset:
0xFF
•
ATT_SIGNAL:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
ATT_SIGNAL(7:0)
This register stores the attenuation value for the signal without the chirp section.
The 16-bit chirp data is multiplied with this 8-bit value and the 24-bit result is
truncated to 16 bits.
Attenuation value = 0xFF  the signal amplitude is not attenuated
Attenuation value = 0x00  the signal amplitude is nullified
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12.1.5.7 TX_TIME Registers
Name
Bit 7
Bit 6
Bit 5
TX_TIME
Bit 4
Bit 3
Address:
0xFE26 – 0xFE29
Access:
Read/write
Reset:
0x00, …, 0x00;
•
TX_TIME:
B it 0
@0xFE26
TX_TIME(11:4)
@0xFE27
“0000”
“00000000”
TX_TIME
Bit 1
TX_TIME(19:12)
TX_TIME(3:0)
Name:
Bit 2
@0xFE28
@0xFE29
This 20-bit value sets the time instant when the MPDU (MAC Protocol Data Unit) has to be
transmitted. The time is expressed in 10µs steps.
When writing a new value to TX_TIME register, a specific writing order must be taken,
always from the most significant byte (TX_TIME(19:12) at address 0xFE26) to the least
significant byte (TX_TIME(3:0) at address 0xFE28), and it is required to write the 3 bytes
to avoid wrong time comparisons in transmission.
The 20-bit TX_TIME value is managed by the microcontroller as a 4-byte variable. The
TX_TIME value is aligned to the 20 most significant bits, being the 12 least significant bits
padded with zeros.
This register is used by the physical layer for being in accordance with PRIME
specifications about transmission time (see PRIME spec.)
Note: TXRX bit (PHY_SFR(2)) has to be cleared to ‘0’ in order to init transmission. Once
this bit has been cleared, the transmission will start when TIMER_BEACON_REF value is
equal to TX_TIME.
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12.1.5.8 TIMER_FRAME Registers
Name
Bit 7
Bit 6
Bit 5
TIMER_FRAME
Bit 4
Bit 3
Address:
0xFE2D – 0xFE30
Access:
Read only
Reset:
0x00, …, 0x00;
•
B it 0
@0xFE2D
TIMER_FRAME(11:4)
@0xFE2E
“0000”
“00000000”
TIMER_FRAME
Bit 1
TIMER_FRAME(19:12)
TIMER_FRAME(3:0)
Name:
Bit 2
@0xFE2F
@0xFE30
TIMER FRAME:
Time of receipt of the preamble associated with the PSDU (PHY Service Data
Unit). It is expressed in 10µs steps and is taken from the physical layer timer
TIMER_BEACON_REF.
It is set by hardware and is a read-only register.
This register is used by the physical layer for being in accordance with PRIME
specification about reception time (see PRIME specification).
The 20-bit TIMER_FRAME value is managed by the microcontroller as a 4-byte variable.
The TIMER_FRAME value is aligned to the 20 most significant bits, being the 12 least
significant bits padded with zeros. This simplifies arithmetic calculations with time values.
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12.1.5.9 TIMER_BEACON_REF Registers
Name
Bit 7
TIMER_BEACON_REF
Bit 6
Bit 5
Bit 4
Bit 3
Address:
0xFE47 – 0xFE4A
Access:
Read only
Reset:
0x00, …, 0x00;
•
TIMER_BEACON_REF:
B it 0
@0xFE47
TIMER_BEACON_REF (11:4)
@0xFE48
“0000”
“00000000”
TIMER_BEACON_REF
Bit 1
TIMER_BEACON_REF(19:12)
TIMER_BEACON_REF (3:0)
Name:
Bit 2
@0xFE49
@0xFE4A
Timer for the physical layer, which consists of a single 20-bit free-running
clock measured in 10µs steps.
It indefinitely increases a unit each 10 microseconds from 0 to 1048575,
overflowing back to 0.
It is set by hardware and is a read-only register.
This register is used by the physical layer for being in accordance with
PRIME specification. It is reserved 32-bit in data memory to be able to
declare as 32-bit variable. The 20-bit register MSB is aligned to the 32bit variable MSB, in order to simplify arithmetic calculations with time
values.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.10 RX_LEVEL Registers
Name
Bit 7
RX_LEVEL
Name:
TABLE_ELEMENT_INIT
Address:
0xFE31 – 0xFE32
Access:
Read only
Reset:
0x00; 0x00
•
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
RX_LEVEL(15:8)
@0xFE31
RX_LEVEL(7:0)
@0xFE32
RX_LEVEL:These registers store the autocorrelation level of the chirp signal.
When the reception process has started, these registers are set by hardware.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.11 RSSI_MIN Register
Name
Bit 7
Bit 6
Bit 5
RSSI_MIN
Name:
RSSI_MIN
Address:
0xFE33
Access:
Read only
Reset:
0xFF
•
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
RSSI_MIN(7:0)
RSSI_MIN: Received Signal Strength Indication Min
This register stores the minimum RSSI value measured in the last message received.
The measurement is done at symbol level.
The value is stored in ¼dB steps
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12.1.5.12 RSSI_AVG Register
Name
Bit 7
Bit 6
Bit 5
RSSI_AVG
Name:
RSSI_AVG
Address:
0xFE34
Access:
Read only
Reset:
0x00
•
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
RSSI_AVG(7:0)
RSSI_AVG: Received Signal Strength Indication Average
This register stores the average RSSI value measured in the last message received.
The measurement is done at symbol level.
The value is stored in ¼dB steps
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.13 RSSI_MAX Register
Name
Bit 7
Bit 6
Bit 5
RSSI_MAX
Name:
RSSI_MAX
Address:
0xFE35
Access:
Read only
Reset:
0x00
•
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
RSSI_MAX(7:0)
RSSI_MAX: Received Signal Strength Indication Max
This register stores the maximum RSSI value measured in the last message received.
The measurement is done at symbol level.
The value is stored in ¼dB steps
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.14 CINR_MIN Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
CINR_MIN
Name:
CINR_MIN
Address:
0xFE38
Access:
Read only
Reset:
0xFF
•
Bit 3
Bit 2
Bit 1
B it 0
CINR_MIN(7:0)
CINR_MIN: Carrier to Interference + Noise ratio Min
This register stores the minimum CINR value measured in the last message received.
In order to calculate CINR properly, the algorithm takes beacon-type messages as a
reference, since this message type allows knowing its content beforehand.
The system uses a table that must be loaded with the beacon data to be received, so CINR
mode must be activated (see PHY_CONFIG register) and the same procedure used to send
beacons must be followed. As CINR mode is activated, physical layer will load the message
in the table instead of sending it (table load time is in the order of microseconds, and is
much shorter than the one used to send the message).
Once the table is loaded, CINR must be disabled, and next messages CINR will be
calculated taken the beacon loaded in the table as reference.
The measurement is done at symbol level.
The value is stored in ¼dB steps.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.15 CINR_AVG Register
Name
CINR_AVG
Name:
CINR_AVG
Address:
0xFE39
Access:
Read only
Reset:
0x00
•
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CINR_AVG(7:0)
CINR_AVG:Carrier to Interference + Noise ratio Average
This register stores the average CINR measured in the last message received.
In order to calculate CINR properly, the algorithm takes beacon-type messages as a
reference, since this message type allows knowing its content beforehand.
The system uses a table that must be loaded with the beacon data to be received, so CINR
mode must be activated (see PHY_CONFIG register) and the same procedure used to send
beacons must be followed. As CINR mode is activated, physical layer will load the message
in the table instead of sending it (table load time is in the order of microseconds, and is
much shorter than the one used to send the message).
Once the table is loaded, CINR must be disabled, and next messages CINR will be
calculated taken the beacon loaded in the table as reference
The measurement is done at symbol level.
The value is stored in ¼dB steps.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.16 CINR_MAX Register
Name
CINR_MAX
Name:
CINR_MAX
Address:
0xFE3A
Access:
Read only
Reset:
0x00
•
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CINR_MAX(7:0)
CINR_MAX:Carrier to Interference + Noise ratio Max
This register stores the maximum CINR value measured in the last message received.
In order to calculate CINR properly, the algorithm takes beacon-type messages as a
reference, since this message type allows knowing its content beforehand.
The system uses a table that must be loaded with the beacon data to be received, so CINR
mode must be activated (see PHY_CONFIG register) and the same procedure used to send
beacons must be followed. As CINR mode is activated, physical layer will load the message
in the table instead of sending it (table load time is in the order of microseconds, and is
much shorter than the one used to send the message).
Once the table is loaded, CINR must be disabled, and next messages CINR will be
calculated taken the beacon loaded in the table as reference
The measurement is done at symbol level.
The value is stored in ¼dB steps.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.17 EVM_HEADER Registers
Name
Bit 7
EVM_HEADER
Name:
EVM_HEADER
Address:
0xFE3B – 0xFE3C
Access:
Read only
Reset:
0x00; 0x00
•
EVM_HEADER:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
EVM_HEADER(15:8)
@0xFE3B
EVM_HEADER (7:0)
@0xFE3C
Header Error Vector MagnitudeThese registers store in a 16-bit value the maximum error vector magnitude
measured in the reception of a message header.
The 7 MSB (EVM_HEADER(15:9)) represent the integer part in %, being the
EVM_HEADER(8:0) bits the fractional part if more precision were required.
This register is used by the physical layer for being in accordance with PRIME
specification. It is reserved 32-bit in data memory to be able to declare as 32-bit
variable. The 20-bit register MSB is aligned to the 32-bit variable MSB, in order to
simplify arithmetic calculations with time values.
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12.1.5.18 EVM_PAYLOAD Registers
Name
Bit 7
EVM_PAYLOAD
Name:
EVM_PAYLOAD
Address:
0xFE3D – 0xFE3E
Access:
Read only
Reset:
0x00; 0x00
•
EVM_PAYLOAD:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
EVM_PAYLOAD(15:8)
@0xFE3D
EVM_PAYLOAD(7:0)
@0xFE3E
Payload Error Vector MagnitudeThese registers store in a 16-bit value the maximum error vector magnitude
measured in the reception of a message payload.
The 7 MSB (EVM_PAYLOAD(15:9)) represent the integer part in %, being the
EVM_PAYLOAD(8:0) bits the fractional part if more precision were required.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.19 EVM_HEADER_ACUM Registers
Name
Bit 7
EVM_HEADER_ACUM
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
EVM_HEADER_ACUM(19:12)
@0xFE3F
EVM_HEADER_ACUM (11:4)
@0xFE40
EVM_HEADER_ACUM (3:0)
“0000”
“00000000”
Name:
EVM_HEADER_ACUM
Address:
0xFE3F – 0xFE42
Access:
Read only
Reset:
0x00, …, 0x00;
•
EVM_HEADER_ACUM:
B it 0
@0xFE41
@0xFE42
Header Total Error Vector Magnitude Accumulator
When receiving an OFDM symbol, the summation of all its individual
carriers EVMs is calculated in order to further calculate the average EVM
value. These registers store the maximum summation between the two
OFDM symbols received in a message header.
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12.1.5.20 EVM_PAYLOAD_ACUM Registers
Name
Bit 7
EVM_PAYLOAD_ACUM
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
EVM_PAYLOAD_ACUM(19:12)
@0xFE43
EVM_PAYLOAD_ACUM(11:4)
@0xFE44
EVM_PAYLOAD_ACUM(3:0)
“0000”
“00000000”
Name:
EVM_PAYLOAD_ACUM
Address:
0xFE43 – 0xFE46
Access:
Read only
Reset:
0x00, …, 0x00;
•
EVM_PAYLOAD_ACUM:
B it 0
@0xFE45
@0xFE46
Payload Total Error Vector Magnitude Accumulator
When receiving an OFDM symbol, the summation of all its individual
carriers EVMs is calculated in order to further calculate the average EVM
value. These registers store the maximum summation between all the
OFDM symbols received in a message payload.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.21 RMS_CALC Register
Name
RMS_CALC
Name:
RMS_CALC
Address:
0xFE58
Access:
Read only
Reset:
0x00
•
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
RMS_CALC(7:0)
RMS_CALC: This register stores an 8-bit value which magnitude is proportional to the emitted signal
amplitude.
By measuring the amplitude of the emitted signal, the hardware can estimate the power
line input impedance. Thus hardware can adjust emission configuration appropriately.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.22 VSENSE_CONFIG Register
Name
Bit 7
Bit 6
VSENSE_CONFIG
Bit 4
--
Name:
VSENSE_CONFIG
Address:
0xFE59
Access:
Read only
Reset:
0x00
•
Bit 5
Bit 3
PFAILURE
Bit 2
PSENSE_SOFT
Bit 1
VFAILURE
B it 0
VSENSE_EN
PFAILURE: Power Failure Flag
This flag is set to 1 when a power failure occurs. The transmission is stopped and a new
transmission is not possible if this flag is not cleared previously.
When a power failure occurs, a consideration about decreasing voltage amplitude in the
source should be taken.
This flag must be cleared by software.
•
•
PSENSE_SOFT:
Current measurement is done every time a transmission takes place. With
PSENSE_SOFT the system can force a continuous current measurement, including both
idle and transmission states.
•
‘0’: Current consumption is measured every time a transmission begins (after a
guard time defined by TRANS_PSENSE). NUMMILIS, NUMCYCLES and
TRANS_PSENSE values must be taken into account to accurate PSENSE
measurements. This is the default mode and it is the expected one when
SAM4SP32A is working.
•
‘1’: Current consumption is measured both in idle and transmission states. This
mode is useful for design purposes, in order to find suitable values for the
current threshold (MAXPOT registers) depending on the external net
requirements.
VFAILURE: Voltage Failure Flag
This flag is set to 1 when a voltage failure occurs. The transmission is stopped and a new
transmission is not possible if this flag is not cleared previously.
When a voltage failure occurs, a consideration about decreasing voltage amplitude in the
source should be taken.
This flag must be cleared by software.
•
VSENSE_EN:VSENSE enable
This bit enables VSENSE.
•
‘0’: VSENSE disabled (default).
•
‘1’: VSENSE enabled.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.23 NUM_FAILS Register
Name
NUM_FAILS
Name:
NUM_FAILS
Address:
0xFE5A
Access:
Read/write
Reset:
0x02
•
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
NUM_FAILS(7:0)
NUM_FAILS: This register stores the number of 50 ns cycles (clk=20MHz) during which a voltage
failure must be detected before shutting off the transmission and setting VFAILURE flag.
This detection shall be done after a guard period set by TTRANS from the beginning of
the transmission.
Default value: 0x02  2 * 50 = 100ns
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.24 TTRANS Register
Name
TTRANS
Name:
TTRANS
Address:
0xFE5B
Access:
Read/write
Reset:
0x2D
•
TTRANS:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
TTRANS(7:0)
This register stores the number of 50 µs cycles (clk=20MHz) to wait from the beginning
of the transmission before looking for a possible voltage failure.
Default value: 0x2D  45 * 50 = 2.25ms (Thus, voltage failures are not expected until the
end of chirp signal period)
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12.1.5.25 AGC0_KRSSI Register
Name
AGC0_KRSSI
Name:
AGC0_KRSSI
Address:
0xFE5C
Access:
Read/write
Reset:
0x00
•
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
AGC0_KRSSI(7:0)
AGC0_KRSSI: This register is used to correct RSSI (Received Signal Strength Indication) computation
when Automatic Gain Control 0 (AGC0) is active.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.26 AGC1 KRSSI Register
Name
AGC1_KRSSI
Name:
AGC1_KRSSI
Address:
0xFE5D
Access:
Read/write
Reset:
0x00
•
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
AGC1_KRSSI(7:0)
AGC1_KRSSI: This register is used to correct RSSI (Received Signal Strength Indication) computation
when Automatic Gain Control 1 (AGC1) is active.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.27 ZERO_CROSS_TIME Registers
Name
Bit 7
Bit 6
ZERO_CROSS_TIME
Bit 5
Bit 4
Bit 3
Address:
0xFE69 – 0xFE6C
Access:
Read only
Reset:
0x00, …, 0x00;
•
ZERO_CROSS_TIME:
B it 0
@0xFE69
ZERO_CROSS_TIME (11:4)
@0xFE6A
“0000”
“00000000”
ZERO_CROSS_TIME
Bit 1
ZERO_CROSS_TIME(19:12)
ZERO_CROSS_TIME (3:0)
Name:
Bit 2
@0xFE6B
@0xFE6C
Instant in time at which the last zero-cross event took place. It is
expressed in 10µs steps and may take values from 0 to 1e6 (20-bit
effective).
It is set by hardware and is a read-only register.
This register is used by the physical layer for being in accordance with
PRIME specification. It is reserved 32-bit in data memory to be able to
declare as 32-bit variable. The 20-bit register MSB is aligned to the 32-bit
variable MSB, in order to simplify arithmetic calculations with time values.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.28 ZERO_CROSS_CONFIG Register
Name
Bit 7
Bit 6
ZERO_CROSS_CONFIG
Bit 5
--
Name:
ZERO_CROSS_CONFIG
Address:
0xFE6D
Access:
Read/write
Reset:
0x06
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
VEZC
REZC
FEZC
•
--:
Reserved bits
•
VEZC:
Virtual Edge for Zero Crossing
In this bit is equal to one, the hardware calculates the middle point between two VNR
edges to calculate de zero crossing.
This mode is used when the VNR signal duty cycle is different from 50%:
VECZ can be used simultaneously with RECZ or FECZ.
Using the three of them at a time is not recommended.
•
REZC:
Rising Edge for Zero Crossing
If this bit is set to ‘1’, the hardware uses the VNR rising edges to calculate zero-crossing.
FEZC and REZC can be used simultaneously.
•
FEZC:
Falling Edge for Zero Crossing
If this bit is set to ‘1’, the hardware uses the VNR falling edges to calculate zero-crossing.
FEZC and REZC can be used simultaneously.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.29 PSENSECYCLES Registers
Name
Bit 7
PSENSECYCLES
Name:
PSENSECYCLES
Address:
0xFE7D – 0xFE7F
Access:
Read/write
Reset:
0x00, …, 0x00;
•
•
--:
FLAG_SENSE:
Bit 6
Bit 5
--
Bit 4
Bit 3
FLAG_PSENSE
Bit 2
Bit 1
B it 0
D(18:16)
@0xFE7D
D(15:8)
@0xFE7E
D(7:0)
@0xFE7F
Reserved bits
Whenever a new power value is written in PSENSECYCLES, FLAG_PSENSE is
set 1.
This flag must be cleared by software
•
D(17:0):
Power supply consumption measurement
The power supply line is sampled (𝑓𝑐𝑙𝑘 =20MHz), and the number of logic ‘1’
detected during NUMMILIS milliseconds is stored in this field in order to calculate
power consumption.
Note: The first valid value is written after NUMMILIS, and then a new valid value is
written every NUMMILIS milliseconds.
Note: Measurement is only active when a message transmission begins or
PSENSE_SOFT bit is active (see Name:12.1.5.22)
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.30 MEAN Registers
Name
Bit 7
MEAN
Name:
PSENSECYCLES
Address:
0xFE80 – 0xFE82
Access:
Read/write
Reset:
0x00, …, 0x00;
Bit 6
Bit 5
--
Bit 4
Bit 3
FLAG_MEAN
Bit 2
Bit 1
B it 0
D(18:16)
@0xFE80
D(15:8)
@0xFE81
D(7:0)
@0xFE82
•
--:
Reserved bits
•
FLAG_MEAN:
Whenever a new value is written in MEAN, FLAG_MEAN is set to ‘1’
This flag must be cleared by software
•
D(17:0):
This value stores the average power consumption calculated from the value in
PSENSECYCLES and having into account the convergence factor “A” (see
A_NUMMILIS register in 12.1.5.36).
Note: The first valid value is written after NUMCYCLES*NUMMILIS, and then a
new valid value is written every NUMMILIS milliseconds
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12.1.5.31 PMAX Registers
Name
Bit 7
PMAX
Name:
PMAX
Address:
0xFE83 – 0xFE85
Access:
Read/write
Reset:
0x00, …, 0x00;
Bit 6
Bit 5
--
Bit 4
Bit 3
FLAG_PMAX
Bit 2
Bit 1
B it 0
D(18:16)
@0xFE83
D(15:8)
@0xFE84
D(7:0)
@0xFE85
•
--:
Reserved bits
•
FLAG_PMAX:
Whenever a new value is written in PMAX, FLAG_PMAX is set to ‘1’.
This flag must be cleared by software
•
D(17:0):
As described in MAXPOT register (see 12.1.5.34), every time the average power
consumption exceeds a user defined threshold value, the current transmission is
cancelled.
PMAX register stores the average power consumption value that has risen above
MAXPOT threshold.
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12.1.5.32 TRANS_PSENSE Register
Name
Bit 7
TRANS_PSENSE
Name:
TRANS_PSENSE
Address:
0xFE86
Access:
Read/write
Reset:
0x2B
•
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
TRANS_PSENSE(7:0)
TRANS_PSENSE: This register stores the number of 50 µs cycles to wait from the beginning of a
transmission before looking for a possible power failure. This guard time is taken
to avoid transient period where the measurement would be inaccurate
Default value: 0x2B  43 * 50 = 2.15ms
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.33 P_TH Registers
Name
Bit 7
P_TH
P_TH
Address:
0xFE87 – 0xFE89
Access:
Read/write
Reset:
0x07, 0xFF, 0xFF.
--:
P_TH:
Bit 5
Bit 4
Bit 3
--
Name:
•
•
Bit 6
Bit 2
Bit 1
B it 0
P_TH(18:16)
@0xFE87
P_TH(15:8)
@0xFE88
P_TH(7:0)
@0xFE89
Reserved bits
These registers contain a user defined power threshold. When the threshold value is
exceeded, a low power consumption mode is automatically activated. In this low power
consumption mode, the power dissipated in the transistors decreases at the expense of
distortion increasing.
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12.1.5.34 MAXPOT Registers
Name
Bit 7
Bit 6
MAXPOT
MAXPOT
Address:
0xFE8A – 0xFE8C
Access:
Read/write
Reset:
0x07, 0xFF, 0xFF.
--:
MAXPOT:
Bit 4
Bit 3
Bit 2
--
Name:
•
•
Bit 5
Bit 1
B it 0
MAXPOT(18:16)
@0xFE8A
MAXPOT (15:8)
@0xFE8B
MAXPOT (7:0)
@0xFE8C
Reserved bits
These registers contain a user defined power consumption threshold. When this threshold
is exceeded, current transmission is cancelled.
When the threshold is exceeded, two flags are activated:
•
POTFAILURE flag (see VSENSE_CONFIG in 12.1.5.22). This flag indicates
that a power failure has occurred.
•
FLAG_PMAX flag (see PMAX in 12.1.5.31). This flag indicates that, after a
power failure, the last mean power value measured has been stored in PMAX
register.
To reset both flags is enough to reset either of them, the other will be automatically reset.
This will enable to start new transmissions.
Atmel SAM4SP32A [PRELIMINARY datasheet]
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12.1.5.35 NUMCYCLES Register
Name
NUMCYCLES
Name:
NUMCYCLES
Address:
0xFE8D
Access:
Read/write
Reset:
0x05
•
NUMCYCLES:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
NUMCYCLES(7:0)
Number of cycles of measuring power before obtaining a mean value that can be
taken as valid.
Example1: If NUMCYCLES=5(cycles) and NUMMILIS=1(milliseconds), 5 power
measurements will be taken during 1 millisecond each one .The first valid power
measurement value will be output in the fifth millisecond.
Example2: If NUMCYCLES=3(cycles) and NUMMILIS=20(milliseconds), 3 power
measurements will be taken during 20 milliseconds each one. The first valid
power measurement value will be output after 60 milliseconds.
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12.1.5.36 A_NUMMILIS Register
Name
Bit 7
NUMMILIS
--
Name:
A_NUMMILIS
Address:
0xFE8E
Access:
Read/write
Reset:
0x21
Bit 6
Bit 5
A(1:0)
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
NUMMILIS(4:0)
•
--:
Reserved bits
•
A(1:0):
Convergence Factor
Averaging factor that sets the convergence speed of the mean calculation
algorithm.
A=00 sets quicker convergence, while A=11 sets the slowest one. A=01,10 are
intermediate values.
Note: Power supply presents high dispersion values, so NUMMILIS value must be
take into account in order to select a suitable value for A. If NUMMILIS is high, the
mean value can be calculated slowly, because the averaging in being calculated
over a long period of time. When NUMMILIS is low, the mean value must be
calculated quickly in order to obtain more accurate values.
•
NUMMILIS(4:0):
Measurement acquisition time in milliseconds
Stores the measurement acquisition time in milliseconds.
Example1: If NUMCYCLES=5(cycles) and NUMMILIS=1(milliseconds), 5 power
measurements will be taken during 1 millisecond each one .The first valid power
measurement value will be output in the fifth millisecond.
Example2: If NUMCYCLES=3(cycles) and NUMMILIS=20(milliseconds), 3 power
measurements will be taken during 20 milliseconds each one. The first valid
power measurement value will be output after 60 milliseconds.
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12.1.5.37 EMIT_CONFIG Register
Name
Bit 7
Bit 6
EMIT_CONFIG
Name:
EMIT_CONFIG
Address:
0xFE8F
Access:
Read/write
Reset:
0x03
•
TR_EMIT:
Bit 5
Bit 4
Bit 3
Bit 2
--
Bit 1
B it 0
TR_EMIT
TWO_H_BRIDGES
Emission mode
This bit selects the emission mode (Internal Drive or External transistors bridge).
• ‘0’: Emission is done by means of internal SAM4SP32A driver.
• ‘1’: Emission is done by means of external transistors (Default).
•
TWO_H_BRIDGES: This bit selects the number of semi-H-bridges in the external interface.
• ‘0’: There is only one semi-H-bridge in the external interface.
• ‘1’: There are two semi-H-bridges in the external interface and the field HIMP
(AFE_CTL register) determines which one is active (Default).
Semi-H-Bridges must be connected following the table below
TWO_H_BRIDGES=’0’
TWO_H_BRIDGES=’1’
EMIT1
P
N1
EMIT2
P
N1
EMIT3
P
N1
EMIT4
N
P2
EMIT5
N
P2
EMIT6
N
P2
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12.1.5.38 AFE_CTL Register
Name
Bit 7
AFE_CTL
Name:
AFE_CTL
Address:
0xFE90
Access:
Read/write
Reset:
0x10
Bit 6
Bit 5
--
Bit 4
HIMP
Bit 3
HIMP_INV
Bit 2
TXRX
•
--:
Reserved bits
•
HIMP:
Analog Front End Impedance control bit-
Bit 1
B it 0
TXRX_HARD
TXRX_INV
This bit selects which branch is active when working with a two half-H-bridge
branches analog front end.
• ‘0’: “Low impedance” half-H-bridge is active (P2-N2).
• ‘1’: “High impedance” half-H-bridge is active (P1-N1).
•
•
HIMP_INV:
TXRX:
HIMP pin polarity control
This field inverts the polarity of the HIMP pin output.
Note: This field only affect to the polarity of the external pin HIMP output, the
value taken from HIMP bit (AFE_CTL(4)) remains unchanged
The value stored in this bit is taken by the microcontroller in order to set the TXRX
pin level.
• ‘0’: TXRX pin output = ‘0’.
• ‘1’: TXRX pin output = ‘1’.
•
TXRX_HARD:
TXRX pin control
This field selects if the TXRX pin is software/hardware controlled.
• ‘0’: TXRX pin is software controlled. TXRX value is set by TXRX bit field
(AFE_CTL(2)).
• ‘1’: TXRX pin is hardware controlled.
•
TXRX_INV:
TXRX pin polarity control
This field inverts the polarity of the TXRX pin output
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12.1.5.39 R Registers
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
B it 0
R1
R1(7:0)
0xFE9F
R2
R2(7:0)
0xFEA0
R3
R3(7:0)
0xFEA1
R4
R4(7:0)
0xFEA2
R5
R5(7:0)
0xFEA3
R6
R6(7:0)
0xFEA4
R7
R7(7:0)
0xFEA5
R8
R8(7:0)
0xFEA6
Name:
R1 – R8
Address:
0xFE9F – 0xFEA6
Access:
Read/write
Reset:
0x60; 0x60; 0x60; 0x60; 0xFF; 0xFF; 0xFF; 0xFF.
•
Bit 3
R:
The value in these registers strongly depends on the external circuit configuration.
Atmel provides values to be used according with the design recommended in SAM4SP32A
kits
Please contact Atmel Power Line if different external configurations are going to be used
Recommended values (according to the configuration recommended in SAM4SP32A kits)
R1(7:0): 0x21
R2(7:0): 0x20
R3(7:0): 0x12
R4(7:0): 0x02
R5(7:0): 0x37
R6(7:0): 0x77
R7(7:0): 0x37
R8(7:0): 0x77
Order of precedence: In the event of a conflict between the Ri(7:0) values above and Ri(7:0)
values specified in the latest documentation in an SAM4SP32A kit, the values in the kit
documentation shall take precedence.
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12.1.5.40 PHY_ERRORS Registers
Name
Bit 7
PHY_ERRORS
Name:
PHY_ERRORS
Address:
0xFE94
Access:
Read/write
Reset:
0x00
Bit 6
Bit 5
Bit 4
--
Bit 3
Bit 2
Bit 1
B it 0
PHY_ERRORS(4:0)
•
--:
Reserved bits
•
PHY_ERRORS:
Physical Layer Error Counter
The system stores in these bits the number of times that a Physical layer error has
occurred. Microcontroller can clear this counter to zero.
The value stored in this register is cleared every time the register is read.
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12.1.5.41 FFT_MODE Registers
Name
Bit 7
FFT_MODE
Name:
FFT_MODE
Address:
0xFEB0
Access:
Read/write
Reset:
0x00
•
NSYM:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NSYM(5:0)
Bit 1
B it 0
CONTINUOUS
TEST_MODE_EN
Number of symbols to transmit
When in continuous transmission mode, symbol data acts as a free-running buffer,
increasing from 0 to NSYM-1 and overflowing back to symbol 0.
•
CONTINUOUS:
This field enables/disables continuous transmission mode.
• ‘0’: Continuous transmission mode disabled.
• ‘1’: Continuous transmission mode enabled.
•
TEST_MODE_EN: This field enables/disables test mode
• ‘0’: Test mode disabled.
• ‘1’: Test mode enabled.
Configuration for test mode. This register is used by the physical layer to fulfill
with
PRIME
specification
(PLME_TESTMODE.request
primitive
and
PLME_TESTMODE.confirm primitive, see PRIME specification). In this mode data
provided to FFT is written in data memory at ADDR_PHY_INI_TX, codifying each
value with 4 bits according to DPSK modulation mapping. The msb of the value is to
indicate an input of zero when set to '1'. Each byte in data memory contains 2 input
values for FFT, with the first value located at high bits. There are 97 input values for
FFT, so many as the number of subcarriers, so there are 48 bytes and a half of the
next byte used for codifying them. The other half of this byte (low bits) will be used
for the next symbol data.
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12.1.5.42 AGC_CONFIG Register
Name
Bit 7
AGC_CONFIG
Bit 6
Bit 5
--
Name:
AGC_CONFIG
Address:
0xFEB1
Access:
Read/write
Reset:
0x24
AGC0_POL
Bit 4
AGC0_VALUE
Bit 3
AGC0_MODE
Bit 2
AGC1_POL
Bit 1
B it 0
AGC1_VALUE
AGC1_MODE
SAM4SP32A has implemented two Automatic Gain Control outputs in order to adjust the received signal level to a
suitable range. When in “automatic” mode, both of them are set to ‘1’ when the received signal is above 16-bit-userdefinable thresholds (AGC1_TH and AGC0_TH) in order to activate external attenuators placed in the external analog
front end.
The value of these outputs is set during the beginning of a received message and is hold until the end of the message.
AGC0 and AGC1 follow different algorithms, thus using both of them ensures more accurate gain control
•
--:
Reserved bits
•
AGC0_POL:
AGC0 polarity
This bit sets the polarity of the AGC0 output.
• ‘0’: Polarity is inverted.
• ‘1’: Polarity is not inverted (default).
•
AGC0_VALUE:
AGC0 output valueThis bit stores the value wrote by the user to be the AGC0 output.
This bit is only taken into account when AGC0 “forced” mode is active
(AGC0_MODE=’1’).
AGC0_POL field can invert this value.
•
AGC0_MODE:
AGC0 mode
This bit selects which AGC0 mode is being used
•
‘0’: “Automatic” Mode. AGC0 output will be managed by the MAC, depending on
saturation detected in received signal. If saturation is detected, AGC0 output
will be ‘1’. Else, AGC0 output will be ‘0’. AGC0_POL field can invert this value.
(See SAT_TH registers in 12.1.5.43)
•
•
AGC1_POL:
‘1’: “Forced” Mode. AGC0 output will be managed by the user, according to the
value wrote in AGC0_VALUE field (AGC_CONFIG(4)).
AGC1 polarity
This bit sets the polarity of the AGC1 output.
• ‘0’: Polarity is inverted.
• ‘1’: Polarity is not inverted (default).
•
AGC1_VALUE:
AGC1 output valueThis bit stores the value wrote by the user to be the AGC1 output.
This bit is only taken into account when AGC1 “forced” mode is active
(AGC1_MODE=’1’).
AGC1_POL field can invert this value.
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•
AGC1_MODE:
AGC1 mode
This bit selects which AGC1 mode is being used
•
‘0’: “Automatic” Mode. AGC1 output will be managed by the MAC, depending on
saturation detected in received signal. If saturation is detected, AGC1 output
will be ‘1’. Else, AGC1 output will be ‘0’. AGC1_POL field can invert this value.
(See SAT_TH registers in 12.1.5.43)
•
‘1’: “Forced” Mode. AGC1 output will be managed by the user, according to the
value wrote in AGC1_VALUE field (AGC_CONFIG(4)).
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12.1.5.43 SAT_TH Registers
Name
Bit 7
SAT_TH
Name:
SAT_TH
Address:
0xFEB7 – 0xFEB8
Access:
Read/write
Reset:
0x40; 0x00
•
SAT_TH:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
SAT_TH(15:8)
@0xFEB7
SAT_TH(7:0)
@0xFEB8
These registers store a threshold for the PLC input-signal amplitude.
If this threshold is exceeded, AGC thresholds (AGC0_TH and AGC1_TH) will be taken into
account.
If this threshold is not exceeded, AGC0_TH and AGC1_TH thresholds will be ignored, thus
the AGC algorithm will be never triggered.
Recommended value for Atmel reference design = 0x37AA.
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12.1.5.44 AGC1_TH Registers
Name
Bit 7
Bit 6
AGC1_TH
Name:
AGC1_TH
Address:
0xFE5F – 0xFE60
Access:
Read/write
Reset:
0x40; 0x00
•
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
AGC1_TH(15:8)
@0xFE5F
AGC1_TH(7:0)
@0xFE60
AGC1_TH: AGC1 Threshold
These registers store the 16-bit upper threshold used by the AGC1 algorithm to determine
that the input signal must be attenuated.
This threshold is only taken
(AGC_CONFIG.AGC1_MODE=’0’).
into
account
in
AGC1
“automatic”
mode
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This threshold is only taken into account if SAT_TH value is exceeded.
Recommended value for Atmel reference design = 0x4A00.
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12.1.5.45 AGC0_TH Registers
Name
Bit 7
Bit 6
AGC0_TH
Name:
AGC0_TH
Address:
0xFEB2 – 0xFEB3
Access:
Read/write
Reset:
0x10; 0x00
•
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
AGC0_TH(15:8)
@0xFEB2
AGC0_TH(7:0)
@0xFEB3
AGC0_TH: AGC0 Threshold
These registers store the 16-bit upper threshold used by the AGC0 algorithm to determine
that the input signal must be attenuated.
This threshold is only taken
(AGC_CONFIG.AGC0_MODE=’0’).
into
account
in
AGC0
“automatic”
mode
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This threshold is only taken into account if SAT_TH value is exceeded.
Recommended value for Atmel reference design = 0x1000.
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12.1.5.46 AGC_PADS Register
Name
Bit 7
Bit 6
Bit 5
AGC_PADS
Name:
AGC_PADS
Address:
0xFE61
Access:
Read/write
Reset:
0x00
Bit 4
Bit 3
Bit 2
--
Bit 1
B it 0
P46_MODE
SWITCH_AGC
•
--:
Reserved bits
•
P46_MODE:
This field controls the P4.6/T2/AGC1 output pin (pin no.94).
• ‘0’: Pin no.94 works as P4.6/T2 output pin.
• ‘1’: Pin no.94 works as AGC1 output pin.
•
SWITCH_AGC:
This bit switches the AGC0 and AGC1 outputs.
• ‘0’: Not switched AGC outputs.
• ‘1’: Switched AGC outputs.
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12.2
SAM4SP32A MAC Layer
The SAM4SP32A hardware MAC layer consists of a hardware implementation of some functionalities of the MAC
Layer Entity specified in PRIME specification. These features are CRC calculation and AES128 block.
Figure 12-9. SAM4SP32A Software Stack Diagram
Control and Data Plane
Management Plane
Convergence Layer (CL)
MAC-SAP Software stack provided by Atmel
MLME-SAP
MAC Layer
Management Entity
Media Access Control (MAC) Layer
AES
CRC
PHY-SAP
PLME-SAP
Physical (PHY) Layer
PHY Layer
Management Entity
Hardware
Atmel PRIME stack implements by software the rest of the MAC layer requirements and capabilities. Furthermore, the
software package allows the communication with the Management Plane by means of the two Access points
described by PRIME (PHY Layer Management Entity SAP and MAC Layer Management Entity SAP) and the interface
to communicate MAC layer with the upper layer (Convergence Layer).
Please check the “Atmel PRIME Stack User Manual” for software package detailed description and functionality.
12.2.1 Cyclic Redundancy Check (CRC)
There are three types of MAC PDUs (generic, promotion and beacon) for different purposes, and each one has its
own specific CRC. In SAM4SP32A there is a hardware implementation of every CRC type calculated by the MAC
layer. This CRC hardware-calculation is enabled by default. Note that the CRC included at the physical layer is also a
hardware implementation available in SAM4SP32A and it is also enabled by default.
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Figure 12-10. Generic MAC PDU format and generic MAC header detail
Generic MAC header
Packet n
Packet 1
CRC
MSB
Unused
Reserved
Reserved
HDR.HT
HDR.DO
HDR.LEVEL
HDR.HCS
LSB
In transmission all CRC bytes are real-time calculated and the last bytes of the MAC PDU are overwritten with these
values, (provided that the field HT in the first byte of the MAC header in transmission data is equal to the
corresponding MAC PDU type).
In reception the CRC bytes are also real-time calculated and these bytes are checked with the last bytes of the MAC
PDU. If the CRC is not correct, then an error flag is activated, the complete frame is discarded, and the corresponding
error counter is increased. These counters allow the MAC layer to take decisions according to error ratio.
For the Generic MAC PDU, there is an 8-bit CRC in the Generic MAC header, which corresponds to PRIME
HDR.HCS. In reception if this CRC doesn’t check successfully, the current frame is discarded and no interruption is
generated.
This works in the same way as CRC for the PHY layer (CRC Ctrl, located in the PHY header, see PRIME specification
for further information).
There is another CRC for the Generic MAC PDU which is the last field of the GPDU. It is 32 bits long and it is used to
detect transmission errors. The CRC shall cover the concatenation of the SNA with the GPDU except for the CRC field
itself. In reception, if the CRC is not successful then an internal flag is set and the error counter is increased.
For the Promotion Needed PDU there is an 8-bit CRC, calculated with the first 13 bytes of the header. In reception, if
this CRC is not correct, then an internal flag is set and the corresponding error counter is increased.
For the Beacon PDU there is a 32-bit CRC calculated with the same algorithm as the one defined for the CRC of the
Generic MAC PDU. This CRC shall be calculated over the complete BPDU except for the CRC field itself. In reception,
if this CRC is not successful, then an internal flag is set and the same error counter as for GPDU is increased. The
hardware used for this CRC is the same as the one used for GPDU.
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12.2.2 Advanced Encryption Standard (AES)
One of the security functionalities in PRIME is the 128-bit AES encryption of data
SAM4SP32A includes a hardware implementation of this block, and it is used by the
transmission/reception. It is possible to use this block externally as a peripheral unit,
registers designed to control it. Therefore there are some configurable parameters and
block.
and its associated CRC.
physical layer in real-time
by accessing the specific
input/output buffers to the
Figure 12-11. PHY Layer transmitter block diagram
(…)
AES Block
CRC
Convolutional
Encoder
Scrambler
Interleaver
Sub-carrier
Modulator
IFFT
(…)
Cyclix Prefix
There are two basic operation ways in SAM4SP32A when using PRIME Security Profile 1. The first one is real-time
encryption and the second one is independent encryption from the PHY layer.
Real-Time Encryption: the AES128 core is integrated in the physical chain, and data is encrypted and decrypted in
real-time when needed. In transmission, data is transferred to the emission buffer by means of the DMA TX channel.
Then the 128 bits located in the buffer are encrypted before starting transmission (Note that Beacon PDU, Promotion
PDU and Generic MAC header, as well as several control packets, are not encrypted). Data is extracted when
required from this buffer until it is empty, and then a new DMA transfer is requested to fill the 16 bytes and a new
encryption is executed. The key used for encryption must be set at the corresponding register, and it can vary from a
packet to another.
In reception, data is obtained from the PHY layer and it is passed to the AES128 block. When the reception buffer is
full with incoming data, the 128 bits are decrypted and transferred to external memory through DMA RX channel. Then
the reception buffer is available again to fill with processed data.
The header is always real-time analyzed in order to know if encryption process must be applied.
Independent Encryption: the AES128 core is used as a peripheral unit, accessible with several registers mapped in
external memory. In this mode, when in transmission, data must be encrypted previously to the use of the
PHY_DATA.request primitive (see PRIME specification), in an independent way. In reception, data passed by the PHY
layer is already encrypted and must be decrypted in a subsequent process.
When working with AES block as a peripheral unit, automatic CRC calculation by hardware is disabled.
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12.2.3 MAC Layer Registers
12.2.3.1 SNA Registers
Name
Bit 7
Bit 6
SNA
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
SNA(47:40)
@FE62
…
…
SNA(7: 0)
Name:
SNA
Address:
0xFE62 – 0xFE67
Access:
Read/write
Reset:
0x00, …, 0x00
•
SNA:
@FE67
Sub Network Address
These registers store the 48-bit Sub Network Address. When the system Sub Network
Address is available, the SAM4SP32A microcontroller must write it down so the Phy layer
will be able to correctly calculate the CRC’s, which depend on this parameter.
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12.2.3.2 VITERBI_BER_HARD Register
Name
Bit 7
VITERBI_BER_HARD
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
VITERBI_BER_HARD(7:0)
Name:
VITERBI_BER_HARD
Address:
0xFE36
Access:
Read only
Reset:
0x00
VITERBI_BER_HARD:
This register stores the number of errors accumulated in a message
reception using Viterbi hard* decision. The value is cleared by hardware
each time a new message is received.
*Hard Decision: in “hard” detection there are only two decision levels. If the
received value is different than the corrected one, the error value taken is
“1”. Otherwise, the error value taken is “0”.
Figure 12-12.
Viterbi Hard detection decision levels
Strong ‘1’
Decision levels
•
Bit 6
1
‘1’
Weak ‘1’
Weak ‘0’
‘0’
0
Strong ‘0’
From the value in VITERBI_BER_HARD register it is possible to calculate de Bit Error Rate
according to the following formula:
BER=
𝑉𝑇𝐵_𝐵𝐸𝑅_𝐻𝐴𝑅𝐷
40
10
100
−1
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12.2.3.3 VITERBI_BER_SOFT Register
Name:
VITERBI_BER_SOFT
Address:
0xFE37
Access:
Read only
Reset:
0x00
•
VITERBI_BER_SOFT:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
VITERBI_BER_SOFT(7:0)
This register stores a value proportional to the number of errors
accumulated in a message reception using Viterbi soft* decision. The
value is cleared by hardware each time a new message is received.
*Soft Decision: in “soft” decision there are fifteen decision levels. A strong
‘0’ is represented by a value of “0”, while a strong ‘1’ is represented by a
value of “15”. The rest of values are intermediate, so “7” is used to
represent a weak ‘0’ and “8” represents a weak ‘1’. Soft decision
calculates the error in one bit received as the distance in decision levels
between the value received (a value in the range 0 to 15) and the
corrected one (0 or 15).
Figure 12-13.
Viterbi Hard detection decision levels
15
Strong ‘1’
...
VITERBI_BER_SOFT
Bit 6
8
7
‘1’
Weak ‘1’
Weak ‘0’
‘0’
...
Bit 7
Decision levels
Name
0
Strong ‘0’
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12.2.3.4 ERR_CRC32_MAC Registers
Name
Bit 7
ERR_CRC32_MAC
Name:
ERR_CRC32_MAC
Address:
0xFEBA – 0xFEBB
Access:
Read/write
Reset:
0x00, 0x00
•
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
ERR_CRC32_MAC(15:8)
@0xFEBA
ERR_CRC32_MAC(7:0)
@0xFEBB
ERR_CRC32_MAC: 16-bit value that stores the number of received messages that have been
discarded by an error in the MAC layer CRC32.
Note: to clear this value, these registers must be reset by the SAM4SP32A
microcontroller.
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12.2.3.5 ERR_CRC8_MAC Registers
Name
Bit 7
ERR_CRC8_MAC
Name:
ERR_CRC8_MAC
Address:
0xFEBC – 0xFEBD
Access:
Read/write
Reset:
0x00, 0x00
•
ERR_CRC8_MAC:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
ERR_CRC8_MAC(15:8)
@0xFEBC
ERR_CRC8_MAC(7:0)
@0xFEBD
16-bit value that stores the number of received messages that have been
discarded by an error in the payload MAC layer CRC8.
Note: to clear this value, these registers must be reset by the SAM4SP32A
microcontroller.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
122
12.2.3.6 ERR_CRC8_AES Registers
Name
Bit 7
ERR_CRC8_AES
Name:
ERR_CRC8_AES
Address:
0xFEBE – 0xFEBF
Access:
Read/write
Reset:
0x00, 0x00
•
ERR_CRC8_AES:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
ERR_CRC8_AES(15:8)
@0xFEBE
ERR_CRC8_AES(7:0)
@0xFEBF
16-bit value that stores the number of received messages that have been
discarded by an error in the payload AES CRC8.
Note: to clear this value, these registers must be reset by the SAM4SP32A
microcontroller.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
123
12.2.3.7 ERR_CRC8_MAC_HD Registers
Name
Bit 7
ERR_CRC8_MAC_HD
Name:
ERR_CRC8_MAC_HD
Address:
0xFEC0 – 0xFEC1
Access:
Read/write
Reset:
0x00, 0x00
•
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
ERR_CRC8_MAC_HD(15:8)
@0xFEC0
ERR_CRC8_MAC_HD(7:0)
@0xFEC1
ERR_CRC8_MAC_HD:16-bit value that stores the number of received messages that have been
discarded by an error in the header MAC layer.
Note: to clear this value, these registers must be reset by the SAM4SP32A
microcontroller.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
124
12.2.3.8 ERR_CRC8_PHY Registers
Name
Bit 7
ERR_CRC8_PHY
Name:
ERR_CRC8_AES
Address:
0xFEC2 – 0xFEC3
Access:
Read/write
Reset:
0x00, 0x00
•
ERR_CRC8_PHY:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
ERR_CRC8_PHY(15:8)
@0xFEC2
ERR_CRC8_PHY(7:0)
@0xFEC3
16-bit value that stores the number of received messages that have been
discarded by an error in the PHY layer CRC8.
Note: to clear this value, these registers must be reset by the SAM4SP32A
microcontroller.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
125
12.2.3.9 FALSE_DET_CONFIG Register
Name
Bit
7
FALSE_DET
_CONFIG
Bit
6
--
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
ERR_CRC8
_MAC
INVALID
_PROTOCOL
ERROR
_LEN
ERROR_PAD
_LEN
UNKNOWN
_PDU
UNKNOWN
_SP
Name:
FALSE_DET_CONFIG
Address:
0xFEC4
Access:
Read/write
Reset:
0x10
•
•
•
•
•
--:
Reserved bits
ERR_CRC8_MAC: If this bit is set to 1, FALSE_DET registers will increase its error counter if a
received message has a correct PHY layer CRC8 but the MAC layer CRC8
present in its header is wrong.
INVALID_PROTOCOL:
If this bit is set to 1, FALSE_DET registers will increase its error counter if a
received message has a correct PHY layer CRC8 but the PROTOCOL field
indicates a modulation not supported by the system.
ERROR_LEN:
If this bit is set to 1, FALSE_DET registers will increase its error counter if a
received message has a correct PHY layer CRC8 but the LEN field indicates a not
valid message length.
ERROR_PAD_LEN:If this bit is set to 1, FALSE_DET registers will increase its error counter if a
received message has a correct PHY layer CRC8 but the PAD_LEN field
indicates a not valid message padding length.
•
UNKNOWN_PDU: If this bit is set to 1, FALSE_DET registers will increase its error counter if a
received message has a correct PHY layer CRC8 but the HT field indicates a
header type different from BEACON, PROMOTION or GENERIC.
•
UNKNOWN_SP:
If this bit is set to 1, FALSE_DET registers will increase its error counter if a
received
message
has
a
correct
PHY
layer
CRC8
but
the
SECURITY_PROTOCOL field is wrong.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
126
12.2.3.10 FALSE_DET Registers
Name
Bit 7
FALSE_DET
Name:
FALSE_DET
Address:
0xFEC5 – 0xFEC6
Access:
Read/write
Reset:
0x00, 0x00
•
FALSE_DET:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
FALSE_DET(15:8)
@0xFEC5
FALSE_DET(7:0)
@0xFEC6
Erroneous non-discarded messages.
16-bit value that stores the number of received messages that have not been
discarded since its PHY layer CRC8 is correct, but in which there are other incorrect
fields. The fields that shall be taken into account to increase the counter in case
they were wrong can be selected by FALSE_DET_CONFIG register.
Note: to clear this value, these registers must be reset by the SAM4SP32A
microcontroller
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
127
12.2.3.11 MAX_LEN_DBPSK Register
Name
Bit 7
MAX_LEN_DBPSK
Bit 6
--
Name:
MAX_LEN_DBPSK
Address:
0xFEC8
Access:
Read/write
Reset:
0xFF
•
•
--:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
MAX_LEN_DBPSK(5:0)
Reserved bits
MAX_LEN_DBPSK:This register sets the maximum length, measured in OFDM symbols, that the
system allows to receive when working with DBPSK modulation and no Viterbi
encoding.
If a message in such modulation/encoding is received and its LEN field indicates
a length above the threshold defined by MAX_LEN_DBPSK value, the message
will be discarded.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
128
12.2.3.12 MAX_LEN_DBPSK_VTB Register
Name
MAX_LEN_DBPSK_VTB
Bit 7
Bit 6
Bit 5
--
Name:
MAX_LEN_DBPSK_VTB
Address:
0xFEC9
Access:
Read/write
Reset:
0xFF
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
MAX_LEN_DBPSK_VTB(5:0)
•
--:
Reserved bits
•
MAX_LEN_DBPSK_VTB:
This register sets the maximum length, measured in OFDM symbols that
the system allows to receive when working with DBPSK modulation and
Viterbi encoding.
If a message in such modulation/encoding is received and its LEN field
indicates
a
length
above
the
threshold
defined
by
MAX_LEN_DBPSK_VTB value, the message will be discarded.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
129
12.2.3.13 MAX_LEN_DQPSK Register
Name
Bit 7
MAX_LEN_DQPSK
Bit 6
--
Name:
MAX_LEN_DQPSK
Address:
0xFECA
Access:
Read/write
Reset:
0xFF
•
•
--:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
MAX_LEN_DQPSK(5:0)
Reserved bits
MAX_LEN_DBPSK:This register sets the maximum length, measured in OFDM symbols, that the
system allows to receive when working with DQPSK modulation and no Viterbi
encoding.
If a message in such modulation/encoding is received and its LEN field indicates
a length above the threshold defined by MAX_LEN_DQPSK value, the message
will be discarded.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
130
12.2.3.14 MAX_LEN_DQPSK_VTB Registers
Name
MAX_LEN_DQPSK_VTB
Bit 7
Bit 6
--
Name:
MAX_LEN_DQPSK_VTB
Address:
0xFECB
Access:
Read/write
Reset:
0xFF
•
•
--:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
MAX_LEN_DQPSK_VTB(5:0)
Reserved bits
MAX_LEN_DQPSK_VTB: This register sets the maximum length, measured in OFDM symbols that
the system allows to receive when working with DQPSK modulation and
Viterbi encoding.
If a message in such modulation/encoding is received and its LEN field
indicates
a
length
above
the
threshold
defined
by
MAX_LEN_DQPSK_VTB value, the message will be discarded.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
131
12.2.3.15 MAX_LEN_D8PSK Registers
Name
Bit 7
MAX_LEN_D8PSK
Bit 6
--
Name:
MAX_LEN_D8PSK
Address:
0xFECC
Access:
Read/write
Reset:
0xFF
•
•
--:
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
MAX_LEN_D8PSK(5:0)
Reserved bits
MAX_LEN_D8PSK:This register sets the maximum length, measured in OFDM symbols, that the
system allows to receive when working with D8PSK modulation and no Viterbi
encoding.
If a message in such modulation/encoding is received and its LEN field indicates
a length above the threshold defined by MAX_LEN_D8PSK value, the message
will be discarded.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
132
12.2.3.16 MAX_LEN_D8PSK_VTB Register
Name
MAX_LEN_D8PSK_VTB
Bit 7
Bit 6
--
Name:
MAX_LEN_D8PSK_VTB
Address:
0xFECD
Access:
Read/write
Reset:
0xFF
•
•
Bit 5
--:
MAX_LEN_D8PSK_VTB:
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
MAX_LEN_D8PSK_VTB(5:0)
Reserved bits
This register sets the maximum length, measured in OFDM symbols that
the system allows to receive when working with D8PSK modulation and
Viterbi encoding.
If a message in such modulation/encoding is received and its LEN field
indicates
a
length
above
the
threshold
defined
by
MAX_LEN_D8PSK_VTB value, the message will be discarded.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
133
12.2.3.17 AES_PAD_LEN Register
Name
Bit 7
AES_PAD_LEN
Name:
AES_PAD_LEN
Address:
0xFE25
Access:
Read/write
Reset:
0x00
•
•
--:
AES_PAD_LEN:
Bit 6
Bit 5
--
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
AES_PAD_LEN(3:0)
Reserved bits
AES protocol works over 16-bytes-lenght blocks. When a block is not 16-bytes
long, this register indicates the number of padding bytes to append.
This register takes values between 0 and 15.
In transmission, if encryption is being used, microcontroller must write the AES
padding length in this register.
In no-encrypted transmission and in reception, the value in this register is not
used.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
134
12.2.3.18 AES_DATA_IN Registers
Name
Bit 7
AES_DATA_IN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
AES_DATA_IN(127:120)
@FFA0
…
…
AES_DATA_IN(7: 0)
Name:
AES_DATA_IN
Address:
0xFFA0 – 0xFFAF
Access:
Read/write
Reset:
0x00, …, 0x00
•
AES_DATA_IN:
@FFAF
Input buffer for AES128 block.
This buffer can be written to be encrypted/decrypted by the key in KEY_PERIPH
(see 12.2.3.20) register.
The resulting data could be read at AES_DATA_OUT (see 12.2.3.19) registers.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
135
12.2.3.19 AES_DATA_OUT Registers
Name
Bit 7
AES_DATA_OUT
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
AES_DATA_OUT(127:120)
@FFB0
…
…
AES_DATA_OUT(7: 0)
Name:
AES_DATA_OUT
Address:
0xFFB0 – 0xFFBF
Access:
Read only
Reset:
0x00, …, 0x00
•
@FFBF
AES_DATA_OUT: Output buffer for AES128 block.
This buffer stores the result of the encryption/decryption processing of data in
AES_DATA_IN (see 12.2.3.18) register with the key in KEY_PERIPH (see
12.2.3.20) register.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
136
12.2.3.20 KEY_PERIPH Registers
Name
Bit 7
Bit 6
Bit 5
KEY_PERIPH
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
KEY_PERIPH(127:120)
@FFC0
…
…
KEY_PERIPH (7: 0)
@FFCF
Name:
KEY_PERIPH
Address:
0xFFC0 – 0xFFCF
Access:
Read/write
Reset:
KEY_PERIPH(127:120) :
0x00;
KEY_PERIPH(119:112) : 0x01;
KEY_PERIPH(111:104) : 0x02;
KEY_PERIPH(103:96) :
0x03;
KEY_PERIPH(95:88) :
0x04;
KEY_PERIPH(87:80) :
0x05;
KEY_PERIPH(79:72) :
0x06;
KEY_PERIPH(71:64) :
0x07;
KEY_PERIPH(63:56) :
0x08;
KEY_PERIPH(55:48) :
0x09;
KEY_PERIPH(47:40) :
0x0A;
KEY_PERIPH(39:32) :
0x0B;
KEY_PERIPH(31:24) :
0x0C;
KEY_PERIPH(23:16) :
0x0D;
KEY_PERIPH(15:8) :
0x0E;
KEY_PERIPH(7:0) :
0x0F;
•
KEY_PERIPH:
Key for AES128 block when used as peripheral part.
This key is used for encrypting/decrypting data in AES_DATA_IN registers.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
137
12.2.3.21 KEY_PHY Registers
Name
Bit 7
Bit 6
Bit 5
KEY_PHY
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
KEY_PHY(127:120)
@FFD0
…
…
KEY_PHY(7: 0)
@FFDF
Name:
KEY_PHY
Address:
0xFFD0 – 0xFFDF
Access:
Read/write
Reset:
KEY_PHY(127:120): 0x00;
KEY_PHY(119:112) :
0x01;
KEY_PHY(111:104) :
0x02;
KEY_PHY(103:96) :
0x03;
KEY_PHY(95:88) :
0x04;
KEY_PHY(87:80) :
0x05;
KEY_PHY(79:72) :
0x06;
KEY_PHY(71:64) :
0x07;
KEY_PHY(63:56) :
0x08;
KEY_PHY(55:48) :
0x09;
KEY_PHY(47:40) :
0x0A;
KEY_PHY(39:32) :
0x0B;
KEY_PHY(31:24) :
0x0C;
KEY_PHY(23:16) :
0x0D;
KEY_PHY(15:8) :
0x0E;
KEY_PHY(7:0) :
0x0F;
•
KEY_PHY: Key for AES128 block when used by the physical layer
This key is used in real time encryption/decryption for Security Profile 1. When any of the
DMA channels of the physical layer accesses to the memory, then this key and the input
data are multiplexed to the AES128-core. Also output data is multiplexed in order to
provide encrypted/decrypted data to the physical buffer.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
138
12.2.3.22 AES_SFR Register
Name
Bit 7
Bit 6
AES_SFR
Name:
AES_SFR
Address:
0xFFE0
Access:
Read/write
Reset:
0x00
Bit 5
Bit 4
--
Bit 3
Bit 2
Bit 1
B it 0
READY
START
CIPHER
•
--:
Reserved bits.
•
READY:
Flag to indicate encryption/decryption process completion.
When the encryption/decryption has been completed, this flag is set to ‘1’.
This flag is automatically cleared when an encryption/decryption process begins.
•
START:
When this bit is set to ‘1’, the encryption/decryption process is triggered.
If encryption/decryption starts successfully, then this bit is automatically cleared to ‘0’.
•
CIPHER:
This field indicates if data must be encrypted or decrypted.
•
‘0’ - Decryption mode
•
‘1’ - Encryption mode
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
139
13.
Electrical Characteristics
13.1
Absolute Maximum Ratings
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions given in the Recommended Operating Conditions section. Exposure to the Absolute
Maximum Conditions for extended periods may affect device reliability.
Table 13-1. SAM4SP32A Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Operating Temperature (Industrial)
OT
-40 to +85
ºC
Storage Temperature
TST
-55 to 125
ºC
--
-0.3 to +4.0
V
Maximum Operating Voltage
(VDDCORE)
VDDCORE
max
1.32
V
Maximum Operating Voltage
(VDDIO)
VDDIO
max
4.0
V
Junction Temperature
TJ
-40 to 125
ºC
Total DC Output Current
On all I/O lines
IO
300
mA
Voltage on Input Pins
With Respect to Ground
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
140
13.2
DC Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40oC to +85oC, unless otherwise
specified.
Table 13-2.
Symbol
SAM4SP32A DC Characteristics
Parameter
Conditions
Min
Typ
Max
1.08
1.20
1.32
3.00
3.30
3.60
VVDDCORE
DC Supply Core
VVDDIO
DC Supply I/Os
VVDDPLL
PLLA, PLLB and
Main Oscillator
Suplly
1.08
--
1.32
AVDD
PLC Analog
Converter Power
Supply
3.00
3.30
3.60
(1) (2)
VIL
Input Low-level
Voltage
PA0-PA25, PB0-PB12, PC0,
PC5, PC26
-0.3
MIN[0.8V:0.3
x VVDDIO]
VIH
Input High-level
Voltage
PA0-PA25, PB0 PB12, PC0,
PC5, PC26
MIN[2.0V:0.7
x VVDDIO]
VVDDIO + 0.3V
Output High-level
Voltage
PA0-PA25, PB0-PB12, PC0,
PC5, PC26
IOL = 4.0 mA
VDDIO [3.0V : 3.60V]
PB0-PB12
VOH
Output Low-level
Voltage
VOL
VHys
Hysteresis Voltage
IOH (or ISOURCE)
IOH
V
VVDDIO
-0.4V
VVDDIO
-0.15V
PA0-PA25, PB0 PB12, PC0,
PC5, PC26
IOL = 4.0 mA
VDDIO [3.0V : 3.60V]
PB0-PB12
PA0-PA25, PB0-PB9, PB12,
PC0,PC5,PC26
(Hysteresis mode enabled)
Units
0.4
0.15
150
mV
VDDIO [3V : 3.60V] ;VOH =
VVDDIO - 0.4V
- PA14 (SPCK)
- PA[12-13],
- PA[0-3]
- Other pins (1)
VDDIO [3.0V : 3.60V]
- PB[10-11]
-30
-EMIT[1:6]
-20
-Other PLC pins
VDDIO [3V : 3.60V] ; VOH =
VVDDIO - 0.4V
- NRST
-10
-4
-4
-2
-2
mA
-2
Atmel SAM4SP32A [PRELIMINARY datasheet]
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141
Table 13-2.
Symbol
SAM4SP32A DC Characteristics (Continued)
Parameter
IOL (or ISINK)
IOL
Conditions
Min
Typ
VDDIO [3V : 3.60V] ;VOH =
VVDDIO - 0.4V
- PA14 (SPCK)
- PA[12-13],
- PA[0-3]
- Other pins (1)
VDDIO [3.0V : 3.60V]
30
20
10
-EMIT[1:6]
-Other PLC pins
VDDIO [3V : 3.60V] ; VOH =
VVDDIO - 0.4V
- NRST
Input Low
IIH
Input High
RPULLUP
RPULLDOWN
PLCRPU
PLCRPD
Internal Pull-up
Resistor
Internal Pull-down
Resistor
PLC Internal Pull-up
Resistor
PLC Internal Pulldown Resistor
Units
4
4
2
2
- PB[10-11]
IIL
Max
2
Pull_up OFF
-1
1
Pull_up ON
10
50
Pull_up OFF
-1
1
Pull_up ON
PA0-PA25, PB0- PB12, PC0,
PC5, PC26, NRST
PA0-PA25, PB0-PB12, PC0,
PC5, PC26, NRST
10
50
70
100
130
70
100
130
3.3v I/O
10
33
80
3.3v I/O
10
33
80
µA
kΩ
Note:
1. At power-up VDDIO needs to reach 0.6V before VDDIN reaches 1.0V
2. VDDIO voltage needs to be equal or below to (VDDIN voltage +0.5V)
Atmel SAM4SP32A [PRELIMINARY datasheet]
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Table 13-3.
1.2V Voltage Regulator Characteristics (VDDOUT12)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VVDDIN
DC Input Voltage Range
(4)(5)
1.6
3.3
3.6
V
VVDDOUT
DC Output Voltage
Normal Mode
Standby Mode
VACCURACY
Output Voltage Accuracy
ILoad = 0.8mA to 80 mA (after trimming)
1.2
0
-3
V
3
%
VVDDIN > 1.8V
VVDDIN ≤ 1.8V
80
40
mA
See Note(3)
400
mA
ILOAD-START
Maximum DC Output
Current
Maximum Peak Current
during startup
DDROPOUT
Dropout Voltage
VVDDIN = 1.6V, ILoad = Max
400
VLINE
Line Regulation
VVDDIN from 2.7V to 3.6V; ILoad MAX
10
30
VLINE-TR
Transient Line regulation
VVDDIN from 2.7V to 3.6V; tr = tf = 5µs; ILoad
Max
50
150
20
40
ILOAD
VLOAD
VLOAD-TR
IQ
Load Regulation
Transient Load Regulation
Quiescent Current
CDIN
Input Decoupling Capacitor
CDOUT
Output Decoupling
Capacitor
mV
mV
VVDDIN ≥ 1.8V;
ILoad = 10% to 90% MAX
VVDDIN ≥ 1.8V;
ILoad = 10% to 90% MAX
tr = tf = 5 µs
mV
50
Normal Mode;
@ ILoad = 0 mA
@ ILoad = 80 mA
Standby Mode;
150
5
500
µA
1
Cf. External Capacitor Requirements
(1)
4.7
Cf. External Capacitor Requirements (2)
1.85
ESR
0.1
TON
Turn on Time
CDOUT= 2.2µF, VVDDOUT reaches 1.2V (+/3%)
TOFF
Turn off Time
CDOUT= 2.2µF
2.2
µF
5.9
µF
10
Ω
300
µs
40
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
ms
143
Note:
1. A 10µF or higher ceramic capacitor must be connected between VDDIN and the closest GND pin of the device.
This large decoupling capacitor is mandatory to reduce startup current, improving transient response and noise
rejection.
Table 13-4.
2.
To ensure stability, an external 2.2µF output capacitor, CDOUT must be connected between the
VDDOUT and the closest GND pin of the device. The ESR (Equivalent Series Resistance) of the
capacitor
must
be
in
the
range
0.1
to
10
ohms.
Solid tantalum and multilayer ceramic capacitors are all suitable as output capacitor.
A 100nF bypass capacitor between VDDOUT and the closest GND pin of the device helps decreasing
output noise and improves the load transient response.
3.
Defined as the current needed to charge external bypass/decoupling capacitor network.
4.
At power-up VDDIO needs to reach 0.6V before VDDIN reaches 1.0V
5.
VDDIO voltage needs to be equal or below to (VDDIN voltage +0.5V)
Core Power Supply Brownout Detector Characteristics
Parameter
Supply Falling
Threshold(1)
Symbol
VTH-
Hysteresis
VHYST
Supply Rising
Threshold
VTH+
Current Consumption
on VDDCOARE
Current Consumption
on VDDIO
VTH- detection
propagation time
IDDON
IDDOFF
IDD33ON
IDD33OFF
TdTSTART
Start Time
Conditions
Min
Typ
Max
Units
0.98
1.0
1.04
V
110
mV
1.08
V
0.8
Brownout Detector enabled
24
Brownout Detector disable
2
µA
Brownout Detector enabled
24
Brownout Detector disable
[-40/+85oC]
2
-2.5
From disable state to enable state
1.0
+2.5
%
320
µs
Note:
1.
The product is guaranteed to be functional at V TH-
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
144
Figure 13-1.
Core Brownout Output Waveform
VDD CORE
Vth+
Vtht
BOD OUTPUT
td-
td+
t
Table 13-5.
VDDIO Supply Monitor
Parameter
Symbol
Supply Monitor
Threshold
VTH
Threshold Level
Accuracy
TACCURACY
Hysteresis
Current Consumption
on VDDCOARE
Start Time
Conditions
Min
16 selectable steps
[-40/+85oC]
VHYST
IDDON
IDDOFF
TSTART
Typ
Max
Units
1.6
3.34
V
-2.5
+2.5
%
30
mV
20
Enabled
40
µA
Disable
10
From disable state to enable state
320
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
µs
145
Table 13-6.
Threshold Selection
Digital Code
Threshold min (V)
Threshold typ (V)
Threshold max (V)
0000
1.58
1.6
1.62
0001
1.7
1.72
1.74
0010
1.82
1.84
1.86
0011
1.94
1.96
1.98
0100
2.05
2.08
2.11
0101
2.17
2.2
2.23
0110
2.29
2.32
2.35
0111
2.41
2.44
2.47
1000
1001
2.53
2.65
2.56
2.68
2.59
2.71
1010
2.77
2.8
2.83
1011
2.8
2.92
2.95
1100
3.0
3.04
3.07
1101
3.12
3.16
3.2
1110
3.24
3.28
3.32
1111
3.36
3.4
3.44
Figure 13-2. VDDIO Supply Monitor
VDDIO
Vth + Vhyst
Vth
Reset
Atmel SAM4SP32A [PRELIMINARY datasheet]
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146
Table 13-7.
Zero-Power-on Reset Characteristics
Parameter
Symbol
Coditions
Min
Typ
Max
Units
Threshold voltage rising
VTH+
At Startup
1.45
1.53
1.59
V
Threshold voltage falling
VTH-
1.35
1.45
1.55
V
Reset Time-out Period
Tres
100
240
500
µs
Figure 13-3. Zero-Power-on Reset Characteristics
VDDIO
Vth+
Vth-
Reset
Table 13-8.
Parameter
Active current
DC Flash Characteristics
Symbol
ICC
Coditions
Typ
Max
Random 144-bit Read:
Maximum Read Frequency onto VDDCORE = 1.2 @ 25oC
16
25
Random 72-bit Read:
o
Maximum Read Frequency onto VDDCORE = 1.2 @ 25 C
10
18
Program onto VDDCORE = 1.2V @ 25oC
3
5
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
Units
mA
147
13.3
Power Consumption
•
Power consumption of the device according to the different Low Power Mode Capabilities (Backup, Wait,
Sleep) and Active Mode.
•
•
Power consumption on power supply in different modes: Backup, Wait, Sleep and Active.
Power consumption by peripheral: calculated as the difference in current measurement after having enabled
then disabled the corresponding clock.
13.3.1 Backup Mode Current Consuption
The Backup Mode configuration and measurements are defined as follows.
Figure 13-4. Measurement Setup
AMP1
3.3V
VDDIO
VDDIN
Voltage
Regulator
VDDOUT12
VDDCORE
VDDPLL
13.3.1.1 Configuration A
•
•
•
•
•
Supply Monitor on VDDIO is disabled
RTT and RTC not used
Embedded slow clock RC Oscillator used
One WKUPx enabled
Current measurement on AMP1 (See Figure 13-4)
13.3.1.2 Configuration B
•
•
•
•
•
Supply Monitor on VDDIO is disabled
RTT used
One WKUPx enabled
Current measurement on AMP1 (See Figure 13-4)
32 KHz Crystal Oscillator used
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
148
Table 13-9. Power Consumption for Backup Mode Configuration A and B
Conditions
Total Consumption (AMP1)
Configuration A
Total Consumption (AMP1)
Configuration B
Unit
VDDIO = 3.3V @25°C
VDDIO = 3.0V @25°C
VDDIO = 2.5V @25°C
VDDIO = 1.8V @25°C
1.98
1.79
1.51
1
1.85
1.66
1.37
0.95
µA
VDDIO = 3.3V @85°C
VDDIO = 3.0V @85°C
VDDIO = 2.5V @85°C
VDDIO = 1.8V @85°C
13.0
12.0
10.5
8.78
12.42
11.42
10.05
8.42
µA
13.3.2 Sleep and Wait Mode Current Consumption
The Wait Mode and Sleep Mode configuration and measurements are defined below.
Figure 13-5. Measurement Setup for Sleep Mode
AMP2
3.3V
VDDIO
VDDIN
Voltage
Regulator
VDDOUT12
AMP1
VDDCORE
VDDPLL
13.3.2.1 Sleep Mode
•
•
•
•
•
Core Clock OFF
Master Clock (MCK) running at various frequencies with PLLA or the fast RC oscillator.
Fast start-up through WKUP0-15 pins
Current measurement as shown in figure Figure 13-6
All peripheral clocks deactivated
Table 13-10 below gives current consumption in typical conditions.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
149
Table 13-10. Typical Current Consumption for Sleep Mode
Conditions
VDDCORE
Consumption
(AMP1)
Total
Consumption
(AMP2)
Unit
2.52
3.04
mA
Figure 13-6 @25°C
MCK = 48 MHz
There is no activity on the I/Os of the device.
Figure 13-6. Current Consumption in Sleep Mode (AMP1) versus Master Clock ranges (Condition from Table 13-10)
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
150
Table 13-11. Sleep mode Current consumptionversus Master Clock (MCK) variation with PLLA
Core Clock/MCK (MHz)
VDDCORE Consumption
(AMP1)
Total Consumption
(AMP2)
Unit
120
8.1
9.9
mA
100
6.7
8.3
mA
84
5.7
7.1
mA
64
4.5
6.4
mA
48
3.4
4.8
mA
32
2.3
3.38
mA
24
1.8
3.31
mA
13.3.2.2 Wait Mode
Figure 13-7. Measurement Setup for Wait Mode
AMP2
3.3V
VDDIO
VDDIN
Voltage
Regulator
VDDOUT12
AMP1
VDDCORE
VDDPLL
•
•
•
Core Clock and Master Clock Stopped
Current measurement as shown in the above figure
All Peripheral clocks deactivated
Table 13-12 gives current consumption in typical conditions.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
151
Table 13-12.
Typical Current Consumption in Wait Mode
Conditions
VDDOUT
Consumption
(AMP1)
Total
Consumption
(AMP2)
Unit
See Figure 13-7 @25°C
There is no activity on the I/Os of the
device. With the Flash in Standby Mode
20.4
32.2
µA
See Figure 13-7 @25°C
There is no activity on the I/Os of the
device. With the Flash in Deep Power
Down Mode
20.5
27.6
µA
13.3.3 Active Mode Power Consumption
The Active Mode configuration and measurements are defined as follows:
•
•
•
•
•
•
•
VDDIO = VDDIN = 3.3V
VDDCORE = 1.2V (Internal Voltage regulator used)
TA = 25°C
Application Running from Flash Memory with128-bit access Mode
All Peripheral clocks are deactivated.
Master Clock (MCK) running at various frequencies with PLLA or the fast RC oscillator.
Current measurement on AMP1 (VDDCORE) and total current on AMP2
Figure 13-8. Active Mode Measurement Setup
AMP2
3.3V
VDDIO
VDDIN
Voltage
Regulator
VDDOUT12
AMP1
VDDCORE
VDDPLL
Tables below give Active Mode Current Consumption in typical conditions.
•
•
VDDCORE at 1.2V
Temperature = 25°C
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
152
Table 13-13.
Active Power Consumption with VDDCORE @ 1.2V (VDDOUT12) running from Flash Memory or SRAM
CoreMark
Unit
Core Clock (MHz)
128-bit Flash access(1)
64-bit Flash access(1)
AMP1
AMP2
AMP1
AMP2
120
24.9
28.8
18
21.4
100
21.9
25.4
16.3
19.5
84
18.5
21.4
13.8
16.6
64
15.0
17.6
11.4
13.9
48
11.9
14.3
9.6
11.8
32
8.1
9.9
7.4
9.3
mA
24
6.0
7.7
5.8
7.5
12
3.4
6.1
3.2
6.0
8
2.3
4.5
2.2
4.5
4
1.2
2.6
1.2
2.9
2
0.7
1.9
0.7
2.0
1
0.4
1.3
0.4
1.6
0.5
0.3
1.1
0.3
1.3
Note:
1. Flash Wait State (FWS) in EEFC_FMR adjusted versus Core Frequency
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
153
13.3.4 Peripheral Power Consumption in Active Mode
Power Consumption on VVDDCORE(1) (when PRIME PLC Transceiver is turned off)
Table 13-14.
Peripheral
Consumption (Typ)
PIO Controller A (PIOA)
5.6
PIO Controller B (PIOB)
7.5
PIO Controller C (PIOC)
5.9
UART
3.8
USART
7.7
PWM
10.5
TWI
5.8
PLC_Bridge
6.9
Timer Counter (TCx)
4.7
ACC
1.3
CRCCU
1.4
SMC
3.6
SSC
6.1
UDP
5
Unit
µA/MHz
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
154
Table 13-15.
PRIME PLC Transceiver Peripheral Power Consumption
Rating
Parameter
Power Consumption
Power Consumption
(worst case)
Condition
Symbol
Unit
Min.
Typ.
Max.
(2)
P25
--
260
--
mW
(3)
P85
--
--
355
--
Note:
1. VDDIO = 3.3V, VVDDCORE = 1.08V, TA = 25°C
2. VDDIO = 3.3V, VVDDCORE = 1.08V, TA = 25°C
3. VDDIO = 3.3V, VVDDCORE = 1.08V, TA = 25°C
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
155
13.4
Oscillator Characteristics
13.4.1 32 kHz RC Oscillator Characteristics
Table 13-16.
Symbol
32 kHz RC Oscillator Characteristics
Parameter
Min
Typ
Max
Unit
RC Oscillator Frequency
20
32
44
kHz
Frequency Supply Dependency
-3
3
%/V
-7
7
%
55
%
100
µs
860
nA
Frequency Temperature
Dependency
Duty
Duty Cycle
TON
Startup Time
IDDON
Current Consumption
Conditions
Over temperature range (-40°C/
+85°C) versus 25°C
45
After Startup Time
Temp. Range = -40°C to +125°C
Typical Consumption at 2.2V
supply and Temp = 25°C
50
540
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
156
13.4.2 4/8/12 MHz RC Oscillators Characteristics
Table 13-17.
4/8/12 MHz RC Oscillators Characteristics
Symbol
Parameter
FRange
RC Oscillator Frequency
Range
ACC4
4 MHz Total Accuracy
ACC8
Conditions
Min
Max
Unit
12
MHz
-40°C<Temp<+85°C
4 MHz output selected (1)(2)
±30
%
-40°C<Temp<+85°C
8 MHz output selected (1)(2)
±30
(1)
Typ
4
8 MHz Total Accuracy
ACC12
%
-40°C<Temp<+85°C
(1)(3)
8 MHz output selected
±5
-40°C<Temp<+85°C
(1)(2)
12 MHz output selected
±30
%
12 MHz Total Accuracy
-40°C<Temp<+85°C
(1)(3)
12 MHz output selected
Frequency deviation versus
trimming code
±5
8 MHz
12 MHz
Duty
Duty Cycle
TON
Startup Time
IDDON
Active Current Consumption
47
64
45
(2)
4MHz
8MHz
12MHz
50
50
65
82
kHz/trimming code
55
%
10
µs
75
95
118
µA
Note:
1. Frequency range can be configured in the Supply Controller Registers
2.
Not trimmed from factory
3.
After Trimming from factory
The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB Bit
command (see EEFC section) and the frequency can be trimmed by software through the PMC.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
157
13.4.3 32.768 kHz Crystal Oscillator Characteristics
Table 13-18.
32.768 kHz Crystal Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Freq
Operating Frequency
Normal mode with crystal
Supply Ripple Voltage (on VDDIO)
Rms value, 10 KHz to 10 MHz
Duty Cycle
40
Rs < 50KΩ
Startup Time
Rs < 100KΩ
(1)
Rs < 50KΩ
Iddon
Current consumption
Rs < 100KΩ
(1)
PON
Drive level
Rf
Internal resistor
CLEXT
Maximum external capacitor
on XIN32 and XOUT32
Cpara
Internal Parasitic Capacitance
Typ
50
Ccrystal = 12.5pF
Ccrystal = 6pF
Ccrystal = 12.5pF
Ccrystal = 6pF
Ccrystal = 12.5pF
Ccrystal = 6pF
Ccrystal = 12.5pF
Ccrystal = 6pF
550
380
820
530
between XIN32 and XOUT32
Max
Unit
32.768
KHz
30
mV
60
%
900
300
1200
500
ms
1150
980
1600
1350
nA
0.1
µW
10
0.6
0.7
MΩ
20
pF
0.8
pF
Note:
1. RS is the series resitor
SAM4
XIN32
C LEXT
XOUT32
C LEXT
CLEXT = 2x(CCRYSTAL – Cpara – CPCB).
Where CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the SAM4 pin.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
158
13.4.4 32.768 kHz Crystal Characteristics
Table 13-19.
Crystal Characteristics
Symbol
Parameter
Conditions
Min
ESR
Equivalent Series Resistor (RS)
Crystal @ 32.768 KHz
CM
Motional capacitance
Crystal @ 32.768 KHz
CSHUNT
Shunt capacitance
Crystal @ 32.768 KHz
Typ
Max
Unit
50
100
KΩ
0.6
3
fF
0.6
2
pF
13.4.5 3 to 20 MHz Crystal Oscillator Characteristics
Table 13-20.
3 to 20 MHz Crystal Oscillator Characteristics
Symbol
Parameter
Conditions
Freq
Operating Frequency
Normal mode with crystal
Supply Ripple Voltage (on VDDPLL)
Rms value, 10 KHz to 10 MHz
Duty Cycle
Typ
Max
Unit
3
16
20
MHz
30
mV
60
%
14.5
4
1.4
2.5
1
ms
350
400
470
560
µA
15
30
50
µW
40
Startup Time
3 MHz, CSHUNT = 3pF
8 MHz, CSHUNT = 7pF
16 MHz, CSHUNT = 7pF with Cm = 8fF
16 MHz, CSHUNT = 7pF with Cm = 1.6fF
20 MHz, CSHUNT = 7pF
IDD_ON
Current consumption
(on VDDIO)
3 MHz (2)
8 MHz(3)
16 MHz(4)
20 MHz(5)
PON
Drive level
3 MHz
8 MHz
16 MHz, 20 MHz
Rf
Internal resistor
between XIN and XOUT
CLEXT
Maximum external capacitor
on XIN and XOUT
CL
Internal Equivalent Load Capacitance
TON
Min
50
230
300
390
450
0.5
12.5
Integrated Load Capacitance
(XIN and XOUT in series)
7.5
9.5
MΩ
17.5
pF
10.5
pF
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
159
Note:
1. RS = 100-200 Ohms; Cs = 2.0 - 2.5pF; Cm = 2 – 1.5 fF(typ, worst case) using 1 K<Symbol>W serial resistor on
XOUT.
2.
RS = 50-100 Ohms; Cs = 2.0 - 2.5pF; Cm = 4 - 3 fF(typ, worst case).
3.
RS = 25-50 Ohms; Cs = 2.5 - 3.0pF; Cm = 7 - 5 fF (typ, worst case).
4.
RS = 20-50 Ohms; Cs = 3.2 - 4.0pF; Cm = 10 - 8 fF(typ, worst case).
SAM4
CL
XOUT
XIN
R = 1K if Crystal Frequency
is lower than 8 MHz
C LEXT
C Crystal
C LEXT
CLEXT = 2x(CCRYSTAL – CL – CPCB).
Where CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the SAM4 pin
13.4.6 3 to 20 MHz Crystal Characteristics
Table 13-21. 3 to 20 MHz Crystal Characteristics
Symbol
Parameter
Conditions
Min
ESR
Equivalent Series Resistor (Rs)
Fundamental @ 3 MHz
Fundamental @ 8 MHz
Fundamental @ 12 MHz
Fundamental @ 16 MHz
Fundamental @ 20 MHz
CM
CSHUNT
Typ
Max
Unit
200
100
80
80
50
Ω
Motional capacitance
8
fF
Shunt capacitance
7
pF
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
160
13.4.7 Crystal Oscillator Design Considerations Information
13.4.7.1 Choosing a Crystal
When choosing a crystal for the 32768 Hz Slow Clock Oscillator or for the 3-20 MHz Oscillator, several parameters
must be taken into account. Important parameters between crystal and SAM4S specifications are as follows:
•
Load Capacitance
•
Ccrystal is the equivalent capacitor value the oscillator must “show” to the crystal in order to oscillate at
the target frequency. The crystal must be chosen according to the internal load capacitance (CL) of the
on-chip oscillator. Having a mismatch for the load capacitance will result in a frequency drift.
•
Drive Level
• Crystal drive level >= Oscillator Drive Level. Having a crystal drive level number lower than the
oscillator specification may damage the crystal.
•
Equivalent Series Resistor (ESR)
• Crystal ESR <= Oscillator ESR Max. Having a crystal with ESR value higher than the oscillator may
cause the oscillator to not start.
•
Shunt Capacitance
• Max. crystal Shunt capacitance <= Oscillator Shunt Capacitance (CSHUNT). Having a crystal with ESR
value higher than the oscillator may cause the oscillator to not start.
13.4.7.2 Printed Circuit Board (PCB)
SAM4SP32A Oscillators are low power oscillators requiring particular attention when designing PCB systems.
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
161
13.5
PLLA, PLLB Characteristics
Table 13-22.
Symbol
Supply Voltage Phase Lock Loop Characteristics
Parameter
Conditions
Supply Voltage Range
VDDPLL
Min
Typ
Max
Unit
1.08
1.2
1.32
V
20
10
mV
RMS Value 10 kHz to 10 MHz
RMS Value > 10 MHz
Allowable Voltage Ripple
Table 13-23. PLLA and PLLB Characteristics
Symbol
Parameter
FIN
Input Frequency
FOUT
Output Frequency
IPLL
Current Consumption
TSTART
Settling Time
Conditions
Min
Active mode @ 80 MHz @1.2V
Active mode @ 96 MHz @1.2V
Active mode @ 160 MHz @1.2V
Active Mode @240 MHz @1.2V
Typ
Max
Unit
3
32
MHz
80
240
MHz
0.94
1.2
2.1
3.34
1.2
1.5
2.5
4
mA
60
150
µS
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
162
13.6
USB Transceiver Characteristics
13.6.1 Typical Connections
For typical connection please refer to the USB Device Section.
13.6.2 Electrical Characteristics
Table 13-24.
Symbol
Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
0.8
V
Input Levels
VIL
Low Level
VIH
High Level
VDI
Differential Input Sensitivity
VCM
Differential Input Common Mode
Range
CIN
Transceiver capacitance
Capacitance to ground on each line
I
Hi-Z State Data Line Leakage
0V < VIN < 3.3V
REXT
Recommended External USB
Series Resistor
In series with each USB pin with ±5%
|(D+) - (D-)|
2.0
V
0.2
V
0.8
-10
2.5
V
9.18
pF
+10
µA
Ω
27
Output Levels
VOL
Low Level Output
Measured with RL of 1.425 kΩ tied to
3.6V
0.0
0.3
V
VOH
High Level Output
Measured with RL of 14.25 kΩ tied to
GND
2.8
3.6
V
VCRS
Output Signal Crossover
Voltage
Measure conditions described in
Figure 13-9
1.3
2.0
V
105
200
µA
80
150
µA
Consumption
IVDDIO
Current Consumption
IVDDCORE
Current Consumption
Transceiver enabled in input mode
DDP = 1 and DDM = 0
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
163
Table 13-23.
Symbol
Electrical Characteristics (Continued)
Parameter
Conditions
Min
Typ
Max
Unit
Pull-up Resistor
RPUI
Bus Pull-up Resistor on
Upstream Port (idle bus)
0.900
1.575
kΩ
RPUA
Bus Pull-up Resistor on
Upstream Port (upstream port receiving)
1.425
3.090
kΩ
13.6.3 Switching Characteristics
Table 13-24.
In Full Speed
Symbol
Parameter
Conditions
tFR
Transition Rise Time
CLOAD = 50 pF
tFE
Transition Fall Time
CLOAD = 50 pF
tFRFM
Rise/Fall time Matching
Min
Typ
Max
Unit
4
20
ns
4
20
ns
90
111.11
%
Figure 13-9. USB Data Signal Rise and Fall Times
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
164
13.7
Analog Comparator Characteristics
Table 13-25.
Analog Comparator Characteristics
Parameter
Conditions
Min
Typ
Max
Units
Voltage Range
The Analog Comparator is supplied by
VDDIN
1.62
3.3
3.6
V
VDDIN - 0.2
V
20
mV
25
170
µA
Input Voltage Range
GND + 0.2
Input Offset Voltage
Current Consumption
On VDDIN
Low Power Option (ISEL = 0)
High Speed Option (ISEL = 1)
Hysteresis
HYST = 0x01 or 0x10
HYST = 0x11
Settling Time
Given for overdrive > 100 mV
Low Power Option
High Speed Option
15
30
50
90
1
0.1
Atmel SAM4SP32A [PRELIMINARY datasheet]
43020A-ATPL-09/12
mV
µs
165
13.8
Temperature Sensor
The temperature sensor is connected to Channel 15 of the ADC.
The temperature sensor provides an output voltage (V T) that is proportional to absolute temperature (PTAT). The VT
output voltage linearly varies with a temperature slope dV T/dT = 4.72 mV/°C.
The V T voltage equals 1.44V at 27°C, with a ±50mV accuracy. The VT slope versus temperature dV T/dT = 4.72 mV/°C
only shows a ±8% slight variation over process, mismatch and supply voltage.
The user needs to calibrate it (offset calibration) at ambient temperature in order to get rid of the VT spread at ambient
temperature (+/-15%).
Table 13-26. Temperature Sensor Characteristics
Symbol
Parameter
Conditions
VT
Output Voltage
T° = 27° C
<Symbol>
DVT
Output Voltage Accuracy
T° = 27° C
dVT/dT
Temperature Sensitivity (slope
voltage versus temperature)
Slope accuracy
Min
Typ
Max
1.44
-50
Units
V
+50
4.72
mV
mV/°C
Over temperature range [-40°C / +85°C]
-8
+8
%
After offset calibration
Over temperature range [-40°C / +85°C]
-5
+5
°C
After offset calibration
Over temperature range [0°C / +80°C]
-3
+3
°C
5
10
µs
70
80
µA
Temperature accuracy
TSTART-UP
Startup Time
IVDDCORE
Current Consumption
After TSON = 1
50
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13.9
AC Characteristics
13.9.1 Master Clock Characteristics
Table 13-27.
Master Clock Waveform Parameters
Symbol
Parameter
Conditions
Min
Max
Units
1/(tCPMCK)
Master Clock Frequency
VDDCORE @ 1.20V
120
MHz
1/(tCPMCK)
Master Clock Frequency
VDDCORE @ 1.08V
100
MHz
13.9.2 I/O Characteristics
Criteria used to define the maximum frequency of the I/Os:
•
•
•
•
Output duty cycle (40%-60%)
Minimum output swing: 100 mV to VDDIO - 100 mV
Minimum output swing: 100 mV to VDDIO - 100 mV
Addition of rising and falling time inferior to 75% of the period
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Table 13-28. I/O Characteristics
Symbol
Parameter
FreqMax1
Pin Group 1 (1) Maximum output
frequency
PulseminH1
PulseminL1
FreqMax2
PulseminH2
PulseminL2
FreqMax3
PulseminH3
PulseminL3
Conditions
(1)
Pin Group 1
Pin Group 1
(1)
Pin Group 3
(3)
(3)
Units
70
MHz
30 pF
VDDIO = 1.62V
10 pF
VDDIO = 1.62V
45
7.2
ns
30 pF
VDDIO = 1.62V
11
10 pF
VDDIO = 1.62V
7.2
ns
30 pF
VDDIO = 1.62V
10 pF
VDDIO = 1.62V
11
46
MHz
25 pF
VDDIO = 1.62V
10 pF
VDDIO = 1.62V
23
11
ns
25pF
VDDIO = 1.62V
21.8
10 pF
VDDIO = 1.62V
11
Low Level Pulse Width
Pin Group3(3) Maximum output frequency
Pin Group 3
VDDIO = 1.62V
Low Level Pulse Width
Pin Group 2 (2) High Level Pulse Width
(2)
Max
High Level Pulse Width
Pin Group 2 (2) Maximum output
frequency
Pin Group 2
10 pF
Min
ns
25 pF
VDDIO = 1.62V
10 pF
VDDIO = 1.62V
21.8
70
MHz
25 pF
VDDIO = 1.62V
10 pF
VDDIO = 1.62V
35
7.2
ns
High Level Pulse Width
25 pF
VDDIO = 1.62V
14.2
10 pF
VDDIO = 1.62V
7.2
ns
Low Level Pulse Width
25 pF
VDDIO = 1.62V
14.2
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Table 13-28.
I/O Characteristics
Symbol
Parameter
Conditions
(4)
Pin Group 4
Maximum output frequency
FreqMax4
(4)
PulseminH4
Pin Group 4
High Level Pulse Width
Pin Group 4(4) Low Level Pulse Width
Min
Max
10 pF
VDDIO = 1.62V
58
25 pF
VDDIO = 1.62V
29
10 pF
VDDIO = 1.62V
8.6
25pF
VDDIO = 1.62V
17.2
10 pF
VDDIO = 1.62V
8.6
25 pF
VDDIO = 1.62V
17.2
25 pF
VDDIO = 1.62V
MHz
ns
ns
PulseminL4
FreqMax5
Units
Pin Group 5(5) Maximum output frequency
25
MHz
Note:
1. Pin Group 1 = PA14, PA29
2.
Pin Group 2 = PA[4-11], PA[15-25], PA[30-31], PB[0-9], PB[12-14], PC[0-31]
3.
Pin Group 3 = PA[12-13], PA[26-28], PA[30-31]
4.
PIn Group 4 = PA[0-3]
5.
PIn Group 5 = PB[10-11]
13.9.3 SSC Timings
Timings are given in the following domain:
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF
3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 30 pF.
Figure 13-10. SSC Transmitter, TK and TF as output
TK (CKI =0)
TK (CKI =1)
SSC0
TF/TD
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Figure 13-11. SSC Transmitter, TK as input and TF as output
TK (CKI =0)
TK (CKI =1)
SSC1
TF/TD
Figure 13-12. SSC Transmitter, TK as output and TF as input
TK (CKI=0)
TK (CKI=1)
SSC2
SSC3
TF
SSC4
TD
Figure 13-13. SSC Transmitter, TK and TF as input
TK (CKI=1)
TK (CKI=0)
SSC5
SSC6
TF
SSC7
TD
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Figure 13-14. SSC Receiver RK and RF as input
RK (CKI=0)
RK (CKI=1)
SSC9
SSC8
RF/RD
Figure 13-15. SSC Receiver, RK as input and RF as output
RK (CKI=1)
RK (CKI=0)
SSC8
SSC9
RD
SSC10
RF
Figure 13-16. SSC Receiver, RK and RF as output
RK (CKI=1)
RK (CKI=0)
SSC11
SSC12
RD
SSC13
RF
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Figure 13-17. SSC Receiver, RK as output and RF as input
RK (CKI=0)
RK (CKI=1)
SSC11
SSC12
RF/RD
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13.9.3.2 SSC Timings
Table 13-29.
Symbol
SSC Timings
Parameter
Condition
Min
Max
Units
Transmitter
SSC0
TK edge to TF/TD (TK output, TF output)
1.8v domain(3)
3.3v domain(4)
-3
-2.6
5.4
5.0
ns
SSC1
TK edge to TF/TD (TK input, TF output)
1.8v domain(3)
3.3v domain(4)
4.5
3.8
16.3
13.3
ns
SSC2
TF setup time before TK edge (TK output)
1.8v domain(3)
3.3v domain(4)
14.8
12.0
ns
SSC3
TF hold time after TK edge (TK output)
1.8v domain(3)
3.3v domain(4)
0
ns
SSC4(1)
TK edge to TF/TD (TK output, TF input)
1.8v domain(3)
3.3v domain(4)
2.6(+2*tCPMCK)
2.3(+2*tCPMCK) (1)(4)
SSC5
TF setup time before TK edge (TK input)
1.8v domain(3)
3.3v domain(4)
0
ns
SSC6
TF hold time after TK edge (TK input)
1.8v domain(3)
3.3v domain(4)
tCPMCK
ns
TK edge to TF/TD (TK input, TF input)
1.8v domain(3)
3.3v domain(4)
4.5(+3*tCPMCK)
3.8(+3*tCPMCK) (1)(4)
SSC7
(1)
(1)(4)
(1)(4)
(1)(4)
5.4(+2*tCPMCK)
5.0(+2*tCPMCK) (1)(4)
ns
(1)(4)
16.3(+3*tCPMCK)
13.3(+3*tCPMCK) (1)(4)
ns
Receiver
SSC8
RF/RD setup time before RK edge (RK input)
1.8v domain(3)
3.3v domain(4)
0
ns
SSC9
RF/RD hold time after RK edge (RK input)
1.8v domain(3)
3.3v domain(4)
tCPMCK
ns
SSC10
RK edge to RF (RK input)
1.8v domain(3)
3.3v domain(4)
4.7
4
SSC11
RF/RD setup time before RK edge (RK output)
1.8v domain(3)
3.3v domain(4)
15.8 - tCPMCK
12.5- tCPMCK
ns
SSC12
RF/RD hold time after RK edge (RK output)
1.8v domain(3)
3.3v domain(4)
tCPMCK - 4.3
tCPMCK - 3.6
ns
SSC13
RK edge to RF (RK output)
1.8v domain(3)
3.3v domain(4)
-3
-2.6
16.1
12.8
4.3
3.8
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ns
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Note:
1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4,
or 5 or 7(Receive Start Selection), two Periods of the MCK must be added to timings.
2.
For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between
the TK (or RK) edge and the signal change. The Max access timing is the time between the TK edge and the
signal stabilization. Figure 13-18 illustrates Min and Max accesses for SSC0. The same applies for SSC1, SSC4,
and SSC7, SSC10 and SSC13.
3.
1.8V domain: VVDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF.
4.
3.3V domain: VVDDIO from 2.85V to 3.6V, maximum external capacitor = 30 pF..
Figure 13-18. Min and Max Access Time of Output Signals
TK (CKI =1)
TK (CKI =0)
SSC0min
SSC0max
TF/TD
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13.9.4 SMC Timings
Timings are given in the following domain:
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 30 pF
3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 50 pF.
Timings are given assuming a capacitance load on data, control and address pads:
In the following tables tCPMCK is MCK period. Timing extraction
13.9.4.1 Read Timings
Table 13-30.
Symbol
SMC Read Signals - NRD Controlled (READ_MODE = 1)
Parameter
Min
(2)
VDDIO Supply
1.8V
Max
(3)
3.3V
(2)
1.8V
Units
(3)
3.3V
NO HOLD SETTINGS (nrd hold = 0)
SMC1
Data Setup before NRD High
SMC2
Data Hold after NRD High
19.9
17.9
ns
0
0
ns
HOLD SETTINGS (nrd hold <Symbol>¹ 0)
SMC3
Data Setup before NRD High
SMC4
Data Hold after NRD High
16.0
14.0
ns
0
0
ns
HOLD or NO HOLD SETTINGS (nrd hold <Symbol>¹ 0, nrd hold = 0)
SMC5
A0 - A22 Valid before NRD High
SMC6
NCS low before NRD High
SMC7
NRD Pulse Width
(nrd setup +
nrd pulse) *
tCPMCK - 6.5
(nrd setup +
nrd pulse)*
tCPMCK - 6.3
ns
(nrd setup +
nrd pulse - ncs
rd setup) *
tCPMCK - 4.6
(nrd setup +
nrd pulse - ncs
rd setup) *
tCPMCK - 5.1
ns
nrd pulse *
tCPMCK - 7.2
nrd pulse *
tCPMCK - 6.2
ns
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Table 13-31.
Symbol
SMC Read Signals - NCS Controlled (READ_MODE= 0)
Parameter
VDDIO supply
Min
1.8V(2)
Max
3.3V(3)
1.8V(2)
Units
3.3V(3)
NO HOLD SETTINGS (ncs rd hold = 0)
SMC8
Data Setup before NCS High
SMC9
Data Hold after NCS High
20.7
18.4
ns
0
0
ns
16.8
14.5
ns
0
0
ns
HOLD SETTINGS (ncs rd hold <Symbol>¹ 0)
SMC10
Data Setup before NCS High
SMC11
Data Hold after NCS High
HOLD or NO HOLD SETTINGS (ncs rd hold <Symbol>¹ 0, ncs rd hold = 0)
SMC12
A0 - A22 valid before NCS High
(ncs rd setup +
ncs rd pulse)*
tCPMCK - 6.5
(ncs rd setup +
ncs rd pulse)*
tCPMCK - 6.3
SMC13
NRD low before NCS High
(ncs rd setup +
(ncs rd setup +
ncs rd pulse - nrd
ncs rd pulse - nrd
setup)* tCPMCKsetup)* tCPMCK - 5.6
5.4
SMC14
NCS Pulse Width
ncs rd pulse length
* tCPMCK -7.7
ns
ns
ncs rd pulse
length * tCPMCK 6.7
ns
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13.9.4.2 Write Timings
Table 13-32. SMC Write Signals - NWE Controlled (WRITE_MODE = 1)
Min
Symbol
1.8V(2)
Parameter
Max
3.3V(3)
1.8V(2)
3.3V(3)
Units
HOLD or NO HOLD SETTINGS (nwe hold <Symbol>¹ 0, nwe hold = 0)
SMC15
Data Out Valid before NWE High
nwe pulse * tCPMCK - nwe pulse * tCPMCK
- 6.7
6.9
ns
SMC16
NWE Pulse Width
nwe pulse * tCPMCK - nwe pulse * tCPMCK
- 6.3
7.3
ns
SMC17
A0 - A22 valid before NWE low
nwe setup * tCPMCK nwe setup * tCPMCK
- 7.2
- 7.0
ns
NCS low before NWE high
(nwe setup - ncs rd
setup + nwe pulse)
* tCPMCK -7.1
SMC18
(nwe setup - ncs
rd setup + nwe
pulse) * tCPMCK 6.8
ns
HOLD SETTINGS (nwe hold <Symbol>¹ 0)
SMC19
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2 - A25
change
nwe hold * tCPMCK - nwe hold * tCPMCK 8.8
6.9
ns
SMC20
NWE High to NCS Inactive (1)
(nwe hold - ncs wr (nwe hold - ncs wr
hold)* tCPMCK - 5.2 hold)* tCPMCK - 5.0
ns
NO HOLD SETTINGS (nwe hold = 0)
SMC21
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2 - A25,
(1)
NCS change
3.0
2.8
ns
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Table 13-33.
SMC Write NCS Controlled (WRITE_MODE = 0)
Min
Symbol
Parameter
Max
1.8V(2)
3.3V(3)
1.8V(2)
3.3V(3)
Units
SMC22
Data Out Valid before NCS High
ncs wr pulse *
tCPMCK - 6.3
ncs wr pulse *
tCPMCK - 6.2
ns
SMC23
NCS Pulse Width
ncs wr pulse *
tCPMCK - 7.7
ncs wr pulse *
tCPMCK - 6.7
ns
SMC24
A0 - A22 valid before NCS low
ncs wr setup *
tCPMCK - 6.5
ncs wr setup *
tCPMCK - 6.3
ns
(ncs wr setup nwe setup + ncs
pulse)* tCPMCK 5.1
(ncs wr setup nwe setup + ncs
pulse)* tCPMCK 4.9
ns
SMC25
NWE low before NCS high
SMC26
NCS High to Data Out,A0 - A25,
change
ncs wr hold *
tCPMCK - 10.2
ncs wr hold *
tCPMCK - 8.4
ns
SMC27
NCS High to NWE Inactive
(ncs wr hold nwe hold)*
tCPMCK - 7.4
(ncs wr hold nwe hold)*
tCPMCK - 7.1
ns
Note:
1. Hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or
“NWE hold length”.
2.
1.8V domain: VDDIO from 1.65 V to 1.95V, maximum external capacitor = 30pF
3.
3.3V domain: VDDIO from2.85V to 3.6V, maximum external capacitor = 50pF.
Figure 13-19. SMC Timings - NCS Controlled Read and Write
SMC12
SMC12
SMC26
SMC24
A0 - A23
SMC13
SMC13
NRD
NCS
SMC14
SMC14
SMC8
SMC9
SMC10
SMC23
SMC11
SMC22
SMC26
DATA
SMC25
SMC27
NWE
NCS Controlled READ
with NO HOLD
NCS Controlled READ
with HOLD
NCS Controlled WRITE
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Figure 13-20. SMC Timings - NRD Controlled Read and NWE Controlled Write
SMC21
SMC17
SMC5
SMC5
SMC17
SMC19
A0-A23
SMC6
SMC21 SMC6
SMC18
SMC18
SMC20
NCS
NRD
SMC7
SMC7
SMC1
SMC2
SMC15
SMC21
SMC3
SMC4
SMC15
SMC19
DATA
NWE
SMC16
NRD Controlled READ
with NO HOLD
NWE Controlled WRITE
with NO HOLD
SMC16
NRD Controlled READ
with HOLD
NWE Controlled WRITE
with HOLD
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13.9.5 USART in SPI Mode Timings
Timings are given in the following domain:
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF
3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF.
Figure 13-21. USART SPI Master Mode
• the MOSI line is driven by the output pin TXD
• the MISO line drives the input pin RXD
• the SCK line is d riven by the output pin SCK
• the NSS line is driven by the output pin RTS
NSS
SPI
SPI
5
3
CPOL=1
SPI
SCK
0
CPOL=0
SPI
MISO
4
SPI
4
SPI
1
SPI
2
LSB
MSB
MOSI
Figure 13-22. USART SPI Slave Mode: (Mode 1 or 2)
• the MOSI line drives the input pin RXD
• the MISO line is driven by the output pin TXD
• the SCK line drives the input pin SCK
• the NSS line drives the input pin CTS
NSS
SPI13
SPI12
SCK
SPI6
MISO
SPI7
SPI8
MOSI
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Figure 13-23. USART SPI Slave mode: (Mode 0 or 3)
NSS
SPI 14
SPI 15
SCK
SPI 9
MISO
SPI 10
SPI 11
MOSI
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13.9.5.2 USART SPI TImings
Table 13-34. USART SPI TImings
Symbol
Parameter
Conditions
Min
Max
Units
Master Mode
SPI0
SCK Period
1.8v domain
3.3v domain
MCK/6
ns
SPI1
Input Data Setup Time
1.8v domain
3.3v domain
0.5 * MCK + 0.8
0.5 * MCK + 1.0
ns
SPI2
Input Data Hold Time
1.8v domain
3.3v domain
1.5 * MCK + 0.3
1.5 * MCK + 0.1
ns
SPI3
Chip Select Active to Serial Clock
1.8v domain
3.3v domain
1.5 * SPCK - 1.5
1.5 * SPCK - 2.1
ns
SPI4
Output Data Setup Time
1.8v domain
3.3v domain
- 7.9
- 7.2
SPI5
Serial Clock to Chip Select Inactive
1.8v domain
3.3v domain
1 * SPCK - 4.1
1 * SPCK - 4.8
9.9
10.7
ns
ns
Slave Mode
SPI6
SCK falling to MISO
1.8V domain
3.3V domain
4.7
4
17.3
15.2
SPI7
MOSI Setup time before SCK rises
1.8V domain
3.3V domain
2 * MCK + 0.7
2 * MCK
ns
SPI8
MOSI Hold time after SCK rises
1.8v domain
3.3v domain
0
0.1
ns
SPI9
SCK rising to MISO
1.8v domain
3.3v domain
4.7
4.1
SPI10
MOSI Setup time before SCK falls
1.8v domain
3.3v domain
2 * MCK + 0.7
2 * MCK + 0.6
ns
SPI11
MOSI Hold time after SCK falls
1.8v domain
3.3v domain
0.2
0.1
ns
17.1
15.5
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ns
182
Table 13-34.
USART SPI Timings (Continued)
Symbol
Parameter
SPI12
NPCS0 setup to SCK rising
SPI13
NPCS0 hold after SCK falling
SPI14
NPCS0 setup to SCK falling
SPI15
NPCS0 hold after SCK rising
Conditions
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
1.8v domain
3.3v domain
Min
2,5 * MCK + 0.5
2,5 * MCK
1,5 * MCK + 0.2
1,5 * MCK
2,5 * MCK + 0.5
2,5 * MCK + 0.3
1,5 * MCK
1,5 * MCK
Max
Units
ns
ns
ns
ns
Note:
1. 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF
2.
3.3V domain: VDDIO from2.85V to 3.6V, maximum external capacitor = 40 pF.
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13.9.6 Two-wire Serial Interface Characteristics
Following table describes the requirements for devices connected to the Two-wire Serial Bus. For timing symbols refer
to Figure 13-24
Table 13-35. Two-wire Serial Bus Requirements
Symbol
Parameter
VIL
Min
Max
Units
Input Low-voltage
-0.3
0.3 VVDDIO
V
VIH
Input High-voltage
0.7xVVDDIO
VCC + 0.3
V
VHYS
Hysteresis of Schmitt Trigger Inputs
0.150
–
V
VOL
Output Low-voltage
-
0.4
V
tR
Rise Time for both TWD and TWCK
(1)(2)
300
ns
tOF
Output Fall Time from VIHmin to VILmax
20 + 0.1Cb(1)(2)
250
ns
Capacitance for each I/O Pin
–
10
pF
TWCK Clock Frequency
0
400
kHz
Ci
(1)
fTWCK
Condition
3 mA sink current
20 + 0.1Cb
10 pF < Cb < 400 pF
Figure 13-24
fTWCK ≤100 kHz
Rp
Ω
Value of Pull-up resistor
fTWCK > 100 kHz
Ω
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Table 13-35. Two-wire Serial Bus Requirements (Continued)
Symbol
tLOW
Parameter
Low Period of the TWCK clock
tHIGH
High period of the TWCK clock
tHD;STA
Hold Time (repeated) START Condition
tSU;STA
Set-up time for a repeated START condition
Condition
fTWCK ≤ 100 kHz
Min
Max
–
Units
µs
fTWCK > 100 kHz
(3)
–
µs
fTWCK ≤ 100 kHz
(4)
–
µs
fTWCK > 100 kHz
(4)
–
µs
fTWCK ≤ 100 kHz
tHIGH
–
µs
fTWCK > 100 kHz
tHIGH
–
µs
fTWCK ≤ 100 kHz
tHIGH
–
µs
fTWCK > 100 kHz
tHIGH
–
(3)
fTWCK ≤ 100 kHz
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tSU;STO
Setup time for STOP condition
tHD;STA
Hold Time (repeated) START Condition
0
µs
3 x TCP_MCK
(5)
µs
3 x TCP_MCK
(5)
µs
fTWCK > 100 kHz
0
fTWCK ≤ 100 kHz
tLOW - 3 x tCP_MCK(5)
–
ns
fTWCK > 100 kHz
(5)
–
ns
tLOW - 3 x tCP_MCK
fTWCK ≤ 100 kHz
tHIGH
–
µs
fTWCK > 100 kHz
tHIGH
–
µs
fTWCK ≤ 100 kHz
tHIGH
–
µs
fTWCK > 100 kHz
tHIGH
–
µs
Note:
1. Required only for fTWCK > 100 kHz.
2.
CB = capacitance of one bus line in pF. Per I2C Standard, Cb Max = 400pF
3.
The TWCK low Period is defined as follows:Tlow = ((CLDIV x 2CKDIV) + 4) x TMCK
4.
The TWCK high period is defined as follows: THigh = ((CHDIV x 2CKDIV) + 4) x TMCK
5.
tCP_MCK = MCK Bus Period.
Figure 13-24. Two-wire Serial Bus Timing
tof
tHIGH
tLO W
tr
tLO W
TWCK
tSU;ST A
TWD
tHD;ST A
tHD;D AT
tSU;D AT
tSU;ST O
tB UF
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185
13.9.7 Embedded Flash Characteristics
The maximum operating frequency is given in Table 13-36 to Table 13-39 below but is limited by the Embedded Flash
access time when the processor is fetching code out of it. The tables below give the device maximum operating
frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required
to access the Embedded Flash Memory.
The embedded flash is fully tested during production test, the flash contents are not set to a known state prior to
shipment. Therefore, the flash contents should be erased prior to programming an application.
Table 13-36.
Table 13-37.
Embedded Flash Wait State VDDCORE set at 1.08V and VDDIO 1.62V to 3.6V @85C
FWS
Read Operations
Maximum Operating Frequency (MHz)
0
1 cycle
16
1
2 cycles
33
2
3 cycles
50
3
4 cycles
67
4
5 cycles
84
5
6 cycles
100
Embedded Flash Wait State VDDCORE set at 1.08V and VDDIO 2.7V to 3.6V @85C
FWS
Read Operations
Maximum Operating Frequency (MHz)
0
1 cycle
20
1
2 cycles
40
2
3 cycles
60
3
4 cycles
80
4
5 cycles
100
Atmel SAM4SP32A [PRELIMINARY datasheet]
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186
Table 13-38.
Table 13-39.
Embedded Flash Wait State VDDCORE set at 1.2V and VDDIO 1.62V to 3.6V @ 85C
FWS
Read Operations
Maximum Operating Frequency (MHz)
0
1 cycle
17
1
2 cycles
34
2
3 cycles
52
3
4 cycles
69
4
5 cycles
87
5
6 cycles
104
6
7 cycles
121
Embedded Flash Wait State VDDCORE set at 1.20V and VDDIO 2.7V to 3.6V @ 85C
FWS
Read Operations
Maximum Operating Frequency (MHz)
0
1 cycle
21
1
2 cycles
42
2
3 cycles
63
3
4 cycles
84
4
5 cycles
105
5
6 cycles
123
Atmel SAM4SP32A [PRELIMINARY datasheet]
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187
Table 13-40.
AC Flash Characteristics
Parameter
Typ
Max
Units
Erase page mode
10
50
ms
Erase block mode (by 4Kbytes)
50
200
ms
Erase sector mode
400
950
ms
Full Chip Erase
1 MBytes
512 KBytes
9
5.5
18
11
s
Data Retention
Not Powered or Powered
20
Endurance
Write/Erase cycles per page, block
or sector @ 25°C
Write/Erase cycles per page, block
or sector @ 85°C
Program Cycle Time
Conditions
Min
Years
100K
cycles
10K
Atmel SAM4SP32A [PRELIMINARY datasheet]
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13.10 Recommended Operating Conditions
Table 13-41.
SAM4SP32A Recommended Operating Conditions
Rating
Parameter
Symbol
Unit
Min
Typ
Max
VVDDCORE
1.08
1.20
1.32
VVDDIN
3.00
3.30
3.60
VVDDIO
3.00
3.30
3.60
VVDDPLL
1.08
--
1.32
AVDD
3.00
3.30
3.60
Junction Temperature
TJ
-40
25
+125
Ambient Temperature
TA
-40
--
+85
Supply Voltage
V
ºC
Atmel SAM4SP32A [PRELIMINARY datasheet]
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14.
Mechanical Characteristics
Figure 14-1. 128-lead LQFP Package Mechanical Drawing
Atmel SAM4SP32A [PRELIMINARY datasheet]
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15.
Ordering Information
Table 15-1. Atmel SAM4SP32A Ordering Codes
Atmel Ordering Code
Package
Package Type
Temperature Range
ATSAM4SP32A-ANU-Y
128 LQFP
Pb-Free
Industrial (-40ºC to 85º)
A T S A M 4 S P 3 2 A - A N U - Y x x
Atmel Designator
Customer marking
AT=Atmel
Product Family
Shipping Carrier Option
Y = Tray
Device Designator
P=Power Line Communications
Flash Size
32=2MBytes (2x1024KB, dual bank)
Device Revision
A=PRIME 1.3.6 compliant
Package Device Grade or
Wafer/Die Thickness
U = Lead free (Pb-free)
Industrial temperature range
(-40°C to +85°C)
Package Option
AN = 128LQFP
Atmel SAM4SP32A [PRELIMINARY datasheet]
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16.
Revision History
Doc. Rev.
Date
Comments
A
10/2012
Initial release
Atmel SAM4SP32A [PRELIMINARY datasheet]
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