MCP79410/MCP79411/MCP79412 Battery-Backed I2C™ Real-Time Clock/Calendar with SRAM, EEPROM and Protected EEPROM Device Selection Table Operating Ranges: MCP79410 Unprogrammed MCP79411 EUI-48™ • 2-Wire Serial Interface, I2C™ Compatible: - I2C clock rate up to 400 kHz • Temperature Range: - Industrial (I): -40°C to +85°C MCP79412 EUI-64™ Packages: Part Number Protected EEPROM Timekeeping Features: • Real-Time Clock/Calendar (RTCC): - Hours, minutes, seconds, day of week, day, month, year - Leap year compensated to 2399 - 12/24-hour modes • Oscillator for 32.768 kHz Crystals: - Optimized for 6-9 pF crystals • On-Chip Digital Trimming/Calibration: - ±1 ppm resolution - ±129 ppm range • Dual Programmable Alarms • Versatile Output Pin: - Clock output with selectable frequency - Alarm output - General purpose output • Power-Fail Time-Stamp: - Time logged on switchover to and from Battery mode Low-Power Features: • Wide Voltage Range: - Operating voltage range of 1.8V to 5.5V - Backup voltage range of 1.3V to 5.5V • Low Typical Timekeeping Current: - Operating from VCC: 1.2 µA at 3.3V - Operating from VBAT: 925 nA at 3.0V • Automatic Switchover to Battery Backup User Memory: • 64-byte Battery-Backed SRAM • 1 Kbit EEPROM Memory: - Software write-protect - Page write up to 8 bytes - Endurance: 1M Erase/Write cycles • 64-bit Protected EEPROM Area: - Robust write unlock sequence - EUI-48™ MAC address (MCP79411) - EUI-64™ MAC address (MCP79412) 2010-2015 Microchip Technology Inc. • 8-Lead SOIC, MSOP, TSSOP and 2x3 TDFN General Description: The MCP7941X Real-Time Clock/Calendar (RTCC) tracks time using internal counters for hours, minutes, seconds, days, months, years, and day of week. Alarms can be configured on all counters up to and including months. For usage and configuration, the MCP7941X supports I2C communications up to 400 kHz. The open-drain, multi-functional output can be configured to assert on an alarm match, to output a selectable frequency square wave or as a general purpose output. The MCP7941X is designed to operate using a 32.768 kHz tuning fork crystal with external crystal load capacitors. On-chip digital trimming can be used to adjust for frequency variance caused by crystal tolerance and temperature. SRAM and timekeeping circuitry are powered from the backup supply when main power is lost, allowing the device to maintain accurate time and the SRAM contents. The times when the device switches over to the back-up supply and when primary power returns are both logged by the power-fail time-stamp. The MCP7941X features 1 Kbit of internal nonvolatile EEPROM with software write-protectable regions. There is an additional 64 bits of protected nonvolatile memory which is only writable after an unlock sequence, making it ideal for storing a unique ID or other critical information. The MCP79411 and MCP79412 are pre-programmed with EUI-48 and EUI-64 addresses, respectively. Custom programming is also available. Package Types SOIC, TSSOP, MSOP TDFN X1 1 8 VCC X2 2 7 MFP X2 2 7 MFP VBAT 3 6 SCL VBAT 3 6 SCL VSS 4 5 SDA VSS 4 5 SDA X1 1 8 VCC DS20002266G-page 1 MCP79410/MCP79411/MCP79412 FIGURE 1-1: TYPICAL APPLICATION SCHEMATIC VCC VCC VCC 8 VCC 6 PIC® MCU 5 7 SCL SDA X2 MFP VBAT 2 CX2 M 3 VBAT VSS 4 FIGURE 1-2: CX1 1 32.768 KHZ X1 BLOCK DIAGRAM VCC VSS Power Control and Switchover Power-Fail Time-Stamp VBAT SCL SDA Control Logic I2C™ Interface and Addressing Configuration Seconds SRAM EEPROM Minutes X1 32.768 kHz Oscillator Hours Clock Divider X2 Day of Week Digital Trimming Date Square Wave Output Alarms Month Year MFP DS20002266G-page 2 Output Logic 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs (except SDA and SCL) w.r.t. VSS .....................................................................-0.6V to VCC +1.0V SDA and SCL w.r.t. VSS ............................................................................................................................... -0.6V to 6.5V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. Symbol No. Characteristic Electrical Characteristics: Industrial (I): VCC = +1.8V to 5.5V Min. Typ.(2) Max. Units TA = -40°C to +85°C Conditions D1 VIH High-level Input Voltage 0.7 VCC — — V D2 VIL Low-level Input Voltage — — 0.3 VCC V VCC 2.5V D3 VHYS 0.05 VCC — — V (Note 1) D4 VOL Low-level Output Voltage (MFP, SDA pins) — — 0.40 V IOL = 3.0 mA; VCC = 4.5V ILI Input Leakage Current — — D6 ILO Output Leakage Current — D7 CIN Pin Capacitance (SDA, SCL, MFP pins) — D8 COSC Oscillator Pin Capacitance (X1, X2 pins) 0.2 VCC D5 COUT Hysteresis of Schmitt Trigger Inputs (SDA, SCL pins) VCC < 2.5V IOL = 2.1 mA; VCC = 2.5V ±1 A — ±1 A VOUT = VSS or VCC — 10 pF VCC = 5.0V (Note 1) — 3 — pF (Note 1) VIN = VSS or VCC TA = 25°C, f = 1 MHz D9 Icceerd EEPROM Operating Icceewr Current — — 400 A VCC = 5.5V, SCL = 400 kHz 3 mA VCC = 5.5V D10 Iccread SRAM/RTCC Register Iccwrite Operating Current — — 300 A VCC = 5.5V, SCL = 400 kHz — — D11 Iccdat VCC Data-retention Current (oscillator off) 400 VCC = 5.5V, SCL = 400 kHz 1 A SCL, SDA, VCC = 5.5V VCC = 3.3V (Note 1) D12 Icct Timekeeping Current — 1.2 — A D13 VTRIP Power-fail Switchover Voltage 1.3 1.5 1.7 V D14 VBAT Backup Supply Voltage Range 1.3 — 5.5 V Note 1: 2: (Note 1) This parameter is not tested but ensured by characterization. Typical measurements taken at room temperature. 2010-2015 Microchip Technology Inc. DS20002266G-page 3 MCP79410/MCP79411/MCP79412 DC CHARACTERISTICS (Continued) Param. Symbol No. D15 D16 Note 1: 2: IBATT IBATDAT Characteristic Timekeeping Backup Current VBAT Data Retention Current (oscillator off) Electrical Characteristics: Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Min. Typ.(2) Max. Units — — 850 nA 925 1200 VBAT = 3.0V, VCC = VSS (Note 1) — 9000 VBAT = 5.5V, VCC = VSS (Note 1) — 750 — nA Conditions VBAT = 1.3V, VCC = VSS (Note 1) VBAT = 3.6V, VCC = VSS This parameter is not tested but ensured by characterization. Typical measurements taken at room temperature. DS20002266G-page 4 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. Symbol No. 1 FCLK Characteristic Clock Frequency Electrical Characteristics: Industrial (I): VCC = +1.8V to 5.5V Min. Typ. Max. Units — — 100 kHz THIGH Clock High Time 4000 — — ns Tlow Clock Low Time 4700 — — ns 5 6 Tr Tf SDA and SCL Rise Time (Note 1) — SDA and SCL Fall Time (Note 1) — Thd:sta Start Condition Hold Time — 1000 ns — 1000 ns — — Tsu:sta Start Condition Setup Time 4700 1.8V VCC < 2.5V 1.8V VCC < 2.5V 2.5V VCC 5.5V 300 ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 600 7 1.8V VCC < 2.5V 2.5V VCC 5.5V 300 4000 1.8V VCC < 2.5V 2.5V VCC 5.5V 1300 4 1.8V VCC < 2.5V 2.5V VCC 5.5V 600 3 Conditions 2.5V VCC 5.5V 400 2 TA = -40°C to +85°C — — ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 600 8 Thd:dat Data Input Hold Time 0 — — ns (Note 3) 9 Tsu:dat Data Input Setup Time 250 — — ns 1.8V VCC < 2.5V 10 Tsu:sto Stop Condition Setup Time 4000 — — ns 1.8V VCC < 2.5V 11 Taa Output Valid from Clock — — 3500 ns 1.8V VCC < 2.5V 12 Tbuf Bus Free Time: Bus time must be free before a new transmission can start 4700 — ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 100 2.5V VCC 5.5V 600 2.5V VCC 5.5V 900 — 2.5V VCC 5.5V 1300 13 Tsp Input Filter Spike Suppression (SDA and SCL pins) — — 50 ns 14 Twc Write Cycle Time (byte or page) — — 5 ms 15 Tfvcc VCC Fall Time 300 — — s (Note 1) 16 Trvcc VCC Rise Time 0 — — s (Note 1) 17 Fosc Oscillator Frequency — 32.768 — kHz 18 Tosf Oscillator Timeout Period 1 — — ms 19 — 1M — — Note 1: 2: 3: Endurance (Note 1) (Note 1) cycles Page Mode, 25°C, VCC = 5.5V (Note 2) Not 100% tested. This parameter is not tested but ensured by characterization. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2010-2015 Microchip Technology Inc. DS20002266G-page 5 MCP79410/MCP79411/MCP79412 I2C™ BUS TIMING DATA FIGURE 1-3: 5 SCL 7 SDA In D3 2 3 8 9 4 10 6 13 12 11 SDA Out FIGURE 1-4: POWER SUPPLY TRANSITION TIMING VCC VTRIP(MAX) VTRIP(MIN) 15 DS20002266G-page 6 16 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 2.0 TYPICAL PERFORMANCE CURVE Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data represented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. IBATT Current (µA) FIGURE 2-1: 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.30 TIMEKEEPING BACKUP CURRENT VS. BACKUP SUPPLY VOLTAGE TA = -40°C TA = 25°C TA = 85°C -40 25 85 1.90 2.50 3.10 3.70 4.30 4.90 5.50 VBAT Voltage (V) 2010-2015 Microchip Technology Inc. DS20002266G-page 7 MCP79410/MCP79411/MCP79412 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Name X1 X2 VBAT Vss SDA SCL MFP Vcc Note: 3.1 PIN FUNCTION TABLE 8-pin SOIC 8-pin MSOP 8-pin TSSOP 8-pin TDFN Function 1 1 1 1 Quartz Crystal Input, External Oscillator Input 2 2 2 2 Quartz Crystal Output 3 3 3 3 Battery Backup Supply Input 4 4 4 4 Ground 5 5 5 5 Bidirectional Serial Data (I2C™) 6 6 6 6 Serial Clock (I2C) 7 7 7 7 Multifunction Pin 8 8 8 8 Primary Power Supply Exposed pad on TFDN can be connected to Vss or left floating. Oscillator Input/Output (X1, X2) These pins are used as the connections for an external 32.768 kHz quartz crystal and load capacitors. X1 is the crystal oscillator input and X2 is the output. The MCP7941X is designed to allow for the use of external load capacitors in order to provide additional flexibility when choosing external crystals. The MCP7941X is optimized for crystals with a specified load capacitance of 6-9 pF. 3.5 Multifunction Pin (MFP) This is an output pin used for the alarm and square wave output functions. It can also serve as a general purpose output pin by controlling the OUT bit in the CONTROL register. The MFP is an open-drain output and requires a pull-up resistor to VCC (typically 10 k). This pin may be left floating if not used. X1 also serves as the external clock input when the MCP7941X is configured to use an external oscillator. 3.2 Backup Supply (VBAT) This is the input for a backup supply to maintain the RTCC and SRAM registers during the time when VCC is unavailable. If the battery backup feature is not being used, the VBAT pin should be connected to VSS. 3.3 Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typically 10 k for 100 kHz, 2 k for 400 kHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 3.4 Serial Clock (SCL) This input is used to synchronize the data transfer to and from the device. DS20002266G-page 8 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 4.0 I2C BUS CHARACTERISTICS 4.1.1.4 4.1 I2C Interface The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The MCP7941X supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data is defined as receiver. The bus has to be controlled by a master device which generates the Start and Stop conditions, while the MCP7941X works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device. 4.1.1.5 4.1.1 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Note 1: The MCP7941X does not generate an Acknowledge in response to an EEPROM control byte if an internal EEPROM programming cycle is in progress, but the SRAM and RTCC registers can still be accessed. 2: The I2C interface is disabled while operating from the backup power supply. Bus Not Busy (A) Both data and clock lines remain high. 4.1.1.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.1.1.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition. FIGURE 4-1: (A) Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1.1.1 Data Valid (D) A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (MCP7941X) will leave the data line high to enable the master to generate the Stop condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA 2010-2015 Microchip Technology Inc. Data Allowed to Change Stop Condition DS20002266G-page 9 MCP79410/MCP79411/MCP79412 FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 SDA 8 9 1 2 3 D D Transmitter must release the SDA line at this point allowing the Receiver must release the SDA line at this point Receiver to pull the SDA line low to acknowledge the previous so the Transmitter can continue sending data. eight bits of data. 4.1.2 DEVICE ADDRESSING The control byte is the first byte received following the Start condition from the master device (Figure 4-3). The control byte begins with a 4-bit control code. For the MCP7941X, this is set as ‘1010’ for EEPROM read and write operations, and ‘1101’ for SRAM/RTCC register read and write operations. The next three bits are non-configurable Chip Select bits that must always be set to ‘1’. FIGURE 4-3: Acknowledge Bit Read/Write Bit Start Bit DS20002266G-page 10 Chip Select Bits Control Code S 1 The last bit of the control byte defines the operation to be performed. When set to a ‘1’ a read operation is selected, and when set to a ‘0’ a write operation is selected. The combination of the 4-bit control code and the three Chip Select bits is called the slave address. Upon receiving a valid slave address, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the MCP7941X will select a read or a write operation. CONTROL BYTE FORMAT 1 0 1 1 1 1 R/W ACK RTCC Register/SRAM Control Byte OR EEPROM Control Byte S 1 0 1 0 1 1 1 R/W ACK Slave Address 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 5.0 FUNCTIONAL DESCRIPTION The MCP7941X is a highly-integrated Real-Time Clock/Calendar (RTCC). Using an on-board, low-power oscillator, the current time is maintained in seconds, minutes, hours, day of week, date, month, and year. The MCP7941X also features 64 bytes of general purpose SRAM, 1 Kbit of EEPROM and eight bytes of protected EEPROM. Two alarm modules allow interrupts to be generated at specific times with flexible comparison options. Digital trimming can be used to compensate for inaccuracies inherent with crystals. Using the backup supply input and an integrated power switch, the MCP7941X will automatically switch to backup power when primary power is unavailable, allowing the current time and the SRAM contents to be maintained. The time-stamp module captures the time when primary power is lost and when it is restored. The RTCC configuration and STATUS registers are used to access all of the modules featured on the MCP7941X. 2010-2015 Microchip Technology Inc. 5.1 Memory Organization The MCP7941X features four different blocks of memory: the RTCC registers, general purpose SRAM, 1 Kbit EEPROM with software write-protect, and protected EEPROM. The RTCC registers and SRAM share the same address space, accessed through the ‘1101111X’ control byte. The EEPROM regions are in a separate address space and are accessed using the ‘1010111X’ control byte (Figure 5-1). Unused locations are not accessible. The MCP7941X will not acknowledge if the address is out of range, as shown in the shaded region of the memory map in Figure 5-1. The RTCC registers are contained in addresses 0x00-0x1F. Table 5-1 shows the detailed RTCC register map. There are 64 bytes of user-accessible SRAM, located in the address range 0x20-0x5F. The SRAM is a separate block from the RTCC registers. All RTCC registers and SRAM locations are maintained while operating from backup power. The EEPROM space is located in addresses 0x00-0x7F while the protected EEPROM section is located in addresses 0xF0-0xF7. A STATUS register, used to protect regions of the EEPROM section, is located at address 0xFF. DS20002266G-page 11 MCP79410/MCP79411/MCP79412 FIGURE 5-1: MEMORY MAP RTCC Registers/SRAM EEPROM 0x00 0x00 Time and Date 0x06 0x07 0x09 0x0A Configuration and Trimming Alarm 0 EEPROM (128 Bytes) 0x10 0x11 Alarm 1 0x17 0x18 Power-Fail/Power-Up Time-Stamps 0x1F 0x20 SRAM (64 Bytes) 0x7F 0x80 Unimplemented; device does not ACK 0x5F 0x60 0xEF 0xF0 Unimplemented; device does not ACK Protected EEPROM (8 Bytes) EUI-48/EUI-64 Node Address 0xF7 0xF8 0xFE 0xFF 0xFF I2C™ Address: 1101111x DS20002266G-page 12 Unimplemented; device does not ACK STATUS Register I2C™ Address: 1010111x 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 TABLE 5-1: DETAILED RTCC REGISTER MAP Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Section 5.3 “Timekeeping” 00h RTCSEC ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 01h RTCMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 02h RTCHOUR — 12/24 AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 03h RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 04h RTCDATE — — 05h RTCMTH — — LPYR MTHTEN0 MTHONE3 MTHONE2 MTHONE1 06h RTCYEAR YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 07h CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 SIGN TRIMVAL6 TRIMVAL5 TRIMVAL4 TRIMVAL3 TRIMVAL2 TRIMVAL1 TRIMVAL0 DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 MTHONE0 08h OSCTRIM 09h EEUNLOCK 0Ah ALM0SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 0Bh ALM0MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 0Ch ALM0HOUR — 12/24(2) AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 ALM0IF WKDAY2 WKDAY1 WKDAY0 Protected EEPROM Unlock Register (not a physical register) Section 5.4 “Alarms” 0Dh ALM0WKDAY 0Eh ALM0DATE ALMPOL — ALM0MSK2 ALM0MSK1 ALM0MSK0 — 0Fh ALM0MTH — — 10h Reserved DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 Reserved – Do not use Section 5.4 “Alarms” 11h ALM1SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 12h ALM1MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 13h ALM1HOUR — 12/24(2) AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 14h ALM1WKDAY ALM1IF WKDAY2 WKDAY1 WKDAY0 15h ALM1DATE — — 16h ALM1MTH — — 17h Reserved ALMPOL(3) ALM1MSK2 ALM1MSK1 ALM1MSK0 DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 Reserved – Do not use Section 5.7.1 “Power-Fail Time-Stamp” Power-Down Time Stamp 18h PWRDNMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 19h PWRDNHOUR — 12/24 AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 1Ah PWRDNDATE — — 1Bh PWRDNMTH WKDAY2 WKDAY1 1Ch PWRUPMIN — MINTEN2 MINTEN1 1Dh PWRUPHOUR — 12/24 AM/PM HRTEN1 DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 Power-Up Time Stamp 1Eh PWRUPDATE — — 1Fh PWRUPMTH WKDAY2 WKDAY1 Note 1: 2: 3: DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 Grey areas are unimplemented. The 12/24 bits in the ALMxHOUR registers are read-only and reflect the value of the 12/24 bit in the RTCHOUR register. The ALMPOL bit in the ALM1WKDAY register is read-only and reflects the value of the ALMPOL bit in the ALM0WKDAY register. 2010-2015 Microchip Technology Inc. DS20002266G-page 13 MCP79410/MCP79411/MCP79412 5.2 Oscillator Configuration EQUATION 5-1: The MCP7941X can be operated in two different oscillator configurations: using an external crystal or using an external clock input. 5.2.1 Figure 5-2 shows the pin connections when using an external crystal. FIGURE 5-2: CRYSTAL OPERATION MCP7941X X1 CX 1 To Internal Logic Quartz Crystal ST X2 CX 2 Note 1: The ST bit must be set to enable the crystal oscillator circuit. 2: Always verify oscillator performance over the voltage and temperature range that is expected for the application. 5.2.1.1 Choosing Load Capacitors CL is the effective load capacitance as seen by the crystal, and includes the physical load capacitors, pin capacitance, and stray board capacitance. Equation 5-1 can be used to calculate CL. CX1 and CX2 are the external load capacitors. They must be chosen to match the selected crystal’s specified load capacitance. Note: C X1 C X2 C L = -------------------------- + C STRAY CX1 + CX2 EXTERNAL CRYSTAL The crystal oscillator circuit on the MCP7941X is designed to operate with a standard 32.768 kHz tuning fork crystal and matching external load capacitors. By using external load capacitors, the MCP7941X allows for a wide selection of crystals. Suitable crystals have a load capacitance (CL) of 6-9 pF. Crystals with a load capacitance of 12.5 pF are not recommended. LOAD CAPACITANCE CALCULATION Where: C L = Effective load capacitance C X1 = Capacitor value on X1 + C OSC C X2 = Capacitor value on X2 + C OSC C STRAY = PCB stray capacitance 5.2.1.2 Layout Considerations The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to VSS. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in Figure 5-3. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): • AN1365, “Recommended Usage of Microchip Serial RTCC Devices” • AN1519, “Recommended Crystals for Microchip Stand-Alone Real-Time Clock Calendar Devices” If the load capacitance is not correctly matched to the chosen crystal’s specified value, the crystal may give a frequency outside of the crystal manufacturer’s specifications. DS20002266G-page 14 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 FIGURE 5-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Single-Sided and In-line Layouts: Copper Pour (tied to ground) Fine-Pitch (Dual-Sided) Layouts: Oscillator Crystal Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) X1 X1 CX1 CX1 X2 GND CX2 Oscillator Crystal GND CX2 ` X2 DEVICE PINS DEVICE PINS 5.2.2 EXTERNAL CLOCK INPUT 5.2.3 A 32.768 kHz external clock source can be connected to the X1 pin (Figure 5-4). When using this configuration, the X2 pin should be left floating. Note: The EXTOSC bit must be set to enable an external clock source. FIGURE 5-4: EXTERNAL CLOCK INPUT OPERATION OSCILLATOR FAILURE STATUS The MCP7941X features an oscillator failure flag, OSCRUN, that indicates whether or not the oscillator is running. The OSCRUN bit is automatically set after 32 oscillator cycles are detected. If no oscillator cycles are detected for more than TOSF, then the OSCRUN bit is automatically cleared (Figure 5-5). This can occur if the oscillator is stopped by clearing the ST bit or due to oscillator failure. X1 Clock from Ext. Source FIGURE 5-5: OSCILLATOR FAILURE STATUS TIMING DIAGRAM X1 32 Clock Cycles TOSF < TOSF OSCRUN Bit TABLE 5-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH OSCILLATOR CONFIGURATION Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RTCSEC ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 19 OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 27 CONTROL Legend: Bit 1 Bit 0 Register on Page Bit 7 SECONE1 SECONE0 17 — = unimplemented location, read as ‘0’. Shaded cells are not used by oscillator configuration. 2010-2015 Microchip Technology Inc. DS20002266G-page 15 MCP79410/MCP79411/MCP79412 5.3 Timekeeping The MCP7941X maintains the current time and date using an external 32.768 kHz crystal or clock source. Separate registers are used for tracking seconds, minutes, hours, day of week, date, month, and year. The MCP7941X automatically adjusts for months with less than 31 days and compensates for leap years from 2001 to 2399. The year is stored as a two-digit value. Both 12-hour and 24-hour time formats are supported and are selected using the 12/24 bit. The day of week value counts from 1 to 7, increments at midnight, and the representation is user-defined (i.e., the MCP7941X does not require 1 to equal Sunday, etc.). All time and date values are stored in the registers as binary-coded decimal (BCD) values. The MCP7941X will continue to maintain the time and date while operating off the backup supply. When reading from the timekeeping registers, the registers are buffered to prevent errors due to rollover of counters. The following events cause the buffers to be updated: • When a read is initiated from the RTCC registers (addresses 0x00 to 0x1F) • During an RTCC register read operation, when the register address rolls over from 0x1F to 0x00 The timekeeping registers should be read in a single operation to utilize the on-board buffers and avoid rollover issues. Note 1: Loading invalid values into the time and date registers will result in undefined operation. 5.3.1 DIGIT CARRY RULES The following list explains which timer values cause a digit carry when there is a rollover: • Time of day: from 11:59:59 PM to 12:00:00 AM (12-hour mode) or 23:59:59 to 00:00:00 (24-hour mode), with a carry to the Date and Weekday fields • Date: carries to the Month field according to Table 5-3 • Weekday: from 7 to 1 with no carry • Month: from 12/31 to 01/01 with a carry to the Year field • Year: from 99 to 00 with no carry TABLE 5-3: Month DAY TO MONTH ROLLOVER SCHEDULE Name Maximum Date 01 January 31 02 February 28 or 29(1) 03 March 31 04 April 30 05 May 31 06 June 30 07 July 31 08 August 31 09 September 30 10 October 31 11 November 30 12 December 31 Note 1: 29 during leap years, otherwise 28. 2: To avoid rollover issues when loading new time and date values, the oscillator/clock input should be disabled by clearing the ST bit for External Crystal mode and the EXTOSC bit for External Clock Input mode. After waiting for the OSCRUN bit to clear, the new values can be loaded and the ST or EXTOSC bit can then be re-enabled. DS20002266G-page 16 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 REGISTER 5-1: RTCSEC: TIMEKEEPING SECONDS VALUE REGISTER (ADDRESS 0x00) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 ST: Start Oscillator bit 1 = Oscillator enabled 0 = Oscillator disabled bit 6-4 SECTEN<2:0>: Binary-Coded Decimal Value of Second’s Tens Digit Contains a value from 0 to 5 bit 3-0 SECONE<3:0>: Binary-Coded Decimal Value of Second’s Ones Digit Contains a value from 0 to 9 REGISTER 5-2: RTCMIN: TIMEKEEPING MINUTES VALUE REGISTER (ADDRESS 0x01) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary-Coded Decimal Value of Minute’s Tens Digit Contains a value from 0 to 5 bit 3-0 MINONE<3:0>: Binary-Coded Decimal Value of Minute’s Ones Digit Contains a value from 0 to 9 2010-2015 Microchip Technology Inc. x = Bit is unknown DS20002266G-page 17 MCP79410/MCP79411/MCP79412 REGISTER 5-3: RTCHOUR: TIMEKEEPING HOURS VALUE REGISTER (ADDRESS 0x02) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — 12/24 AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown If 12/24 = 1 (12-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour TIme Format bit 1 = 12-hour format 0 = 24-hour format bit 5 AM/PM: AM/PM Indicator bit 1 = PM 0 = AM bit 4 HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 1 bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 If 12/24 = 0 (24-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour TIme Format bit 1 = 12-hour format 0 = 24-hour format bit 5-4 HRTEN<1:0>: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 2 bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 DS20002266G-page 18 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 REGISTER 5-4: RTCWKDAY: TIMEKEEPING WEEKDAY VALUE REGISTER (ADDRESS 0x03) U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 OSCRUN: Oscillator Status bit 1 = Oscillator is enabled and running 0 = Oscillator has stopped or has been disabled bit 4 PWRFAIL: Power Failure Status bit(1, 2) 1 = Primary power was lost and the power-fail time-stamp registers have been loaded (must be cleared in software). Clearing this bit resets the power-fail time-stamp registers to ‘0’. 0 = Primary power has not been lost bit 3 VBATEN: External Battery Backup Supply (VBAT) Enable bit 1 = VBAT input is enabled 0 = VBAT input is disabled bit 2-0 WKDAY<2:0>: Binary-Coded Decimal Value of Day of Week Contains a value from 1 to 7. The representation is user-defined. Note 1: 2: The PWRFAIL bit must be cleared to log new time-stamp data. This is to ensure previous time-stamp data is not lost. The PWRFAIL bit cannot be written to a ‘1’ in software. Writing to the RTCWKDAY register will always clear the PWRFAIL bit. REGISTER 5-5: RTCDATE: TIMEKEEPING DATE VALUE REGISTER (ADDRESS 0x04) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DATETEN<1:0>: Binary-Coded Decimal Value of Date’s Tens Digit Contains a value from 0 to 3 bit 3-0 DATEONE<3:0>: Binary-Coded Decimal Value of Date’s Ones Digit Contains a value from 0 to 9 2010-2015 Microchip Technology Inc. x = Bit is unknown DS20002266G-page 19 MCP79410/MCP79411/MCP79412 REGISTER 5-6: RTCMTH: TIMEKEEPING MONTH VALUE REGISTER (ADDRESS 0x05) U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — LPYR MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 LPYR: Leap Year bit 1 = Year is a leap year 0 = Year is not a leap year bit 4 MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit Contains a value of 0 or 1 bit 3-0 MTHONE<3:0>: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value from 0 to 9 REGISTER 5-7: RTCYEAR: TIMEKEEPING YEAR VALUE REGISTER (ADDRESS 0x06) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear bit 7-4 x = Bit is unknown YRTEN<3:0>: Binary-Coded Decimal Value of Year’s Tens Digit Contains a value from 0 to 9 bit 4 YRONE<3:0>: Binary-Coded Decimal Value of Year’s Ones Digit Contains a value from 0 to 9 TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH TIMEKEEPING Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RTCSEC ST SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 17 RTCMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 17 RTCHOUR — 12/24 AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 18 RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 19 RTCDATE — — Name DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 19 RTCMTH — — LPYR MTHTEN0 MTHONE3 MTHONE2 MTHONE‘ MTHONE0 20 RTCYEAR YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 27 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in timekeeping. DS20002266G-page 20 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 5.4 Alarms TABLE 5-5: ALARM MASKS The MCP7941X features two independent alarms. Each alarm can be used to either generate an interrupt at a specific time in the future, or to generate a periodic interrupt every minute, hour, day, day of week, or month. ALMxMSK<2:0> Alarm Asserts on Match of 000 Seconds 001 Minutes There is a separate interrupt flag, ALMxIF, for each alarm. The interrupt flags are set by hardware when the chosen alarm mask condition matches (Table 5-5). The interrupt flags must be cleared in software. 010 Hours 011 Day of Week If either alarm module is enabled by setting the corresponding ALMxEN bit in the CONTROL register, and if the square wave clock output is disabled (SQWEN = 0), then the MFP will operate in Alarm Interrupt Output mode. Refer to Section 5.5 “Output Configurations” for details. The alarm interrupt output is available while operating from the backup power supply. Reserved 110 Reserved 111 Seconds, Minutes, Hours, Day of Week, Date, and Month 2: Loading invalid values into the alarm registers will result in undefined operation. Throughout this section, references to the register and bit names for the alarm modules are referred to generically by the use of ‘x’ in place of the specific module number. Thus, “ALMxSEC” might refer to the seconds register for Alarm0 or Alarm1. FIGURE 5-6: Date 101 Note 1: The alarm interrupt flags must be cleared by the user. If a flag is cleared while the corresponding alarm condition still matches, the flag will be set again, generating another interrupt. Both Alarm0 and Alarm1 offer identical operation. All time and date values are stored in the registers as binary-coded decimal (BCD) values. Note: 100 ALARM BLOCK DIAGRAM Alarm0 Registers Timekeeping Registers Alarm1 Registers ALM0SEC RTCSEC ALM1SEC ALM0MIN RTCMIN ALM1MIN ALM0HOUR RTCHOUR ALM1HOUR ALM0WKDAY RTCWKDAY ALM1WKDAY ALM0DATE RTCDATE ALM1DATE ALM0MTH RTCMTH ALM1MTH Alarm0 Mask Comparator Comparator Set ALM0IF ALM0MSK<2:0> 2010-2015 Microchip Technology Inc. MFP Output Logic Alarm1 Mask Set ALM1IF MFP ALM1MSK<2:0> DS20002266G-page 21 MCP79410/MCP79411/MCP79412 5.4.1 CONFIGURING THE ALARM In order to configure the alarm modules, the following steps need to be performed: 1. 2. 3. 4. 5. 6. Load the timekeeping registers and enable the oscillator Configure the ALMxMSK<2:0> bits to select the desired alarm mask Set or clear the ALMPOL bit according to the desired output polarity Ensure the ALMxIF flag is cleared Based on the selected alarm mask, load the alarm match value into the appropriate register(s) Enable the alarm module by setting the ALMxEN bit REGISTER 5-8: ALMxSEC: ALARM0/1 SECONDS VALUE REGISTER (ADDRESSES 0x0A/0x11) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary-Coded Decimal Value of Second’s Tens Digit Contains a value from 0 to 5 bit 3-0 SECONE<3:0>: Binary-Coded Decimal Value of Second’s Ones Digit Contains a value from 0 to 9 REGISTER 5-9: ALMxMIN: ALARM0/1 MINUTES VALUE REGISTER (ADDRESSES 0x0B/0x12) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary-Coded Decimal Value of Minute’s Tens Digit Contains a value from 0 to 5 bit 3-0 MINONE<3:0>: Binary-Coded Decimal Value of Minute’s Ones Digit Contains a value from 0 to 9 DS20002266G-page 22 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 REGISTER 5-10: ALMxHOUR: ALARM0/1 HOURS VALUE REGISTER (ADDRESSES 0x0C/0x13) U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — 12/24 AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown If 12/24 = 1 (12-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit(1) 1 = 12-hour format 0 = 24-hour format bit 5 AM/PM: AM/PM Indicator bit 1 = PM 0 = AM bit 4 HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 1 bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 If 12/24 = 0 (24-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit(1) 1 = 12-hour format 0 = 24-hour format bit 5-4 HRTEN<1:0>: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 Note 1: This bit is read-only and reflects the value of the 12/24 bit in the RTCHOUR register. 2010-2015 Microchip Technology Inc. DS20002266G-page 23 MCP79410/MCP79411/MCP79412 REGISTER 5-11: ALMxWKDAY: ALARM0/1 WEEKDAY VALUE REGISTER (ADDRESSES 0x0D/0x14) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 ALMPOL ALMxMSK2 ALMxMSK1 ALMxMSK0 ALMxIF WKDAY2 WKDAY1 WKDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 ALMPOL: Alarm Interrupt Output Polarity bit 1 = Asserted output state of MFP is a logic high level 0 = Asserted output state of MFP is a logic low level bit 6-4 ALMxMSK<2:0>: Alarm Mask bits 000 = Seconds match 001 = Minutes match 010 = Hours match (logic takes into account 12-/24-hour operation) 011 = Day of week match 100 = Date match 101 = Reserved; do not use 110 = Reserved; do not use 111 = Seconds, Minutes, Hour, Day of Week, Date and Month bit 3 ALMxIF: Alarm Interrupt Flag bit(1,2) 1 = Alarm match occurred (must be cleared in software) 0 = Alarm match did not occur bit 2-0 WKDAY<2:0>: Binary-Coded Decimal Value of Day bits Contains a value from 1 to 7. The representation is user-defined. Note 1: 2: If a match condition still exists when this bit is cleared, it will be set again automatically. The ALMxIF bit cannot be written to a 1 in software. Writing to the ALMxWKDAY register will always clear the ALMxIF bit. REGISTER 5-12: ALMxDATE: ALARM0/1 DATE VALUE REGISTER (ADDRESSES 0x0E/0x15) U-0 U-0 R/W-0 — — DATETEN1 R/W-0 R/W-0 DATETEN0 DATEONE3 R/W-0 R/W-0 R/W-1 DATEONE2 DATEONE1 DATEONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DATETEN<1:0>: Binary-Coded Decimal Value of Date’s Tens Digit Contains a value from 0 to 3 bit 3-0 DATEONE<3:0>: Binary-Coded Decimal Value of Date’s Ones Digit Contains a value from 0 to 9 DS20002266G-page 24 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 REGISTER 5-13: ALMxMTH: ALARM0/1 MONTH VALUE REGISTER (ADDRESSES 0x0F/0x16) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit Contains a value of 0 or 1 bit 3-0 MTHONE<3:0>: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value from 0 to 9 TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH ALARMS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ALM0SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 22 ALM0MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 22 ALM0HOUR — 12/24 AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 23 Name ALMPOL ALM0MSK2 ALM0MSK1 ALM0MSK0 ALM0IF WKDAY2 WKDAY1 WKDAY0 24 ALM0DATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 24 ALM0MTH — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 25 ALM1SEC — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 22 ALM1MIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 22 ALM1HOUR — 12/24 AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 23 ALM0WKDAY ALMPOL ALM1MSK2 ALM1MSK1 ALM1MSK0 ALM1IF WKDAY2 WKDAY1 WKDAY0 24 ALM1DATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 24 ALM1MTH — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 25 CONTROL OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 27 ALM1WKDAY Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by alarms. 2010-2015 Microchip Technology Inc. DS20002266G-page 25 MCP79410/MCP79411/MCP79412 5.5 TABLE 5-7: Output Configurations SQWEN ALM0EN ALM1EN The MCP7941X features Square Wave Clock Output, Alarm Interrupt Output, and General Purpose Output modes. All of the output functions are multiplexed onto MFP according to Table 5-7. Only the alarm interrupt outputs are available while operating from the backup power supply. If none of the output functions are being used, the MFP can safely be left floating. Note: MFP OUTPUT MODES 0 0 0 0 1 0 0 0 1 0 1 1 1 x x General Purpose Output Alarm Interrupt Output Square Wave Clock Output The MFP is an open-drain output and requires a pull-up resistor to VCC (typically 10 k). FIGURE 5-7: Mode MFP OUTPUT BLOCK DIAGRAM MCP7941X SQWFS<1:0> Oscillator 8.192 kHz X2 4.096 kHz Postscaler EXTOSC Digital Trim ST 1 Hz 11 10 01 00 64 Hz MUX 32.768 kHz X1 0 1 CRSTRIM ALM1EN,ALM0EN ALMPOL 11 10 0 01 OUT ALM0IF 1 1 00 MUX ALM1IF MFP 0 SQWEN 1 0 DS20002266G-page 26 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 REGISTER 5-14: CONTROL: RTCC CONTROL REGISTER (ADDRESS 0x07) R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear bit 7 x = Bit is unknown OUT: Logic Level for General Purpose Output bit Square Wave Clock Output mode (SQWEN = 1): Unused. Alarm Interrupt Output mode (ALM0EN = 1 or ALM1EN = 1): Unused. General Purpose Output mode (SQWEN = 0, ALM0EN = 0, and ALM1EN = 0): 1 = MFP signal level is logic high 0 = MFP signal level is logic low bit 6 SQWEN: Square Wave Output Enable bit 1 = Enable Square Wave Clock Output mode 0 = Disable Square Wave Clock Output mode bit 5 ALM1EN: Alarm 1 Module Enable bit 1 = Alarm 1 enabled 0 = Alarm 1 disabled bit 4 ALM0EN: Alarm 0 Module Enable bit 1 = Alarm 0 enabled 0 = Alarm 0 disabled bit 3 EXTOSC: External Oscillator Input bit 1 = Enable X1 pin to be driven by external 32.768 kHz source 0 = Disable external 32.768 kHz input bit 2 CRSTRIM: Coarse Trim Mode Enable bit Coarse Trim mode results in the MCP7941X applying digital trimming every 64 Hz clock cycle. 1 = Enable Coarse Trim mode. If SQWEN = 1, MFP will output trimmed 64 Hz(1) nominal clock signal. 0 = Disable Coarse Trim mode See Section 5.6 “Digital Trimming” for details bit 1-0 SQWFS<1:0>: Square Wave Clock Output Frequency Select bits If SQWEN = 1 and CRSTRIM = 0: Selects frequency of clock output on MFP 00 = 1 Hz(1) 01 = 4.096 kHz(1) 10 = 8.192 kHz(1) 11 = 32.768 kHz If SQWEN = 0 or CRSTRIM = 1: Unused. Note 1: The 8.192 kHz, 4.096 kHz, 64 Hz, and 1 Hz square wave clock output frequencies are affected by digital trimming. 2010-2015 Microchip Technology Inc. DS20002266G-page 27 MCP79410/MCP79411/MCP79412 5.5.1 SQUARE WAVE OUTPUT MODE The MCP7941X can be configured to generate a square wave clock signal on MFP. The input clock frequency, FOSC, is divided according to the SQWFS<1:0> bits as shown in Table 5-8. The square wave output is not available when operating from the backup power supply. Note: All of the clock output rates are affected by digital trimming except for the 1:1 postscaler value (SQWFS<1:0> = 00). 5.5.2.2 When both alarm modules are enabled, the MFP output is determined by a combination of the ALM0IF, ALM1IF, and ALMPOL flags. If ALMPOL = 1, the ALM0IF and ALM1IF flags are OR’d together and the result is output on MFP. If ALMPOL = 0, the ALM0IF and ALM1IF flags are AND’d together, and the result is inverted and output on MFP (Table 5-10). This provides the user with flexible options for combining alarms. Note: TABLE 5-8: CLOCK OUTPUT RATES SQWFS<1:0> Postscaler Nominal Frequency(1) 00 1:1 32.768 kHz 01 1:4 8.192 kHz 10 1:8 4.096 kHz 11 1:32,768 1 Hz Note 1: 5.5.2 The ALMxIF flags control when the MFP is asserted, as described in the following sections. 5.5.2.1 Single Alarm Operation When only one alarm module is enabled, the MFP output is based on the corresponding ALMxIF flag and the ALMPOL flag. If ALMPOL = 1, the MFP output reflects the value of the ALMxIF flag. If ALMPOL = 0, the MFP output reflects the inverse of the ALMxIF flag (Table 5-9). TABLE 5-9: DUAL ALARM OUTPUT TRUTH TABLE ALMPOL ALM0IF ALM1IF MFP 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 ALARM INTERRUPT OUTPUT MODE The alarm interrupt output is available when operating from the backup power supply. If ALMPOL = 0 and both alarms are enabled, the MFP will only assert when both ALM0IF and ALM1IF are set. TABLE 5-10: Nominal frequency assumes FOSC is 32.768 kHz. The MFP will provide an interrupt output when enabled alarms match and the square wave clock output is disabled. This prevents the user from having to poll the alarm interrupt flag to check for a match. Dual Alarm Operation 5.5.3 GENERAL PURPOSE OUTPUT MODE If the square wave clock output and both alarm modules are disabled, the MFP acts as a general purpose output. The output logic level is controlled by the OUT bit. The general purpose output is not available when operating from the backup power supply. SINGLE ALARM OUTPUT TRUTH TABLE ALMPOL ALMxIF(1) MFP 0 0 1 0 1 0 1 0 0 1 1 1 Note 1: ALMxIF refers to the interrupt flag corresponding to the alarm module that is enabled. DS20002266G-page 28 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 TABLE 5-11: SUMMARY OF REGISTERS ASSOCIATED WITH OUTPUT CONFIGURATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ALM0WKDAY ALMPOL ALM0MSK2 ALM0MSK1 ALM0MSK0 ALM0IF WKDAY2 WKDAY1 WKDAY0 24 ALM1WKDAY ALMPOL ALM1MSK2 ALM1MSK1 ALM1MSK0 ALM1IF WKDAY2 WKDAY1 WKDAY0 24 OUT SQWEN ALM1EN ALM0EN EXTOSC CRSTRIM SQWFS1 SQWFS0 27 Name CONTROL Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in output configuration. 2010-2015 Microchip Technology Inc. DS20002266G-page 29 MCP79410/MCP79411/MCP79412 5.6 Digital Trimming The MCP7941X features digital trimming to correct for inaccuracies of the external crystal or clock source, up to roughly ±129 ppm when CRSTRIM = 0. In addition to compensating for intrinsic inaccuracies in the clock, this feature can also be used to correct for error due to temperature variation. This can enable the user to achieve high levels of accuracy across a wide temperature operating range. Digital trimming consists of the MCP7941X periodically adding or subtracting clock cycles, resulting in small adjustments in the internal timing. The adjustment occurs once per minute when CRSTRIM = 0. The SIGN bit specifies whether to add cycles or to subtract them. The TRIMVAL<6:0> bits are used to specify by how many clock cycles to adjust. Each step in the TRIMVAL<6:0> value equates to adding or subtracting two clock pulses to or from the 32.768 kHz clock signal. This results in a correction of roughly 1.017 ppm per step when CRSTRIM = 0. Setting TRIMVAL<6:0> to 0x00 disables digital trimming. Digital trimming also occurs while operating off the backup supply. . REGISTER 5-15: OSCTRIM: OSCILLATOR DIGITAL TRIM REGISTER (ADDRESS 0x08) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SIGN TRIMVAL6 TRIMVAL5 TRIMVAL4 TRIMVAL3 TRIMVAL2 TRIMVAL1 TRIMVAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear bit 7 SIGN: Trim Sign bit 1 = Add clocks to correct for slow time 0 = Subtract clocks to correct for fast time bit 6-0 TRIMVAL<6:0>: Oscillator Trim Value bits When CRSTRIM = 0: 1111111 = Add or subtract 254 clock cycles every minute 1111110 = Add or subtract 252 clock cycles every minute • • • 0000010 = Add or subtract 4 clock cycles every minute 0000001 = Add or subtract 2 clock cycles every minute 0000000 = Disable digital trimming x = Bit is unknown When CRSTRIM = 1: 1111111 = Add or subtract 254 clock cycles 128 times per second 1111110 = Add or subtract 252 clock cycles 128 times per second • • • 0000010 = Add or subtract 4 clock cycles 128 times per second 0000001 = Add or subtract 2 clock cycles 128 times per second 0000000 = Disable digital trimming DS20002266G-page 30 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 5.6.1 CALIBRATION In order to perform calibration, the number of error clock pulses per minute must be found and the corresponding trim value must be loaded into TRIMVAL<6:0>. There are two methods for determining the trim value. The first method involves measuring an output frequency directly and calculating the deviation from ideal. The second method involves observing the number of seconds gained or lost over a period of time. Once the OSCTRIM register has been loaded, digital trimming will automatically occur every minute. 5.6.1.1 5.6.1.2 Calibration by Observing Time Deviation To calibrate the MCP7941X by observing the deviation over time, perform the following steps: 1. 2. 3. 4. Calibration by Measuring Frequency Ensure TRIMVAL<6:0> is reset to 0x00. Load the timekeeping registers to synchronize the MCP7941X with a known-accurate reference time. Enable the crystal oscillator or external clock input by setting the ST bit or EXTOSC bit, respectively. Observe how many seconds are gained or lost over a period of time (larger time periods offer more accuracy). Calculate the PPM deviation (see Equation 5-3). To calibrate the MCP7941X by measuring the output frequency, perform the following steps: 5. 1. EQUATION 5-3: 2. 3. 4. 5. 6. Enable the crystal oscillator or external clock input by setting the ST bit or EXTOSC bit, respectively. Ensure TRIMVAL<6:0> is reset to 0x00. Select an output frequency by setting SQWFS<1:0>. Set SQWEN to enable the square wave output. Measure the resulting output frequency using a calibrated measurement tool, such as a frequency counter. Calculate the number of error clocks per minute (see Equation 5-2). EQUATION 5-2: CALCULATING TRIM VALUE FROM MEASURED FREQUENCY 32768 F IDEAL – F MEAS ------------------- 60 F IDEAL TRIMVAL<6:0> = --------------------------------------------------------------------------------2 SecDeviation PPM = ----------------------------------- 1000000 ExpectedSec Where: ExpectedSec = Number of seconds in chosen period SecDeviation = Number of seconds gained or lost • If the MCP7941X has gained time relative to the reference clock, then the oscillator is faster than ideal and the SIGN bit must be cleared. • If the MCP7941X has lost time relative to the reference clock, then the oscillator is slower than ideal and the SIGN bit must be set. 6. Calculate the trim value (see Equation 5-4). EQUATION 5-4: Where: Note: CALCULATING TRIM VALUE FROM ERROR PPM PPM 32768 60 TRIMVAL<6:0> = ------------------------------------------1000000 2 F IDEAL = Ideal frequency based on SQWFS<1:0> F MEAS = Measured frequency • If the number of error clocks per minute is negative, then the oscillator is faster than ideal and the SIGN bit must be cleared. • If the number of error clocks per minute is positive, then the oscillator is slower than ideal and the SIGN bit must be set. 7. Load the correct value into TRIMVAL<6:0>. CALCULATING ERROR PPM 7. Load the correct value into TRIMVAL<6:0>. Note 1: Choosing a longer time period for observing deviation will improve accuracy. 2: Large temperature variations during the observation period can skew results. Using a lower output frequency and/or averaging the measured frequency over a number of clock pulses will reduce the effects of jitter and improve accuracy. 2010-2015 Microchip Technology Inc. DS20002266G-page 31 MCP79410/MCP79411/MCP79412 5.6.2 COARSE TRIM MODE When CRSTRIM = 1, Coarse Trim mode is enabled. While in this mode, the MCP7941X will apply trimming at a rate of 128 Hz. If SQWEN is set, the MFP will output a trimmed 64 Hz nominal clock signal. Because trimming is applied at a rate of 128 Hz rather than once every minute, each step of the TRIMVAL<6:0> value has a significantly larger effect on the resulting time deviation and output clock frequency. TABLE 5-12: Name Note 1: The 64 Hz Coarse Trim mode square wave output is not available while operating from the backup power supply. 2: With Coarse Trim mode enabled, the TRIMVAL<6:0> value has a drastic effect on timing. Leaving the mode enabled during normal operation will likely result in inaccurate time. SUMMARY OF REGISTERS ASSOCIATED WITH DIGITAL TRIMMING Bit 7 CONTROL OUT OSCTRIM SIGN Legend: By monitoring the MFP output frequency while in this mode, the user can easily observe the TRIMVAL<6:0> value affecting the clock timing. Bit 6 Bit 5 Bit 4 SQWEN ALM1EN ALM0EN TRIMVAL6 TRIMVAL5 TRIMVAL4 Bit 3 Bit 2 EXTOSC CRSTRIM TRIMVAL3 TRIMVAL2 Bit 1 Bit 0 Register on Page SQWFS1 SQWFS0 27 TRIMVAL1 TRIMVAL0 30 — = unimplemented location, read as ‘0’. Shaded cells are not used by digital trimming. DS20002266G-page 32 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 5.7 5.7.1 Battery Backup The MCP7941X features a backup power supply input (VBAT) that can be used to provide power to the timekeeping circuitry, RTCC registers, and SRAM while primary power is unavailable. The MCP7941X will automatically switch to backup power when VCC falls below VTRIP, and back to VCC when it is above VTRIP. The MCP7941X includes a power-fail time-stamp module that stores the minutes, hours, date, and month when primary power is lost and when it is restored (Figure 5-8). The PWRFAIL bit is also set to indicate that a power failure occurred. Note: The VBATEN bit must be set to enable the VBAT input. The following functionality operating on backup power: • • • • • is maintained while Timekeeping Alarms Alarm Output Digital Trimming RTCC Register and SRAM Contents The following features are not available while operating on backup power: • • • Throughout this section, references to the register and bit names for the Power-Fail Time-Stamp module are referred to generically by the use of ‘x’ in place of the specific module name. Thus, “PWRxxMIN” might refer to the minutes register for Power-Down or Power-Up. To utilize the power-fail time-stamp feature, a backup power supply must be available with the VBAT input enabled, and the oscillator should also be running to ensure accurate functionality. I2C Communication Square Wave Clock Output General Purpose Output FIGURE 5-8: POWER-FAIL TIME-STAMP Note 1: The PWRFAIL bit must be cleared to log new time-stamp data. This is to ensure previous time-stamp data is not lost. 2: Clearing the PWRFAIL bit will clear all time-stamp registers. POWER-FAIL TIME-STAMP TIMING VCC VTRIP Power-Down Time-Stamp 2010-2015 Microchip Technology Inc. Power-Up Time-Stamp DS20002266G-page 33 MCP79410/MCP79411/MCP79412 REGISTER 5-16: PWRxxMIN: POWER-DOWN/POWER-UP TIME-STAMP MINUTES VALUE REGISTER (ADDRESSES 0x18/0x1C) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary-Coded Decimal Value of Minute’s Tens Digit Contains a value from 0 to 5 bit 3-0 MINONE<3:0>: Binary-Coded Decimal Value of Minute’s Ones Digit Contains a value from 0 to 9 REGISTER 5-17: PWRxxHOUR: POWER-DOWN/POWER-UP TIME-STAMP HOURS VALUE REGISTER (ADDRESSES 0x19/0x1D) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — 12/24 AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown If 12/24 = 1 (12-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit 1 = 12-hour format 0 = 24-hour format bit 5 AM/PM: AM/PM Indicator bit 1 = PM 0 = AM bit 4 HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 1 bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 If 12/24 = 0 (24-hour format): bit 7 Unimplemented: Read as ‘0’ bit 6 12/24: 12 or 24 Hour Time Format bit 1 = 12-hour format 0 = 24-hour format bit 5-4 HRTEN<1:0>: Binary-Coded Decimal Value of Hour’s Tens Digit Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary-Coded Decimal Value of Hour’s Ones Digit Contains a value from 0 to 9 DS20002266G-page 34 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 REGISTER 5-18: PWRxxDATE: POWER-DOWN/POWER-UP TIME-STAMP DATE VALUE REGISTER (ADDRESSES 0x1A/0x1E) U-0 U-0 R/W-0 — — DATETEN1 R/W-0 R/W-0 DATETEN0 DATEONE3 R/W-0 R/W-0 R/W-0 DATEONE2 DATEONE1 DATEONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DATETEN<1:0>: Binary-Coded Decimal Value of Date’s Tens Digit Contains a value from 0 to 3 bit 3-0 DATEONE<3:0>: Binary-Coded Decimal Value of Date’s Ones Digit Contains a value from 0 to 9 REGISTER 5-19: PWRxxMTH: POWER-DOWN/POWER-UP TIME-STAMP MONTH VALUE REGISTER (ADDRESSES 0x1B/0x1F) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown bit 7-5 WKDAY<2:0>: Binary-Coded Decimal Value of Day bits Contains a value from 1 to 7. The representation is user-defined. bit 4 MTHTEN0: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value of 0 or 1 bit 3-0 MTHONE<3:0>: Binary-Coded Decimal Value of Month’s Ones Digit Contains a value from 0 to 9 TABLE 5-13: Name SUMMARY OF REGISTERS ASSOCIATED WITH BATTERY BACKUP Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RTCWKDAY — — OSCRUN PWRFAIL VBATEN WKDAY2 WKDAY1 WKDAY0 19 PWRDNMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 34 PWRDNHOUR — 12/24 AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 34 PWRDNDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 35 PWRDNMTH WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 35 PWRUPMIN — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 34 PWRUPHOUR — 12/24 AM/PM HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 34 PWRUPDATE — — DATETEN1 DATETEN0 DATEONE3 DATEONE2 DATEONE1 DATEONE0 35 PWRUPMTH WKDAY2 WKDAY1 WKDAY0 MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 35 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used with battery backup. 2010-2015 Microchip Technology Inc. DS20002266G-page 35 MCP79410/MCP79411/MCP79412 6.0 ON-BOARD MEMORY Therefore, the next byte transmitted by the master is the address and will be written into the Address Pointer of the MCP7941X. After receiving another Acknowledge bit from the MCP7941X, the master device transmits the data byte to be written into the addressed memory location. The MCP7941X stores the data byte into memory and acknowledges again, and the master generates a Stop condition (Figure 6-1). The MCP7941X has 1 Kbits (128 bytes) of EEPROM, eight bytes of protected EEPROM for storing crucial information, and 64 bytes of SRAM for general purpose usage. The SRAM is retained when the primary power supply is removed if a backup supply is present and enabled. Since the EEPROM is nonvolatile, it does not require a supply for data retention. Although the SRAM is a separate block from the RTCC registers, they are accessed using the same control byte, ‘1101111X’. The EEPROM is in a different address space and requires the use of a different control byte, ‘1010111X’. RTCC and SRAM can be accessed for reads or writes immediately after starting an EEPROM write cycle. If an attempt is made to write to an address past 0x5F, the MCP7941X will not acknowledge the address or data bytes, and no data will be written. After a byte Write command, the internal Address Pointer will point to the address location following the one that was just written. 6.1.2 6.1 SRAM/RTCC Registers The write control byte, address, and the first data byte are transmitted to the MCP7941X in the same way as in a byte write. But instead of generating a Stop condition, the master transmits additional data bytes. Upon receipt of each byte, the MCP7941X responds with an Acknowledge, during which the data is latched into memory and the Address Pointer is internally incremented by one. As with the byte write operation, the master ends the command by generating a Stop condition (Figure 6-2). The RTCC registers are located at addresses 0x00 to 0x1F, and the SRAM is located at addresses 0x20 to 0x5F. The SRAM can be accessed while the RTCC registers are being internally updated. The SRAM is not initialized by a Power-On Reset (POR). Neither the RTCC registers nor the SRAM can be accessed when the device is operating off the backup power supply. 6.1.1 SRAM/RTCC REGISTER BYTE WRITE There is no limit to the number of bytes that can be written in a single command. However, because the RTCC registers and SRAM are separate blocks, writing past the end of each block will cause the Address Pointer to roll over to the beginning of the same block. Specifically, the Address Pointer will roll over from 0x1F to 0x00, and from 0x5F to 0x20. Following the Start condition from the master, the control code and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address byte will follow after it has generated an Acknowledge bit during the ninth clock cycle. FIGURE 6-1: SRAM/RTCC BYTE WRITE BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY DS20002266G-page 36 SRAM/RTCC REGISTER SEQUENTIAL WRITE S T A R T CONTROL BYTE ADDRESS BYTE S1 1 01111 0 S T O P DATA P 0 A C K A C K A C K 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 FIGURE 6-2: SRAM/RTCC SEQUENTIAL WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S11 0 11110 CONTROL BYTE A C K SRAM/RTCC REGISTER CURRENT ADDRESS READ Upon receipt of the control byte with R/W bit set to ‘1’, the MCP7941X issues an Acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the MCP7941X discontinues transmission (Figure 6-3). The Address Pointer is shared between the SRAM/RTCC registers and the EEPROM. FIGURE 6-3: SRAM/RTCC CURRENT ADDRESS READ S T BUS ACTIVITY A CONTROL MASTER BYTE R T SDA LINE S 1 1 0 1 1 1 1 1 BUS ACTIVITY 6.1.4 S T O P DATA BYTE P A C K DATA BYTE N DATA BYTE 0 P The MCP7941X contains an address counter that maintains the address of the last byte accessed, internally incremented by one. Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Note: S T O P 0 A C K BUS ACTIVITY 6.1.3 ADDRESS BYTE A C K A C K transmission (Figure 6-4). After a random Read command, the internal address counter will point to the address location following the one that was just read. 6.1.5 SRAM/RTCC REGISTER SEQUENTIAL READ Sequential reads are initiated in the same way as a random read except that after the MCP7941X transmits the first data byte, the master issues an Acknowledge as opposed to the Stop condition used in a random read. This Acknowledge directs the MCP7941X to transmit the next sequentially addressed 8-bit word (Figure 6-5). Following the final byte transmitted to the master, the master will NOT generate an Acknowledge but will generate a Stop condition. To provide sequential reads, the MCP7941X contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory block to be serially read during one operation. Because the RTCC registers and SRAM are separate blocks, reading past the end of each block will cause the Address Pointer to roll over to the beginning of the same block. Specifically, the Address Pointer will roll over from 0x1F to 0x00, and from 0x5F to 0x20. N O A C K SRAM/RTCC REGISTER RANDOM READ Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the address must be set. This is done by sending the address to the MCP7941X as part of a write operation (R/W bit set to ‘0’). After the address is sent, the master generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then, the master issues the control byte again but with the R/W bit set to a ‘1’. The MCP7941X will then issue an Acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but it does generate a Stop condition which causes the MCP7941X to discontinue 2010-2015 Microchip Technology Inc. DS20002266G-page 37 MCP79410/MCP79411/MCP79412 FIGURE 6-4: SRAM/RTCC RANDOM READ BUS ACTIVITY MASTER SDA LINE S T A R T CONTROL BYTE S1 1 0 1 1 1 1 0 BUS ACTIVITY MASTER CONTROL BYTE S 1 1 0 1 1 1 1 1 P N O A C K A C K SRAM/RTCC SEQUENTIAL READ CONTROL BYTE DATA n DATA n + 1 DATA n + 2 DS20002266G-page 38 S T O P DATA n + X P SDA LINE BUS ACTIVITY S T O P DATA BYTE A C K A C K BUS ACTIVITY FIGURE 6-5: S T A R T ADDRESS BYTE A C K A C K A C K A C K N O A C K 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 6.2 EEPROM TABLE 6-1: The MCP7941X features 1 Kbits of EEPROM organized in 8-byte pages with software write protection configured through the STATUS register. 6.2.1 STATUS REGISTER The STATUS register contains bits BP<1:0> which are used to set the block write protection for the EEPROM array. The STATUS register is a nonvolatile Control register in the EEPROM address space at location 0xFF. The STATUS register is accessed using control byte '1010111X'. Setting the BP<1:0> bits in the STATUS register determines which regions are protected in the EEPROM array per Table 6-1. BLOCK PROTECTION BP1 BP0 Array Addresses Write-Protected 0 0 None 0 1 Upper 1/4 (60h-7Fh) 1 0 Upper 1/2 (40h-7Fh) 1 1 All (00h-7Fh) If multiple bytes are loaded to the STATUS register, only the last byte is written. The write to the STATUS register is initiated by the I2C Stop condition. REGISTER 6-1: STATUS: EEPROM BLOCK PROTECTION CONTROL REGISTER (ADDRESS 0XFF) U U U U R/W-0 R/W-0 U U — — — — BP1 BP0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BP<1:0>: EEPROM Array Block Protection bits bit 1-0 Unimplemented: Read as ‘0’ 6.2.2 EEPROM BYTE WRITE Following the Start condition from the master, the control code and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address byte will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the address and will be written into the Address Pointer of the MCP7941X. After receiving another Acknowledge bit from the MCP7941X, the master device transmits the data byte to be written into the addressed memory location. The MCP7941X acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and, during this time, the MCP7941X does not generate Acknowledge signals for EEPROM commands. Access to the RTCC registers and SRAM is still possible during an EEPROM write cycle. 2010-2015 Microchip Technology Inc. X = Bit is unknown If an attempt is made to write to an address outside of the defined regions, the MCP7941X will not acknowledge the address or data bytes, no data will be written, and the device will immediately accept a new command. After a Byte Write command, the internal Address Pointer will point to the address location following the one that was just written. DS20002266G-page 39 MCP79410/MCP79411/MCP79412 6.2.3 EEPROM SEQUENTIAL WRITE word, the three lower Address Pointer bits are internally incremented by one. If the master should transmit more than eight bytes prior to generating the Stop condition, the address counter will roll over and the data received previously will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-7). The write control byte, word address, and the first data byte are transmitted to the MCP7941X in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to seven additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a Stop condition. After receipt of each FIGURE 6-6: EEPROM BYTE WRITE BUS ACTIVITY MASTER SDA LINE S T A R T CONTROL BYTE S1 0 10111 0 P A C K A C K EEPROM PAGE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S10 1 01110 BUS ACTIVITY DS20002266G-page 40 S T O P DATA 0 A C K BUS ACTIVITY FIGURE 6-7: ADDRESS BYTE CONTROL BYTE ADDRESS BYTE S T O P DATA BYTE 7 DATA BYTE 0 0 A C K P A C K A C K A C K 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 6.2.4 ACKNOWLEDGE POLLING Note: Since the device will not acknowledge an EEPROM control byte during an internal EEPROM write cycle, this can be used to determine when the cycle is complete. This feature can be used to maximize bus throughput. Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK, and the master can then proceed with the next Read or Write command. See Figure 6-8 for the flow diagram. FIGURE 6-8: For added systems robustness, it is recommended that time-out functionality be implemented in the acknowledge polling routine to avoid potentially hanging the system by entering an infinite loop. This can easily be done by designing in a maximum number of loops the routine will execute, or through the use of a hardware timer. If a time out occurs, polling should be aborted by sending a Stop condition. A user-generated error-handling routine can then be called, allowing the system to recover in a manner appropriate for the application. ACKNOWLEDGE POLLING FLOW Send EEPROM Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? NO* YES Next Operation Note*: For added system robustness, implement time-out checking to avoid a potential infinite loop. 2010-2015 Microchip Technology Inc. DS20002266G-page 41 MCP79410/MCP79411/MCP79412 6.2.5 EEPROM CURRENT ADDRESS READ MCP7941X as part of a write operation (R/W bit set to ‘0’). After the address is sent, the master generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then, the master issues the control byte again but with the R/W bit set to a ‘1’. The MCP7941X will then issue an Acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but it does generate a Stop condition which causes the MCP7941X to discontinue transmission (Figure 6-10). After a random Read command, the internal address counter will point to the address location following the one that was just read. The MCP7941X contains an address counter that maintains the address of the last byte accessed, internally incremented by one. Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to ‘1’, the MCP7941X issues an Acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition, and the MCP7941X discontinues transmission (Figure 6-9). Note: FIGURE 6-9: S T A R T SDA LINE S 1 0 1 0 1 1 1 1 S T O P DATA BYTE CONTROL BYTE P A C K BUS ACTIVITY N O A C K EEPROM RANDOM READ Random read operations allow the master to access any EEPROM location in a random manner. To perform this type of read operation, first the address must be set. This is done by sending the address to the FIGURE 6-10: EEPROM RANDOM READ BUS ACTIVITY MASTER SDA LINE S T A R T CONTROL BYTE BUS ACTIVITY MASTER S T A R T ADDRESS BYTE S1 0 1 0 1 1 1 0 CONTROL BYTE S T O P DATA BYTE S 1 0 1 0 1 1 1 1 A C K BUS ACTIVITY FIGURE 6-11: EEPROM SEQUENTIAL READ Sequential reads are initiated in the same way as a random read except that after the MCP7941X transmits the first data byte, the master issues an Acknowledge as opposed to the Stop condition used in a random read. This Acknowledge directs the MCP7941X to transmit the next sequentially addressed 8-bit word (Figure 6-11). Following the final byte transmitted to the master, the master will NOT generate an Acknowledge but will generate a Stop condition. To provide sequential reads, the MCP7941X contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire EEPROM block to be serially read during one operation. The internal Address pointer will automatically roll over from address 0x7F to address 0x00 if the master acknowledges the byte received from address 0x7F. EEPROM CURRENT ADDRESS READ BUS ACTIVITY MASTER 6.2.6 6.2.7 The Address Pointer is shared between the SRAM/RTCC registers and the EEPROM. A C K P N O A C K A C K EEPROM SEQUENTIAL READ CONTROL BYTE DATA n DATA n + 1 DATA n + 2 S T O P DATA n + X P SDA LINE BUS ACTIVITY DS20002266G-page 42 A C K A C K A C K A C K N O A C K 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 6.3 6.3.1 Protected EEPROM The MCP7941X features a 64-bit protected EEPROM block that requires a special unlock sequence to be followed in order to write to the memory. Note that reading from the memory does not require the unlock sequence to be performed. The protected EEPROM can be used for storing crucial information such as a unique serial number. The MCP79411 and MCP79412 include an EUI-48 and EUI-64 node address, respectively, pre-programmed into the protected EEPROM block. Custom programming is also available. The protected EEPROM block requires a special unlock sequence to prevent unintended writes, utilizing the EEUNLOCK register. The EEUNLOCK register is not a physical register; it is used exclusively in the EEPROM write sequence. Reading from EEUNLOCK will read all 0’s. To unlock the block, the following sequence must be followed: 1. 2. 3. The protected EEPROM block is located at addresses 0xF0 to 0xF7 and is accessed using the ‘1010111X’ control byte. Note: PROTECTED EEPROM UNLOCK SEQUENCE Write 0x55 to the EEUNLOCK register Write 0xAA to the EEUNLOCK register Write the desired data bytes to the EEPROM Figure 6-12 illustrates the sequence. Note 1: Diverging from any step of the unlock sequence may result in the EEPROM remaining locked and the write operation being ignored. Attempts to access invalid addresses (Figure 5-1) will result in the MCP7941X not acknowledging the address. 2: Unlocking the EEPROM is not required in order to read from the memory. The entire EEPROM block does not have to be written in a single operation. However, the block is locked after each write operation and must be unlocked again to start a new Write command. FIGURE 6-12: 1. Write 0x55 to EEUNLOCK Register PROTECTED EEPROM UNLOCK AND SEQUENTIAL WRITE S T A R T BUS ACTIVITY MASTER SDA LINE CONTROL BYTE S 11011110 S T A R T BUS ACTIVITY MASTER SDA LINE CONTROL BYTE S 110 1111 0 S T BUS ACTIVITY A R MASTER T SDA LINE BUS ACTIVITY 2010-2015 Microchip Technology Inc. S T O P 00001001 0 1 0 1 0 10 1 P A C K CONTROL BYTE DATA S T O P 00001001 10101010 P A C K ADDRESS BYTE S101 0111 0 A C K ADDRESS BYTE A C K BUS ACTIVITY 3. Write Data to EEPROM DATA A C K BUS ACTIVITY 2. Write 0xAA to EEUNLOCK Register ADDRESS BYTE A C K DATA BYTE 0 S T O P DATA BYTE n P 11110 A C K A C K A C K A C K DS20002266G-page 43 MCP79410/MCP79411/MCP79412 6.4 The MCP79411 and MCP79412 are programmed at the factory with a globally unique node address stored in the protected EEPROM block. 6.4.1 EUI-48™ NODE ADDRESS (MCP79411) The 6-byte EUI-48™ node address value of the MCP79411 is stored in EEPROM locations 0xF2 through 0xF7, as shown in Figure 6-13. The first three bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. The remaining three bytes are the Extension Identifier, and are generated by Microchip to ensure a globally-unique, 48-bit value. Note: 6.4.1.1 EUI-64™ NODE ADDRESS (MCP79412) 6.4.2 Pre-Programmed EUI-48™ or EUI-64™ Node Address The 8-byte EUI-64™ node address value of the MCP79412 is stored in array locations 0xF0 through 0xF7, as shown in Figure 6-14. The first three bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. The remaining five bytes are the Extension Identifier, and are generated by Microchip to ensure a globally-unique, 64-bit value Note: Currently, Microchip's OUIs are 0x0004A3, 0x001EC0 and 0xD88039, though this will change as addresses are exhausted. Note: In conformance with IEEE guidelines, Microchip will not use the values 0xFFFE and 0xFFFF for the first two bytes of the EUI-64 Extension Identifier. These two values are specifically reserved to allow applications to encapsulate EUI-48 addresses into EUI-64 addresses. . Currently, Microchip's OUIs are 0x0004A3, 0x001EC0 and 0xD88039, though this will change as addresses are exhausted. Eui-64™ Support Using The MCP79411 The pre-programmed EUI-48 node address of the MCP79411 can easily be encapsulated at the application level to form a globally unique, 64-bit node address for systems utilizing the EUI-64 standard. This is done by adding 0xFFFE between the OUI and the Extension Identifier, as shown below. Note: As an alternative, the MCP79412 features an EUI-64 node address that can be used in EUI-64 applications directly without the need for encapsulation, thereby simplifying system software. See Section 6.4.2 “Eui-64™ Node Address (MCP79412)” for details. FIGURE 6-13: Description EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (MCP79411) 24-bit Organizationally Unique Identifier Data 00h Array Address F2h 04h A3h 24-bit Extension Identifier 12h 34h 56h F7h Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56 Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56 DS20002266G-page 44 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 FIGURE 6-14: Description EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (MCP79412) 24-bit Organizationally Unique Identifier Data 00h Array Address F0h 04h A3h 40-bit Extension Identifier 12h 34h 56h 78h 90h F7h Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90 2010-2015 Microchip Technology Inc. DS20002266G-page 45 MCP79410/MCP79411/MCP79412 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead SOIC (3.90 mm) Example: XXXXXXXT XXXXYYWW NNN 79410I SN e3 1406 13F Example: 8-Lead TSSOP XXXX 7941 TYWW I406 NNN 13F Example: 8-Lead MSOP XXXXXT 79410I YWWNNN 40613F 8-Lead 2x3 TDFN Example: XXX YWW NN AAP 303 13 1st Line Marking Codes Part Number SOIC TSSOP MSOP TDFN MCP79410 79410T 7941 79410T AAP MCP79411 79411T 9411 79411T AAQ MCP79412 79412T 9412 79412T AAR T = Temperature grade Legend: XX...X Y YY WW NNN e3 * Note: DS20002266G-page 46 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2015 Microchip Technology Inc. DS20002266G-page 47 MCP79410/MCP79411/MCP79412 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002266G-page 48 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 !"#$% & ! "#$%&"'"" ($) % *++&&&! !+$ 2010-2015 Microchip Technology Inc. DS20002266G-page 49 MCP79410/MCP79411/MCP79412 '(() '** !"'% & ! "#$%&"'"" ($) % *++&&&! !+$ D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 @" !" A!" E#!7 )(" AA88 E E EG H ( G3K L J;>? L %%($$"" 1 1; % )) 1 ; L 1; 1 G3N% 8 %%($N% 81 < J>? %%($A < <1 A A ; J ; A1 ; 18 O L O A%$"" L A%N% 7 1 L < & 1 (13"#%6)#!3'7#!#"7 %&% !" "%81% #%! %)" #" " %)" #" "" 6%1;!!"% < !" % 8=1; >?* >"!" 63#" && # " 8* )!" '#"#& # ') ) ! # "" & ?J> DS20002266G-page 50 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2015 Microchip Technology Inc. DS20002266G-page 51 MCP79410/MCP79411/MCP79412 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002266G-page 52 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2015 Microchip Technology Inc. DS20002266G-page 53 MCP79410/MCP79411/MCP79412 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002266G-page 54 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2015 Microchip Technology Inc. DS20002266G-page 55 MCP79410/MCP79411/MCP79412 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002266G-page 56 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 + , )-./0012 !"'+,% & ! "#$%&"'"" ($) % *++&&&! !+$ 2010-2015 Microchip Technology Inc. DS20002266G-page 57 MCP79410/MCP79411/MCP79412 APPENDIX A: REVISION HISTORY Revision F (03/2014) • Updated overall content for improved clarity • Added detailed descriptions of registers • Updated block diagram and application schematic. • Defined names for all bits and registers, and renamed the bits shown in Table 7-1 for clarification. • Renamed the DC characteristics shown in Table 7-2 for clarification. Revision A (10/2010) • Original release of this document. Revision B (03/2011) • Minor typographical edits • Added Appendix B: Device Errata. Revision C (07/2011) TABLE 7-1: • Updated Section 4.2.6 “Crystal Specs” • Revised Figure 4-4. Old Bit Name Revision D (12/2011) • Added DC/AC Char. Charts. Revision E (04/2013) • • • • Revised Features page Revised Schematic, Block Diagram Added detailed descriptions for Registers Minor updates to the overall content. TABLE 7-2: BIT NAME CHANGES New Bit Name OSCON OSCRUN VBAT PWRFAIL LP LPYR SQWE SQWEN ALM0 ALM0EN ALM1 ALM1EN RS0 SQWFS0 RS1 SQWFS1 RS2 CRSTRIM CALIBRATION TRIMVAL<6:0> ALM0POL ALMPOL ALM1POL ALMPOL ALM0C<2:0> ALM0MSK<2:0> ALM1C<2:0> ALM1MSK<2:0> DC CHARACTERISTIC NAME CHANGES Old Name Operating Current EEPROM Old Symbol ICC Read New Name EEPROM Operating Current ICC Write Operating Current SRAM ICC Read Standby Current ICCEERD ICCEEWR SRAM/RTCC Register Operating Current ICC Write Operating Current New Symbol ICCREAD ICCWRITE IVCC Timekeeping Current ICCT IBAT Timekeeping Backup Current IBATT ICCS VCC Data Retention Current (oscillator off) ICCDAT Revision G (01/2015) • Updated Section 6.4 • Updated Product Identification System. DS20002266G-page 58 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. 2010-2015 Microchip Technology Inc. DS20002266G-page 59 MCP79410/MCP79411/MCP79412 NOTES: DS20002266G-page 60 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering combination is listed below. PART NO. [X](1) X /XX Device Tape and Reel Option Temperature Range Package Device: MCP79410 = MCP79410T = MCP79411 = MCP79411T = MCP79412 = MCP79412T = 1.8V - 5.5V I2C™ Serial RTCC 1.8V - 5.5V I2C Serial RTCC (Tape and Reel) 1.8V - 5.5V I2C Serial RTCC, EUI-48TM 1.8V - 5.5V I2C Serial RTCC, EUI-48TM (Tape and Reel) 1.8V - 5.5V I2C Serial RTCC, EUI-64TM 1.8V - 5.5V I2C Serial RTCC, EUI-64TM (Tape and Reel) Tape and Reel Option: Blank = Standard packaging (tube or tray) T=Tape and Reel(1) Temperature Range: I = -40°C to +85°C Package: SN ST = = 8-Lead Plastic Small Outline (3.90 mm body) 8-Lead Plastic Thin Shrink Small Outline (4.4 mm) 8-Lead Plastic Micro Small Outline 8-Lead Plastic Dual Flat, No Lead MS = MNY(2) = Examples: a) MCP79410-I/SN: Industrial Temperature, SOIC package. b) MCP79410T-I/SN: Industrial Temperature, SOIC package, Tape and Reel. c) MCP79410T-I/MNY: Industrial Temperature, TDFN package, Tape and Reel. d) MCP79411-I/SN: Industrial Temperature, SOIC package, EUI-48TM. e) MCP79411-I/MS: Industrial Temperature MSOP package, EUI-48TM. f) MCP79412-I/SN: Industrial Temperature, SOIC package, EUI-64TM. g) MCP79412-I/ST: Industrial Temperature, TSSOP package, EUI-64TM. h) MCP79412T-I/ST: Industrial Temperature, TSSOP package, Tape and Reel, EUI-64TM. Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2: "Y" indicates a Nickel Palladium Gold (NiPdAu) finish. 2010-2015 Microchip Technology Inc. DS20002266G-page 61 MCP79410/MCP79411/MCP79412 NOTES: DS20002266G-page 62 2010-2015 Microchip Technology Inc. MCP79410/MCP79411/MCP79412 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2010-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-968-8 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2010-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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