Circuit Note CN-0374 Devices Connected/Referenced Circuits from the Lab® reference designs are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0374. ADL5380 400 MHz to 6000 MHz Quadrature Demodulator ADA4940-2 Ultralow Power, Low Distortion ADC Driver AD7903 Dual Differential 16-Bit, 1 MSPS PulSAR 12.0 mW ADC ADR435 Ultralow Noise XFET 5.0 V Voltage Reference with Current Sink and Source Capability RF-to-Bits Solution Offers Precise Phase and Magnitude Data to 6 GHz EVALUATION AND DESIGN SUPPORT CIRCUIT FUNCTION AND BENEFITS Circuit Evaluation Boards ADL5380 Evaluation Board (ADL5380-EVALZ) ADA4940-2 Evaluation Board (ADA4940-2ACP-EBZ) AD7903 Evaluation Board (EVAL-AD7903SDZ) System Demonstration Platform (EVAL-SDP-CB1Z) Design and Integration Files Schematics, Layout Files, Bill of Materials The circuit shown in Figure 1 precisely converts a 400 MHz to 6 GHz RF input signal to its corresponding digital magnitude and digital phase. The signal chain achieves 0° to 360° of phase measurement with 1° of accuracy at 900 MHz. The circuit uses a high performance quadrature demodulator, a dual differential amplifier, and a dual differential 16-bit, 1 MSPS successive approximation analog-to-digital converter (SAR ADC). 7.5V 5V 5V_REF ADR435 2.5V 5V RF 3 2 1 4 5 6 LO 100pF RFIP 100pF 3 499Ω I+ I– RFIN 2 4 5 1 6 100pF LOIP 0° 100pF LOIN 90° GND 249Ω 22Ω 249Ω 22Ω 2700pF 499Ω ZOUT = 50Ω ZIN = 500Ω VCM = 2.5V VCM = 2.5V 499Ω 249Ω VCM = 2.5V 22Ω Q+ Q– 2700pF 2700pF 249Ω 22Ω 2700pF ADA4940-2 Gv = 6dB AD7903 FULL SCALE = 10V p-p 12940-001 499Ω ADL5380 Gv = 5.36dB Figure 1. Simplified Receiver Subsystem for Magnitude and Phase Measurements (All Connections and Decoupling Not Shown) Rev. 0 Circuits from the Lab reference designs from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due toanycausewhatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2015 Analog Devices, Inc. All rights reserved. CN-0374 Circuit Note CIRCUIT DESCRIPTION Quadrature Demodulator A quadrature demodulator provides an in-phase (I) signal and a quadrature (Q) signal that are exactly 90° out of phase. The I and Q signals are vector quantities; therefore, the amplitude and phase shift of the received signal can be calculated using trigonometric identities, as shown in Figure 2. The local oscillator (LO) input is the original transmitted signal and the RF input is the received signal. The demodulator generates a sum and difference term. Both the RF and LO signals are at the exact same frequency, ωLO = ωRF, and therefore the high frequency sum term is filtered, while the difference term resides at dc. The received signal has a different phase (φRF) than that of the transmitted signal (φLO), and this phase shift can be represented as φLO − φRF. A real-world I/Q demodulator has many imperfections, including quadrature phase error, gain imbalance, and LO to RF leakage, all of which can degrade the quality of the demodulated signal. To select a demodulator, first determine the requirements for RF input frequency range, amplitude accuracy, and phase accuracy. Powered from a single 5 V supply, the ADL5380 demodulator accepts RF or IF input frequencies from 400 MHz to 6 GHz, making it ideal for the receiver signal chain. Configured to provide a 5.36 dB voltage conversion gain, the differential I and Q outputs of the ADL5380 can drive a 2.5 V p-p differential signal into a 500 Ω load. Its 10.9 dB noise figure (NF), 11.6 dBm firstorder intercept (IP1), and 29.7 dBm third-order intercept (IP3) at 900 MHz provide outstanding dynamic range; and its 0.07 dB amplitude balance and 0.2° phase balance achieve excellent demodulation accuracy. Manufactured using an advanced SiGe bipolar process, the ADL5380 is available in a tiny 4 mm × 4 mm, 24-lead LFCSP package. ADC Driver and High Resolution Precision ADC The excellent dynamic performance and adjustable output common-mode voltage of the ADA4940-2 fully differential dual amplifier make it ideal for driving high resolution, dual SAR ADCs. Powered from a single 5 V supply, the ADA4940-2 provides ±5 V differential outputs with a 2.5 V common-mode voltage. Configured to provide a gain of 2 (6 dB), it drives the ADC inputs to full-scale. The RC filter (22 Ω/2.7 nF) limits the noise and reduces the kickback coming from the capacitive digital-toanalog converter (DAC) at the ADC input. Manufactured using a proprietary SiGe complementary bipolar process, the ADA4940-2 is available in a tiny 4 mm × 4 mm, 24-lead LFCSP package. The AD7903 dual 16-bit, 1 MSPS SAR ADC offers excellent precision, with ±0.006% FS gain error and ±0.015 mV offset error. Operating from a single 2.5 V power supply, the AD7903 dissipates only 12 mW at 1 MSPS. The main goal of using a high resolution ADC is to achieve ±1° phase accuracy, especially when the input signal has a small dc amplitude. The 5 V reference required by the ADC is generated by the ADR435 low noise reference. LO COS (ωLOt + φLO) VI 2 + VQ 2 A VI = — COS (φRF – φLO) 2 COS (ωLOt + φLO) RF COS (ωRFt + φRF) VQ θ VI 0° 90° SIN (ωLOt + φLO) A VQ = — SIN (φRF – φLO) 2 MAGNITUDE = VI 2 + VQ 2 VQ PHASE = ARCTAN2 V I A Q = Acos(ωRF t + φRF) × sin(ωLO t + φLO) = — [sin(ωRFt – ωLOt + φRF – φLO) + sin(ωRFt + ωLOt + φRF + φLO] 2 A Sum term gets filtered Let ωRF = ωLO VQ = — [cos(φRF – φLO)] 2 difference term at dc Figure 2. Magnitude and Phase Measurement Using a Quadrature Demodulator Rev. 0 | Page 2 of 7 (1) (2) 12940-002 A I = Acos(ωRF t + φRF) × cos(ωLO t + φLO) = — [cos(ωRF t – ωLO t + φRF – φLO) + cos(ωRF t + ωLO t + φRF + φLO] 2 A VI = — [cos(φRF – φLO)] Sum term gets filtered Let ωRF = ωLO 2 difference term at dc Circuit Note CN-0374 COMMON VARIATIONS Table 1. Input and Output Voltage Levels of Figure 1 The frequency range of the circuit can be extended to lower frequencies by using the ADL5387 30 MHz to 2 GHz quadrature demodulator. Depending on the specific application, the amplifier between the demodulator and ADC may or may not be necessary. The ADL5380 can interface directly to the AD7903 because the common-mode voltages of both devices are compatible. If using an alternative ADC with a common-mode voltage that is not within the range of the demodulator, an amplifier is necessary to achieve the level translation with minimal power loss. The AD798x and AD769x family of ADCs can be used as alternatives to the AD7903. RF Input +11.6 dBm 0 dBm ADL5380 Output +6.957 dBm 4.455 V p-p −4.643 dBm 1.172 V p-p AD7903 Input −1.022 dBFS −12.622 dBFS −20 dBm −40 dBm −68 dBm −24.643 dBm −44.643 dBm −72.643 dBm −32.622 dBFS −52.622 dBFS −80.622 dBFS 0.117 V p-p 0.012 V p-p 466 μV p-p Receiver Subsystem Error Calibration The receiver subsystem contains three major error sources: offset, gain, and phase. The individual differential dc magnitudes of the I and Q channels have sinusoidal relationships with respect to the relative phase of the RF and LO signals. As a result, the ideal dc magnitude of the I and Q channels can be calculated as follows: CIRCUIT EVALUATION AND TEST As shown in Figure 3, the receiver subsystem is implemented using the ADL5380-EVALZ, ADA4940-2ACP-EBZ, EVALAD7903SDZ, and EVAL-SDP-CB1Z evaluation kits. These circuit components are optimized for interconnection in the subsystem. Two high frequency, phase-locked input sources provide the RF and LO input signals. Table 1 summarizes the input and output voltage levels for each of the components in the receiver subsystem. An 11.6 dBm signal at the RF input of the demodulator produces an input within −1 dB of the ADC full-scale range. Table 1 assumes a 500 Ω load, 5.3573 dB conversion gain, and −4.643 dB power gain for the ADL5380, and 6 dB gain for the ADA4940-2. The calibration routine and performance results achieved for this receiver subsystem are discussed in the following sections. Voltage ICHANNEL = Max I/Q Output × cos(θ) (3) Voltage QCHANNEL = Max I/Q Output × sin(θ) (4) As the phase moves through the polar grid, some locations ideally produce the same voltage. For example, the voltage on the I (cosine) channel should be identical with phase shifts of +90° or −90°. However, a constant phase shift error, independent of the relative phase of RF and LO, causes the subsystem channel to generate different results for input phases that should produce the same dc magnitude. This is illustrated in Figure 4 and Figure 5, where two different output codes are generated when the input should be at 0 V. In this case, the −37° phase shift is much larger than expected in a real-world system containing phase-locked loops. The result is +90° actually appearing as +53°, and −90° as −127°. EVAL-AD7903SDZ ADA4940-2ACP-EBZ EVAL-SDP-CB1Z 12940-003 ADL5380-EVALZ Figure 3. Receiver Subsystem Evaluation Platform Rev. 0 | Page 3 of 7 CN-0374 Circuit Note Table 2 Measured Phase Shift for 0 dBm RF Input Average Q Channel Output Code +4524.038 −5842.293 −4396.769 +5858.444 +4429.286 I Channel Voltage −0.893 V −0.682 V +0.902 V +0.682 V −0.904 V Results were gathered in 10° steps from −180° to +180°, with the uncorrected data generating the elliptical shapes shown in Figure 4 and Figure 5. This error can be accounted for by determining the amount of additional phase shift present in the system. Table 2 shows that the system phase shift error is constant throughout the transfer function. System Phase Error Calibration With a step size of 10°, the average measured phase shift error was −37.32° for the system shown in Figure 3. With this additional phase shift known, the adjusted subsystem dc voltages can now be calculated. The variable φPHASE_SHIFT is defined as the average observed additional system phase shift. The dc voltage generated in the phase-compensated signal chain can be computed as Measured Phase +142.29° −127.43° −36.65° +52.66° +143.22° (5) Voltage QCHANNEL = Max I/Q Output × (sin(θTARGET)cos(φPHASE_SHIFT) + cos(θTARGET)sin(φPHASE_SHIFT)) (6) Equation 5 and Equation 6 provide the target input voltage for a given phase setting. The subsystem has now been linearized, and the offset error and gain error can now be corrected. The linearized I and Q channel results can also be seen in Figure 4 and Figure 5. A linear regression on the data sets generates the best fit line shown in the figures. This line is the measured subsystem transfer function for each conversion signal chain. 10k 8k y = 6273.1x + 22.599 6k 4k 2k 0 –2k –4k –6k IDEAL SIN INPUT VS. OUTPUT CODE ADJUSTED IDEAL SIN INPUT VS. OUTPUT CODE LINEAR (ADJUSTED IDEAL SIN INPUT VS. OUTPUT CODE) –8k –10k –1.5 –1.0 –0.5 0 0.5 1.0 IDEAL Q CHANNEL INPUT VOLTAGE (V) The offset of each signal chain within the receiver subsystem is ideally 0 LSB; however, the measured offsets were −12.546 LSB and +22.599 LSB for the I and Q channels, respectively. The slope of the best fit line represents the slope of the subsystem. The ideal subsystem slope can be calculated as Ideal Slope Max Code Min Code VREF VREF 65,535 0 5 5 6553.5 8k 6k y = 6315.5x – 12.546 0 –2k –4k IDEAL COS INPUT VS. OUTPUT CODE ADJUSTED IDEAL COS INPUT VS. OUTPUT CODE LINEAR (ADJUSTED IDEAL COS INPUT VS. OUTPUT CODE) –10k –1.5 –1.0 Codes V –0.5 0 0.5 1.0 IDEAL I CHANNEL INPUT VOLTAGE (V) 1.5 Offset Error Correction = −Measured Offset Error (8) The gain error correction coefficient is 12940-004 –8k (7) The results in Figure 4 and Figure 5 show that that measured slopes were 6315.5 and 6273.1 for the I and Q channels, respectively. These slopes must be adjusted to correct the system gain error. Correcting for gain error and offset error ensures that the signal magnitude computed using Equation 1 matches the ideal signal magnitude. The offset correction is the opposite of the measured offset error: 4k –6k 1.5 System Offset and Gain Error Calibration 10k 2k Measured Receiver Subsystem Phase Shift −37.71° −37.43° −36.65° −37.34° −36.78° Figure 5. Linearized Q Channel Results Voltage ICHANNEL = Max I/Q Output × (cos(θTARGET)cos(φPHASE_SHIFT) − sin(θTARGET)sin(φPHASE_SHIFT)) MEASURED I CHANNEL AD7903 OUTPUT CODE Q Channel Voltage +0.690 V −0.891 V −0.671 V +0.894 V +0.676 V 12940-005 Average I Channel Output Code −5851.294 −4471.731 +5909.982 +4470.072 −5924.423 MEASURED Q CHANNEL AD7903 OUTPUT CODE Input Phase RF to LO −180° −90° 0° +90° +180° Gain Error Correction Figure 4. Linearized I Channel Results Rev. 0 | Page 4 of 7 Ideal Slope Measured Slope (9) Circuit Note CN-0374 The received conversion result can be corrected by Figure 6 is a histogram of the measured absolute phase error showing better than 1° accuracy for every 10° step from −180° to +180°. Corrected Output Code = Received Output Code × Ideal Slope Measured Slope + (10) 18 16 Offset Error Correction 2N − 1 Use Equation 11 on both the I and Q channels to compute the perceived analog input voltage for each subsystem signal chain. These fully adjusted I and Q channel voltages are used to compute the RF signal amplitude as defined by the individual dc signal magnitudes. To evaluate the accuracy of the full calibration routine, convert the collected results to ideal subsystem voltages produced at the output of the demodulator as if no phase shift error were present; multiply the average dc magnitude computed previously by the sinusoidal fraction of the measured phase at each trial with the computed phase shift error removed. The calculation is as follows: Fully Corrected I Channel Voltage = Average Post Calibration Magnitude × (cos(θMEASURED)cos(φPHASE_SHIFT) + sin(θMEASURED)sin(φPHASE_SHIFT)) (12) Fully Corrected Q Channel Voltage = Average Post Calibration Magnitude × (sin(θMEASURED)cos(φPHASE_SHIFT) − cos(θMEASURED)sin(φPHASE_SHIFT)) (13) where: φPHASE_SHIFT is the phase error previously computed. Average Post Calibration Magnitude is the dc magnitude result from Equation 1 that has been compensated for offset error and gain error. Table 3 shows the results of the calibration routine at various target phase inputs for the 0 dBm RF input amplitude case. The calculations performed in Equation 12 and Equation 13 are the correction factors to be built into any system intended to sense phase and magnitude in the manner described in this circuit note. Table 3. Results Achieved at Certain Target Phase Inputs with 0 dBm RF Input Amplitude Target Phase −180° −90° 0° +90° +180° I Channel Fully Corrected Input Voltage −1.172 V −0.00218 V +1.172 V +0.000409 V −1.172 V Q Channel Fully Corrected Input Voltage +0.00789 V −1.172 V +0.0138 V +1.171 V −0.0111 V Fully Corrected Phase Result −180.386° −90.107° +0.677° +89.98° +180.542° 10 8 6 4 2 0 0 0.2 0.6 0.8 1.0 Figure 6. Measured Absolute Phase Error Histogram for 0 dBm Input Level with 10° Phase Steps For accurate phase measurements at any given input level, the perceived phase shift error (φPHASE_SHIFT) of RF relative to LO must be constant. If the measured phase shift error begins to change as a function of the target phase step (θTARGET) or amplitude, the calibration routine presented in this section begins to lose accuracy. Evaluation results at room temperature show that the phase shift error is relatively constant for RF amplitudes ranging from a maximum of 11.6 dBm to approximately −20 dBm at 900 MHz. Figure 7 shows the dynamic range of the receiver subsystem along with the corresponding amplitude-induced additional phase error. As the input amplitude decreases past −20 dBm, the phase error calibration accuracy begins to degrade. The system user must determine the acceptable level of signal chain error to determine the minimum acceptable signal magnitude. 50 40k 40 30k 30 20k 20 10k 10 0 0 –10 –10k –20 I CHANNEL (COS) ADC CODE Q CHANNEL (SIN) ADC CODE PHASE ERROR CALIBRATION ACCURACY –20k Absolute Measured Phase Error 0.386° 0.107° 0.676° 0.020° 0.541° 0.4 ABSOLUTE PHASE ERROR (Degrees) DEGREES (11) –30k –40k 11.6 –30 –40 –50 8 2 –4 –8 –14 –20 –24 –30 –36 –42 –46 INPUT LEVEL (dBm) 12940-007 2 × VREF × Corrected Output Code 12 12940-006 Measured Signal Input Voltage = ADC OUTPUT CODE The calibrated dc input voltage of the subsystem is calculated as NUMBER OF OCCURRENCES CALCULATED PHASE ERROR 14 Figure 7. Dynamic Range of Receiver Subsystem and Corresponding Additional Phase Error The results shown in Figure 7 were collected with a 5 V ADC reference. The magnitude of the ADC reference can be reduced, providing a smaller quantization level for the system, which Rev. 0 | Page 5 of 7 CN-0374 Circuit Note provides an incremental improvement in phase error accuracy for small signals but increases the chance for system saturation. To increase system dynamic range, another option is to implement an oversampling scheme that increases the noise-free bit resolution of the ADC. Every doubling in samples averaged provides a ½ LSB increase in system resolution. The oversampling ratio for a given resolution increase is calculated as follows: Oversampling Ratio = 22N (14) where N is the number of bits increase. 12940-008 Oversampling reaches a point of diminishing returns when the noise amplitude is no longer sufficient to randomly change the ADC output code from sample to sample. At this point, the effective resolution of the system can no longer be increased. The bandwidth reduction from oversampling is not a significant concern because the system is measuring signals with a slowly changing magnitude. Figure 8. Receiver Subsystem Calibration GUI Equipment Needed The following equipment are used to evaluate the circuit. The AD7903 evaluation software is available with a calibration routine that allows the user to correct the ADC output results for the three sources of error: phase, gain, and offset. The user must collect uncorrected results with their system to determine the calibration coefficients calculated in this circuit note. Figure 8 shows the Amp/Phase Panel tab of the GUI with the calibration coefficients highlighted. When the coefficients are determined, this tab can also be used to deliver phase and magnitude results from the demodulator. The polar plot provides a visual indication of the observed RF input signal. The amplitude and phase calculations are performed using Equation 1 and Equation 2. The oversampling ratio can be controlled by adjusting the number of samples per capture using the Num Samples drop-down box. A Windows® XP, Windows Vista (32-bit), or Windows 7 (32-bit) PC with USB port The ADL5380-EVALZ, ADA4940-2ACP-EBZ, EVALAD7903SDZ, and EVAL-SDP-CB1Z evaluation boards Two RF signal generators with phase control (such as the R&S SMT06) A digital multimeter 5 V and 9 V power supplies The AD7903 evaluation software, used to digitally process the resulting magnitude and phase information Figure 9 shows a block diagram of the test setup. 5V SUPPLY VPOS ADL5380-EVALZ LO_SE 9V SUPPLY +VS1 IPx +IN1 +OUT1 VIN1+ INx −IN1 −OUT1 VIN1− EVAL-AD7903SDZ ADA4940-2ACP-EB RFx VIN QPx +IN2 +OUT2 VIN2+ QNx −IN2 −OUT2 VIN2− 120 LO RF CON A OR CON B RF GENERATOR PC EVAL-SDP-CB1Z 12940-009 LO GENERATOR USB Figure 9. Test Setup Functional Diagram Rev. 0 | Page 6 of 7 Circuit Note CN-0374 LEARN MORE Data Sheets and Evaluation Boards CN-0374 Design Support Package: www.analog.com/CN0374-DesignSupport ADL5380 Data Sheet and Evaluation Board UG-609. EVAL-AD7903SDZ Evaluation Board User Guide. Analog Devices. AD7903 Data Sheet and Evaluation Board UG-018. Evaluation Board for High Speed Differential Amplifiers. Analog Devices. 1/15—Revision 0: Initial Version ADA4940-2 Data Sheet and Evaluation Board REVISION HISTORY Ardizzoni, John. A Practical Guide to High-Speed PrintedCircuit-Board Layout. Analog Dialogue 39-09, September 2005. ADIsimRF Design Tool. MT-031 Tutorial. Grounding Data Converters and Solving the Mystery of "AGND" and "DGND". Analog Devices. MT-101 Tutorial. Decoupling Techniques. Analog Devices. Ryan Curran, Qui Luu, Maithil Pachchigar. RF-to-Bits Solution Offers Precise Phase and Magnitude Data for Material Analysis. Analog Dialogue 48-4, October 2014. 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Analog Devices reserves the right to change any Circuits from the Lab reference designs at any time without notice but is under no obligation to do so. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CN12940-0-1/15(0) Rev. 0 | Page 7 of 7