Ultralow Input Bias Current Operational Amplifier AD549 Data Sheet FEATURES CONNECTION DIAGRAM GUARD PIN, CONNECTED TO CASE Ultralow input bias current 60 fA maximum (AD549L) 100 fA maximum (AD549K) 250 fA maximum (AD549J) Input bias current guaranteed over the common-mode voltage range Low offset voltage 0.50 mV maximum (AD549K) 1.00 mV maximum (AD549J) Low offset drift 15 μV/°C maximum (AD549K) 20 μV/°C maximum (AD549J) Low power 700 μA maximum supply current Low input voltage noise 4 μV (typ) p-p over 0.1 Hz to 10 Hz MIL-STD-883B parts available OFFSET NULL INVERTING INPUT V+ 8 1 AD549 7 2 6 5 3 NONINVERTING INPUT 4 OUTPUT OFFSET NULL V– 5 4 VOS TRIM –15V 00511-001 10kΩ 1 Figure 1. APPLICATIONS Electrometer amplifier Photodiode preamp pH electrode buffer GENERAL DESCRIPTION The AD549 is a monolithic electrometer operational amplifier with very low input bias current. Input offset voltage and input offset voltage drift are laser trimmed for precision performance. The ultralow input current of the part is achieved with Topgate™ JFET technology, a process development exclusive to Analog Devices, Inc. This technology allows fabrication of extremely low input current JFETs compatible with a standard junction isolated bipolar process. The 1015 Ω common-mode impedance, which results from the bootstrapped input stage, ensures that the input current is essentially independent of the commonmode voltage. The AD549 is suited for applications requiring very low input current and low input offset voltage. It excels as a preamp for a wide variety of current output transducers, such as photodiodes, photomultiplier tubes, or oxygen sensors. The AD549 can also be used as a precision integrator or low droop sample-and-hold. The AD549 is pin compatible with standard FET and electrometer op amps, allowing designers to upgrade the performance of present systems at little additional cost. The AD549 is available in a TO-99 hermetic package. The case is connected to Pin 8, thus, the metal case can be independently Rev. K connected to a point at the same potential as the input terminals, minimizing stray leakage to the case. The AD549 is available in four performance grades. The J, K, and L versions are rated over the commercial temperature range of 0°C to +70°C. The S grade is specified over the military temperature range of −55°C to +125°C and is available processed to MIL-STD-883B, Rev. C. Extended reliability plus screening is also available. Plus screening includes 168 hour burn-in, as well as other environmental and physical tests derived from MIL-STD-883B, Rev. C. PRODUCT HIGHLIGHTS 1. The AD549 input currents are specified, 100% tested, and guaranteed after the device is warmed up. They are guaranteed over the entire common-mode input voltage range. 2. The AD549 input offset voltage and drift are laser trimmed to 0.50 mV and 15 μV/°C (AD549K), and to 1 mV and 20 μV/°C (AD549J). 3. A maximum quiescent supply current of 700 μA minimizes heating effects on input current and offset voltage. 4. AC specifications include 1 MHz unity-gain bandwidth and 3 V/μs slew rate. Settling time for a 10 V input step is 5 μs to 0.01%. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD549 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Offset Nulling ............................................................................. 11 Applications ....................................................................................... 1 Connection Diagram ....................................................................... 1 AC Response with High Value Source and Feedback Resistance .................................................................................... 12 General Description ......................................................................... 1 Common-Mode Input Voltage Overload................................ 12 Product Highlights ........................................................................... 1 Differential Input Voltage Overload ........................................ 13 Revision History ............................................................................... 2 Input Protection ......................................................................... 13 Specifications..................................................................................... 3 Sample-and-Difference Circuit to Measure Electrometer Leakage Currents ........................................................................ 13 Absolute Maximum Ratings............................................................ 5 ESD Caution .................................................................................. 5 Typical Performance Characteristics ............................................. 6 Functional Description .................................................................. 10 Minimizing Input Current ........................................................ 10 Circuit Board Notes ................................................................... 10 Photodiode Interface ................................................................. 14 Log Ratio Amplifier ................................................................... 15 Temperature Compensated pH Probe Amplifier................... 16 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18 REVISION HISTORY 2/15—Rev. J to Rev. K 7/07—Rev. F to Rev. G Updated Outline Dimensions ....................................................... 18 Changes to Figure 45...................................................................... 16 Changes to Temperature Compensated pH Probe Amplifier Section............................................................................ 17 Changes to Figure 46...................................................................... 17 Changes to Ordering Guide .......................................................... 18 12/14—Rev. I to Rev. J Added L Model ................................................................... Universal Changes to Features Section and Applications Section ............... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Log Ratio Amplifier Section ..................................... 15 Changes to Temperature Compensated pH Probe Amplifier Section ............................................................................ 16 Changes to Ordering Guide .......................................................... 18 5/06—Rev. E to Rev. F Removed ESD Caution .....................................................................5 8/05—Rev. D to Rev. E Change to Figure 22 ..........................................................................9 6/14—Rev. H to Rev. I 5/04—Rev. C to Rev. D Deleted L Model............................................................. Throughout Change to Features Section ............................................................. 1 Changes to Input Offset Voltage Parameter and Input Voltage Noise Parameter, Table 1.................................................................. 3 Changes to Ordering Guide .......................................................... 18 Updated Format .................................................................. Universal Changes to Features ..........................................................................1 Updated Outline Dimensions ....................................................... 18 Added Ordering Guide .................................................................. 18 3/08—Rev. G to Rev. H Deleted Product Highlights #5 ........................................................1 Edits to Specifications .......................................................................3 Deleted Metallization Photograph ..................................................3 Updated Outline Dimensions ....................................................... 13 Changes to Features.......................................................................... 1 Changes to Figure 1 .......................................................................... 1 Deleted Package Option Parameter ............................................... 4 Inserted ESD Caution ...................................................................... 5 Changes to Figure 2, Figure 3, and Figure 7.................................. 6 Changes to Figure 11 ........................................................................ 7 Changes to Figure 17 ........................................................................ 8 Changes to Figure 41 ...................................................................... 14 10/02—Rev. B to Rev. C 7/02—Rev. A to Rev. B Edits to Specifications .......................................................................2 Rev. K | Page 2 of 18 Data Sheet AD549 SPECIFICATIONS At 25°C and VS = ±15 V dc, unless otherwise noted; all minimum and maximum specifications are guaranteed; specifications in boldface are tested on all production units at final electrical test, and results from those tests are used to calculate outgoing quality levels. Table 1. Parameter INPUT BIAS CURRENT1 Either Input, VCM = 0 V Either Input, VCM = ±10 V Either Input at TMAX, VCM = 0 V Offset Current Offset Current at TMAX INPUT OFFSET VOLTAGE2 Initial Offset Offset at TMAX vs. Temperature vs. Supply vs. Supply, TMIN to TMAX Long-Term Offset Stability INPUT VOLTAGE NOISE f = 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz INPUT CURRENT NOISE f = 0.1 Hz to 10 Hz f = 1 kHz INPUT IMPEDANCE Differential VDIFF = ±1 Common Mode VCM = ±10 V OPEN-LOOP GAIN VOUT at ±10 V, RL = 10 kΩ VOUT at ±10 V, RL = 10 kΩ, TMIN to TMAX VOUT = ±10 V, RL = 2 kΩ VOUT = ±10 V, RL = 2 kΩ, TMIN to TMAX INPUT VOLTAGE RANGE Differential3 Common-Mode Voltage Common-Mode Rejection Ratio −10 V ≤ VCM ≤ +10 V TMIN to TMAX OUTPUT CHARACTERISTICS VOUT at RL = 10 kΩ, TMIN to TMAX VOUT at RL = 2 kΩ, TMIN to TMAX Short-Circuit Current TMIN to TMAX Load Capacitance Stability, G = +1 Min AD549J Typ Max 150 150 11 Min 75 75 4.2 250 250 50 2.2 0.5 10 32 32 15 AD549K Typ Max Min 40 40 2.8 100 100 30 1.3 0.15 1.0 1.9 20 100 100 10 10 10 15 AD549L Typ Max Min 60 60 20 0.85 AD549S Typ Max Unit 75 75 420 fA fA pA 100 100 30 125 0. 5 0.9 15 32 32 0.3 6 4 90 60 35 35 4 90 60 35 35 μV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz 5 10 10 15 0.3 fA pA 0.5 0.9 10 32 32 10 10 32 15 0.5 2.0 15 32 50 mV mV μV/°C μV/V μV/V μV/month 4 90 60 35 35 4 90 60 35 35 0.7 0.22 0.5 0.16 0.36 0.11 0.5 0.16 fA rms fA/√Hz 1013||1 1013||1 1013||1 1013||1 Ω||pF 1015||0.8 1015||0.8 1015||0.8 1015||0.8 Ω||pF 300 300 1000 800 300 300 1000 800 300 300 1000 800 300 300 1000 800 V/mV V/mV 100 80 250 200 100 80 250 200 100 80 250 200 100 25 250 150 V/mV V/mV ±20 +10 −10 80 76 90 80 −12 −10 15 9 20 4000 ±20 +10 −10 90 80 +12 −12 +10 35 −10 15 9 100 90 20 90 80 +12 −12 +10 35 −10 15 9 4000 Rev. K | Page 3 of 18 ±20 +10 −10 100 90 20 4000 ±20 +10 −10 90 80 +12 −12 +10 35 −10 15 6 100 90 20 4000 V V dB dB +12 V +10 35 V mA mA pF AD549 Parameter FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate Settling Time, 0.1% Settling Time, 0.01% Overload Recovery, 50% Overdrive, G = −1 POWER SUPPLY Rated Performance Operating Quiescent Current TEMPERATURE RANGE Operating, Rated Performance Storage Data Sheet Min 0.7 2 AD549J Typ Max 1.0 50 3 4.5 5 2 Min 0.7 2 ±15 ±5 1.0 50 3 4.5 5 2 Min 0.7 2 ±15 ±18 0.70 ±5 0 70 −65 +150 0.60 AD549K Typ Max 1.0 50 3 4.5 5 2 Min 0.7 2 ±15 ±18 0.70 ±5 0 70 −65 +150 0.60 AD549L Typ Max 1 Unit 1.0 50 3 4.5 5 2 MHz kHz V/μs μs μs μs ±15 ±18 0.70 V V mA −55 +125 °C −65 +150 °C ±18 0.70 ±5 0 70 −65 +150 0.60 AD549S Typ Max 0.60 Bias current specifications are guaranteed after five minutes of operation at TA = 25°C. Bias current increases by a factor of 2.3 for every 10°C rise in temperature. Input offset voltage specifications are guaranteed after five minutes of operation at TA = 25°C. 3 Defined as maximum continuous voltage between the inputs, such that neither input exceeds ±10 V from ground. 2 Rev. K | Page 4 of 18 Data Sheet AD549 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Internal Power Dissipation Input Voltage1 Output Short-Circuit Duration Differential Input Voltage Storage Temperature Range Operating Temperature Range AD549J, AD549K, AD549L AD549S Lead Temperature (Soldering, 60 sec) 1 Rating ±18 V 500 mW ±18 V Indefinite +VS and −VS −65°C to +125°C 0°C to +70°C −55°C to +125°C 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage. Rev. K | Page 5 of 18 AD549 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 800 INPUT VOLTAGE (V) 15 VIN+ 10 VIN– 0 00511-002 5 0 5 10 15 700 600 500 400 20 00511-005 AMPLIFIER QUIESCENT CURRENT (µA) 20 0 5 SUPPLY VOLTAGE (±V) Figure 2. Input Voltage Range vs. Supply Voltage 15 –VOUT 10 5 0 5 10 15 110 100 90 80 70 –20 20 SUPPLY VOLTAGE (±V) 00511-006 COMMON-MODE REJECTION RATIO (dB) +VOUT 00511-003 OUTPUT VOLTAGE SWING (V) 20 120 25°C RL = 10kΩ –10 0 10 20 INPUT COMMON-MODE VOLTAGE (V) Figure 3. Output Voltage Swing vs. Supply Voltage Figure 6. CMRR vs. Input Common-Mode Voltage 30 3000 VS = ±15V OPEN-LOOP GAIN (V/mV) 25 20 15 10 1000 300 0 10 100 1k 10k 100 100k LOAD RESISTANCE (Ω) 00511-007 5 00511-004 OUTPUT VOLTAGE SWING (V p-p) 15 Figure 5. Quiescent Current vs. Supply Voltage 20 0 10 SUPPLY VOLTAGE (±V) 0 5 10 15 SUPPLY VOLTAGE (±V) Figure 7. Open-Loop Gain vs. Supply Voltage Figure 4. Output Voltage Swing vs. Load Resistance Rev. K | Page 6 of 18 20 Data Sheet AD549 3000 50 INPUT CURRENT (fA) OPEN-LOOP GAIN (V/mV) 45 1000 300 40 35 30 –25 5 35 65 95 20 125 00511-011 100 –55 00511-008 25 0 5 TEMPERATURE (°C) Figure 8. Open-Loop Gain vs. Temperature 15 10 00511-009 5 1 2 3 4 5 6 120 100 80 60 40 20 10 7 100 WARM-UP TIME (Minutes) Figure 9. Change in Offset Voltage vs. Warm-Up Time 45 10k INPUT NOISE VOLTAGE (µV p-p) 100k 40 35 30 00511-010 25 –5 0 10k Figure 12. Input Voltage Noise Spectral Density 50 20 –10 1k FREQUENCY (Hz) 5 WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR THE APPLICATION 1kHz BANDWIDTH 1k RESISTOR JOHNSON NOISE 100 10 10Hz BANDWIDTH 1 00511-013 0 140 00511-012 NOISE SPECTRAL DENSITY (nV/ Hz) 20 ∆IVOSI (µV) 20 160 25 INPUT CURRENT (fA) 15 Figure 11. Input Bias Current vs. Power Supply Voltage 30 0 10 POWER SUPPLY VOLTAGE (±V) AMPLIFIER GENERATED NOISE 0.1 100k 10 COMMON-MODE VOLTAGE (V) 1M 10M 100M 1G SOURCE RESISTANCE (Ω) Figure 10. Input Bias Current vs. Common-Mode Voltage Figure 13. Noise vs. Source Resistance Rev. K | Page 7 of 18 10G 100G AD549 Data Sheet 60 60 40 40 20 20 0 0 –20 –40 10 100 1k 10k 100k 00511-014 –20 –40 10M 1M 100 80 +PSSR 60 40 –PSSR 20 0 –20 10 00511-017 80 POWER SUPPLY REJECTION RATIO (dB) 80 120 PHASE MARGIN (Degrees) 100 OEPN-LOOP GAIN (dB) 100 100 FREQUENCY (Hz) 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 14. Open-Loop Frequency Response Figure 17. PSRR vs. Frequency Response 40 10 30 25 20 15 10 0 10 00511-015 5 100 1k 10k 100k 60 40 20 0 00511-016 COMMON-MODE REJECTION RATIO (dB) 80 1k 10k 100k 0 10mV 5mV –5 1mV 0 1 2 3 4 Figure 18. Output Voltage Swing and Error vs. Settling Time 100 100 1mV SETTLING TIME (µs) Figure 15. Large Signal Frequency Response –20 10 5mV –10 1M FREQUENCY (Hz) 10mV 5 00511-018 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) 35 1M 10M FREQUENCY (Hz) Figure 16. CMRR vs. Frequency Rev. K | Page 8 of 18 5 Data Sheet AD549 10kΩ +VS +VS 0.1µF 0.1µF 7 4 0.1µF RL 10kΩ SQUARE WAVE INPUT CL 100pF –VS 7 AD549 3 4 0.1µF 5 RL 10kΩ VOUT CL 100pF –VS 00511-022 SQUARE WAVE INPUT 3 2 Figure 22. Unity-Gain Inverter Figure 19. Unity-Gain Follower 5V 5µs 00511-020 5V 5µs Figure 20. Unity-Gain Follower Large Signal Pulse Response 00511-023 VIN VIN VOUT 5 10kΩ Figure 23. Unity-Gain Inverter Large Signal Pulse Response 10mV 1µs 00511-021 10mV 1µs Figure 21. Unity-Gain Follower Small Signal Pulse Response 00511-024 AD549 00511-019 2 Figure 24. Unity-Gain Inverter Small Signal Pulse Response Rev. K | Page 9 of 18 AD549 Data Sheet FUNCTIONAL DESCRIPTION MINIMIZING INPUT CURRENT CIRCUIT BOARD NOTES The AD549 is optimized for low input current and offset voltage. Careful attention to how the amplifier is used reduces input currents in actual applications. A number of physical phenomena generate spurious currents that degrade the accuracy of low current measurements. Figure 27 is a schematic of a current to voltage (I-to-V) converter with these parasitic currents modeled. Keep the amplifier operating temperature as low as possible to minimize input current. Like other JFET input amplifiers, the AD549 input current is sensitive to chip temperature, rising by a factor of 2.3 for every 10°C. Figure 25 is a plot of the AD549 input current vs. ambient temperature. CF RF 2 AD549 1nA fS 3 8 6 + VOUT – 10pA RP 1pA VS V dCP dV C II' = R + dT V + dT P P Figure 27. Sources of Parasitic Leakage Currents 100fA 00511-025 10fA 1fA –55 –25 5 35 65 95 125 TEMPERATURE (°C) Figure 25. Input Bias Current vs. Ambient Temperature On-chip power dissipation raises the chip operating temperature, causing an increase in input bias current. Due to the low quiescent supply current of the AD549, the chip temperature is less than 3°C higher than its ambient temperature when the (unloaded) amplifier is operating with 15 V supplies. The difference in the input current is negligible. However, heavy output loads can cause a significant increase in chip temperature and a corresponding increase in the input current. Maintaining a minimum load resistance of 10 Ω is recommended. Input current vs. additional power dissipation due to output drive current is plotted in Figure 26. 6 5 4 BASED ON TYPICAL IB = 40fA 3 2 1 00511-026 NORMALIZED INPUT BIAS CURRENT CP 00511-027 INPUT BIAS CURRENT 100pA 0 25 50 75 100 125 150 175 Finite resistance from input lines to voltages on the board, modeled by Resistor RP, results in parasitic leakage. Insulation resistance of more than 1015 Ω must be maintained between the amplifier signal and supply lines to capitalize on the low input currents of the AD549. Standard PCB material does not have high enough insulation resistance; therefore, connect the input leads of the AD549 to standoffs made of insulating material with adequate volume resistivity (that is, Teflon®). The surface of the insulator must be kept clean to preserve surface resistivity. For Teflon, an effective cleaning procedure consists of swabbing the surface with high grade isopropyl alcohol, rinsing with deionized water, and baking the board at 80°C for 10 minutes. In addition to high volume and surface resistivity, other properties are desirable in the insulating material chosen. Resistance to water absorption is important because surface water films drastically reduce surface resistivity. The insulator chosen should also exhibit minimal piezoelectric effects (charge emission due to mechanical stress) and triboelectric effects (charge generated by friction). Charge imbalances generated by these mechanisms can appear as parasitic leakage currents. These effects are modeled by Variable Capacitor CP in Figure 27. Table 3 lists various insulators and their properties.2 Guarding the input lines by completely surrounding them with a metal conductor biased near the potential of the input lines has two major benefits. First, parasitic leakage from the signal line is reduced because the voltage between the input line and the guard is very low. Second, stray capacitance at the input node is minimized. Input capacitance can substantially degrade signal bandwidth and the stability of the I-to-V converter. 200 ADDITIONAL INTERNAL POWER DISSIPATION (mW) Figure 26. Input Bias Current vs. Additional Power Dissipation 2 Electronic Measurements, pp. 15–17, Keithley Instruments, Inc., Cleveland, Ohio, 1977. Rev. K | Page 10 of 18 Data Sheet AD549 The case of the AD549 is connected to Pin 8 so that it can be bootstrapped near the input potential. This minimizes pin leakage and input common-mode capacitance due to the case. Guard schemes for inverting and noninverting amplifier topologies are illustrated in Figure 28 and Figure 29. CF GUARD RF OFFSET NULLING The AD549 input offset voltage can be nulled by using balance Pin 1 and Pin 5, as shown in Figure 30. Nulling the input offset voltage in this fashion introduces an added input offset voltage drift component of 2.4 μV/°C per mV of nulled offset (a maximum additional drift of 1.2 μV/°C for the AD549K and AD549L, and 2.4 μV/°C for the AD549J). +VS 2 + VOUT – 6 8 7 2 AD549 00511-028 3 5 + VOUT – 6 1 3 4 10kΩ Figure 28. Inverting Amplifier with Guard 00511-030 AD549 –VS Figure 30. Standard Offset Null Circuit GUARD The approach in Figure 31 can be used when the amplifier is used as an inverter. This method introduces a small voltage referenced to the power supplies in series with the positive input terminal of the amplifier. The amplifier input offset voltage drift with temperature is not affected. However, variation of the power supply voltages causes offset shifts. 3 AD549 + VS 2 8 6 VOUT + RF RI – 00511-029 – RF RI Figure 29. Noninverting Amplifier with Guard 2 AD549 + Other guidelines include keeping the circuit layout as compact as possible and keeping the input lines short. Keeping the assembly rigid and minimizing sources of vibration reduces triboelectric and piezoelectric effects. All precision, high impedance circuitry requires shielding against interference noise. Use low noise coaxial or triaxial cables for remote connections to the input signal lines. VI 3 +VS – 499kΩ 200Ω 6 499kΩ 0.1µF + VOUT – 100kΩ –VS 00511-031 IN Figure 31. Alternate Offset Null Circuit for Inverter Table 3. Insulating Materials and Characteristics Material Teflon Kel-F® Sapphire Polyethylene Polystyrene Ceramic Glass Epoxy PVC Phenolic 1 Volume Resistivity (V to CM) 1017 to 1018 1017 to 1018 1016 to 1018 1014 to 1018 1012 to 1018 1012 to 1014 1010 to 1017 1010 to 1015 105 to 1012 Minimal Triboelectric Effect1 W W M M W W W G W Minimal Piezoelectric Effect1 W M G G M M M M G G: good with regard to property; M: moderate with regard to property; W: weak with regard to property. Rev. K | Page 11 of 18 Resistance to Water Absorption1 G G G M M W W G W AD549 Data Sheet AC RESPONSE WITH HIGH VALUE SOURCE AND FEEDBACK RESISTANCE Source and feedback resistances greater than 100 kΩ magnify the effect of the input capacitances (stray and inherent to the AD549) on the ac behavior of the circuit. The effects of common-mode and differential input capacitances should be taken into account because the circuit bandwidth and stability can be adversely affected. 10mV Figure 34. Inverter Pulse Response with 1 MΩ Source and Feedback Resistance Figure 32. Follower Pulse Response from 1 MΩ Source Resistance, Case Not Bootstrapped 10mV 5µs 00511-035 5µs 00511-033 10mV 5µs 00511-034 5µs 00511-032 10mV In an inverting configuration, the differential input capacitance forms a pole in the loop transmission of the circuit. This can create peaking in the ac response and possible instability. A feedback capacitance can be used to stabilize the circuit. The inverter pulse response with RF and RS equal to 1 MΩ appears in Figure 34. Figure 35 shows the response of the same circuit with a 1 pF feedback capacitance. Typical differential input capacitance for the AD549 is 1 pF. Figure 35. Inverter Pulse Response with 1 MΩ Source and Feedback Resistance, 1 pF Feedback Capacitance Figure 33. Follower Pulse Response from 1 MΩ Source Resistance, Case Bootstrapped In a follower, the source resistance and input common-mode capacitance form a pole that limits the bandwidth to ½πRSCS. Bootstrapping the metal case by connecting Pin 8 to the output minimizes capacitance due to the package. Figure 32 and Figure 33 show the follower pulse response from a 1 MΩ source resistance with and without the package connected to the output. Typical common-mode input capacitance for the AD549 is 0.8 pF. COMMON-MODE INPUT VOLTAGE OVERLOAD The rated common-mode input voltage range of the AD549 is from 3 V less than the positive supply voltage to 5 V greater than the negative supply voltage. Exceeding this range degrades the CMRR of the amplifier. Driving the common-mode voltage above the positive supply causes the amplifier output to saturate at the upper limit of the output voltage. Recovery time is typically 2 μs after the input has been returned to within the normal operating range. Driving the input common-mode voltage within 1 V of the negative supply causes phase reversal of the output signal. In this case, normal operation typically resumes within 0.5 μs of the input voltage returning within range. Rev. K | Page 12 of 18 Data Sheet AD549 RPROTECT DIFFERENTIAL INPUT VOLTAGE OVERLOAD SOURCE A plot of the AD549 input currents vs. differential input voltage (defined as VIN+ − VIN−) appears in Figure 36. The input current at either terminal stays below a few hundred femtoamps until one input terminal is forced higher than 1 V to 1.5 V above the other terminal. Under these conditions, the input current limits at 30 μA. 10µ IIN– 6 00511-038 Figure 38. Follower with Input Current Limit IIN+ 100n 10n 1n 100p RF SOURCE 10p 2 AD549 00511-036 1p 100f 10f –5 –4 –3 –2 –1 0 1 2 3 4 3 PROTECT DIODES 5 Figure 39. Input Voltage Clamp with Diodes DIFFERENTIAL INPUT VOLTAGE (V) (VIN+ – VIN–) SAMPLE-AND-DIFFERENCE CIRCUIT TO MEASURE ELECTROMETER LEAKAGE CURRENTS Figure 36. Input Current vs. Differential Input Voltage INPUT PROTECTION The AD549 safely handles any input voltage within the supply voltage range. Subjecting the input terminals to voltages beyond the power supply can destroy the device or cause shifts in input current or offset voltage if the amplifier is not protected. A protection scheme for the amplifier as an inverter is shown in Figure 37. RP is chosen to limit the current through the inverting input to 1 mA for expected transient (less than 1 sec) overvoltage conditions, or to 100 μA for a continuous overload. Because RP is inside the feedback loop and is much lower in value than the amplifier input resistance, it does not affect the dc gain of the inverter. However, the Johnson noise of the resistor adds root sum of squares to the amplifier input noise. RF RPROTECT CF 2 AD549 6 3 00511-037 SOURCE 6 00511-039 INPUT CURRENT (A) AD549 2 Figure 39 is a schematic of the AD549 as an inverter with an input voltage clamp. Bootstrapping the clamp diodes at the inverting input minimizes the voltage across the clamps and keeps the leakage due to the diodes low. Use low leakage diodes, such as the FD333s, and shield them from light to prevent photocurrents from being generated. Even with these precautions, the diodes measurably increase input current and capacitance. 100µ 1µ 3 There are a number of methods used to test electrometer leakage currents, including current integration and direct I-to-V conversion. Regardless of the method used, board and interconnect cleanliness, proper choice of insulating materials (such as Teflon or Kel-F), correct guarding and shielding techniques, and care in physical layout are essential to making accurate leakage measurements. Figure 40 is a schematic of the sample-and-difference circuit. It uses two AD549 electrometer amplifiers (A and B) as I-to-V converters with high value (1010 Ω) sense resistors (RSa and RSb). R1 and R2 provide for an overall circuit sensitivity of 10 fA/mV (10 pA full scale). CC and CF provide noise suppression and loop compensation. CC should be a low leakage polystyrene capacitor. An ultralow leakage Kel-F test socket is used for contacting the device under test. Rigid Teflon coaxial cable is used to make connections to all high impedance nodes. The use of rigid coaxial cable affords immunity to error induced by mechanical vibration and provides an outer conductor for shielding. The entire circuit is enclosed in a grounded metal box. Figure 37. Inverter with Input Current Limit In the corresponding version of this scheme for a follower, shown in Figure 38, RP and the capacitance at the positive input terminal produce a pole in the signal frequency response at a f = ½πRC. Again, the Johnson noise, RP, adds to the input voltage noise of the amplifier. Rev. K | Page 13 of 18 AD549 Data Sheet The test apparatus is calibrated without a device under test present. After power is turned on, a 5 minute stabilization period is required. First, VERR1 and VERR2 are measured. These voltages are the errors caused by the offset voltages and leakage currents of the I-to-V converters. VERR1 = 10 (VOSA – IBA × RSa) VERR2 = 10 (VOSB – IBB × RSb) CC 20pF CF 0.1µF RSa 1010Ω R2 9.01kΩ PHOTODIODE INTERFACE R1 1kΩ 2 A 6 AD549 8 3 Although a series of devices can be tested after only one calibration measurement, calibration should be updated periodically to compensate for any thermal drift of the I-to-V converters or changes in the ambient environment. Laboratory results have shown that repeatable measurements within 10 fA can be realized when this apparatus is properly implemented. These results are achieved in part by the design of the circuit, which eliminates relays and other parasitic leakage paths in the high impedance signal lines, and in part by the inherent cancellation of errors through the calibration and measurement procedure. CAL/TEST + VERR1 /VA – The low input current and low input offset voltage of the AD549 make it an excellent choice for very sensitive photodiode preamps (see Figure 41). The photodiode develops a signal current, IS, equal to IS = R × P GUARD where P is light power incident on the diode surface, in watts, and R is the photodiode responsivity in amps/watt. RF converts the signal current to an output voltage I (+) VOUT – CF 0.1µF R2 9.01kΩ VOUT = RF × IS I (–) R1 1kΩ RF 109Ω VERR2 /VB 8 3 B 6 AD549 CF 10pF + 2 2 IS CF 0.1µF RSb 1010Ω R2 9.01kΩ R1 1kΩ 5 + 6 1µF 1 3 VOUT 4 – –VS 00511-040 CC 20pF 10kΩ AD549 Figure 40. Sample and Difference Circuit for Measuring Electrometer Leakage Currents Once measured, these errors are subtracted from the readings taken with a device under test present. Amplifier B closes the feedback loop to the device under testing in addition to providing the I-to-V conversion. The offset error of the device under testing appears as a common-mode signal and does not affect the test measurement. As a result, only the leakage current of the device under testing is measured. Figure 41. Photodiode Preamp The dc error sources and an equivalent circuit for a small area (0.2 mm square) photodiode are indicated in Figure 42. RF 109Ω CF 10pF IS VA – VERR1 = 10[RSa × IB(+)] RS 109Ω CS 20pF A IS– – VOS + Figure 42. Photodiode Preamp DC Error Sources VX – VERR2 = 10[RSb × IB(–)] Rev. K | Page 14 of 18 + VOUT – 00511-042 DEVICE UNDER TEST 00511-041 – VOS + Data Sheet AD549 Input current, IB, contributes an output voltage error, VE1, proportional to the feedback resistance VE1 = IB × RF The input voltage offset of the op amp causes an error current through the photodiode shunt resistance, RS gain that multiplies the op amp input voltage noise contribution. A single-pole filter at the output of the amplifier limits the op amp output voltage noise bandwidth to 26 Hz, comparable to the signal bandwidth. This greatly improves the signal-tonoise ratio of the preamplifier (in this case, by a factor of 3). 10µ IF AND CS, NO FILTERS VE2 = (1 + RF/RS)VOS Given typical values of photodiode shunt resistance (on the order of 109 Ω), RF/RS can easily be greater than 1, especially if a large feedback resistance is used. Also, RF/RS increases with temperature because photodiode shunt resistance typically drops by a factor of 2 for every 10°C rise in temperature. An op amp with low offset voltage and low drift must be used to maintain accuracy. The AD549K offers a guaranteed maximum 0.50 mV offset voltage and 15 mV/°C drift for very sensitive applications. Noise sources associated with the photodiode, amplifier, and feedback resistance are shown in Figure 43; Figure 44 is the spectral density vs. frequency plot of the contribution of each of the noise sources to the output voltage noise (circuit parameters in Figure 42 are assumed). The rms contribution of each noise source to the total output voltage noise is obtained by integrating the square of its spectral density function over frequency. The rms value of the output voltage noise is the square root of the sum of all contributions. Minimizing the total area under these curves optimizes the resolution of the preamplifier for a given bandwidth. IF AD549 OPEN-LOOP GAIN 1µ 100n EN CONTRIBUTION, NO FILTER 10n EN CONTRIBUTION, WITH FILTER 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 44. Spectral Density of the Photodiode Preamp Noise Sources vs. Frequency Photodiode Preamp Noise Noise limits the signal resolution obtainable with the preamp. The output voltage noise divided by the feedback resistance is the minimum current signal that can be detected. This minimum detectable current divided by the responsivity of the photodiode represents the lowest light power that is detectable by the preamp. IF AND CS, WITH FILTERS 00511-044 The error current results in an error voltage (VE2) at the amplifier output equal to VOLTAGE NOISE CONTRIBUTIONS NOISE SPECTRAL DENSITY (nV/ Hz) I = VOS/RS LOG RATIO AMPLIFIER Logarithmic ratio circuits are useful for processing signals with wide dynamic range. The 60 fA maximum input current of the AD549L makes it possible to build a log ratio amplifier with 1% log conformance for input currents ranging from 10 pA to 1 mA, a dynamic range of 160 dB. The log ratio amplifier in Figure 45 provides an output voltage proportional to the log base 10 of the ratio of Input Current I1 and Input Current I2. Resistor R1 and Resistor R2 are provided for voltage inputs. Because NPN devices are used in the feedback loop of the front-end amplifiers that provide the log transfer function, the output is valid only for positive input voltages and input currents. The input currents set the Collector Current IC1 and Collector Current IC2 of a matched pair of log transistors, Q1 and Q2, to develop Voltage VA and Voltage VB VA, VB = –(kT/q)ln IC/IES where IES is the saturation current of the transistor. RF The difference of VA and VB is taken by the subtractor section to obtain CF VC = (kT/q)ln(IC2/IC1) RS CS A IN EN VC is scaled up by the ratio of (R9 + R10)/R8, which is equal to approximately 16 at room temperature, resulting in the output voltage 00511-043 IS Figure 43. Photodiode Preamp Noise Sources The photodiode preamp in Figure 41 can detect a signal current of 26 fA rms at a bandwidth of 16 Hz, which, assuming a photodiode responsivity of 0.5 A/W, translates to a 52 fW rms minimum detectable power. The photodiode used has a high source resistance and low junction capacitance. CF sets the signal bandwidth with RF and also limits the peak in the noise VOUT = 1 V × log(IC2/IC1) R8 is a resistor with a positive 3500 ppm/°C temperature coefficient to provide the necessary temperature compensation. The parallel combination of R15 and R7 is provided to keep the gain of the subtractor section for positive and negative inputs matched over temperature. Rev. K | Page 15 of 18 AD549 Data Sheet composed of R13, D1, R16, R14, D2, and R17 compensate for these errors, so that this circuit has less than a 1% log conformance error at 1 mA input currents. The correct value for R13 and R14 depends on the type of log transistors used. The 49.9 kΩ resistors were chosen for use with LM394 transistors. Smaller resistance values are needed for smaller log transistors. Frequency compensation is provided by R11, R12, C1, and C2. The bandwidth of the circuit is 300 kHz at input signals greater than 50 μA; bandwidth decreases smoothly with decreasing signal levels. To trim the circuit, set the input currents to 10 μA and trim the A3 offset using the trim potentiometer of the amplifier for the output to equal 0. Next, set I1 to 1 μA and adjust the output to equal 1 V by trimming R10. Additional offset trims on Amplifier A1 and Amplifier A2 can be used to increase the voltage input accuracy and dynamic range. TEMPERATURE COMPENSATED pH PROBE AMPLIFIER A pH probe can be modeled as an mV-level voltage source with a series source resistance dependent on the electrode composition and configuration. The glass bulb resistance of a typical pH electrode pair falls between 106 Ω and 109 Ω. It is therefore important to select an amplifier with low enough input currents such that the voltage drop produced by the amplifier input bias current and the electrode resistance does not become an appreciable percentage of a pH unit. The very low input current of the AD549 makes this circuit useful over a very wide range of signal currents. The total input current (which determines the low level accuracy of the circuit) is the sum of the amplifier input current, the leakage across the compensating capacitor (negligible if a polystyrene or Teflon capacitor is used), and the collector-to-collector and collectorto-base leakages of one side of the dual log transistors. The magnitudes of these last two leakages depend on the amplifier input offset voltage and are typically less than 10 fA with 1 mV offsets. The low level accuracy is limited primarily by the amplifier input current, only 60 fA maximum when the AD549L is used. The circuit in Figure 46 illustrates the use of the AD549 as a pH probe amplifier. As with other electrometer applications, the use of guarding, shielding, and Teflon standoffs is necessary to capitalize on the AD549 low input current. If an AD549L (60 fA maximum input current) is used, the error contributed by the input current is held below 60 μV for pH electrode source impedances up to 109 Ω. Input offset voltages (which can be trimmed) are below 0.5 mV. The effects of the emitter resistance of Q1 and Q2 can degrade circuit accuracy at input currents above 100 μA. The networks FOR EACH AMPLIFIER 1 5 A1 D3 6 AD549 I1 IN 2 R1 10kΩ 0.1µF 0.1µF PIN 4 R11 4.99kΩ Q1 R15 1kΩ R3 20kΩ R5 20kΩ R7 15kΩ 3 D1 VOUT A3 AD549 D2 R17 10Ω V2 IN R13 49.9kΩ R2 10kΩ C2 100pF Q2 R4 20kΩ B 1 2 4 R6 20kΩ * 2 A2 D4 AD549 5 6 1 3 4 10kΩ V2 OFFSET 5 6 R10 10kΩ 2kΩ OUTPUT OFFSET SCALE FACTOR ADJ R9 R8 14.3kΩ 1kΩ VOUT = 1V × LOG10 4.99kΩ I2 IN –VS * A R16 10Ω R14 49.9kΩ +VS Q1, Q2 = LM394 DUAL LOG TRANSISTORS C1 100pF V1 IN PIN 7 V2 V1 I2 VOUT = 1V × LOG10 I1 D1, D4 1N4148 DIODES R8, R15 1kΩ + 350 ppm/°C TC RESISTOR *TELLAB QB1 OR PRECISION RESISTOR PT146 ALL OTHER RESISTORS ARE 1% METAL FILM Figure 45. Log Ratio Amplifier Rev. K | Page 16 of 18 00511-045 4 3 10kΩ V1 OFFSET Data Sheet AD549 the compensation. The AD549 is set for a noninverting gain of 13.51. The output of the AD590 circuitry (Point C) is equal to 10 V at 100°C and decreases by 26.8 mV/°C. The output of the AD534 analog divider (Point D) is a temperature-compensated output voltage centered at 0 V for a pH of 7 and has a transfer function of –1.00 V/pH unit. The output range spans from −7.00 V (pH = 14) to +7.00 V (pH = 0). The pH probe output is ideally 0 V at a pH of 7, independent of temperature. The slope of the transfer function of the probe, though predictable, is temperature dependent (−54.2 mV/pH at 0°C and −74.04 mV/pH at 100°C). By using an AD590 temperature sensor and an AD534 analog divider, an accurate temperature compensation network can be added to the basic pH probe amplifier. Table 4 shows voltages at various points, thereby illustrating +15V 0.1µF 0.1µF pH PROBE OUTPUT 14 (A) 3 7 AD549 2 (B) 6 0.1µF (D) OUTPUT 11 Z1 12kΩ Y2 7 1 X1 2 X2 Y1 6 8 1kΩ SCALE FACTOR ADJUST 0.1µF +15V AD590 IN STAINLESS STEEL PROBE OR AC2626 OUT 12 4 8 (C) 1kΩ AD534 10 Z2 –15V + – 00511-046 26.6kΩ Figure 46. Temperature Compensated pH Amplifier Table 4. Illustration of Temperature Compensation Point Probe Temperature (°C) 0 25 37 60 100 A (Probe Output) (mV) 54.20 59.16 61.54 66.10 74.04 B (A × 13.51) (V) 0.732 0.799 0.831 0.893 1.000 Rev. K | Page 17 of 18 C (AD590 Output) (V) 7.32 7.99 8.31 8.93 10.00 D (10 × (B ÷ C)) (V) 1.00 1.00 1.00 1.00 1.00 AD549 Data Sheet OUTLINE DIMENSIONS REFERENCE PLANE 0.50 (12.70) MIN 0.185 (4.70) 0.165 (4.19) 0.100 (2.54) BSC 0.250 (6.35) MIN 0.050 (1.27) MAX 0.160 (4.06) 0.140 (3.56) 5 0.370 (9.40) 0.335 (8.51) 0.021 (0.53) 0.016 (0.40) 6 4 0.200 (5.08) BSC 0.335 (8.51) 0.305 (7.75) 7 3 2 SIDE VIEW 0.040 (1.02) MAX 8 1 0.100 (2.54) BSC 0.019 (0.48) 0.016 (0.41) 0.045 (1.14) 0.027 (0.69) 0.034 (0.86) 0.028 (0.71) BOTTOM VIEW 45° BSC 0.040 (1.02) 0.010 (0.25) COMPLIANT TO JEDEC STANDARDS MO-002-AK CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 01-15-2015-B BASE & SEATING PLANE Figure 47. 8-Lead Metal Can [TO-99] (H-08) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 AD549JHZ AD549KHZ AD549LHZ AD549SH/883B 1 Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C −55°C to +125°C Package Description 8-Lead Metal Can (TO-99) 8-Lead Metal Can (TO-99) 8-Lead Metal Can (TO-99) 8-Lead Metal Can (TO-99) Z = RoHS Compliant Part. ©2002–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00511-0-2/15(K) Rev. K | Page 18 of 18 Package Option H-08 H-08 H-08 H-08