200 MHz to 6 GHz 35 dB TruPwr™ Detector ADL5903 Data Sheet FUNCTIONAL BLOCK DIAGRAM Accurate rms-to-dc conversion from 200 MHz to 6 GHz Measurement dynamic range of 35 dB Ripple-free transfer function Single-ended input, 50 Ω source compatible No external matching required Waveform and modulation independent, such as GSM/CDMA/W-CDMA/TD-SCDMA/LTE Linear in decibels output, scaled 35.5 mV/dB at 900 MHz Excellent temperature stability Operates from 3.0 V to 5.0 V from −55°C to +125°C Low power consumption: 3 mA at 3.0 V to 5.0 V supply 8-lead, 2 mm × 2 mm LFCSP package VPOS CREG 5 4 ADL5903 ENBL 6 INTERNAL FILTERING 1kΩ 630pF 3 CRMS 4pF RFIN 1 100Ω RMS CORE 7 VRMS BUFFER 2 8 GND NIC EP 11769-001 FEATURES Figure 1. APPLICATIONS Power amplifier linearization/control loops Transmitter power controls Transmitter signal strength indication (TSSI) RF instrumentation Wireless repeaters GENERAL DESCRIPTION The ADL5903 is a true rms responding power detector that has a 35 dB measurement range. It features low power consumption and an intrinsically ripple-free error transfer function. The ADL5903 provides a solution in a variety of high frequency systems requiring an accurate measurement of signal power. Requiring only a single supply of 3.0 V to 5.0 V and a few capacitors, it is easy to use and capable of being driven singleended or with a balun for differential input drive. An on-chip matching network provides good return loss over the specified frequency range of the device. The ADL5903 can operate from 200 MHz to 6 GHz and can accept inputs from −30 dBm to +20 dBm. Rev. B The ADL5903 can be used to determine the true power of a high frequency signal with a complex modulation envelope including large crest factor signals such as GSM, CDMA, W-CDMA, TD-SCDMA, and LTE modulated signals. The output is then proportional to the logarithm of the rms value of the input. In other words, the reading is presented directly in decibels and is scaled about 35.5 mV/dB at 900 MHz. The ADL5903 has low power consumption when operational and a disable mode that further reduces the power consumption. Power consumption is less than 100 µA when the ADL5903 enters power-down mode through a logic low at Pin ENBL. The ADL5903 is supplied in a 2 mm × 2 mm, 8-lead LFCSP for operation over the wide temperature range of −55°C to +125°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5903 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Measurement Setups ...................................................................... 14 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 15 Functional Block Diagram .............................................................. 1 RF Input Interface ...................................................................... 15 General Description ......................................................................... 1 Basic Connections ...................................................................... 15 Revision History ............................................................................... 2 Choosing a Value for CRMS......................................................... 16 Specifications..................................................................................... 3 Device Calibration and Error Calculation .............................. 17 Absolute Maximum Ratings ............................................................ 6 Evaluation Board Schematic and Configuration Options ........ 19 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 20 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 20 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 5/15—Rev. A to Rev. B Changes to Figure 49 ...................................................................... 19 2/15—Rev. 0 to Rev. A Added ADL5903ACPZN Operating Temperature Range of −40°C to +85°C; Table 2 .................................................................. 6 Changes to Ordering Guide .......................................................... 20 10/13—Revision 0: Initial Version Rev. B | Page 2 of 20 Data Sheet ADL5903 SPECIFICATIONS VPOS = 5.0 V, TA = 25°C, ZO = 50 Ω, Capacitor CRMS = 10 nF, unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Frequency Range RF INPUT INTERFACE Nominal Input Impedance1 OUTPUT INTERFACE DC Output Resistance Rise Time Fall Time f = 300 MHz ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept f = 700 MHz ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept f = 900 MHz ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Test Conditions/Comments Pin RFIN Single-ended drive Pin VRMS PIN = off to 0 dBm, 10% to 90%, CRMS = 10 nF PIN = off to 0 dBm, 10% to 90%, CRMS = 100 nF PIN = 0 dBm to off, 90% to 10%, CRMS = 10 nF PIN = 0 dBm to off, 90% to 10%, CRMS = 100 nF Continuous wave (CW) input, TA = 25°C, VPOS = 5.0 V CW input, TA = 25°C, VPOS = 3.0 V Three-point calibration at −16 dBm, −4 dBm, and +12 dBm Three-point calibration at −16 dBm, −4 dBm, and +12 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = 10 dBm −55°C < TA < +125°C; PIN = 10 dBm −40°C < TA < +85°C; PIN = −10 dBm −55°C < TA < +125°C; PIN = −10 dBm Calibration at −16 dBm and +4 dBm Calibration at −16 dBm and +4 dBm (X-intercept) CW input, TA = 25°C, VPOS = 5.0 V CW input, TA = 25°C, VPOS = 3.0 V Three-point calibration at −16 dBm, −3 dBm, and +13 dBm Three-point calibration at −16 dBm, −3 dBm, and +13 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = 10 dBm −55°C < TA < +125°C; PIN = 10 dBm −40°C < TA < +85°C; PIN = −10 dBm −55°C < TA < +125°C; PIN = −10 dBm Calibration at −16 dBm and +4 dBm Calibration at −16 dBm and +4 dBm (X-intercept) CW input, TA = 25°C, VPOS = 5.0 V CW input, TA = 25°C, VPOS = 3.0 V Three-point calibration at −16 dBm, −3 dBm, and +13 dBm Three-point calibration at −16 dBm, −3 dBm, and +13 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = 10 dBm −55°C < TA < +125°C; PIN = 10 dBm −40°C < TA < +85°C; PIN = −10 dBm −55°C < TA < +125°C; PIN = −10 dBm Calibration at −16 dBm and +4 dBm Calibration at −16 dBm and +4 dBm (X-intercept) Rev. B | Page 3 of 20 Min Typ Max Unit 200 to 6000 MHz 50 Ω 100 3.5 34 32 330 Ω µs µs µs µs 37 34 13 −24 dB dB dBm dBm −0.2/+0.032 −0.25/+0.052 −0.2/+0.152 −0.25/+0.22 36.3 −39 dB dB dB dB mV/dB dBm 37 34 14 −23 dB dB dBm dBm −0.13 −0.16 −0.15/+0.12 −0.2/+0.22 36.4 −38 dB dB dB dB mV/dB dBm 37 33 14 −23 dB dB dBm dBm −0.12 −0.15/+0.022 −0.1/+0.022 −0.1/+0.12 35.5 −38 dB dB dB dB mV/dB dBm ADL5903 Parameter f = 1900 MHz ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept f = 2140 MHz ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept f = 2600 MHz ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept f = 3500 MHz ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Data Sheet Test Conditions/Comments CW input, TA = 25°C, VPOS = 5.0 V CW input, TA = 25°C, VPOS = 3.0 V Three-point calibration at −15 dBm, −3 dBm, and +13 dBm Three-point calibration at −15 dBm, −3 dBm, and +13 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = 10 dBm −55°C < TA < +125°C; PIN = 10 dBm −40°C < TA < +85°C; PIN = −10 dBm −55°C < TA < +125°C; PIN = −10 dBm Calibration at −16 dBm and +4 dBm Calibration at −16 dBm and +4 dBm (X-intercept) Min Typ Max Unit 37 33 15 −22 dB dB dBm dBm −0.15 −0.15 −0.3/+0.22 −0.35/+0.252 37.2 −35.5 dB dB dB dB mV/dB dBm 35 32 15 −20 dB dB dBm dBm −0.2 −0.2 −0.4/+0.22 −0.5/+0.32 37.4 −35 dB dB dB dB mV/dB dBm CW input, TA = 25°C, VPOS = 5.0 V CW input, TA = 25°C, VPOS = 3.0 V Three-point calibration at −14 dBm, −2 dBm, and +14 dBm Three-point calibration at −14 dBm, −2 dBm, and +14 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = 10 dBm −55°C < TA < +125°C; PIN = 10 dBm −40°C < TA < +85°C; PIN = −10 dBm −55°C < TA < +125°C; PIN = −10 dBm Calibration at −16 dBm and +4 dBm Calibration at −16 dBm and +4 dBm (X-intercept) 34 32 15 −19 dB dB dBm dBm −0.2 −0.25 −0.5/+0.22 −0.6/+0.32 37.7 −34 dB dB dB dB mV/dB dBm CW input, TA = 25°C, VPOS = 5.0 V CW input, TA = 25°C, VPOS = 3.0 V Three-point calibration at −12 dBm, 0 dBm, and +14 dBm Three-point calibration at −12 dBm, 0 dBm, and +14 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = 10 dBm −55°C < TA < +125°C; PIN = 10 dBm −40°C < TA < +85°C; PIN = −10 dBm −55°C < TA < +125°C; PIN = −10 dBm Calibration at −12 dBm and +8 dBm Calibration at −12 dBm and +8 dBm (X-intercept) 33 31 16 −17 dB dB dBm dBm −0.2 −0.25 −0.6/+0.32 −0.75/+0.42 39 −31.5 dB dB dB dB mV/dB dBm CW input, TA = 25°C, VPOS = 5.0 V CW input, TA = 25°C, VPOS = 3.0 V Three-point calibration at −15 dBm, −3 dBm, and +13 dBm Three-point calibration at −15 dBm, −3 dBm, and +13 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = 10 dBm −55°C < TA < +125°C; PIN = 10 dBm −40°C < TA < +85°C; PIN = −10 dBm −55°C < TA < +125°C; PIN = −10 dBm Calibration at −16 dBm and +4 dBm Calibration at −16 dBm and +4 dBm (X-intercept) Rev. B | Page 4 of 20 Data Sheet Parameter f = 5800 MHz ±1.0 dB Dynamic Range Maximum Input Level, ±1.0 dB Minimum Input Level, ±1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept POWER-DOWN INTERFACE Voltage Level to Enable Voltage Level to Disable Input Bias Current POWER SUPPLY INTERFACE Supply Voltage Quiescent Current Power-Down Current 1 2 ADL5903 Test Conditions/Comments Min CW input, TA = 25°C, VPOS = 5.0 V CW input, TA = 25°C, VPOS = 3.0 V Three-point calibration at −12 dBm, −2 dBm, and +12 dBm Three-point calibration at −12 dBm, −2 dBm, and +12 dBm Deviation from output at 25°C −40°C < TA < +85°C; PIN = 10 dBm −55°C < TA < +125°C; PIN = 10 dBm −40°C < TA < +85°C; PIN = −10 dBm −55°C < TA < +125°C; PIN = −10 dBm Calibration at −12 dBm and +8 dBm Calibration at −12 dBm and +8 dBm (X-intercept) Pin ENBL Typ dB dB dBm dBm −0.6/+0.32 −0.7/+0.42 −1.1/+0.72 −1.4/+1.12 40 −27 dB dB dB dB mV/dB dBm VPOS 0.6 V V nA 5.25 V mA mA µA <20 3.0 TA = 25°C, no signal at RFIN, VPOS = 5.0 V TA = 125°C, no signal at RFIN, VPOS = 5.0 V ENBL input low condition Refer to Figure 12, input return loss, S11 (dB). The slash indicates a range. For example, −0.2/+0.03 means −0.2 to +0.03. Rev. B | Page 5 of 20 Unit 35 32 19 −16 2 0 VENBL = 2.2 V Pin VPOS Max 3 3.6 <100 ADL5903 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 2. Parameter Supply Voltage, VPOS Input Average RF Power1, 2 Equivalent Voltage, Sine Wave Input Internal Power Dissipation θJC3 θJA3 Maximum Junction Temperature Operating Temperature Range (ADL5903ACPZN) Operating Temperature Range (ADL5903SCPZN) Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 20 dBm 3.16 V peak 200 mW 3.95°C/W 78.5°C/W 150°C −40°C to +85°C ESD CAUTION −55°C to +125°C −65°C to +150°C 300°C 1 This is for long durations. Excursions above this level, with durations much less than 1 second, are possible without damage. 2 Driven from a 50 Ω source. 3 No airflow with the exposed pad soldered to a 4-layer JEDEC board. Rev. B | Page 6 of 20 Data Sheet ADL5903 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFIN 1 8 NIC GND 2 ADL5903 7 VRMS CRMS 3 TOP VIEW (Not to Scale) 6 ENBL 5 VPOS NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GND AND REQUIRES A GOOD THERMAL AND ELECTRICAL CONNECTION TO THE GROUND OF THE PRINTED CIRCUIT BOARD (PCB). 11769-002 CREG 4 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic RFIN 2 3 GND CRMS 4 CREG 5 6 VPOS ENBL 7 VRMS 8 0 NIC EP Description Signal Input. This pin is internally ac-coupled with a broadband matching network. See the RF Input Interface section for broadband matching options. Device Ground. Connect GND to system ground using a low impedance path. RMS Averaging Pin. Connect a capacitor between the CREG and CRMS pins for rms averaging. See the Choosing a Value for CRMS section for choosing the correct CRMS capacitor value. Bypass Capacitor Connection for On-Chip Regulator. Bypass this pin to ground using a capacitor and a series resistor. See Basic Connections section for more information. Supply Voltage. The operational range is 3.0 V to 5.25 V. Enable. Connect the ENBL pin to a logic high (2 V to VPOS) to enable the device. Connect the ENBL pin to a logic low (0 V to 0.6 V) to disable the device. Signal Output. The output from the VRMS pin is proportional to the logarithm of the rms value at the input level. No Internal Connection. Do not connect to this pin. This pin is not internally connected. Exposed Pad. The exposed pad is internally connected to GND and requires a good thermal and electrical connection to the ground of the printed circuit board (PCB). Rev. B | Page 7 of 20 ADL5903 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VPOS = 5.0 V, CRMS = 10 nF, TA = −55°C (light blue), TA = −40°C (blue), +25°C (green), +85°C (red), +125°C (orange) where appropriate. Input levels referred to 50 Ω source. Input RF signal is a sine wave (CW), unless otherwise indicated. 2.0 2.0 1.8 1.6 1.2 1.0 300MHz 700MHz 900MHz 1.90GHz 2.14GHz 2.60GHz 3.50GHz 5.80GHz 10dBm 0dBm –10dBm –20dBm 0.5 0.2 0 5 10 15 20 PIN (dBm) 0 100M 6 2.4 5 2.2 4 2.0 3 1.8 5 4 3 1 1.2 0 1.0 –1 0.8 –2 –3 0.6 –3 0.4 –4 0.4 –4 0.2 –5 0.2 –5 1.4 1 1.2 0 1.0 –1 0.8 –2 0.6 ERROR (dB) 2 1.4 2 0 –30 –6 –25 –20 –15 –10 –5 0 5 10 PIN (dBm) Figure 4. Error from CW Linear Reference vs. Input Level and Signal Modulation (QPSK, 16 QAM, 64 QAM), Frequency = 900 MHz, CRMS = 1 µF 0 –30 –6 –25 –20 –15 –10 –5 0 5 10 PIN (dBm) Figure 7. Error from CW Linear Reference vs. Input Level and Signal Modulation (QPSK, 16 QAM, 64 QAM), Frequency = 2.14 GHz, CRMS = 1 µF 6 4 2.0 1.8 3 1.8 3 1.6 2 1.6 2 1.4 1 1.4 1 1.2 0 1.2 0 1.0 –1 1.0 –1 0.8 –2 –3 0.6 –3 –4 0.4 –4 –5 0.2 –5 0.8 –2 0.6 0.4 0.2 0 –30 –6 –25 –20 –15 –10 –5 0 5 10 PIN (dBm) 11769-005 2.0 CW 4-CARRIER W-CDMA PEP = 12.08dBm 1-CARRIER W-CDMA PEP = 10.56dB CALIBRATION AT –15dBm, –3dBm, AND +8dBm OUTPUT VOLTAGE (V) 2.4 2.2 2.2 ERROR (dB) 6 5 2.4 OUTPUT VOLTAGE (V) 6 CW 16 QAM PEP = 6.34dB 64 QAM PEP = 7.17dB QPSK PEP = 3.8dB CALIBRATION AT –15dBm, –3dBm, AND +8dBm 1.6 1.6 11769-004 OUTPUT VOLTAGE (V) 1.8 CW 16 QAM PEP = 6.34dB 64 QAM PEP = 7.17dB QPSK PEP = 3.8dB CALIBRATION AT –16dBm, –3dBm, AND +8dBm OUTPUT VOLTAGE (V) 2.4 2.0 6G Figure 6. Typical VRMS vs. Frequency for Four Input Levels Figure 3. Typical VRMS vs. Input Level vs. Frequency (300 MHz to 5.80 GHz) at 25°C 2.2 1G FREQUENCY (Hz) ERROR (dB) –5 11769-003 0.0 –40 –35 –30 –25 –20 –15 –10 11769-007 0.4 Figure 5. Error from CW Linear Reference vs. Input Level and Signal Modulation (One-Carrier W-CDMA, Four-Carrier W-CDMA), Frequency = 2.14 GHz, CRMS = 1 µF 0 –30 CW LTE TM1 1-CARRIER 20MHz PEP = 11.58dB CALIBRATION AT –15dBm, –3dBm, AND +8dBm –25 –20 –15 –10 –5 0 5 4 5 ERROR (dB) 0.6 –6 10 PIN (dBm) Figure 8. Error from CW Linear Reference vs. Input Level and Signal Modulation (LTE TM1 One-Carrier, 20 MHz), Frequency = 2.14 GHz, CRMS = 1 µF Rev. B | Page 8 of 20 11769-008 0.8 1.0 11769-006 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.5 1.4 Data Sheet ADL5903 0 2.5 4.00V TO 5.00V FOLLOW SAME PLOT –5 RETURN LOSS, S11 (dB) 1.5 3.00V 3.40V 3.80V 4.00V 4.25V 4.50V 5.00V 1.0 –15 –20 –10 0 10 20 PIN (dBm) –25 11769-009 –30 0 1 2 Figure 9. Output Voltage vs. Input Level and Supply Voltage at 900 MHz +5dBm 1.4 0dBm 1.2 OUTPUT (V) 1.0 –15dBm 0.8 0.4 0.4 0.2 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 0 –0.2 11769-010 0.2 –15dBm 0.8 0.6 0 –5dBm 1 0.6 –0.2 0dBm 1.2 –5dBm Figure 10. Output Response to RF Burst Input, Carrier Frequency = 900 MHz, CRMS = 100 nF (see Figure 36 in the Measurement Setups Section) 0 0.2 0.4 TIME (ms) 0.6 0.8 11769-011 1.4 VOUT (V) 6 RF BURST PULSE 1.6 +5dBm Figure 13. Output Response to RF Burst Input, Carrier Frequency = 900 MHz, CRMS = 10 nF (see Figure 36 in the Measurement Setups Section) 1.8 1.8 ENABLE PULSE SUPPLY VOLTAGE PULSE 1.6 1.6 +5 dBm 1.4 +5dBm 1.4 0 dBm 1.2 0dBm 1.2 OUTPUT (V) –5 dBm 1.0 –15 dBm 0.8 0.8 0.6 0.4 0.4 0.2 0.2 –0.1 0 0.1 0.2 TIME (ms) 0.3 0.4 1.5 0.6 –5dBm 1.0 0.6 0 –0.2 11769-016 OUTPUT (V) 5 1.8 RF BURST PULSE 1.6 0 –0.2 4 Figure 12. Input Return Loss vs. RF Frequency 1.8 0 –0.4 3 FREQUENCY (GHz) 11769-012 –20 0.5 0 –40 –10 –15dBm –0.1 0 0.1 0.2 TIME (ms) Figure 11. Output Response to Gating on ENBL Pin for Various RF Input Levels, Carrier Frequency = 900 MHz, CRMS = 100 nF (see Figure 38 in the Measurement Setups Section) 0.3 0.4 0.5 0.6 11769-015 OUTPUT VOLTAGE (V) 2.0 Figure 14. Output Response to Gating on Power Supply for Various RF Input Levels, Carrier Frequency = 900 MHz, CRMS = 100 nF, 5.0 V Supply (see Figure 37, in the Measurement Setups Section)) Rev. B | Page 9 of 20 ADL5903 Data Sheet 6 2.2 5 4 2.0 3 1.8 1.2 0 1.4 1 1.2 0 1.0 –1 0.8 –2 1.0 –1 0.8 –2 0.6 –3 0.6 –3 0.4 –4 0.4 –4 0.2 –5 0.2 –5 0 –40 –35 –30 –25 –20 –15 –10 –6 –5 0 5 10 15 20 PIN (dBm) Figure 15. VRMS and Log Conformance Error vs. Input Level and Temperature at 300 MHz 2.0 1.8 1.6 CALIBRATION AT –16dBm, –3dBm, AND +13dBm –55°C –40°C +25°C +85°C +125°C 2.4 2.2 4 2.0 3 1.8 1.4 1 1.2 0 1.0 –1 0.8 –2 0.6 0 5 10 15 –6 20 Figure 18. Distribution of Log Conformance Error with Respect to Calibration at 25°C vs. Input Level and Temperature at 300 MHz 5 2 –5 PIN (dBm) 6 ERROR (dB) 2.2 0 –40 –35 –30 –25 –20 –15 –10 OUTPUT VOLTAGE (V) 2.4 1.6 6 5 –55°C –40°C +25°C +85°C +125°C 4 3 2 1.4 1 1.2 0 1.0 –1 0.8 –2 –3 0.6 –3 0.4 –4 0.4 –4 0.2 –5 0.2 –5 0 –40 –35 –30 –25 –20 –15 –10 –6 –5 0 5 10 15 20 PIN (dBm) Figure 16. VRMS and Log Conformance Error vs. Input Level and Temperature at 700 MHz 2.4 0 –40 –35 –30 –25 –20 –15 –10 11769-021 OUTPUT VOLTAGE (V) 2 1.6 ERROR (dB) 1 4 3 11769-020 2 1.4 –55°C –40°C +25°C +85°C +125°C –5 0 5 10 15 ERROR (dB) 1.6 2.4 5 –6 20 11769-024 1.8 –55°C –40°C +25°C +85°C +125°C 6 11769-017 OUTPUT VOLTAGE (V) 2.0 CALIBRATION AT –16dBm, –4dBm, AND +12dBm ERROR (dB) 2.2 OUTPUT VOLTAGE (V) 2.4 PIN (dBm) Figure 19. Distribution of Log Conformance Error with Respect to Calibration at 25°C vs. Input Level and Temperature at 700 MHz 6 2.4 5 2.2 4 2.0 3 1.8 6 4 3 1.6 2 1.4 1 1.2 0 1.0 –1 0.8 –2 1.4 1 1.2 0 1.0 –1 0.8 –2 0.6 –3 0.6 –3 0.4 –4 0.4 –4 0.2 –5 0.2 –5 0 –40 –35 –30 –25 –20 –15 –10 –6 –5 PIN (dBm) 0 5 10 15 20 0 –40 –35 –30 –25 –20 –15 –10 Figure 17. VRMS and Log Conformance Error vs. Input Level and Temperature at 900 MHz –6 –5 PIN (dBm) 0 5 10 15 20 ERROR (dB) 2 5 –55°C –40°C +25°C +85°C +125°C 11769-025 1.6 ERROR (dB) 1.8 –55°C –40°C +25°C +85°C +125°C 11769-022 OUTPUT VOLTAGE (V) 2.0 OUTPUT VOLTAGE (V) CALIBRATION AT –16dBm, –3dBm, AND +13dBm 2.2 Figure 20. Distribution of Log Conformance Error with Respect to Calibration at 25°C vs. Input Level and Temperature at 900 MHz Rev. B | Page 10 of 20 Data Sheet ADL5903 2.2 4 2.0 3 1.8 2 6 5 –55°C –40°C +25°C +85°C +125°C 4 3 1.6 2 1.4 1 1.2 0 1.0 –1 0.8 –2 1.4 1 1.2 0 1.0 –1 0.8 –2 0.6 –3 0.6 –3 0.4 –4 0.4 –4 0.2 –5 0.2 –5 0 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 –6 20 0 –40 –35 –30 –25 –20 –15 –10 PIN (dBm) Figure 21. VRMS and Log Conformance Error vs. Input Level and Temperature at 1.9 GHz –6 –5 0 5 10 15 20 PIN (dBm) Figure 24. Distribution of Log Conformance Error with Respect to Calibration at 25°C vs. Input Level and Temperature at 1.9 GHz 6 2.4 2.2 5 2.2 2.0 4 2.0 3 1.8 2.4 ERROR (dB) 1.6 –55°C –40°C +25°C +85°C +125°C 2.4 5 11769-023 OUTPUT VOLTAGE (V) 1.8 6 11769-026 2.0 CALIBRATION AT –15dBm, –3dBm, AND +13dBm ERROR (dB) 2.2 OUTPUT VOLTAGE (V) 2.4 6 4 2 1.4 1 1.2 0 1.0 –1 0.8 –2 1 1.2 0 1.0 –1 0.8 –2 0.6 –3 0.6 –3 0.4 –4 0.4 –4 0.2 –5 0.2 –5 5 10 15 PIN (dBm) Figure 22. VRMS and Log Conformance Error vs. Input Level and Temperature at 2.14 GHz 6 2.4 5 2.2 2.0 4 2.0 3 1.8 2 ERROR (dB) 1.6 OUTPUT VOLTAGE (V) –55°C –40°C +25°C +85°C +125°C 5 10 15 20 Figure 25. Distribution of Log Conformance Error with Respect to Calibration at 25°C vs. Input Level and Temperature at 2.14 GHz CALIBRATION AT –14dBm, –2dBm, AND +14dBm 1.8 0 PIN (dBm) 2.2 2.4 –6 –5 6 5 –55°C –40°C +25°C +85°C +125°C 4 3 1.6 2 1.4 1 1.2 0 1.0 –1 0.8 –2 1.4 1 1.2 0 1.0 –1 0.8 –2 0.6 –3 0.6 –3 0.4 –4 0.4 –4 0.2 –5 0.2 –5 –5 PIN (dBm) 0 5 10 15 –6 20 0 –40 –35 –30 –25 –20 –15 –10 11769-028 0 –40 –35 –30 –25 –20 –15 –10 Figure 23. VRMS and Log Conformance Error vs. Input Level and Temperature at 2.6 GHz 11769-030 0 0 –40 –35 –30 –25 –20 –15 –10 –6 –5 PIN (dBm) 0 5 10 15 20 ERROR (dB) –5 –6 20 ERROR (dB) 3 1.6 1.4 0 –40 –35 –30 –25 –20 –15 –10 OUTPUT VOLTAGE (V) 5 –55°C –40°C +25°C +85°C +125°C 11769-031 2 ERROR (dB) 1.6 –55°C –40°C +25°C +85°C +125°C 11769-027 OUTPUT VOLTAGE (V) 1.8 OUTPUT VOLTAGE (V) CALIBRATION AT –15dBm, –3dBm, AND +13dBm Figure 26. Distribution of Log Conformance Error with Respect to Calibration at 25°C vs. Input Level and Temperature at 2.6 GHz Rev. B | Page 11 of 20 ADL5903 Data Sheet 2.2 2.0 4 2.0 3 1.8 4 3 1.6 2 1.4 1 1.2 0 1.0 –1 0.8 –2 1.4 1 1.2 0 1.0 –1 0.8 –2 0.6 –3 0.6 –3 0.4 –4 0.4 –4 0.2 –5 0.2 –5 –5 0 5 10 15 –6 20 PIN (dBm) Figure 27. VRMS and Log Conformance Error vs. Input Level and Temperature at 3.5 GHz 2.0 1.8 2.4 5 2.2 4 2.0 3 1.8 2 1.4 1 1.2 0 1.0 –1 0.8 –2 0.6 0 5 10 15 20 Figure 30. Distribution of Log Conformance Error with Respect to Calibration at 25°C vs. Input Level and Temperature at 3.5 GHz 6 1.6 –6 –5 PIN (dBm) OUTPUT VOLTAGE (V) –55°C –40°C +25°C +85°C +125°C 2.2 ERROR (dB) 2.4 0 –40 –35 –30 –25 –20 –15 –10 6 –55°C –40°C +25°C +85°C +125°C 5 4 3 1.6 2 1.4 1 1.2 0 1.0 –1 0.8 –2 –3 0.6 –3 0.4 –4 0.4 –4 0.2 –5 0.2 –5 0 –40 –35 –30 –25 –20 –15 –10 11769-033 CALIBRATION AT –12dBm, –2dBm, AND +12dBm 0 –6 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 PIN (dBm) Figure 28. VRMS and Log Conformance Error vs. Input Level and Temperature at 5.8 GHz –6 –5 0 5 10 15 20 PIN (dBm) Figure 31. Distribution of Log Conformance Error with Respect to Calibration at 25°C vs. Input Level and Temperature at 5.8 GHz 1400 1400 REPRESENTS MORE THAN 8000 PARTS REPRESENTS MORE THAN 8000 PARTS 1200 1000 1000 800 800 600 600 400 400 200 200 0 1.50 1.55 1.60 1.65 1.70 1.75 VRMS (V) 0 0.60 0.65 0.70 0.75 0.80 0.85 VRMS (V) Figure 32. Distribution of VRMS, PIN = −16 dBm, 900 MHz Figure 29. Distribution of VRMS, PIN = 8 dBm, 900 MHz Rev. B | Page 12 of 20 11769-037 COUNT 1200 11769-034 COUNT ERROR (dB) 0 –40 –35 –30 –25 –20 –15 –10 OUTPUT VOLTAGE (V) 5 –55°C –40°C +25°C +85°C +125°C 11769-036 ERROR (dB) 2 11769-029 OUTPUT VOLTAGE (V) 1.6 OUTPUT VOLTAGE (V) –55°C –40°C +25°C +85°C +125°C 1.8 6 ERROR (dB) 2.4 5 CALIBRATION AT –12dBm, 0Bm, AND +14dBm 11769-032 6 2.2 2.4 Data Sheet CALIBRATION BETWEEN –16dBm AND –4dBm CALIBRATION BETWEEN –16dBm AND –4dBm REPRESENTS MORE THAN 8000 PARTS 1200 1000 COUNT COUNT 1000 800 600 –40 –38 –36 –34 –32 11769-038 –42 INTERCEPT (dBm) 30 –55°C –40°C +25°C +85°C +125°C 25 20 15 10 –20 –10 0 10 PIN (dBm) 20 11769-014 5 –30 0 30 32 34 36 SLOPE (mV/dB) 38 Figure 35. Distribution of Slope at 900 MHz Figure 33. Distribution of Intercept at 900 MHz SUPPLY CURRENT (mA) 600 200 200 0 –40 800 400 400 0 –44 REPRESENTS MORE THAN 8000 PARTS 1200 Figure 34. Supply Current vs. Input Level (at −55°C, −40°C, +25°C, +85°C, +125°C) Rev. B | Page 13 of 20 40 11769-035 1400 ADL5903 ADL5903 Data Sheet MEASUREMENT SETUPS RF OUT RFIN PULSE IN VPOS AGILENT 33522A FUNCTION/ARBITRATRY WAVEFORM GENERATOR RF OUT VRMS ENBL HP E3631A POWER SUPPLY VPOS TEKTRONIX DIGITAL PHOSPHOR OSCILLOSCOPE TDS5104 HP E3631A POWER SUPPLY 1MΩ TRIGGER 11769-013 Figure 36. Hardware Configuration for Output Response to RF Burst Input Measurements PULSE IN CH1 CH2 VRMS VPOS ENBL TEKTRONIX DIGITAL PHOSPHOR OSCILLOSCOPE TDS5104 1MΩ TRIGGER AD8019 EVALUATION BOARD AGILENT 33522A FUNCTION/ARBITRATRY WAVEFORM GENERATOR ENBL TEKTRONIX DIGITAL PHOSPHOR OSCILLOSCOPE TDS5104 1MΩ TRIGGER Figure 38. Hardware Configuration for Output Response to ENBL Pin Gating Measurements ADL5903 EVALUATION BOARD RFIN VRMS AGILENT 33522A FUNCTION/ARBITRATRY WAVEFORM GENERATOR CH2 RF OUT RFIN PULSE IN CH1 ROHDE & SCHWARZ SIGNAL GENERATOR SMR 40 ADL5903 EVALUATION BOARD +1 11769-018 CH1 CH2 11769-019 ROHDE & SCHWARZ SIGNAL GENERATOR SMR 40 ROHDE & SCHWARZ SIGNAL GENERATOR SMR 40 ADL5903 EVALUATION BOARD Figure 37. Hardware Configuration for Output Response to Power Supply Gating Measurements Rev. B | Page 14 of 20 Data Sheet ADL5903 THEORY OF OPERATION ESD 4pF CREG 5 4 ADL5903 ENBL 6 GND Figure 40. Simplified RF Input Interface 0 EXTERNAL 127Ω SHUNT TERM NO SHUNT TERM –5 –20 100Ω RMS CORE 7 VRMS 8 GND NIC EP 11769-039 BUFFER 2 –25 0 1 2 3 4 FREQUENCY (GHz) 5 6 The ADL5903 requires a single supply of 3.0 V to 5.0 V. The supply is connected to the VPOS supply pin. This pin is decoupled using two capacitors with values equal or similar to those shown in Figure 44. Place these capacitors as near the VPOS pin as possible. 3 CRMS RFIN 1 –15 BASIC CONNECTIONS 630pF 4pF –10 Figure 41. Return Loss with and Without External Shunt Termination INTERNAL FILTERING 1kΩ 133Ω 11769-040 OPTIONAL 127Ω An RF input matching network allows the device to be driven with a 50 Ω source with reasonable input return loss. The measurement intercept varies with frequency, as shown in Table 1 and the Typical Performance Characteristics section. VPOS MATCHING NETWORK 11769-041 The core rms processing of the ADL5903 uses a proprietary technique that provides accuracy for complex modulation signals irrespective of the crest factor of the input signal. An integrating filter capacitor at Pin CRMS performs the square domain averaging. VPOS ESD The ADL5903 operates from a nominal supply voltage of 3.0 V to 5.0 V. The rms core is internally regulated to 3.6 V, that is, the full measurement range is available for supply voltages between 3.8 V and 5.0 V. Below 3.8 V, the high end of the measurement range degrades gradually whereas the low end shows no noticeable change in error characteristics or calibration requirements. At 2.14 GHz, the measurement range extends to 14 dBm for 3.8 V and above, and to 12 dBm at a supply voltage of 3.0 V. The low end of the ADL5903 measurement range is limited by internal device offsets that vary from device to device but tracks well over temperature. See the Device Calibration and Error Calculation section for more information. 200 MHz. Add an external shunt resistance of 127 Ω, if desired, when operating at low frequencies to improve input return loss over the range of 200 MHz to 1.7 GHz. Figure 41 shows a comparison of the input return loss, with and without the external shunt resistor. RETURN LOSS, S11 (dB) The ADL5903 is a true rms detector with a 35 dB measurement range at 2.14 GHz with useable range up to 6 GHz. It features no error ripple over its range, low temperature drift, and very low power consumption. Temperature stability of the rms output measurements provides ≤±0.5 dB error typical over the temperature range of −40°C to +85°C up to 3.5 GHz. The measurement output voltage scales linearly in decibels with a slope of approximately 36 mV/dB. Figure 39. Simplified Architecture RF INPUT INTERFACE A single-ended input at the RFIN pin drives the ADL5903, and a 50 Ω source can drive it directly without any external components. Figure 40 shows the simplified RF input interface. An on-chip matching network presents 133 Ω of shunt resistance to ground and ac coupling to the rms core. The ESD protection circuitry is designed to allow voltage swings as high as ±2 V at the input. The CREG pin provides a bypass capacitor connection for an on-chip regulator. The CREG pin is connected to ground with a 4.02 Ω resistor and a 0.1 μF capacitor. The CRMS pin provides an averaging function for the rms computation and is referenced to Pin 4 (CREG). A filter capacitor can be placed between the CRMS and CREG pins. More information on choosing the CRMS capacitor is provided in the Choosing a Value for CRMS section. Using smaller values for CRMS allows quicker response times to a pulsed waveform. Higher values of CRMS are required for correct rms computation as the peak to average ratio of modulated signals increases and the bandwidth of the modulated signals decreases. As shown in Figure 12 (input return loss, S11), the device offers excellent input return loss over most of the operating range but rises to around −9 dB near its minimum operating frequency of Rev. B | Page 15 of 20 ADL5903 Data Sheet 1M OUTPUT NOISE (mV p-p) 10% TO 90% RISE TIME (µs) 90% to 10% FALL TIME (µs) OUTPUT NOISE (mV p-p) 600 The output buffer of the ADL5903 features a PMOS common source drive transistor and a resistive pull-down load. Under typical operating conditions, the internal measurement range of the device limits the output signal range to ≤2.2 V. Place a 100 Ω resistor on chip in series with the output to allow additional filtering, if desired. 500 10k 400 1k 300 100 200 10 100 1 0 0.1 CHOOSING A VALUE FOR CRMS 1 10 0.1 1000 Figure 42. Output Noise, Rise/Fall Times vs. CRMS Capacitance, Single Carrier W-CDMA (Test Model TM1-64) at 2.14 GHz with PIN = 0 dBm 100M OUTPUT NOISE (mV p-p) 400 Figure 42 and Figure 43 show how output noise varies with CRMS when the ADL5903 is driven by a single carrier W-CDMA (Test Model TM1-64, peak envelope power = 10.56 dB, bandwidth = 3.84 MHz) and an LTE signal (Test Model TM1-20, peak envelope power = 11.58 dB, bandwidth = 20 MHz), respectively. 350 1M 300 100k 250 10k 200 1k 150 100 100 10 50 1 0 0.1 1 10 100pF 4.02Ω 0.1μF 0.1μF VPOS 0.1μF CREG 5 4 ADL5903 1kΩ 630pF INTERNAL FILTERING 3 4pF 1 100Ω RMS CORE 7 CRMS VRMS VRMS BUFFER 2 GND 8 NIC EP Figure 44. Basic Connections Rev. B | Page 16 of 20 11769-044 RFIN 0.1 1000 CFLT4 (nF) VPOS 6 100 Figure 43. Output Noise, Rise/Fall Times vs. CRMS Capacitance, Single Carrier LTE (Test Model TM1-20) at 2.14 GHz with PIN = 0 dBm Figure 42 and Figure 43 also show how the value of CRMS affects the response time. This is measured by applying an RF burst at 2.14 GHz at 0 dBm to the ADL5903. The 10% to 90% rise time and 90% to 10% fall time are then measured. ENBL 10M RISE/FALL TIME (µs) OUTPUT NOISE (mV p-p) 10% TO 90% RISE TIME (µs) 90% to 10% FALL TIME (µs) 11769-043 450 In applications where the response time is not critical, place a relatively large capacitor on the CRMS pin. In Figure 44, a value of 0.1 µF is used. For most signal modulation schemes, this value ensures excellent rms measurement compliance and low residual output noise. There is no maximum capacitance limit for CRMS. RFIN 100 CRMS CAPACITANCE (nF) CRMS provides the averaging function for the internal rms computation. Using the minimum value for CRMS allows the quickest response time to a pulsed waveform but leaves significant output noise on the output voltage signal. However, a large filter capacitor reduces output noise and improves the rms measurement accuracy but at the expense of the response time. VENBL 100k RISE/FALL TIME (µs) 700 11769-042 The ENBL pin configures the device enable interface. Connecting the ENBL pin to a logic high signal (2 V to 5.0 V) enables the device, and connecting the pin to a logic low signal (0 V to 0.6 V) disables the device. The exposed pad is internally connected to GND and must be soldered to a low impedance ground plane. Data Sheet ADL5903 Table 4. Recommended Minimum CRMS Values for Various Modulation Schemes The values in Table 4 were experimentally determined to be the minimum capacitance that ensures good rms accuracy for that particular signal type. This test was initially performed with a large capacitance value on the CRMS pin (for example, 10 μF). The value of VRMS was noted for a fixed input level (for example, −10 dBm). The value of CRMS was then progressively reduced (this can be accomplished with press-down capacitors) until the value of VRMS started to deviate from its original value (this indicates that the accuracy of the rms computation is degrading and that CRMS is becoming too small). In general, the minimum CRMS required increases as the peak-toaverage ratio of the carrier increases. The minimum required CRMS also tends to increase as the bandwidth of the carrier decreases. With narrow-band carriers, the noise spectrum of the VRMS output tends to have a correspondingly narrow profile. The relatively narrow spectral profile demands a larger value of CRMS that reduces the low-pass corner frequency of the averaging function and ensures a valid rms computation. Output Noise (mV p-p) 140 80 60 50 50 80 96 76 CRMSMIN (nF) 10 10 1000 100 100 100 100 100 Rise/Fall Times (μs) 3.5/32 3.5/32 280/2600 34/330 34/330 34/330 34/330 34/330 2.4 6 CALIBRATION AT –10dBm AND +10dBm 2.2 5 2.0 4 –55°C –40°C +25°C +85°C +125°C 1.8 1.6 3 2 1.4 1 1.2 0 1.0 –1 0.8 –2 0.6 –3 0.4 –4 0.2 –5 0 –40 –35 –30 –25 –20 –15 –10 ERROR (dB) Table 4 shows the recommended minimum values of CRMS for popular modulation schemes. The output response time and noise performance are also shown. Using lower capacitor values results in faster response times but can result in degraded rms measurement accuracy. If the output noise shown in Table 4 is unacceptably high, it can be reduced by increasing CRMS or by implementing an averaging algorithm after the output voltage of the ADL5903 has been sampled by an analog-to-digital converter (ADC). Carrier Bandwidth (MHz) 5 15 1 5 13 3.84 18.84 20 –6 –5 0 5 10 15 20 PIN (dBm) 11769-045 QPSK, 5 MSPS (SQR COS Filter, = 0.35) QPSK ,15 MSPS (SQR COS Filter, = 0.35) 64 QAM, 1 MSPS (SQR COS Filter, = 0.35) 64 QAM, 5 MSPS (SQR COS Filter, = 0.35) 64 QAM, 13 MSPS (SQR COS Filter, = 0.35) W-CDMA, One-Carrier, TM1-64 W-CDMA Four-Carrier, TM1-64, TM1-32, TM1-16, TM1-8 LTE, TM1, One-Carrier, 20 MHz (2048 QPSK Subcarriers) Peak Envelope Power Ratio (dB) 4.0 4.1 7.4 7.4 7.4 10.56 12.08 11.58 OUTPUT VOLTAGE (V) Modulation/Standard Figure 45. 2.14 GHz VRMS and Log Conformance Error at +25°C, −40°C, −55°C, +85°C, and +125°C Board level calibration must be performed to achieve high accuracy because the slope and intercept vary from device to device. For a two-point calibration, write the equation for the idealized output voltage as VRMS(IDEAL) = Slope × (PIN − Intercept) (1) DEVICE CALIBRATION AND ERROR CALCULATION where: Slope is the change in output voltage divided by the change in input level (dBm). PIN is the input level. Intercept is the calculated input level at which the output voltage is equal to 0 V (note that Intercept is an extrapolated theoretical value and not a measured value). The measured transfer function of the ADL5903 at 2.14 GHz is shown in Figure 45, which contains plots of both output voltage and log conformance error vs. input level for one device. As the input level varies from −30 dBm to +14 dBm, the output voltage varies from near 0 V to 1.9 V. In general, calibration is performed during equipment manufacture by applying two or more known signal levels to the input of the ADL5903 and measuring the corresponding output voltages. The calibration points must be within the linear operating range of the device. With a two-point calibration, calculate the slope and intercept as follows: Rev. B | Page 17 of 20 Slope = (VRMS1 − VRMS2)/(PIN1 − PIN2) (2) Intercept = PIN1 − (VRMS1/Slope) (3) ADL5903 Data Sheet After the slope and intercept are calculated (and stored in some form) an equation can be used to calculate an unknown input level based on the output voltage of the detector. Error (dB) = (VRMS(MEASURED) − VRMS(IDEAL))/Slope (5) Figure 45 shows the log conformance error at five temperatures, ranging from −55°C to +125°C, when using a two-point calibration (calibration points are +10 dBm and −10 dBm) measured at one temperature, 25°C. The error at the two calibration points passes through 0 dB for the 25°C curve by definition. Multipoint calibration can be used to further extend the measurement dynamic range. In this case, the transfer function is segmented, with each segment having its own slope and intercept. Figure 46 shows the error plot of the same device with calibration points at −16 dBm, −4 dBm, and+12 dBm. The three-point, dual-slope calibration results in tighter error bounds over the high end of the range and extends the lower measurement range to better than −20 dBm for ±1 dB error. 2.4 6 5 2.0 4 –55°C –40°C +25°C +85°C +125°C 1.8 1.6 3 2 1.4 1 1.2 0 ERROR (dB) OUTPUT VOLTAGE (V) CALIBRATION AT –16dBm, –4dBm, AND +12dBm 2.2 4 –55°C –40°C +25°C +85°C +125°C 1.8 1.6 3 2 1.4 1 1.2 0 1.0 –1 0.8 –2 0.6 –3 0.4 –4 0.2 –5 0 –40 –35 –30 –25 –20 –15 –10 ERROR (dB) The log conformance error is the difference between this straight line and the actual performance of the detector. 5 2.0 –6 –5 0 5 10 15 11769-047 (4) 6 CALIBRATION AT –16dBm, –4dBm, AND +12dBm 2.2 OUTPUT VOLTAGE (V) PIN (Unknown) = (VRMS(MEASURED)/Slope) + Intercept 2.4 20 PIN (dBm) Figure 47. 2.14 GHz VRMS and Log Conformance Error for Second Device at +25°C, −40°C, −55°C, +85°C, and +125°C For comparison, the three-point calibration of a different device is shown in Figure 47 for the same frequency and calibration points. For this example, note that the device has greater dynamic range, and the temperature dependence of error at lower power levels is inverted. Finally, Figure 48 shows the log conformance error at 2.14 GHz for a collection of four devices at +25°C, −40°C, and +85°C with three-point calibration (−16 dBm, −4 dBm, and+12 dBm). The error plots at each temperature are calculated with respect to the slope and intercept measurements from the 25°C line for each device. This is consistent with a typical production environment where calibration at one temperature is required. Figure 48 illustrates the various error scenarios possible at low input levels. The dynamic range of the three-point calibrated devices extends to below −20 dBm for ±1.0 dB error. 1.0 –1 0.8 –2 0.6 –3 2.4 0.4 –4 2.2 5 0.2 –5 2.0 4 –6 1.8 6 5 10 15 20 Figure 46. 2.14 GHz VRMS and Log Conformance Error at +25°C, −40°C, −55°C, +85°C, and +125°C For the example shown in Figure 46, the error drift with temperature is very small over the upper 20 dB of the measurement range, varying ±0.3 dB, but widens at lower power levels, from −20 dBm to −5 dBm to as high as ±0.9 dB. This is typical performance, although some devices may perform better. –40°C +25°C +85°C 1.6 3 2 1.4 1 1.2 0 1.0 –1 0.8 –2 0.6 –3 0.4 –4 0.2 –5 0 –40 –35 –30 –25 –20 –15 –10 –6 –5 PIN (dBm) 0 5 10 15 20 ERROR (dB) PIN (dBm) 0 11769-048 –5 OUTPUT VOLTAGE (V) 0 –40 –35 –30 –25 –20 –15 –10 11769-046 CALIBRATION AT –16dBm, –4dBm, AND +12dBm Figure 48. 2.14 GHz VRMS and Log Conformance +25°C, −40°C, and +85°C for Multiple Devices Rev. B | Page 18 of 20 Data Sheet ADL5903 EVALUATION BOARD SCHEMATIC AND CONFIGURATION OPTIONS P201 (24-PIN TEST HEADER) A B 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 R209 DNI R208 DNI OUT EP RFIN NIC 8 1 RFIN VPOS C210 DNI R204 2 COMM COMM VRMS 7 0Ω ADL5903 3 CRMS VOUT S201 ENBL 6 4 CREG C205A DNI C205 DNI TO P201 R202 0.1μF 4.02Ω C203A 0.1μF C203 DNI C201 100pF ENBL 1 VPOS C209 3 2 R205 100kΩ VPOS 5 R206 100kΩ DNI C202 0.1μF TO P201 R203 TO P201 DNI R207 DNI C204 DNI 11769-049 C204A DNI TO P201 Figure 49. Evaluation Board Schematic Table 5. Evaluation Board Configuration Options Component RFIN, R208 R205, R206, S201 C201, C202 C209 R202, C203A R204, C210 C203, C204, C204A, C205, C205A, R203, R207, R209 EP 1 Description RF input. R208 is a shunt input termination to optimize low frequency input return loss. Device enable interface. Header S201 configures the enable network. Pin 2 and Pin 3 of S201 enable the resistive divider network. R205 and R206 form a resistive divider network to step down the voltage provided by VPOS for an optimal enable setpoint condition. Power supply decoupling. The nominal supply decoupling consists of a 100 pF and a 0.1 μF capacitor placed near the device. RMS averaging capacitor. C209 is the capacitor (CRMS) interfacing CREG and CRMS for rms averaging. Set the value of the rms averaging capacitor on the peak-to-average ratio of the input signal and based on the desired output response time and residual output noise. See the Choosing a Value for CRMS section for more information. Bypass capacitor connection for on-chip regulator. R202 and C203A are connected to the CREG pin to provide decoupling for the internal regulator. RMS output. R204 and C210 provide options for output filtering and to mimic system load conditions. Test header interface. Exposed pad. The exposed pad is soldered to a ground pad, which provides both a thermal ground and an electrical ground. DNI = do not install. Rev. B | Page 19 of 20 Default Value RFIN = SMA connector, R208 = DNI1 R205 = 100 kΩ, R206 = 100 kΩ, S201 = Jumper Pin 2 and Jumper Pin 3 C201 = 100 pF, C202 = 0.1 µF C209 = 0.1 µF R202 = 4.02 Ω, C203A = 0.1 µF R204 = 0 Ω, C210 = DNI1 C203, C204, C204A, C205, C205A, R203, R207, R208, R209 = DNI1 ADL5903 Data Sheet OUTLINE DIMENSIONS 1.70 1.60 1.50 2.10 2.00 SQ 1.90 0.50 BSC 8 5 PIN 1 INDEX AREA 1.10 1.00 0.90 EXPOSED PAD 0.425 0.350 0.275 1 4 TOP VIEW BOTTOM VIEW 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 01-14-2013-C 0.60 0.55 0.50 0.15 REF 0.20 REF Figure 50. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD] 2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead (CP-8-10) Dimensions shown in millimeters ORDERING GUIDE Model1 ADL5903ACPZN-R7 ADL5903SCPZN-R7 ADL5903-EVALZ 1 Temperature Range −40°C to +85°C −55°C to +125°C Package Description 8-Lead LFCSP_UD, 7’’ Tape and Reel 8-Lead LFCSP_UD, 7’’ Tape and Reel Evaluation Board Z = RoHS Compliant Part. ©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11769-0-5/15(B) Rev. B | Page 20 of 20 Package Option CP-8-10 CP-8-10 Branding BS CJ Ordering Quantity 3,000 3,000